Semiconductor device and manufacturing method thereof

Abstract

Provided is a technique capable of improving the trade-off relationship between on-resistance reduction and off-loss reduction. On the premise that a low-carbon hole density region (20) having a small carbon hole density is formed on the upper surface side of a drift region (4) and a high-carbon hole density region (30) having a large carbon hole density is formed on the lower surface side of the drift region (4), isodensity lines are included in a boundary region (40) between the low-carbon hole density region (20) and the high-carbon hole density region (30). The position of an isodensity line (100) having a carbon hole concentration corresponding to a density equal to 1 / 2 of the carbon hole density in the high-carbon hole density region (30) is located deeper than an end portion (200) of a depletion layer extending to the drift region (4) when the IGBT is turned off.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and, for example, to a technology effectively applied to a semiconductor device having an insulated gate bipolar transistor and a method for manufacturing the same. Background Art

[0002] To achieve energy-saving power electronics, research is underway to develop low-loss power semiconductor devices using wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and diamond. Because silicon carbide and gallium nitride have dielectric breakdown field strengths approximately 10 times higher than silicon (Si), the drift region thickness of power semiconductor devices with the same withstand voltage can be reduced to one-tenth that of silicon. This thinning of the drift region significantly reduces resistance within the drift region, thereby lowering the overall on-resistance of the device.

[0003] Wide-bandgap semiconductor materials are used in unipolar devices such as Schottky barrier diodes (SBDs) and power MOSFETs (metal oxide field effect transistors), as well as bipolar devices such as pn junction diodes and insulated gate bipolar transistors (IGBTs). In particular, bipolar devices using silicon carbide are expected to achieve low conduction losses in ultra-high withstand voltage applications exceeding 6.5 kV.

[0004] In silicon carbide, the minority carrier lifetime in the material at the end of growth of the epitaxial crystal layer (the as-grown state, where as-grown means "as-grown") is significantly shortened compared to silicon. Therefore, in order to improve the conductivity modulation effect in bipolar devices and reduce the resistance during on-state operation, a process for increasing the minority carrier lifetime in the drift region is implemented during device manufacturing. On the other hand, when the minority carrier lifetime of the drift region as a whole is large, the turn-off loss increases due to the increase in residual carriers discharged during the turn-off operation when the device switches from the on state to the off state. Therefore, it is possible to reduce the on-state voltage and turn-off loss by using a "local lifetime control structure" in the drift region where the minority carrier lifetime is locally short only on the collector side.

[0005] Patent Document 1 describes a device in which the end of a depletion layer formed in a drift region when an operating voltage is applied is positioned in a region where the minority carrier lifetime is short.

[0006] In addition, Patent Document 2 describes the following method: when forming a region that extends the minority carrier lifetime inside a silicon carbide epitaxial layer, by changing the annealing temperature or annealing time of the annealing used to diffuse and activate carbon atoms ion-implanted into the silicon carbide epitaxial layer, a method is used to arbitrarily change the depth of the carrier lifetime extension region from the injection surface of the silicon carbide epitaxial layer, so that the thickness of the region is thicker than other regions of the epitaxial layer.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent No. 3622405

[0010] Patent Document 2: Japanese Patent Application Laid-Open No. 2021-19157 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] However, in Patent Document 1, a region with a short minority carrier lifetime exists within the depletion layer. Since there are no residual carriers in the depletion layer, even a short minority carrier lifetime in the depletion layer does not affect the suppression of conduction losses. However, it increases the on-resistance, worsening the trade-off between on-resistance and turn-off losses.

[0013] Furthermore, Patent Document 2 does not describe the relationship between the carrier lifetime extension region and the depletion layer. Therefore, similar to Patent Document 1, the trade-off relationship between on-resistance and off-loss may be deteriorated.

[0014] In view of the above problems, an object of the present invention is to provide a technology capable of improving the trade-off relationship between reduction of on-resistance and reduction of turn-off loss.

[0015] Means for solving problems

[0016] A semiconductor device in one embodiment includes an insulated gate bipolar transistor (IGBT) having a first conductivity type drift region, the drift region being formed of silicon carbide. The drift region includes a first region having a first carbon vacancy density, a second region having a second carbon vacancy density higher than the first, and a boundary region sandwiched between the first and second regions, the carbon vacancy density being higher in the first region and lower in the second region. In this case, an isodensity line included in the boundary region, corresponding to a carbon vacancy concentration of half the second density, is located deeper than the end of a depletion layer extending into the drift region when the IGBT is turned off.

[0017] A method for manufacturing a semiconductor device in one embodiment is a method for manufacturing a semiconductor device including an insulated gate bipolar transistor in which an end portion of an extended depletion layer resides within a drift region when the device is off. The method includes the following steps: (a) forming a first conductivity type drift region whose constituent material includes silicon carbide; (b) implanting carbon atoms into the upper surface of the drift region; and (c) diffusing the carbon atoms into the interior of the drift region.

[0018] Furthermore, after step (c), the drift region includes a first region having a first carbon vacancy density, a second region having a second carbon vacancy density higher than the first density, and a boundary region sandwiched between the first and second regions, wherein the carbon vacancy density is higher in the first region but lower in the second region. In this case, the position of the isodensity line included in the boundary region, where the carbon vacancy concentration corresponds to half the second density, is deeper than the end of the depletion layer extending during the off state.

[0019] Effects of the Invention

[0020] According to one embodiment, it is possible to achieve improvements in both reduction of on-state voltage and reduction of turn-off loss, which are in a trade-off relationship with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a diagram showing an active cell of an IGBT in a concrete embodiment.

[0022] Figure 2 A diagram showing a manufacturing process of a semiconductor device in a specific embodiment.

[0023] Figure 3 It shows the next Figure 2 A diagram of the manufacturing process of a semiconductor device.

[0024] Figure 4 It shows the next Figure 3 A diagram of the manufacturing process of a semiconductor device.

[0025] Figure 5 It shows the next Figure 4 A diagram of the manufacturing process of a semiconductor device.

[0026] Figure 6 It shows the next Figure 5 A diagram of the manufacturing process of a semiconductor device.

[0027] Figure 7 It shows the next Figure 6 A diagram of the manufacturing process of a semiconductor device.

[0028] Figure 8 It is a figure which shows the modification example of a manufacturing method.

[0029] Figure 9 This is a graph showing simulation results of time changes in the current and voltage at the off time for each case in which the lifetime of minority carriers in the high carbon hole density region as the “local lifetime control structure” is changed.

[0030] Figure 10 It is a diagram showing a first modification of the structure.

[0031] Figure 11 It is a diagram showing a second modification of the structure.

[0032] Figure 12 It is a diagram showing a third structural modification. DETAILED DESCRIPTION

[0033] In all the drawings for explaining the embodiments, the same reference numerals are generally given to the same components, and their repeated descriptions are omitted. It should be noted that hatching may be applied to the top views to make the drawings clearer.

[0034] In this embodiment, a semiconductor device including an insulated gate bipolar transistor (IGBT) having an n-type channel structure in which the drift region and emitter region are formed of an n-type semiconductor region and the body region is formed of a p-type semiconductor region is described as an example. However, the technical concepts in this embodiment can also be applied to an IGBT having a p-type channel structure in which the conductivity type is reversed.

[0035] <Study by the inventors of this application>

[0036] In an insulated-gate bipolar transistor (IGBT), when a gate voltage exceeding the threshold voltage is applied to the gate electrode, turning the IGBT on, holes, which are minority carriers, are injected from the collector region into the drift region. This causes electrons, which are majority carriers, to be injected from the emitter region into the drift region, attracted by the injected holes. This results in conductivity modulation in the drift region, reducing the IGBT's on-resistance.

[0037] On the other hand, in an IGBT, when a gate voltage less than the threshold is applied to the gate electrode, causing the IGBT to switch from on to off, the IGBT turns off after all electrons and holes injected into the drift region are swept out of the drift region. In other words, in an IGBT, when turned off, all electrons and holes injected into the drift region must be swept out of the drift region. After the tail current caused by this sweep flows out, the IGBT turns off.

[0038] In an IGBT operating in this manner, the longer the lifetime of holes, which are minority carriers, the lower the on-resistance can be. This is because a longer lifetime of holes injected into the drift region increases the number of holes available to attract electrons. Consequently, the number of electrons attracted to the drift region increases, reducing the on-resistance. Therefore, to reduce the on-resistance of an IGBT, it is desirable to extend the lifetime of holes.

[0039] On the other hand, turn-off loss is generated when the IGBT is turned off. The cause of this turn-off loss is the tail current. Therefore, in order to reduce the turn-off loss, it is necessary to reduce the tail current. This tail current is the current generated when all the electrons and holes injected into the drift region are swept out to the outside of the drift region. The shorter the lifetime of the holes, the smaller the tail current can be. The reason is that if the lifetime of the holes is short, the number of holes eliminated before being swept out to the outside of the drift region increases. As a result, the number of holes swept out to the outside of the drift region decreases, which means that the tail current is reduced.

[0040] Therefore, in an IGBT, a longer hole lifetime reduces on-resistance, while a shorter hole lifetime reduces turn-off losses. In other words, in an IGBT, reducing on-resistance and reducing turn-off losses are in a trade-off relationship. Therefore, the inventors of this application have studied improvements that balance this trade-off between reducing on-resistance and reducing turn-off losses.

[0041] For example, the drift region can be formed using epitaxial growth. However, in IGBTs using silicon carbide as a component material, the lifetime of holes in the "as-grown" drift region is known to be significantly shorter than that of IGBTs using silicon as a component material. Therefore, using the "as-grown" drift region directly reduces turn-off losses due to the shorter hole lifetime, but also increases on-resistance. Therefore, using the "as-grown" drift region directly is undesirable in IGBTs using silicon carbide as a component material.

[0042] Regarding this, carbon vacancies exist in the drift region made of silicon carbide. These carbon vacancies function as trap levels for holes. Consequently, in drift regions with high carbon vacancy density, the number of trap levels for hole capture increases, shortening the hole lifetime. In other words, in drift regions with low carbon vacancy density, the number of trap levels for hole capture decreases, extending the hole lifetime.

[0043] Based on the above, it is believed that by implanting carbon into the drift region in the "generated state," carbon vacancies can be filled with the injected carbon. In this case, the number of carbon vacancies that function as trap levels for holes can be reduced, resulting in a longer hole lifetime. Specifically, the inventors of this application have studied extending the hole lifetime by implanting carbon into the drift region. The reasoning is that if the hole lifetime can be extended, the on-resistance of the IGBT can be reduced.

[0044] However, implanting carbon throughout the drift region increases the lifetime of holes throughout the drift region, leading to increased turn-off losses. Therefore, in order to strike a balance between reducing on-resistance and reducing turn-off losses, which are a trade-off, it is important to specify the depth of carbon implantation in the drift region.

[0045] That is to say, on the premise that a low carbon hole density region is set in the drift region where carbon is injected to reduce the carbon vacancy density and a high carbon hole density region is set in which carbon is not injected but the "generated state" is maintained to increase the carbon hole density, it is important to determine the position (depth) at which the depth of the boundary region between the low carbon hole density region and the high carbon hole density region is determined.

[0046] Regarding this point, the inventors of the present application have discovered a new insight, namely, when specifying the depth of the above-mentioned boundary area, in order to achieve improvements in both reduced on-resistance and reduced turn-off loss, which are in a trade-off relationship with each other, it is important to specify the relationship with the end of the depletion layer that extends to the drift region when the IGBT is turned off.

[0047] For example, consider a case where the depth of the aforementioned boundary region is shallower than the end of the depletion layer, which extends into the drift region when the IGBT is turned off. In this case, the low carbon hole density region becomes narrower, which is disadvantageous from the perspective of reducing on-resistance. On the other hand, within the depletion layer, residual carriers are swept out by the electric field within the depletion layer. Therefore, even if a high carbon hole density region with a short hole lifetime exists within the depletion layer, it is located within the depletion layer, thus not affecting the improvement of turn-off loss.

[0048] That is, from the perspective of achieving improvements in both reduction of on-resistance and reduction of off-loss, which are in a trade-off relationship, a configuration in which the depth of the boundary region is shallower than that of the end portion of the depletion layer is not appropriate.

[0049] Therefore, in this embodiment, in order to achieve a compromise between reducing on-resistance and reducing off-loss, efforts are made to appropriately define the depth of the boundary region between the low carbon hole density region and the high carbon hole density region relative to the end of the depletion layer. The technical concept of this embodiment that led to this effort is described below.

[0050] <Basic Concept of Implementation>

[0051] The basic concept of this embodiment is based on the premise that, in an IGBT using silicon carbide as its constituent material, a low carbon hole density region, where carbon is injected to reduce the carbon vacancy density, and a high carbon hole density region, where no carbon is injected but the carbon vacancy density is maintained in a "grown state," thereby increasing the carbon hole density, are provided in the drift region. Furthermore, the basic concept is that the boundary between the low carbon hole density region and the high carbon hole density region is located deeper than the end of the depletion layer that extends into the drift region when the IGBT is turned off.

[0052] This basic concept increases the thickness of the low-carbon hole density region, which has a long hole lifetime, thereby reducing the on-resistance of the IGBT. Meanwhile, the basic concept places the high-carbon hole density region, which has a short hole lifetime, below the depletion layer. Adjusting the thickness of the high-carbon hole density region reduces turn-off losses caused by tail current. Specifically, by positioning the boundary region deeper than the end of the depletion layer, the basic concept achieves a compromise between reducing on-resistance and reducing turn-off losses.

[0053] The following describes how to implement the basic concept.

[0054] <Method of Manifestation>

[0055] <<Semiconductor Device Structure>>

[0056] Figure 1 It is a cross-sectional view schematically showing an active cell of an “n-channel SiC-IGBT” (hereinafter sometimes simply referred to as IGBT) included in a semiconductor device in a specific embodiment.

[0057] exist Figure 1 In the embodiment, the IGBT has an n-type drift region 4 containing n-type impurities (doped) such as nitrogen and phosphorus, and the drift region 4 includes silicon carbide as its main constituent material. The drift region 4 includes, for example, a buffer region 3a and a low-concentration drift region 3b, with the buffer region 3a formed below the low-concentration drift region 3b. That is, the drift region 4 includes the low-concentration drift region 3b and the buffer region 3a. The buffer region 3a is located below the low-concentration drift region 3b and is in contact with the low-concentration drift region 3b, and has a higher impurity concentration than the low-concentration drift region 3b. The buffer region 3a is not essential, but is provided to improve the withstand voltage of the IGBT and suppress conduction losses (reduce the on-resistance of the IGBT).

[0058] There is a p in the lower layer of the buffer zone 3a. + Type collector region 2, in the p + The collector 1 is provided in the lower layer of the p-type collector region 2. + The p-type collector region 2 is composed of a p-type semiconductor region containing p-type impurities such as aluminum and boron, for example.

[0059] Next, a body region 5 as a p-type semiconductor region containing aluminum, boron, etc. is formed inside the low-concentration drift region 3b, and an n-type semiconductor region containing nitrogen, phosphorus, etc. is formed inside the body region 5. + A body contact region 7 having an impurity concentration higher than that of the body region 5 is formed in the contact opening of the body region 5 .

[0060] Next, to cover n + A gate insulating film 8 is formed so as to cover the n-type emitter region 6, the body region 5 and the low concentration drift region 3b, and a gate electrode 9 is provided so as to cover the gate insulating film 8. + An emitter electrode 10 is provided so as to form a gate-type emitter region 6 and a body contact region 7 , and an interlayer insulating film 11 is formed to insulate the gate electrode 9 from the emitter electrode 10 .

[0061] In an IGBT structured as described above, the drift region 4 includes silicon carbide as its main constituent material, which inevitably results in the presence of carbon vacancies. Furthermore, in the drift region 4 of the embodiment, the carbon vacancies have a desired density distribution.

[0062] In other words, the drift region 4 in the embodiment includes: a low carbon hole density region 20 having a first carbon hole density; a high carbon hole density region 30 having a second carbon hole density higher than the first carbon hole density; and a boundary region 40 sandwiched between the low carbon hole density region 20 and the high carbon hole density region 30, wherein the carbon hole density is higher in the low carbon hole density region 20 and lower in the high carbon hole density region 30. For example, the first carbon hole density is less than 1×10 13 / cm 3 , the second density is 1×10 13 / cm 3 above.

[0063] In this embodiment, the low carbon vacancy density region 20 is located within the low-concentration drift region 3b. Meanwhile, the high carbon vacancy density region 30 is located within a portion of the low-concentration drift region 3b and the buffer region 3a. Furthermore, as isodensity lines included in the boundary region 40, isodensity lines 100 corresponding to a carbon vacancy concentration of half the second density are located deeper than the end 200 of the depletion layer that extends into the drift region 4 when the IGBT is turned off. In this embodiment, isodensity lines 100 are located within the low-concentration drift region 3b, and the end 200 of the depletion layer is also located within the low-concentration drift region 3b.

[0064] For example, in Figure 1The graph shown on the right side of FIG shows the depth-wise distribution of the carbon vacancy density contained in the drift region 4 (dashed line) and the depth-wise distribution of the electric field generated in the drift region 4 when the IGBT is turned off with a power supply voltage applied between the collector electrode 1 and the emitter electrode 10 (single-dot chain line). Figure 1 As can be seen in the graph on the right, a low carbon hole density region 20, where the carbon vacancy density is low, extends from the upper surface of the drift region 4. Furthermore, a high carbon hole density region 30, where the carbon vacancy density is high, is formed below the low carbon hole density region 20, across a boundary region 40. Within the boundary region 40, an isodensity line 100, where the carbon hole density is half that of the high carbon hole density region 30, is located deeper than an end 200 of the depletion layer where the electric field generated in the drift region 4 is "0."

[0065] It should be noted that carbon vacancies function as trap levels that capture minority carriers (holes). Therefore, the minority carrier lifetime in the low carbon hole density region 20, where the carbon vacancy density is low, is longer than the minority carrier lifetime in the high carbon hole density region 30, where the carbon vacancy density is high. Thus, the semiconductor device in the embodiment includes an IGBT configured such that the drift region 4 includes regions with different minority carrier lifetimes.

[0066] <<Method for manufacturing a semiconductor device>>

[0067] Next, a method for manufacturing a semiconductor device in a practical embodiment will be described.

[0068] First, if Figure 2 As shown in FIG. 1 , an n-type bulk substrate 12 made of silicon carbide is prepared. Then, p-type silicon carbide is grown on the upper surface of the bulk substrate 12 by epitaxial growth. + type collector region 2, buffer region 3a and low concentration drift region 3b.

[0069] Here, p + The impurity concentration of the collector region 2 is, for example, 1×10 18 / cm 3 The impurity concentration of the buffer region 3a is higher than that of the low-concentration drift region 3b. The impurity concentration of the low-concentration drift region 3b is, for example, lower than 5×10 15 / cm 3 The temperature in the epitaxial growth method is set to 1700°C or higher, for example, and the epitaxial growth is performed so that p + The carbon vacancy density in each of the collector region 2, the buffer region 3a and the low concentration drift region 3b is 1×10 13 / cm 3For example, when the withstand voltage of the IGBT is 6.5 kV, the thickness of the low-concentration drift region 3b is approximately 50 μm to 100 μm. Furthermore, when the withstand voltage of the IGBT is 20 kV, the thickness of the low-concentration drift region 3b is approximately 180 μm to 250 μm.

[0070] Next, if Figure 3 As shown in FIG. 1 , carbon atoms are ion-implanted from the upper surface of the low-concentration drift region 3 b. The implantation amount of carbon atoms is, for example, 1×10 15 / cm 2 Then, as Figure 4 As shown, heat treatment causes carbon atoms to diffuse into the low-concentration drift region 3b. This allows carbon atoms to fill the carbon vacancies in the region from the upper surface of the low-concentration drift region 3b to a predetermined depth, thereby reducing the density of carbon vacancies in this region. The heat treatment temperature (annealing temperature) is, for example, 1300°C or higher, and the heat treatment time is, for example, 60 minutes or longer.

[0071] Like this, such as Figure 4 As shown, in the embodiment, a low carbon hole density region 20 having a first carbon hole density, a high carbon hole density region 30 having a second carbon hole density higher than the first carbon hole density, and a boundary region 40 sandwiched between the low carbon hole density region 20 and the high carbon hole density region 30, wherein the carbon hole density is higher than that of the low carbon hole density region 20 and lower than that of the high carbon hole density region 30, are formed. Figure 4 In FIG. 4 , as the isopycnts 100 included in the boundary region 40 , for example, the isopycnts 100 corresponding to a carbon vacancy concentration having a density half of the second density are shown.

[0072] Next, if Figure 5 As shown, the main body region 5, n and n regions are formed on the upper surface of the low concentration drift region 3b, for example, by ion implantation using a photoresist as a patterned mask. + The type emitter region 6 and the body contact region 7. The impurity concentration of the body region 5 is, for example, 2×10 16 / cm 3 to 2×10 18 / cm 3 Around. + The type emitter region 6 and the body contact region 7 are formed by, for example, implanting conductive impurities at a high concentration so that the impurity concentration is 1×10 19 / cm 3 Next, after forming a protective film made of, for example, carbon on the surface, a heat treatment is performed at, for example, 1700° C. to 1900° C. to activate the conductive impurities implanted by the ion implantation method.

[0073] Next, after removing the protective film by oxygen plasma treatment or the like, for example, a gate insulating film 8 is formed on the low concentration drift region 3 b by forming a silicon oxide film using wet oxidation, dry oxidation, or CVD (Chemical Vapor Deposition).

[0074] Next, the gate electrode 9 is formed by the following method: after forming the gate insulating film 8, a polysilicon film is formed directly on it by CVD method, or an amorphous silicon film is formed by CVD method, and then the amorphous silicon film is modified into a polysilicon film by heat treatment. In addition, after forming the interlayer insulating film 11 composed of a silicon oxide film by CVD method, a contact portion is opened in the interlayer insulating film 11 by using dry etching method, for example. As a result, at the bottom of the contact portion, n + The type emitter region 6 and the body contact region 7 are exposed from the interlayer insulating film 11 .

[0075] Then, for example, the emitter electrode 10 made of a metal film such as aluminum, titanium, or nickel is formed by sputtering or metal vapor deposition. A portion of the emitter electrode 10 is buried in the contact portion, and the emitter electrode 10 is connected to the n + The emitter region 6 and the body contact region 7 are electrically connected.

[0076] It should be noted that, before forming the emitter electrode 10, an n-type electrode may be formed to cover the exposed bottom portion of the contact portion. + A silicide layer is formed on the upper surface of the emitter region 6 and the body contact region 7. The silicide layer can be formed using, for example, a self-aligned silicide technique.

[0077] Next, if Figure 6 As shown, the bulk substrate 12 is removed by a grinding process, thereby making the p + The lower surface of the p-type collector region 2 is exposed. + A semiconductor substrate consisting of a type collector region 2, a buffer region 3a and a low concentration drift region 3b.

[0078] It should be noted that, here, an example is described in which the bulk substrate 12 is removed after forming the device structure such as the gate electrode 9 on the semiconductor substrate. However, if the drift region 4 (epitaxial growth layer) on the bulk substrate 12 has sufficient strength, such as Figure 2 As shown, the bulk substrate 12 may be removed after the drift region 4 is formed, and then device structures such as the body region 5 and the gate electrode 9 may be formed.

[0079] Next, if Figure 7 As shown in p +The collector electrode 1 is formed on the lower surface of the p-type collector region 2. The collector electrode 1 can be formed of a metal film such as aluminum, titanium, nickel or gold by using a sputtering method or a metal vapor deposition method. + A silicide layer is formed on the lower surface of the collector region 2. The silicide layer can be formed by laser annealing technology, for example.

[0080] As described above, a semiconductor device in a practical embodiment can be manufactured.

[0081] The following summarizes a method for manufacturing a semiconductor device in a specific embodiment. Specifically, the method for manufacturing a semiconductor device in a specific embodiment is a method for manufacturing an IGBT in which the end of a depletion layer extending during the off state resides within the drift region 4. The method includes the following steps: (a) forming an n-type drift region 4 composed of silicon carbide; (b) implanting carbon atoms into the upper surface of the drift region 4; and (c) diffusing the carbon atoms into the interior of the drift region 4.

[0082] Then, in the completed semiconductor device after step (c), the drift region 4 includes a low carbon hole density region having a first carbon hole density, a high carbon hole density region having a second carbon hole density higher than the first carbon hole density, and a boundary region sandwiched between the low carbon hole density region and the high carbon hole density region, wherein the carbon hole density is higher in the low carbon hole density region but lower in the high carbon hole density region. Furthermore, the boundary region includes an isodensity line corresponding to a carbon hole concentration of half the second density, located deeper than the end of the depletion layer extending during the off state.

[0083] <<Variations in the production method>>

[0084] Next, a modified example of the production method will be described.

[0085] In this modification, if Figure 2 As shown, in the sequential growth of each p + After the collector region 2, buffer region 3a and low concentration drift region 3b, Figure 8 As shown in FIG. 1 , a silicon oxide film 50 is formed by thermal oxidation. In this case, the silicon carbide on the upper surface side of the low concentration drift region 3b is decomposed by thermal oxidation. As a result, the silicon generated during the decomposition forms the silicon oxide film 50 in the form of silicon dioxide, while the carbon generated during the decomposition reacts with the silicon carbide on the upper surface side of the low concentration drift region 3b. Figure 3 Likewise, it is located in an atomic form on the upper surface side of the low concentration drift region 3 b.

[0086] Simultaneously, the carbon atoms diffuse during the thermal oxidation process, filling the carbon vacancies present in the region extending from the upper surface of the low-concentration drift region 3 b to a predetermined depth. Consequently, the density of carbon vacancies in this region decreases. The thermal oxidation process is performed at a temperature of, for example, 1300° C. or higher, and for, for example, 60 minutes or longer.

[0087] Then, after the silicon oxide film 50 is removed using hydrofluoric acid, for example, a device structure (element structure) is formed in the same manner as in the above-mentioned embodiment.

[0088] In the method for manufacturing a semiconductor device according to this modification, carbon atom generation and carbon vacancy filling by diffusion of carbon atoms can be performed in the same thermal oxidation step. Furthermore, the step of removing the silicon oxide film 50 is also performed as a substrate surface cleaning step in the embodiment. Therefore, in this modification, a semiconductor device can be manufactured with a reduced number of steps.

[0089] <<Characteristics of the Manifestation>>

[0090] Next, the characteristic points of the embodiment will be described.

[0091] The characteristic point of the embodiment is that, for example, Figure 1 As shown, on the premise that a low carbon hole density region 20 with a small carbon hole density is formed on the upper surface side of the drift region 4 and a high carbon hole density region 30 with a large carbon hole density is formed on the lower surface side of the drift region 4, an isodensity line 100 corresponding to a carbon hole concentration of 1 / 2 of the carbon hole density of the high carbon hole density region 30 is located deeper than an end 200 of the depletion layer extending to the drift region 4 when the IGBT is turned off, as contained in the boundary region 40 between the low carbon hole density region 20 and the high carbon hole density region 30.

[0092] Here, carbon vacancies act as a factor that reduces the lifetime of minority carriers in silicon carbide. Therefore, the lifetime of minority carriers in the low carbon vacancy density region 20 where the carbon vacancy density is small is longer than that in the high carbon vacancy density region 30 where the carbon vacancy density is large.

[0093] Therefore, the presence of the low-carbon hole density region 20 reduces the on-resistance of the IGBT during operation. Meanwhile, when the IGBT is turned off, there are no residual carriers in the depletion layer extending into the drift region 4. Therefore, as long as the low-carbon hole density region 20 is within the depletion layer, it does not affect turn-off losses. Consequently, the characteristic features of this embodiment improve the trade-off between the on-resistance (on-voltage) of the IGBT during operation and the turn-off losses of the IGBT during turn-off.

[0094] For example, since the impurity concentration difference between the low-concentration drift region 3b and the main region 5 is large and the built-in voltage generated by the pn junction of silicon carbide is much smaller than the power supply voltage, the depth Wd (cm) of the depletion layer formed in the IGBT when voltage is applied can be expressed by the following formula.

[0095] Wd={(2·εs·Vcc) / (q·Nd)} 0.5

[0096] Here, the power supply voltage is set to Vcc (V), the impurity concentration of the low-concentration drift region 3b is set to Nd (1 / cm 3 ), let the charge of the electron be q(C), and let the dielectric constant of silicon carbide be εs(F / cm).

[0097] Therefore, if the thickness of the low carbon hole density region 20 is set to W (cm), and the characteristic point in the embodiment (Wd<W) is combined with the above relationship, the power supply voltage Vcc that realizes the characteristic point satisfies the following conditions.

[0098] Vcc<{(q·Nd) / (2·εs)}·W 2

[0099] Furthermore, the high carbon hole density region 30 functions as a region with a short minority carrier lifetime, a so-called "local lifetime control structure." That is, in a practical embodiment, the high carbon hole density region 30 constitutes a "local lifetime control structure."

[0100] Figure 9 This is a graph showing simulation results of time changes in the current and voltage at the off time in various cases in which the lifetime of minority carriers in the high carbon hole density region 30 as the “local lifetime control structure” is changed.

[0101] When the minority carrier lifetime in the high carbon hole density region 30 is made the same as that in the low carbon hole density region 20, that is, when there is no "local lifetime control structure", the collector current decreases over time but slopes gently in the middle, generating a tail current.

[0102] In contrast, if the lifetime of minority carriers in the high carbon vacancy density region 30 is shortened, the waveform becomes basically the same as that without the "local lifetime control structure" in the case of 5μs represented by the dotted line, but the tail current decreases in the case of 2μs represented by the single-dot chain line and in the case of 0.5μs represented by the double-dot chain line.

[0103] That is, by setting the minority carrier lifetime in the high carbon hole density region 30 to approximately 2 μs or less, the turn-off loss reduction effect due to the “local lifetime control structure” can be achieved. Therefore, the carbon hole density in the high carbon hole density region 30 is 1×10 13 / cm 3 In this regard, the carbon vacancy density of the high carbon vacancy density region 30 is the same as the carbon vacancy density of the epitaxial growth layer in the as-grown state. Therefore, the carbon vacancy density can be reduced to 1×10 13 / cm 3 The above realizes the "local life control structure" in the embodiment.

[0104] It should be noted that in the embodiment, silicon carbide is used as the semiconductor material. In this case, carbon vacancies, which are the main factor that shortens the lifetime of minority carriers, form a "deep energy level" of 0.63 eV from the conduction band of silicon carbide. This is deeper than the energy level formed by crystal defects, which are the main factor that shortens the lifetime of minority carriers in silicon. Therefore, according to the embodiment, the "local lifetime control structure" can be maintained even at higher temperatures to reduce turn-off losses. IGBTs are power switching elements that are used to pass large currents. Therefore, the temperature becomes high when the IGBT is in operation. Therefore, by using silicon carbide as the semiconductor material, the effect of the "local lifetime control structure" can be obtained even at high temperatures, thereby obtaining an IGBT with a wider operating range.

[0105] Thus, based on the characteristic features of the embodiment, the trade-off between reduced on-resistance and reduced turn-off loss can be improved. In particular, by using silicon carbide as the semiconductor material, the trade-off improvement effect can be achieved even at high temperatures.

[0106] <<Structural modification example 1>>

[0107] Next, this modification example 1 will be described.

[0108] Figure 10 1 is a cross-sectional view showing an active cell of the IGBT in the first modification.

[0109] like Figure 10 As shown, the difference between the IGBT in this variant example 1 and the IGBT in the above-mentioned embodiment is that, in this variant example 1, the position of the isodensity line 100 corresponding to the carbon vacancy concentration and the density of 1 / 2 of the carbon vacancy density in the high carbon vacancy density region 30 is located inside the buffer zone 3a and the end 200 of the depletion layer is also located inside the buffer zone 3a.

[0110] Such a device structure is realized in the manufacturing process of the IGBT. Figure 4In the heat treatment (annealing) after the carbon atoms are implanted, the heat treatment temperature and the heat treatment time are set higher than those in the embodiment mode to allow the carbon atoms to diffuse deeper.

[0111] In this modification 1, if Figure 10 As shown, the drift region 4 includes a low concentration drift region 3b and a buffer region 3a. The buffer region 3a is located below the low concentration drift region 3b, is adjacent to the low concentration drift region 3b, and has a higher impurity concentration than the low concentration drift region 3b.

[0112] At this time, in this variant example 1, the low carbon vacancy density region 20 is set in a part of the buffer zone 3a and the low concentration drift zone 3b, the high carbon vacancy density region 30 is set in the buffer zone 3a, the equal density line 100 is located in the buffer zone 3a, and the end 200 of the depletion layer is also located in the buffer zone 3a.

[0113] In an IGBT configured in this manner, the depth-direction distribution of the electric field generated in the drift region 4 between the collector electrode 1 and the emitter electrode 10 when the IGBT is turned off has a steeper slope in the buffer region 3a, where the impurity concentration is high. This allows the depletion layer to be suppressed even when the power supply voltage is increased. Consequently, even when the power supply voltage is increased, the position of the isodensity line 100 can be positioned greater than the depth of the depletion layer end 200. Therefore, according to this first modification, the trade-off between reduced on-resistance and reduced turn-off loss can be improved over a wider power supply voltage range than that of the embodiment.

[0114] <<Structural Modification 2>>

[0115] Next, this modification example 2 will be described.

[0116] Figure 11 1 is a cross-sectional view showing an active cell of an IGBT in the second modification.

[0117] The difference between the IGBT in this modification 2 and the IGBT in the above embodiment is that a high-concentration drift region 3c having an impurity concentration greater than that of the low-concentration drift region 3b and less than that of the buffer region 3a is provided between the low-concentration drift region 3b and the buffer region 3a. Other differences are as follows: Figure 11 As shown, in this variation example 2, the position of the isodensity line 100 corresponding to the carbon vacancy concentration being 1 / 2 of the carbon vacancy density in the high carbon vacancy density region 30 is located inside the high concentration drift region 3c, and the end 200 of the depletion layer is also located inside the high concentration drift region 3c.

[0118] Such a device structure can be used in the manufacturing process of IGBT in the actual form. Figure 2When forming the low-concentration drift region 3b by the epitaxial growth method shown in FIG. 1 , the impurity-doped raw material gas supplied is increased only during the initial predetermined period. Alternatively, the high-concentration drift region 3c may be grown after forming the buffer region 3a, and then the low-concentration drift region 3b may be formed. In addition, if the drift region 4 on the bulk substrate 12 has sufficient strength, as shown in FIG. 1 , the high-concentration drift region 3c may be grown after forming the buffer region 3a, and then the low-concentration drift region 3b may be formed. Figure 5 As shown, it is also possible to form p + After removing the bulk substrate 12, the collector region 2, the buffer region 3a, and the low concentration drift region 3b, the bulk substrate 12 is removed. + N-type impurities such as nitrogen and phosphorus are ion-implanted (doped) into the lower surface side (back surface side) of the N-type collector region 2 to form a high-concentration drift region 3 c.

[0119] In this modification 2, if Figure 11 As shown, the drift region 4 has a low concentration drift region 3b, a high concentration drift region 3c and a buffer region 3a. The high concentration drift region 3c is located in the lower layer of the low concentration drift region 3b, is connected to the low concentration drift region 3b and has a higher impurity concentration than the low concentration drift region 3b. The buffer region 3a is located in the lower layer of the high concentration drift region 3c, is connected to the high concentration drift region 3c and has a higher impurity concentration than the high concentration drift region 3c.

[0120] At this time, in this variant example 2, the low carbon vacancy density region 20 is set in a part of the high concentration drift region 3c and the low concentration drift region 3b, the high carbon vacancy density region 30 is set in a part of the high concentration drift region 3c and the buffer zone 3a, the equal density line 100 is located in the high concentration drift region 3c, and the end 200 of the depletion layer is also located in the high concentration drift region 3c.

[0121] In an IGBT configured in this manner, the depth-direction distribution of the electric field generated in the drift region 4 between the collector electrode 1 and the emitter electrode 10 when the IGBT is turned off has a steeper slope in the high-concentration drift region 3 c, where the impurity concentration is high. This allows the expansion of the depletion layer to be suppressed even when the power supply voltage is increased. Consequently, even when the power supply voltage is increased, the position of the isodensity line 100 can be positioned greater than the depth of the depletion layer end 200. Therefore, according to this second variation, the trade-off between reduced on-resistance and reduced turn-off loss can be improved over a wider power supply voltage range than that of the embodiment.

[0122] Furthermore, because the impurity concentration of the high-concentration drift region 3c is lower than that of the buffer region 3a, the slope of the electric field within the depletion layer becomes gentler than that of the IGBT in Modification 1 described above. Consequently, the temporal variation in the voltage applied between the collector electrode 1 and the emitter electrode 10 after the depletion layer reaches the high-concentration drift region 3c when the IGBT is turned off can be made gentler than that of the IGBT in Modification 1. Consequently, Modification 2 achieves the advantage of suppressing the generation of noise and the like caused by this temporal variation in voltage.

[0123] <<Structural Modification Example 3>>

[0124] Next, the present modification example 3 will be described.

[0125] Figure 12 3 is a cross-sectional view showing the active unit in the third modification.

[0126] The difference between the IGBT in this modification example 3 and the IGBT in the above embodiment is that the IGBT in this modification example 3 adopts a trench structure in the gate electrode 9. Specifically, in this modification example 3, Figure 12 As shown, the surface is penetrated by n + The trench 15 of the emitter region 6 and the body region 5 is formed. + A gate insulating film 8 is formed so as to form the emitter region 6 and the trench 15 , and a gate electrode 9 is provided so as to cover the gate insulating film 8 .

[0127] Such a device structure can form the body region 5 and n in the manufacturing process of the IGBT in the embodiment. + This is achieved by forming the conductive type emitter region 6 and the body contact region 7 and activating the conductive type impurities implanted by ion implantation, and then forming the trench 15 by, for example, dry etching.

[0128] In the IGBT of this third variation, the cell pitch can be reduced using the trench gate structure, thereby increasing the channel density per unit area and, as a result, reducing the on-resistance of the IGBT. Furthermore, since the crystal planes on the side surfaces of the trenches 15 serve as channels, and since channel mobility is high on the trench side surfaces in silicon carbide, this combined effect with the reduced cell pitch further reduces on-resistance.

[0129] As mentioned above, the invention proposed by the inventors of the present application has been specifically described based on the embodiments. However, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention.

[0130] Description of Reference Numerals

[0131] 1 collector

[0132] 2p + Type collector region

[0133] 3a buffer zone

[0134] 3b low concentration drift zone

[0135] 3c high concentration drift area

[0136] 4Drift Zone

[0137] 5 Main area

[0138] 6n + Type emitter region

[0139] 7 Main body contact area

[0140] 8Gate insulating film

[0141] 9Gate electrode

[0142] 10 emitter electrode

[0143] 11 interlayer insulating film

[0144] 12 substrates

[0145] 15 grooves

[0146] 20 Low carbon hole density area

[0147] 30 High carbon vacancy density area

[0148] 40 border areas

[0149] 50 silicon oxide film

[0150] 100 isopycnal lines

[0151] 200 end

Claims

1. A semiconductor device comprising an insulated gate bipolar transistor, characterized in that: The insulated gate bipolar transistor has a first conductive type drift region, The drift region includes silicon carbide as a constituent material, The drift region has: The first region where the carbon vacancy density is the first density; a second region having a carbon vacancy density that is a second density higher than the first density; and a boundary region sandwiched between the first region and the second region, wherein the carbon vacancy density is higher than that of the first region and lower than that of the second region, The isodensity line included in the boundary region, where the carbon vacancy concentration corresponds to a density half of the second density, is located deeper than an end of a depletion layer extending to the drift region when the insulated gate bipolar transistor is turned off.

2. The semiconductor device according to claim 1, wherein The second density is 1×10 13 / cm 3 above.

3. The semiconductor device according to claim 1, wherein The lifetime of minority carriers in the first region is longer than the lifetime of minority carriers in the second region.

4. The semiconductor device according to claim 1, wherein The voltage applied between the collector and emitter when the insulated gate bipolar transistor is turned off is Vcc, and its unit is V. The thickness of the first region is set to W, and its unit is cm. The impurity concentration of the first region is denoted as Nd, and its unit is 1 / cm 3 , Let the charge of an electron be q, whose unit is C, The dielectric constant of the first region is εs, whose unit is F / cm. At this time, Vcc<{(q·Nd) / (2·εs)}·W 2 The relationship is established.

5. The semiconductor device according to claim 1, wherein The drift region has: Low concentration drift region; and a buffer zone, which is located in the lower layer of the low concentration drift region, is in contact with the low concentration drift region and has a higher impurity concentration than the low concentration drift region; The first region is arranged in the low-concentration drift region, The second region is provided in a portion of the low-concentration drift region and the buffer region, The isopycnal lines are located within the low-concentration drift region. An end portion of the depletion layer is located in the low-concentration drift region. The semiconductor device according to claim 1 , wherein: The drift region has: low concentration drift zone; a buffer zone, which is located in the lower layer of the low concentration drift region, is in contact with the low concentration drift region and has a higher impurity concentration than the low concentration drift region; The first region is provided in a portion of the buffer region and the low-concentration drift region. The second area is set in the buffer zone, The isodensity line is located within the buffer zone, An end portion of the depletion layer is located within the buffer zone.

7. The semiconductor device according to claim 1, wherein The drift region has: low concentration drift zone; a high-concentration drift region, which is located below the low-concentration drift region, is in contact with the low-concentration drift region, and has a higher impurity concentration than that of the low-concentration drift region; and a buffer zone, which is located in the lower layer of the high-concentration drift region, is in contact with the high-concentration drift region and has a higher impurity concentration than the high-concentration drift region; The first region is provided in a portion of the high concentration drift region and the low concentration drift region. The second region is provided in a portion of the high-concentration drift region and the buffer region, The isopycnal lines are located within the high concentration drift region. An end portion of the depletion layer is located in the high-concentration drift region.

8. The semiconductor device according to claim 1, wherein The insulated gate bipolar transistor is a trench gate insulated gate bipolar transistor.

9. A method for manufacturing a semiconductor device comprising an insulated gate bipolar transistor in which an end of a depletion layer extending when off resides within a drift region, The manufacturing method is characterized by comprising the following steps: (a) forming a first conductivity type drift region whose constituent material includes silicon carbide; (b) implanting carbon atoms into the upper surface of the drift region; and (c) diffusing the carbon atoms into the interior of the drift region, After the step (c), The drift region has: The first region where the carbon vacancy density is the first density; a second region having a carbon vacancy density that is a second density higher than the first density; and a boundary region sandwiched between the first region and the second region, wherein the carbon vacancy density is higher than that of the first region and lower than that of the second region, The position of the isodensity line included in the boundary region, where the carbon vacancy concentration corresponds to a density half of the second density, is located deeper than the end of the depletion layer extending in the off state.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: In the step (b), the carbon atoms are ion implanted.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The steps (b) and (c) are performed by thermal oxidation steps.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: The carbon vacancy density of the drift region formed in the step (a) is 1×10 13 / cm 3 above.

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