Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device includes: an oxide insulating layer; an oxide semiconductor layer over the oxide insulating layer; a gate insulating layer over the oxide semiconductor layer; and a gate electrode over the gate insulating layer, the gate electrode containing impurities in a first region in which the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are laminated in this order, and the gate electrode containing impurities in a second region in which the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are laminated in this order without containing the gate electrode. The oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer contain impurities in a third region in which the oxide insulating layer and the gate insulating layer are stacked in this order without including the gate electrode and the oxide semiconductor layer, and the oxide insulating layer and the gate insulating layer contain impurities in the stacking direction of the second region. The concentration profile of the impurity includes a first peak and a second peak.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel and a method for manufacturing the same. Background Art

[0002] In recent years, the development of semiconductor devices that use oxide semiconductor films as channels, instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon, has been progressing (see, for example, Patent Documents 1 to 6). Semiconductor devices including such oxide semiconductor films can be manufactured using simple structures and low-temperature processes, similar to thin-film transistors including amorphous silicon films. Furthermore, semiconductor devices including oxide semiconductor films are known to have higher field-effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Laid-Open No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Laid-Open No. 2021-108405 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] In an oxide semiconductor, carriers are generated when hydrogen is combined with an oxygen defect. Utilizing this mechanism, in a semiconductor device, by forming oxygen defects in an oxide semiconductor layer and supplying hydrogen to the formed oxygen defects, a source region and a drain region as low-resistance regions can be formed. On the other hand, if hydrogen diffuses into the channel region of the oxide semiconductor layer, the function of the channel as a semiconductor device is reduced. Specifically, due to the diffusion of hydrogen into the channel region, the threshold voltage in the electrical characteristics of the semiconductor device changes, so the deviation of the threshold voltage increases and the manufacturing yield of the semiconductor device is reduced. Therefore, by using an oxide layer containing excess oxygen that can capture hydrogen as an insulating layer connected to the oxide semiconductor layer, the intrusion of hydrogen into the channel region is suppressed.

[0013] However, an oxide layer containing excess oxygen functions as an electron trap, significantly reducing the reliability of a semiconductor device including such an oxide layer. Therefore, a semiconductor device that can suppress the reduction in reliability, supply hydrogen to the source and drain regions of the oxide semiconductor layer, and suppress hydrogen intrusion into the channel region of the oxide semiconductor layer is desired.

[0014] One embodiment of the present invention has been made in view of the above-mentioned problems, and one object of the present invention is to provide a semiconductor device including a hydrogen trapping region that prevents hydrogen from invading the channel region.

[0015] Means for solving problems

[0016] A semiconductor device according to one embodiment of the present invention includes: an oxide insulating layer; an oxide semiconductor layer above the oxide insulating layer; a gate insulating layer above the oxide semiconductor layer; and a gate electrode above the gate insulating layer. In a first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in sequence, the gate electrode contains impurities. In a second region where the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in sequence but not including the gate electrode, the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer contain impurities. In a third region where the oxide insulating layer and the gate insulating layer are stacked in sequence but not including the gate electrode and the oxide semiconductor layer, the oxide insulating layer and the gate insulating layer contain impurities. In the second region, a concentration profile of the impurities includes a first peak and a second peak in the stacking direction.

[0017] A semiconductor device according to one embodiment of the present invention includes: an oxide insulating layer; an oxide semiconductor layer above the oxide insulating layer; a gate insulating layer above the oxide semiconductor layer; and a gate electrode above the gate insulating layer. In a first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in sequence, the gate electrode contains impurities. In a second region where the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in sequence but not including the gate electrode, the oxide semiconductor layer and the gate insulating layer contain impurities. In a third region where the oxide insulating layer and the gate insulating layer are stacked in sequence but not including the gate electrode and the oxide semiconductor layer, the oxide insulating layer and the gate insulating layer contain impurities. In the stacking direction of the third region, the impurity concentration profile includes a first peak and a second peak.

[0018] In a method for manufacturing a semiconductor device according to one embodiment of the present invention, an oxide insulating layer is formed, a mask layer having a first pattern is formed over the oxide insulating layer, a first impurity is injected into the oxide insulating layer using the mask layer as a mask, an oxide semiconductor layer having a second pattern is formed over the oxide insulating layer, a gate insulating layer is formed over the oxide insulating layer and over the oxide semiconductor layer to cover the oxide semiconductor layer, a gate electrode having a third pattern is formed over the gate insulating layer, and a second impurity is injected into the oxide semiconductor layer using the gate electrode as a mask.

[0019] In a method for manufacturing a semiconductor device according to one embodiment of the present invention, an oxide insulating layer is formed, an oxide semiconductor layer having a first pattern is formed over the oxide insulating layer, a first impurity is injected into the oxide insulating layer using a resist having the first pattern for forming the oxide semiconductor layer as a mask, a gate insulating layer is formed over the oxide insulating layer and the oxide semiconductor layer to cover the oxide semiconductor layer, a gate electrode having a second pattern is formed over the gate insulating layer, and a second impurity is injected into the oxide semiconductor layer using the gate electrode as a mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] [ Figure 1 ] is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0021] [ Figure 2 ] is a top view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0022] [ Figure 3 ] is a schematic partially enlarged cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0023] [ Figure 4 ] is a graph showing the profile of impurity concentrations in the first to third regions of a semiconductor device according to one embodiment of the present invention.

[0024] [ Figure 5 ] is a graph showing the profile of impurity concentrations in the first to third regions of a semiconductor device according to one embodiment of the present invention.

[0025] [ Figure 6 ] is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] [ Figure 7 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0027] [ Figure 8] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] [ Figure 9 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0029] [ Figure 10 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] [ Figure 11 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0031] [ Figure 12 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] [ Figure 13 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] [ Figure 14 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] [ Figure 15 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0035] [ Figure 16 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0036] [ Figure 17 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0037] [ Figure 18 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0038] [ Figure 19 ] is a schematic cross-sectional view illustrating hydrogen capture regions in the second region and the third region in a semiconductor device according to one embodiment of the present invention.

[0039] [ Figure 20 ] is a schematic cross-sectional view illustrating hydrogen capture regions in the second region and the third region in a semiconductor device according to one embodiment of the present invention.

[0040] [ Figure 21 ] is a schematic partially enlarged cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0041] [ Figure 22 ] is a graph showing the profile of impurity concentrations in the first to third regions of a semiconductor device according to one embodiment of the present invention.

[0042] [ Figure 23 ] is a graph showing the profile of impurity concentrations in the first to third regions of a semiconductor device according to one embodiment of the present invention.

[0043] [ Figure 24 ] is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0044] [ Figure 25 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0045] [ Figure 26 ] is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0046] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual manner. However, the shape shown in the drawings is merely an example and does not limit the interpretation of the present invention. In this specification and the drawings, the same elements as those described with respect to the accompanying drawings are marked with the same figure numerals, and detailed descriptions are sometimes appropriately omitted.

[0047] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the phrases "above" or "below" are used for explanation, but, for example, the up-down relationship between the substrate and the oxide semiconductor layer may be configured in a manner opposite to that shown in the figure. In the following description, for example, expressions such as the oxide semiconductor layer on the substrate are merely used to illustrate the up-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure having multiple layers stacked. In the case of expressing the pixel electrode above the transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of expressing the pixel electrode vertically above the transistor, it means a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0048] In this specification, the term "film" and the term "layer" can be used interchangeably depending on circumstances.

[0049] In this specification, a "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure in which other optical components (such as polarizing components, backlight sources, touch panels, etc.) are assembled relative to the display unit. As long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to display devices including the other electro-optical layers mentioned above.

[0050] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," or "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C. Furthermore, the above expressions do not exclude the case where α includes other elements.

[0051] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0052] <First embodiment>

[0053] Reference Figures 1 to 20 The semiconductor device 10 according to one embodiment of the present invention will be described. The semiconductor device 10 according to the embodiment described below can be used not only as a transistor used in a display device but also as an integrated circuit (IC) such as a microprocessor (MPU) or a memory circuit.

[0054] [1. Configuration of Semiconductor Device 10]

[0055] use Figure 1 and Figure 2 The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 1 It is a cross-sectional view schematically showing a semiconductor device 10 according to one embodiment of the present invention. Figure 2 1 is a top view showing an outline of a semiconductor device 10 according to an embodiment of the present invention. Specifically, Figure 1 It is along Figure 2 A cross-sectional view obtained by cutting along the AA' line.

[0056] like Figure 1 As shown, the semiconductor device 10 is provided on a substrate 100. The semiconductor device 10 includes a light shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not specifically distinguished, they are sometimes collectively referred to as the source / drain electrode 200.

[0057] A light-shielding layer 105 is provided on a substrate 100. A nitride insulating layer 110 and an oxide insulating layer 120 are provided on the substrate 100 and the light-shielding layer 105. The nitride insulating layer 110 covers the upper surface and ends of the light-shielding layer 105. An oxide semiconductor layer 140 is provided on the oxide insulating layer 120. The oxide semiconductor layer 140 is patterned. A portion of the oxide insulating layer 120 extends beyond the ends of the oxide semiconductor layer 140 and outward from the pattern of the oxide semiconductor layer 140.

[0058] In this embodiment, a configuration in which the oxide insulating layer 120 and the oxide semiconductor layer 140 are in contact with each other is described as an example, but the present invention is not limited to this configuration. For example, a metal oxide layer may be provided between the oxide insulating layer 120 and the oxide semiconductor layer 140. For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer. Specifically, aluminum oxide may be used as the metal oxide layer.

[0059] The gate insulating layer 150 covers the upper surface 141 and side surfaces 143 of the oxide semiconductor layer 140 and is provided on the oxide semiconductor layer 140. That is, the upper surface 141 and side surfaces 143 of the oxide semiconductor layer 140 are in contact with the gate insulating layer 150, and the lower surface 142 of the oxide semiconductor layer 140 is in contact with the oxide insulating layer 120. The gate electrode 160 is provided on the gate insulating layer 150 so as to face the oxide semiconductor layer 140.

[0060] The insulating layer 170 is provided over the gate insulating layer 150 and the gate electrode 160. The insulating layer 170 covers the gate electrode 160. The insulating layer 180 is provided over the insulating layer 170. The insulating layers 170 and 180 are provided with openings 171 and 173 that reach the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0061] The light-shielding layer 105 blocks light incident on the oxide semiconductor layer 140 from the substrate 100 side. The nitride insulating layer 110 functions as a barrier film to block impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The light-shielding layer 105 may also function as a bottom gate of the semiconductor device 10. In this case, the nitride insulating layer 110 and the oxide insulating layer 120 function as gate insulating layers for the bottom gate.

[0062] The operation of semiconductor device 10 is primarily controlled by the voltage supplied to gate electrode 160. When light shielding layer 105 functions as a bottom gate, an auxiliary voltage is supplied to light shielding layer 105. However, the same voltage as gate electrode 160 may be supplied to light shielding layer 105. On the other hand, when light shielding layer 105 serves solely as a light shielding film, a specific voltage may not be supplied to light shielding layer 105, and the potential of light shielding layer 105 may be left floating. Alternatively, light shielding layer 105 may be an insulator.

[0063] The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 based on the patterns of the gate electrode 160 and the oxide semiconductor layer 140. The first region A1 is a region that overlaps with the gate electrode 160 when viewed from above. In the first region A1, the oxide insulating layer 120, the oxide semiconductor layer 140, the gate insulating layer 150, and the gate electrode 160 are stacked in this order. The second region A2 is a region that does not overlap with the gate electrode 160 and overlaps with the oxide semiconductor layer 140 when viewed from above. In the second region A2, the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 are stacked in this order. The third region A3 is a region that does not overlap with either the gate electrode 160 or the oxide semiconductor layer 140 when viewed from above. In the third region A3, the oxide insulating layer 120 and the gate insulating layer 150 are stacked in this order.

[0064] The thickness of the gate insulating layer 150 is, for example, not less than 100 nm, but may be not less than 250 nm or not less than 300 nm.

[0065] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the pattern of the gate electrode 160. The source region S and the drain region D are regions belonging to the second region A2. The channel region CH is a region belonging to the first region A1. When viewed from above, the end of the channel region CH coincides with the end of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH has semiconductor properties. Each oxide semiconductor layer 140 in the source region S and the drain region D has conductor properties. That is, the carrier concentration of the oxide semiconductor layer 140 in the source region S and the drain region D is higher than the carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 are respectively in contact with the source region S and the drain region D, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 can have a single-layer structure or a stacked structure.

[0066] In this embodiment, a top-gate transistor configuration in which the gate electrode 160 is provided above the oxide semiconductor layer 140 is used as an example of the semiconductor device 10, but the present invention is not limited to this configuration. For example, as described above, the semiconductor device 10 may also be a dual-gate transistor in which the light shielding layer 105 functions as a gate in addition to the gate electrode 160. Alternatively, the semiconductor device 10 may be a bottom-gate transistor in which the light shielding layer 105 primarily functions as a gate. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0067] exist Figure 2 In the illustrated direction D1, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. The D1 direction connects the source electrode 201 and the drain electrode 203 and represents the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of the region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W. The light shielding layer 105 and the gate electrode 160 extend along the D2 direction.

[0068] exist Figure 2 , a configuration in which the source / drain electrode 200 does not overlap with the light shielding layer 105 and the gate electrode 160 in a plan view is illustrated, but the present invention is not limited to this configuration. For example, the source / drain electrode 200 may overlap with at least one of the light shielding layer 105 and the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0069] [2. Materials of Components of Semiconductor Device 10]

[0070] As the substrate 100, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 100 needs to be flexible, a substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate 100. When a substrate containing resin is used as the substrate 100, impurities can also be introduced into the above-mentioned resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emitting display, the substrate 100 does not need to be transparent, so impurities that deteriorate the transparency of the substrate 100 can also be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, a non-light-transmitting substrate such as a silicon substrate, a silicon carbide substrate, or a semiconductor substrate such as a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate can be used as the substrate 100.

[0071] As the light shielding layer 105, the gate electrode 160 and the source / drain electrode 200, a common metal material is used. For example, as these components, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), or alloys or compounds thereof can be used. As the light shielding layer 105, the gate electrode 160 and the source / drain electrode 200, the above-mentioned materials can be used in a single layer form or in a stacked form. As the light shielding layer 105, when conductivity is not required, materials other than the above-mentioned metal materials can also be used. For example, as the light shielding layer 105, a black matrix such as black resin can be used. The light shielding layer 105 can be a single-layer structure or a stacked structure. For example, the light shielding layer 105 can also be a stacked structure of a red color filter, a green color filter and a blue color filter.

[0072] As the nitride insulating layer 110, the oxide insulating layer 120, and the insulating layers 170 and 180, a common insulating material can be used. For example, as the oxide insulating layer 120 and the insulating layer 180, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y ) or the like. As the nitride insulating layer 110 and the insulating layer 170, silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ), aluminum nitride (AlN x O yHowever, as the insulating layer 170, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y ) or the like. As the insulating layer 180, silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ) or aluminum oxide nitride (AlN x O y ) and other inorganic insulating layers.

[0073] As the gate insulating layer 150, an insulating layer containing oxygen among the above insulating layers can be used. For example, as the gate insulating layer 150, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y ) and other inorganic insulating layers.

[0074] As the oxide insulating layer 120, an insulating layer capable of releasing oxygen by heat treatment can be used. That is, an oxide insulating layer containing an excess of oxygen can be used as the oxide insulating layer 120. The temperature of the heat treatment for releasing oxygen from the oxide insulating layer 120 is, for example, 600°C or less, 500°C or less, 450°C or less, or 400°C or less. That is, the oxide insulating layer 120 releases oxygen at the heat treatment temperature performed during the manufacturing process of the semiconductor device 10, for example, when a glass substrate is used as the substrate 100. As with the oxide insulating layer 120, an insulating layer capable of releasing oxygen by heat treatment can be used for at least one of the insulating layers 170 and 180.

[0075] As the gate insulating layer 150, an insulating layer with few defects can be used. For example, when the composition ratio of oxygen in the gate insulating layer 150 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "another insulating layer"), the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, silicon oxide (SiO x), the oxygen composition ratio of the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of the silicon oxide used as the insulating layer 180. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating layer 150.

[0076] The above-mentioned SiO x N y and AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio smaller than that of nitrogen (x>y).

[0077] As the oxide semiconductor layer 140, a metal oxide having semiconductor properties can be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) can be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a composition different from the above can also be used. For example, in order to improve mobility, an oxide semiconductor layer with an In ratio greater than the above can also be used. On the other hand, in order to increase the band gap and reduce the influence of light irradiation, an oxide semiconductor layer with a Ga ratio greater than the above can also be used.

[0078] For example, an oxide semiconductor containing two or more metals including indium (In) may be used as the oxide semiconductor layer 140 having a higher In ratio than described above. In this case, the ratio of indium to all metal elements in the oxide semiconductor layer 140 may be 50% or more in atomic ratio. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanide elements may be used as the oxide semiconductor layer 140. Metal elements other than those described above may also be used as the oxide semiconductor layer 140.

[0079] As the oxide semiconductor layer 140, other elements, such as metal elements such as Al and Sn, may be added to the oxide semiconductor containing In, Ga, Zn, and O. In addition to the above-mentioned oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), and an oxide semiconductor containing In and W may also be used as the oxide semiconductor layer 140.

[0080] When the indium ratio is high, the oxide semiconductor layer 140 easily crystallizes. By using a material containing 50% or more indium relative to all metal elements in the oxide semiconductor layer 140 as described above, a polycrystalline oxide semiconductor layer 140 can be obtained. Gallium is preferably included as a metal element other than indium. Gallium and indium both belong to Group 13. Therefore, gallium does not impair the crystallinity of the oxide semiconductor layer 140, resulting in a polycrystalline structure.

[0081] The detailed manufacturing method of the oxide semiconductor layer 140 will be described later. The oxide semiconductor layer 140 can be formed using a sputtering method. The composition of the oxide semiconductor layer 140 formed by the sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target is substantially consistent with the composition of the oxide semiconductor layer 140. In this case, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the composition of the metal elements of the sputtering target.

[0082] In the case where the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer can also be determined using an X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method. In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. However, the oxygen contained in the oxide semiconductor layer 140 varies depending on the sputtering process conditions, etc., and is therefore not limited thereto.

[0083] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. Polycrystalline oxide semiconductors can be produced using Poly-OS (Poly-crystalline Oxide Semiconductor) technology. Hereinafter, to distinguish between oxide semiconductors with an amorphous structure and those with an amorphous structure, polycrystalline oxide semiconductors may be referred to as Poly-OS.

[0084] As described above, when a metal oxide layer is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, a metal oxide containing aluminum as a main component can be used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ) or aluminum nitride (AlN x ) or other inorganic insulating layers. The term "metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the total metal oxide layer. The ratio of aluminum contained in the metal oxide layer may also be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide layer. The above ratios may be by mass or by weight.

[0085] [3. Composition of the Hydrogen Capture Region]

[0086] The hydrogen capture region is formed in the oxide insulating layer 120 and the gate insulating layer 150. Therefore, referring to Figures 3 to 5 The structure of the hydrogen trapping region formed in the oxide insulating layer 120 and the gate insulating layer 150 will be described.

[0087] Figure 3 1 is a schematic partially enlarged cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention. Specifically, Figure 3 It will Figure 1 An enlarged cross-sectional view of area P in FIG. Figure 3 The region P shown is a region near the drain region D, but the region near the source region S also has the same structure as that of the region P.

[0088] The source region S and the drain region D of the oxide semiconductor layer 140 are formed by ion implantation of impurities using the gate electrode 160 as a mask, and the details will be described later. As impurities, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) can be used. By ion implantation of impurities, oxygen vacancies are generated in the source region S and the drain region D. By combining hydrogen with the generated oxygen vacancies, the resistance of the source region S and the drain region D is reduced. Silicon nitride contains more hydrogen than silicon oxide, so, for example, by using silicon nitride as the insulating layer 170, hydrogen can be diffused from the insulating layer 170 to reduce the resistance of the source region S and the drain region D.

[0089] The impurity ion implantation uses the gate electrode 160 as a mask, but the impurity ion implantation into the oxide semiconductor layer 140 is performed via the gate insulating layer 150. Therefore, the impurity is also implanted into the gate insulating layer 150 in the second and third regions A2 and A3, thereby forming dangling bond defects DB in the gate insulating layer 150. Furthermore, in the second and third regions A2 and A3, the impurity can also pass through the oxide semiconductor layer 140 and the gate insulating layer 150 and be implanted into the oxide insulating layer 120. It should be noted that in this embodiment, in order to form dangling bond defects DB in the oxide insulating layer 120 in the second and third regions A2 and A3, the impurity ion implantation into the oxide insulating layer 120 is performed separately from the above-described impurity ion implantation.

[0090] As a result, if Figure 3 As shown, in the second region A2 and the third region A3, dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150. When silicon oxide is used for the oxide insulating layer 120 and the gate insulating layer 150, dangling bond defects DB of silicon are formed in the oxide insulating layer 120 and the gate insulating layer 150.

[0091] The dangling bond defects DB formed in the oxide insulating layer 120 and the gate insulating layer 150 capture hydrogen. That is, hydrogen capture regions are formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3. Therefore, for example, when the insulating layer 170 is formed, hydrogen diffused from the insulating layer 170 is captured by the hydrogen capture regions of the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3, thereby suppressing the intrusion of hydrogen into the channel region CH. It should be noted that since hydrogen is captured in the hydrogen capture regions, after the insulating layer 170 is formed, the hydrogen concentration of the gate insulating layer 150 in the second region A2 and the third region A3 is greater than the hydrogen concentration of the gate insulating layer 150 in the first region A1. Similarly, the hydrogen concentration of the oxide insulating layer 120 in the second region A2 and the third region A3 is greater than the hydrogen concentration of the oxide insulating layer 120 in the first region A1.

[0092] As described above, since the dangling bond defects DB in the hydrogen capture region are formed by ion implantation, the oxide insulating layer 120 and the gate insulating layer 150 contain impurities introduced by the ion implantation. The distribution of the amount of dangling bond defects DB formed in the oxide insulating layer 120 and the gate insulating layer 150 corresponds to the concentration profile of the impurities contained therein. In other words, by adjusting the concentration profile of the impurities introduced by ion implantation, the location and amount of the dangling bond defects DB can be adjusted.

[0093] In order to suppress abnormalities in the electrical characteristics of the semiconductor device 10 caused by hydrogen intrusion into the channel region CH, it is effective to form dangling bond defects DB in the oxide insulating layer 120 in the second region A2 and the third region A3. Therefore, in this embodiment, impurity ions are implanted into the oxide insulating layer 120 without passing through the gate insulating layer 150. As a result, hydrogen trapping regions can be formed in the oxide insulating layer 120 in the second region A2 and the third region A3, independent of the thickness of the gate insulating layer 150. In addition, the thickness of the gate insulating layer 150 can be increased, thereby improving the high voltage resistance of the gate insulating layer 150. For example, the thickness of the gate insulating layer 150 is 200 nm or greater.

[0094] Figure 4 and Figure 5 These are graphs respectively showing the concentration profiles of impurities in the first region A1 to the third region A3 in the semiconductor device according to one embodiment of the present invention. Figure 4 and Figure 5 The vertical axis of each of the three concentration profiles shown represents the concentration of impurities per unit volume (Concentration [ / cm 3 ]), where the horizontal axis represents the names of the layers in the stacking direction (thickness direction). "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the gate insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0095] like Figure 4As shown, in the first region A1, the impurity concentration profile has a peak in the gate electrode 160 (GL). That is, the first region A1 contains a single peak. Metal materials have a high barrier capability against impurities introduced by ion implantation. When a metal material is used as the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the gate insulating layer 150 (GI). Therefore, the gate insulating layer 150 in the first region A1 does not form dangling bond defects DB associated with the introduction of impurities. However, impurities may reach the gate insulating layer 150 as long as they do not affect the electrical characteristics of the semiconductor device 10.

[0096] In the second region A2, the concentration profile of the impurities has peaks in the oxide insulating layer 120 (UC) and the oxide semiconductor layer 140 (OS). That is, the second region A2 contains two peaks. In the stacking direction in the second region A2, the concentration of the impurities at the peak position of the oxide insulating layer 120 and the concentration of the impurities at the peak position of the oxide semiconductor layer 140 are greater than the concentration of the impurities contained in the gate insulating layer 150. The purpose of introducing the impurities in the second region A2 is to form the source region S and the drain region D, so it is preferable to set the conditions for ion implantation in a manner to form the above-mentioned concentration profile, but it is not limited thereto. The concentration profile of the impurities in the second region A2 may also have peaks in the oxide insulating layer 120 (UC) and the gate insulating layer 150 (GI) (refer to Figure 5 In this case, in the stacking direction in the second region A2, the impurity concentration at the peak position of the oxide insulating layer 120 and the impurity concentration at the peak position of the gate insulating layer 150 may be higher than the impurity concentration included in the oxide semiconductor layer 140.

[0097] In the third region A3, the impurity concentration profile has a peak in the oxide insulating layer 120 (UC). That is, the third region A3 contains a peak. In the stacking direction in the third region A3, the concentration of impurities at the peak position of the oxide insulating layer 120 is sometimes higher than the concentration of impurities contained in the gate insulating layer 150. The impurity concentration profile of the gate insulating layer 150 in the third region A3 is substantially the same as the impurity concentration profile of the gate insulating layer 150 in the second region A2. Therefore, in Figure 5 The impurity concentration profile in the third region A3 shown may have peaks in the oxide insulating layer 120 (UC) and the gate insulating layer 150 (GI). In this case, the third region A3 includes two peaks.

[0098] In this embodiment, at least two impurity ion implantations are performed, as will be described in detail later. In the first impurity ion implantation, impurities are introduced into the oxide insulating layer 120 in the second and third regions A2 and A3. On the other hand, in the second impurity ion implantation, impurities are introduced into the oxide insulating layer 120 in the second and third regions A2 and A3 via the gate insulating layer 150. Therefore, the impurity concentration in the oxide insulating layer 120 in the first, second, and third regions A1, A2, and A3 may increase in the order of the first, second, and third regions.

[0099] In this embodiment, the concentration of impurities contained in a predetermined position in the oxide insulating layer 120 in the stacking direction in the third region A3 is 1×10 16 / cm 3 Above, 1×10 17 / cm 3 Above or 1×10 18 / cm 3 The predetermined position may be the peak position of the concentration profile or the position corresponding to the interface between the oxide insulating layer 120 and the gate insulating layer 150. Alternatively, the predetermined position may be a position shifted by a predetermined depth toward the oxide insulating layer 120 from the position corresponding to the interface.

[0100] Reference Figure 2 The channel region CH belongs to the first region A1, the source region S and the drain region D belong to the second region A2, and the region other than the channel region CH, the source region S, and the drain region D belongs to the third region A3. That is, the channel region CH is sandwiched between the second region A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by the hydrogen trapping regions formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3 surrounding the channel region CH. As a result, the hydrogen can be suppressed from entering the channel region CH.

[0101] [4. Method for Manufacturing Semiconductor Device 10]

[0102] Reference Figures 6 to 15 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 6 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 7 to 15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0103] like Figure 6 and Figure 7As shown, a light shielding layer 105 is formed on the substrate 100, and a nitride insulating layer 110 and an oxide insulating layer 120 are formed on the light shielding layer 105 ( Figure 6 (See "Insulating layer / light shielding layer formation" in step S1010 of FIG. 1 ). For example, silicon nitride is formed as the nitride insulating layer 110. For example, silicon oxide is formed as the oxide insulating layer 120. The nitride insulating layer 110 and the oxide insulating layer 120 are formed by CVD (Chemical Vapor Deposition). For example, the thickness of the nitride insulating layer 110 is between 50 nm and 500 nm, or between 150 nm and 300 nm. The thickness of the oxide insulating layer 120 is between 50 nm and 500 nm, or between 150 nm and 300 nm.

[0104] By using silicon nitride as the nitride insulating layer 110, the nitride insulating layer 110 can block impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. For example, silicon oxide used as the oxide insulating layer 120 releases oxygen by heat treatment.

[0105] like Figure 6 and Figure 8 As shown, an oxide semiconductor layer 140 ( Figure 6 The oxide semiconductor layer 140 is formed by sputtering or atomic layer deposition (ALD).

[0106] When a metal oxide layer containing aluminum as a main component is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140 , the metal oxide layer is also formed by sputtering or atomic layer deposition in the same manner as described above.

[0107] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, the thickness of the oxide semiconductor layer 140 is 30 nm. The oxide semiconductor layer 140 is amorphous before the heat treatment (OS annealing) described later.

[0108] When the oxide semiconductor layer 140 is crystallized by the OS annealing described later, it is preferable that the oxide semiconductor layer 140 be amorphous (having a low crystalline oxide semiconductor component) after film formation and before the OS annealing. In other words, the film formation conditions of the oxide semiconductor layer 140 are preferably such that crystallization of the oxide semiconductor layer 140 is minimized immediately after film formation. For example, when the oxide semiconductor layer 140 is formed by sputtering, the oxide semiconductor layer 140 is formed while controlling the temperature of the object to be formed (the substrate 100 and the structures formed thereon).

[0109] When a film is formed on an object to be formed by sputtering, the ions generated in the plasma and the atoms ejected by the sputtering target collide with the object to be formed, so the temperature of the object to be formed rises as the film is formed. If the temperature of the object to be formed rises during the film formation process, the oxide semiconductor layer 140 will contain microcrystals in the state just after the film is formed, which sometimes hinders the subsequent crystallization based on OS annealing. In order to control the temperature of the object to be formed as described above, for example, the film can be formed while the object to be formed is cooled. For example, the object to be formed can be cooled from the surface opposite to the film-forming surface in such a manner that the temperature of the film-forming surface of the object to be formed (hereinafter referred to as the "film-forming temperature") is below 100°C, below 70°C, below 50°C, or below 30°C. As described above, by forming the oxide semiconductor layer 140 while cooling the object to be formed, it is possible to form an oxide semiconductor layer 140 with a small crystalline component in the state just after the film is formed. The oxygen partial pressure in the film formation conditions of the oxide semiconductor layer 140 is 2% to 20%, 3% to 15%, or 3% to 10%.

[0110] like Figure 6 and Figure 9 As shown, the pattern of the oxide semiconductor layer 140 is formed ( Figure 6 (See "OS pattern formation" in step S1030 of FIG. 2 ). Although not shown, a resist mask is formed over the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 can be etched by wet etching or dry etching. Wet etching can be performed using an acidic etchant. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used as the etchant. Since the oxide semiconductor layer 140 in step S1020 is amorphous, the oxide semiconductor layer 140 can be easily patterned into a predetermined shape by wet etching.

[0111] After the patterning of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Figure 6(See "OS annealing" in step S1040.) During the OS annealing, the oxide semiconductor layer 140 is maintained at a predetermined target temperature for a predetermined time. The predetermined target temperature is between 300°C and 500°C, or between 350°C and 450°C. The holding time at the target temperature is between 15 minutes and 120 minutes, or between 30 minutes and 60 minutes. In this embodiment, the oxide semiconductor layer 140 is crystallized by the OS annealing. However, crystallization of the oxide semiconductor layer 140 is not necessarily required by the OS annealing.

[0112] like Figure 6 and Figure 10 As shown, a mask layer 300 ( Figure 6 (See "Formation of Mask Layer" in step S1050 ). The mask layer 300 may be formed using a resist or a metal. The mask layer 300 is patterned through a photolithography process. The predetermined pattern of the mask layer 300 may be substantially identical to or different from the pattern of the gate electrode 160. If the predetermined pattern of the mask layer 300 is different from the pattern of the gate electrode 160, the mask layer 300 is formed so that the width of the mask layer 300 is substantially identical to the width of the gate electrode 160 when viewed in cross-section.

[0113] like Figure 6 and Figure 11 As shown, the mask layer 300 is used as a mask to perform ion implantation of impurities into the oxide insulating layer 120 ( Figure 6 (The "first ion implantation" of step S1060 is shown in FIG. ) Impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) can be used. Thus, impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are introduced into the oxide insulating layer 120. The impurities introduced into the oxide insulating layer 120 form dangling bond defects DB. The regions in the oxide insulating layer 120 where dangling bond defects DB are formed can function as hydrogen trapping regions.

[0114] In the first ion implantation of step S1060, it is important to form dangling bond defects DB in the oxide insulating layer 120, while not forming dangling bond defects DB in the nitride insulating layer 110. Therefore, in the first ion implantation, the ion implantation of impurities is performed in a manner such that a concentration profile has a peak in the oxide insulating layer 120. The position of the peak and the amount of impurities can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, a dose of 1×10 14 / cm 2 Above, 5×10 14 / cm 2 , or 1×10 15 / cm2 For example, the acceleration voltage is greater than 10 keV, 15 keV or greater, or 20 keV or greater.

[0115] Note that, in step S1060, impurities are also introduced into the oxide semiconductor layer 140. Therefore, oxygen vacancies are formed in the oxide semiconductor layer 140, forming the source region S and the drain region D. However, sufficient oxygen vacancies may not be formed in the oxide semiconductor layer 140 in step S1060.

[0116] like Figure 6 and Figure 12 As shown, the gate insulating layer 150 ( Figure 6 ("GI formation" of step S1070). As the gate insulating layer 150, for example, silicon oxide is formed. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 150, the gate insulating layer 150 can also be formed at a film forming temperature of 350°C or above. The thickness of the gate insulating layer 150 is, for example, not less than 100 nm and not more than 500 nm, not less than 200 nm and not more than 400 nm, or not less than 250 nm and not more than 350 nm. After the gate insulating layer 150 is formed, the upper part of the gate insulating layer 150 can also be subjected to a treatment of implanting oxygen. As a treatment of implanting oxygen, a metal oxide layer can be formed on the gate insulating layer 150 by a sputtering method.

[0117] In a state where the gate insulating layer 150 is formed on the oxide semiconductor layer 140, heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed ( Figure 6 (The "oxidation annealing" of step S1080 is omitted.) During the process from forming the oxide semiconductor layer 140 to forming the gate insulating layer 150 on the oxide semiconductor layer 140, a large number of oxygen vacancies are generated on the upper surface 141 and side surfaces 143 of the oxide semiconductor layer 140. Through the oxidation annealing described above, oxygen released from the oxide insulating layer 120 and the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, thereby repairing the oxygen vacancies. In the absence of oxygen implantation into the gate insulating layer 150, the oxidation annealing may be performed with an insulating layer formed on the gate insulating layer 150 that releases oxygen through heat treatment.

[0118] To increase the amount of oxygen supplied from the gate insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer primarily composed of aluminum may be formed on the gate insulating layer 150 by sputtering, and oxidation annealing may be performed in this state. By using aluminum oxide, which has high gas barrier properties, as the metal oxide layer, it is possible to suppress the outward diffusion of oxygen injected into the gate insulating layer 150 during the oxidation annealing. Through the formation of the metal oxide layer and the oxidation annealing described above, the oxygen injected into the gate insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140.

[0119] like Figure 6 and Figure 13 As shown, the gate electrode 160 is formed and patterned ( Figure 6 ("GE formation" in step S1090) The gate electrode 160 is formed by sputtering or atomic layer deposition. The gate electrode 160 is patterned by a photolithography process.

[0120] like Figure 6 and Figure 14 As shown, the gate electrode 160 is used as a mask to perform ion implantation of impurities into the oxide semiconductor layer 140 ( Figure 6 The second ion implantation in step S1100 is performed. For example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used as the impurity. The impurity implanted in the second ion implantation in step S1090 may be the same as or different from the impurity implanted in the first ion implantation in step S1060. Thus, boron (B), phosphorus (P), argon (Ar), nitrogen (N), or the like is introduced into the oxide semiconductor layer 140.

[0121] In the second ion implantation in step S1100, the gate electrode 160 is used as a mask. Consequently, impurities are introduced into the region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160, forming oxygen vacancies. Hydrogen is bonded to the generated oxygen vacancies, thereby reducing the resistance of the oxide semiconductor layer 140. In other words, a source region S and a drain region D are formed in the oxide semiconductor layer 140. On the other hand, no impurities are introduced into the region of the oxide semiconductor layer 140 that overlaps with the gate electrode 160, and no oxygen vacancies are formed. In other words, a channel region CH is formed in the oxide semiconductor layer 140. It should be noted that impurities are introduced into the gate electrode 160 used as a mask.

[0122] Furthermore, during the second ion implantation in step S1100, impurities are also introduced into the gate insulating layer 150 and the oxide insulating layer 120. The impurities introduced into the gate insulating layer 150 and the oxide insulating layer 120 form dangling bond defects DB. The regions in the gate insulating layer 150 and the oxide insulating layer 120 where the dangling bond defects DB are formed can function as hydrogen trapping regions.

[0123] By performing the first ion implantation in step S1060 and the second ion implantation in step S1100, a first region A1, a second region A2, and a third region A3 are formed. In the first region A1, the gate electrode 160 contains impurities. In the second region A2, the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 contain impurities. The oxide semiconductor layer 140 in the second region A2 functions as a source region or a drain region. In addition, the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 function as a hydrogen trapping region. In the third region A3, the oxide insulating layer 120 and the gate insulating layer 150 contain impurities. The oxide insulating layer 120 and the gate insulating layer 150 in the third region A3 function as a hydrogen trapping region.

[0124] In the second ion implantation of step S1100, the impurity ion implantation is performed in such a manner that a concentration profile has a peak in one of the oxide semiconductor layer 140 and the gate insulating layer 150 in the second region A2. The position of the peak and the amount of the impurity can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, a dose of 1×10 14 / cm 2 Above, 5×10 14 / cm 2 , or 1×10 15 / cm 2 For example, the acceleration voltage is greater than 10 keV, 15 keV or greater, or 20 keV or greater.

[0125] Hydrogen is introduced into the oxygen vacancies in the source region S and the drain region D to reduce the resistance. However, if hydrogen invades the channel region CH, the channel region CH will also reduce the resistance, a hump will appear or depletion will occur, and the electrical characteristics of the semiconductor device will deteriorate. Therefore, it is necessary to form a hydrogen capture region that suppresses the invasion of hydrogen into the channel region CH. In particular, in the film formation of the insulating layer 170 described later, it is important to form a hydrogen capture region not only in the gate insulating layer 150 but also in the oxide insulating layer 120. In this embodiment, before forming the gate insulating layer 150, in step S1060, a first ion implantation is performed to form a hydrogen capture region in the oxide insulating layer 120. Therefore, even when the film thickness of the gate insulating layer 150 is large (for example, when the film thickness of the gate insulating layer 150 is greater than 200 nm), sufficient impurities can be ion implanted into the oxide insulating layer 120 to form dangling bond defects DB, thereby forming a hydrogen capture region.

[0126] like Figure 6 and Figure 15As shown, insulating layers 170 and 180 are formed on the gate insulating layer 150 and the gate electrode 160 as interlayer films ( Figure 6 (See "Interlayer Film Formation" in step S1110 of FIG. ) Insulating layers 170 and 180 are formed by CVD. For example, a silicon nitride layer is formed as insulating layer 170, and a silicon oxide layer is formed as insulating layer 180. However, the materials used for insulating layers 170 and 180 are not limited to the above. The thickness of insulating layer 170 is between 50 nm and 500 nm. The thickness of insulating layer 180 is between 50 nm and 500 nm.

[0127] like Figure 6 and Figure 16 As shown, openings 171 and 173 are formed in the insulating layers 170 and 180 ( Figure 6 The source region S is exposed through the opening 171. The drain region D is exposed through the opening 173. Source and drain electrodes 200 are formed on the source region S and drain region D exposed through the openings 171 and 173 and on the insulating layer 180. Figure 6 Step S1130 "SD formation"), thereby completing Figure 1 The semiconductor device 10 is shown.

[0128] Figure 1 The manufacturing method of the semiconductor device 10 shown is not limited to the above method. For example, step S1050 and step S1060 may be performed after step S1010. In this case, a mask layer 300 having a predetermined pattern is formed on the oxide insulating layer 120 (see Figure 17 ). In addition, impurity ions are implanted into the oxide insulating layer 120 using the mask layer 300 as a mask (see Figure 18 ). Afterwards, steps S1020 to S1040 and steps S1070 to S1130 are performed in sequence.

[0129] [5. Hydrogen Traps in Dangling Bond Defect DBs]

[0130] Figure 19 and Figure 20 Each of the diagrams is a schematic cross-sectional view illustrating a hydrogen trapping region in the second region and the third region in the semiconductor device according to an embodiment of the present invention.

[0131] like Figure 19 As shown, impurities are introduced into the oxide insulating layer 120 and the gate insulating layer 150 in the second area A2 and the third area A3 through the first ion implantation in step S1060 and the second ion implantation in step S1100, thereby forming dangling bond defects DB in the oxide insulating layer 120 and the gate insulating layer 150 in the second area A2 and the third area A3.

[0132] exist Figure 20 , the insulating layer 170 is formed. In order for the insulating layer 170 to have the function of blocking impurities diffused from above, the insulating layer 170 is preferably a dense film with few defects. In order to obtain such an insulating layer 170, the insulating layer 170 needs to be formed at a high temperature. For example, when a silicon nitride layer is formed as the insulating layer 170, a large amount of hydrogen is contained in the insulating layer 170. Due to the film formation temperature, a large amount of hydrogen diffuses from the insulating layer 170 to the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150. Therefore, if a hydrogen capture region is not formed in the oxide insulating layer 120 and the gate insulating layer 150, hydrogen diffuses not only into the source region S and the drain region D via the oxide insulating layer 120 and the gate insulating layer 150, but also into the channel region CH.

[0133] On the other hand, Figure 20 As shown, when dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150, hydrogen H diffused from the insulating layer 170 during the formation of the insulating layer 170 is captured by the above-mentioned dangling bond defects DB (indicated by overlapping "○" on "×"). That is, the region including the dangling bond defects DB in the oxide insulating layer 120 and the gate insulating layer 150 functions as a hydrogen capture region. Therefore, in step S1110, hydrogen H diffused from the insulating layer 170 during or after film formation can be suppressed from invading the channel region CH. Therefore, since a film containing a large amount of hydrogen can be used as the insulating layer 170, an insulating layer 170 with a high impurity barrier function can be realized. In addition, the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D can be sufficiently low.

[0134] In the case of this embodiment, based on the distribution of dangling bond defects DB formed in the oxide insulating layer 120, the amount of captured hydrogen H sometimes increases in the order of the oxide insulating layer 120 in the first area A1, the oxide insulating layer 120 in the second area A2, and the oxide insulating layer 120 in the third area A3.

[0135] In this embodiment, hydrogen trapping regions including a large number of dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3 surrounding the channel region CH. This suppresses hydrogen intrusion into the channel region CH. As a result, a semiconductor device 10 having electrical characteristics with suppressed hump can be obtained.

[0136] <Second embodiment>

[0137] Reference Figures 21 to 26A semiconductor device 20 according to an embodiment of the present invention will be described. In the following, when the configuration of the semiconductor device 20 is the same as that of the semiconductor device 10 , the description of the semiconductor device 20 may be omitted.

[0138] [1. Configuration of Semiconductor Device 20 and Materials of Each Component]

[0139] The semiconductor device 20 is schematically shown in FIG. Figure 1 and Figure 2 The semiconductor device 10 shown is similar in outline to the semiconductor device 10 , and therefore its description is omitted. Furthermore, the materials of the components of the semiconductor device 20 are also similar to those of the semiconductor device 10 , and therefore its description is omitted.

[0140] [2. Composition of the Hydrogen Capture Region]

[0141] The hydrogen trapping region is formed in the oxide insulating layer 120 and the gate insulating layer 150. Therefore, referring to Figures 21 to 23 The structure of the hydrogen trapping region formed in the oxide insulating layer 120 and the gate insulating layer 150 will be described.

[0142] Figure 21 1 is a schematic partially enlarged cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention. Specifically, Figure 21 It will Figure 1 An enlarged cross-sectional view of area P in FIG. Figure 21 The region P shown is a region near the drain region D, and the region near the source region S has the same structure as that of the region P.

[0143] The impurity ion implantation for forming the source region S and the drain region D uses the gate electrode 160 as a mask, and the impurity ion implantation is performed into the oxide semiconductor layer 140 via the gate insulating layer 150. Therefore, impurities are also implanted into the gate insulating layer 150 in the second region A2 and the third region A3, thereby forming dangling bond defects DB in the gate insulating layer 150. Furthermore, in the second region A2 and the third region A3, impurities may sometimes pass through the oxide semiconductor layer 140 and the gate insulating layer 150 and be implanted into the oxide insulating layer 120. It should be noted that in this embodiment, in order to form dangling bond defects DB in the oxide insulating layer 120 in the third region A3, impurity ion implantation is performed into the oxide insulating layer 120 separately from the above-described impurity ion implantation.

[0144] As a result, if Figure 21As shown, in the second region A2, dangling bond defects DB are formed in the gate insulating layer 150, and in the third region A3, dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150. When silicon oxide is used as the oxide insulating layer 120 and the gate insulating layer 150, respectively, dangling bond defects DB of silicon are formed in the oxide insulating layer 120 and the gate insulating layer 150.

[0145] Figure 22 and Figure 23 These are graphs respectively showing the concentration profiles of impurities in the first region A1 to the third region A3 in the semiconductor device according to one embodiment of the present invention. Figure 22 and Figure 23 The vertical axis of each of the three concentration profiles shown represents the concentration of impurities per unit volume (concentration [ / cm 3 ]), where the horizontal axis represents the names of the layers in the stacking direction (thickness direction). "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the gate insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0146] like Figure 22 As shown, in the first region A1, the impurity concentration profile has a peak in the gate electrode 160 (GL). That is, the first region A1 contains a single peak. Metal materials have a high barrier capability against impurities introduced by ion implantation. When a metal material is used as the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the gate insulating layer 150 (GI). Therefore, the gate insulating layer 150 in the first region A1 does not form dangling bond defects DB associated with the introduction of impurities. However, impurities may reach the gate insulating layer 150 as long as they do not affect the electrical characteristics of the semiconductor device 10.

[0147] In the second region A2, the concentration profile of the impurity has a peak in the oxide semiconductor layer 140 (OS). That is, the second region A2 contains a peak. In the stacking direction of the second region A2, the concentration of the impurity at the peak position of the oxide semiconductor layer 140 is greater than the concentration of the impurity contained in the gate insulating layer 150. Since the purpose of introducing the impurities in the second region A2 is to form the source region S and the drain region D, it is preferable to set the conditions for ion implantation in such a manner as to form the concentration profile as described above, but it is not limited thereto. The concentration profile of the impurity in the second region A2 may also have a peak in the gate insulating layer 150 (GI) (see Figure 23 In this case, the concentration of the impurity at the peak position of the gate insulating layer 150 is higher than the concentration of the impurity included in the oxide semiconductor layer 140 in the stacking direction of the second region A2.

[0148] In the third region A3, the concentration profile of the impurities has a peak in the oxide insulating layer 120 (UC). That is, the third region A3 contains a peak. In the stacking direction of the third region A3, the concentration of the impurities at the peak position of the oxide insulating layer 120 is greater than the concentration of the impurities contained in the gate insulating layer 150. The concentration profile of the impurities of the gate insulating layer 150 in the third region A3 is substantially the same as the concentration profile of the impurities of the gate insulating layer 150 in the second region A2. Therefore, in Figure 23 The impurity concentration profile of the third region A3 shown may have peaks in the oxide insulating layer 120 (UC) and the gate insulating layer 150 (GI). In this case, the third region A3 includes two peaks.

[0149] In this embodiment, at least two impurity ion implantations are performed, and the details will be described later. In the first impurity ion implantation, impurities are introduced into the oxide insulating layer 120 in the third region A3. On the other hand, in the second impurity ion implantation, impurities are introduced into the oxide insulating layer 120 in the second region A2 and the third region A3 via the gate insulating layer 150. It should be noted that, in the second impurity ion implantation, impurities are sometimes introduced into the oxide insulating layer 120. Therefore, in the oxide insulating layer 120 of the first region A1, the second region A2, and the third region A3, the concentration of impurities sometimes increases in the order of the first region A1, the second region A2, and the third region A3. It should be noted that, when impurities are introduced into the oxide insulating layer 120 in the second region A2, the concentration of impurities in the oxide insulating layer 120 in the second region A2 is less than 1×10 16 / cm 3 .

[0150] In this embodiment, the concentration of impurities contained in a predetermined position in the oxide insulating layer 120 in the stacking direction of the third region A3 is 1×10 16 / cm 3 Above, 1×10 17 / cm 3 Above, or 1×10 18 / cm 3 The predetermined position may be the peak position of the concentration profile or the position corresponding to the interface between the oxide insulating layer 120 and the gate insulating layer 150. Alternatively, the predetermined position may be a position shifted by a predetermined depth toward the oxide insulating layer 120 from the position corresponding to the interface.

[0151] Reference Figure 2The channel region CH belongs to the first region A1, the source region S and the drain region D belong to the second region A2, and the area other than the channel region CH, source region S, and drain region D belongs to the third region A3. In other words, the channel region CH is sandwiched between the second region A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by the hydrogen trapping regions formed in the gate insulating layer 150 in the second and third regions A2 and A3, and in the oxide insulating layer 120 in the third region A3, surrounding the channel region CH. As a result, the hydrogen can be prevented from entering the channel region CH.

[0152] [3. Method for Manufacturing Semiconductor Device 10]

[0153] Reference Figures 24 to 26 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 24 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 25 and Figure 26 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0154] Figure 24 Steps S2010 to S2030 shown in FIG. Figure 5 The steps S1010 to S1030 shown in FIG. 2 are the same. However, in step S2030, if Figure 25 As shown, the resist mask 310 used for patterning the oxide semiconductor layer 140 is not removed but remains as it is.

[0155] like Figure 24 and Figure 26 As shown, the resist mask 310 is used as a mask to perform ion implantation of impurities into the oxide insulating layer 120 ( Figure 24 (The "first ion implantation" of step S2040 is described). For example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used as an impurity. Thus, impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are introduced into the oxide insulating layer 120. The impurities introduced into the oxide insulating layer 120 form dangling bond defects DB. The regions in the oxide insulating layer 120 where dangling bond defects DB are formed can function as hydrogen trapping regions.

[0156] In the first ion implantation of step S2040, it is important to form dangling bond defects DB in the oxide insulating layer 120, while not forming dangling bond defects DB in the nitride insulating layer 110. Therefore, in the first ion implantation, the ion implantation of impurities is performed in a manner such that a concentration profile has a peak in the oxide insulating layer 120. The position of the peak and the amount of impurities can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, a dose of 1×10 14 / cm 2 Above, 5×10 14 / cm 2 , or 1×10 15 / cm 2 For example, the acceleration voltage is greater than 10 keV, 15 keV or greater, or 20 keV or greater.

[0157] Note that, after the impurities are introduced into the oxide insulating layer 120 , the resist mask 310 is removed.

[0158] After the first ion implantation in step S2040, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Figure 24 (The "OS annealing" of step S2050 is shown in FIG. 2 ). Step S2040 is the same as step S1050.

[0159] Figure 24 Steps S2060 to S2120 shown are Figure 5 The steps S1070 to S1130 shown are the same.

[0160] In the case of this embodiment, based on the distribution of dangling bond defects DB formed in the oxide insulating layer 120, the amount of captured hydrogen H sometimes increases in the order of the oxide insulating layer 120 in the first area A1, the oxide insulating layer 120 in the second area A2, and the oxide insulating layer 120 in the third area A3.

[0161] In this embodiment, hydrogen trapping regions including a large number of dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3 surrounding the channel region CH. This suppresses hydrogen intrusion into the channel region CH. As a result, a semiconductor device 20 having electrical characteristics with suppressed hump can be obtained.

[0162] The various embodiments described above as embodiments of the present invention can be implemented in appropriate combinations as long as they do not contradict each other. In addition, solutions obtained by those skilled in the art by appropriately adding, deleting, or changing the design of components based on the various embodiments, or by adding, omitting, or changing the conditions of processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0163] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0164] Description of Reference Numerals

[0165] 10, 20: semiconductor device, 100: substrate, 105: light shielding layer, 110: nitride insulating layer, 120: oxide insulating layer, 140: oxide semiconductor layer, 141: upper surface, 142: lower surface, 143: side surface, 150: gate insulating layer, 160: gate electrode, 165A: oxide insulating layer, 170: insulating layer, 171: opening, 173: opening, 180: insulating layer, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 300: mask layer, 310: resist mask, A1: first region, A2: second region, A3: third region, CH: channel region, D: drain region, DB: dangling bond defect, S: source region.

Claims

1. A semiconductor device comprising: oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer on the oxide semiconductor layer; and a gate electrode on the gate insulating layer, In the first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order, the gate electrode contains impurities. In a second region that does not include the gate electrode and in which the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in this order, the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer contain the impurity. In a third region that does not include the gate electrode and the oxide semiconductor layer and in which the oxide insulating layer and the gate insulating layer are sequentially stacked, the oxide insulating layer and the gate insulating layer contain the impurity. In the stacking direction of the second region, the impurity concentration profile includes a first peak and a second peak.

2. The semiconductor device according to claim 1, wherein The first peak is included in the oxide insulating layer.

3. The semiconductor device according to claim 2, wherein The second peak is included in the oxide semiconductor layer.

4. The semiconductor device according to claim 2, wherein The second peak is included in the gate insulating layer.

5. The semiconductor device according to claim 1, wherein In the stacking direction of the third region, the impurity concentration profile includes a third peak and a fourth peak. The semiconductor device according to claim 5 , wherein: The third peak is included in the oxide insulating layer.

7. The semiconductor device according to claim 6, wherein The fourth peak is included in the gate insulating layer.

8. A semiconductor device comprising: oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer on the oxide semiconductor layer; and a gate electrode on the gate insulating layer, In the first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order, the gate electrode contains impurities. In a second region that does not include the gate electrode and in which the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in this order, the oxide semiconductor layer and the gate insulating layer contain the impurity. In a third region that does not include the gate electrode and the oxide semiconductor layer and in which the oxide insulating layer and the gate insulating layer are sequentially stacked, the oxide insulating layer and the gate insulating layer contain the impurity. In the stacking direction of the third region, the impurity concentration profile includes a first peak and a second peak.

9. The semiconductor device according to claim 8, wherein The first peak is included in the oxide insulating layer.

10. The semiconductor device according to claim 9, wherein The second peak is included in the gate insulating layer.

11. The semiconductor device according to claim 8, wherein In the second region, the concentration of the impurities contained in the oxide insulating layer is less than 1×10 16 / cm 3 .

12. The semiconductor device according to any one of claims 1 to 11, wherein The impurity is one selected from the group consisting of boron, phosphorus, argon and nitrogen.

13. The semiconductor device according to any one of claims 1 to 11, wherein The gate insulating layer has a thickness of 100 nm or more.

14. A method for manufacturing a semiconductor device, wherein: forming an oxide insulating layer, forming a mask layer having a first pattern on the oxide insulating layer, implanting a first impurity into the oxide insulating layer using the mask layer as a mask, forming an oxide semiconductor layer having a second pattern over the oxide insulating layer, covering the oxide semiconductor layer and forming a gate insulating layer on the oxide insulating layer and the oxide semiconductor layer, forming a gate electrode having a third pattern on the gate insulating layer, A second impurity is implanted into the oxide semiconductor layer using the gate electrode as a mask.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The first pattern is substantially consistent with the third pattern.

16. A method for manufacturing a semiconductor device, wherein: forming an oxide insulating layer, forming an oxide semiconductor layer having a first pattern over the oxide insulating layer, implanting a first impurity into the oxide insulating layer using the resist having the first pattern forming the oxide semiconductor layer as a mask, covering the oxide semiconductor layer and forming a gate insulating layer on the oxide insulating layer and the oxide semiconductor layer, forming a gate electrode having a second pattern on the gate insulating layer, A second impurity is implanted into the oxide semiconductor layer using the gate electrode as a mask.

17. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein: The first impurity and the second impurity are the same element.

18. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein: The first impurity and the second impurity are different elements.

19. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein: The first impurity and the second impurity are each one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

20. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein: The gate insulating layer has a thickness of 100 nm or more.

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