Chip testing method and device and storage medium

Abstract

The embodiment of the invention provides a chip testing method and device and a storage medium. The method is applied to an upper computer in a test system, and comprises the following steps: displaying a configuration information setting interface; setting values corresponding to the configuration items are obtained on the configuration information setting interface, and a test configuration file is obtained; generating a test script based on the test configuration file; and running the test script to test the chip to be tested. According to the technical scheme provided by the embodiment of the invention, when the to-be-tested chip is tested, only the configuration information related to the test process needs to be filled in the test configuration interface to form the test configuration file, the test configuration file is processed by utilizing the automatic test program, the test script is automatically generated, and the test efficiency is improved. And finally, the test script is run to test the chip to be tested, and the test script does not need to be customized by technical personnel in the process, so that the development difficulty of the test script can be reduced, the compiling efficiency of the test script is improved, and the test efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip testing technology, and in particular to a method, device, and storage medium for testing a chip. Background Art

[0002] Chip testing is an integral part of chip R&D. The chip testing solution provided by related technologies typically works as follows: testers develop custom test scripts based on automated testing requirements, the capabilities of the test equipment, and the chip under test. These scripts are then run to test the chip under test.

[0003] In related technologies, customizing test scripts is difficult and inefficient. Summary of the Invention

[0004] Embodiments of the present application provide a method, device, and storage medium for testing a chip.

[0005] In the first aspect, an embodiment of the present application provides a method for testing a chip, which is applied to a host computer in a test system. The test system also includes at least one test device, a test board and a chip to be tested. The host computer is connected to at least one test device and a test board respectively, and at least one test device is connected to the test board. The chip to be tested is set on the test board. The method includes: displaying a configuration information setting interface, the configuration information setting interface includes multiple configuration items, and the configuration items refer to configuration parameters involved in the process of testing the chip to be tested; obtaining setting values ​​corresponding to multiple configuration items in the configuration information setting interface to obtain a test configuration file; generating a test script based on the test configuration file; and running the test script to test the chip to be tested.

[0006] In the second aspect, an embodiment of the present application provides a device for testing a chip, the device comprising: a file editing module for displaying a configuration information setting interface, the configuration information setting interface comprising multiple configuration items, the configuration items referring to configuration parameters involved in the process of testing the chip to be tested; obtaining setting values ​​corresponding to the multiple configuration items in the configuration information setting interface to obtain a test configuration file; an automatic testing module for generating a test script based on the test configuration file; and running the test script to test the chip to be tested.

[0007] In a third aspect, an embodiment of the present application provides a computer device comprising: a memory; one or more processors coupled to the memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the method for testing a chip as described in the first aspect.

[0008] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program or computer instructions are stored. When the computer program or computer instructions are executed by a processor, a method for testing a chip as in the first aspect is implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed, is used to implement the method for testing a chip as in the first aspect.

[0010] Compared with the related technology, the technical solution provided by the embodiment of the present application, when testing the chip to be tested, only needs to fill in the configuration information involved in this test process in the test configuration interface to form a test configuration file, and the test configuration file will be processed by the automatic test program to automatically generate a test script, and finally the test script will be run to realize the test of the chip to be tested. This process does not require technical personnel to customize the test script, so it can reduce the difficulty of developing the test script, improve the efficiency of writing the test script, and thus improve the testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 This is a schematic diagram of a test system provided in one embodiment of the present application.

[0013] Figure 2 This is a flowchart of a method for testing a chip provided by an embodiment of the present application.

[0014] Figure 3 This is a flowchart of a method for testing a chip provided by an embodiment of the present application.

[0015] Figure 4 This is a schematic diagram of the first sub-interface provided by an embodiment of the present application.

[0016] Figure 5 This is a schematic diagram of the first sub-interface provided by an embodiment of the present application.

[0017] Figure 6 This is a schematic diagram of the first sub-interface provided by an embodiment of the present application.

[0018] Figure 7 This is a schematic diagram of the first sub-interface provided by an embodiment of the present application.

[0019] Figure 8This is a flowchart of a method for testing a chip provided in another embodiment of the present application.

[0020] Figure 9 This is a block diagram of a device for testing a chip provided in one embodiment of the present application.

[0021] Figure 10 This is a block diagram of a computer device provided by one embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0023] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0024] In the related art, testers’ customized test scripts have the following defects: 1. The development and optimization of test scripts have a high technical threshold. Since it involves specific programming knowledge, it requires high programming ability from testers.

[0025] 2. There are many chip test modules. If the test script is customized for each requirement, it will lead to a huge workload and increase the testing cost. In addition, as the iteration speed of chips is getting faster and faster, the test scripts should also be optimized synchronously. Optimizing customized test scripts also brings the problem of heavy workload.

[0026] 3. Under the customized development model, test equipment generally exists independently, does not form a system, is difficult to call, and is generally only compatible with one or two devices, resulting in problems such as inconvenience in subsequent function expansion and inconvenience in adding other types of test equipment.

[0027] Based on the problems existing in the related art, the embodiment of the present application designs a new test chip solution. When testing the chip to be tested, it is only necessary to fill in the configuration information involved in this test process in the test configuration interface to form a test configuration file. The test configuration file will be processed by the automatic test program, and a test script will be automatically generated. Finally, the test script is run to implement the test of the chip to be tested. This process does not require technicians to customize the test script, so it can reduce the difficulty of developing the test script, improve the efficiency of writing the test script, and thus improve the test efficiency. In addition, since the test personnel in this process only need to fill in the corresponding setting values ​​according to the file editing specifications, on the one hand, the requirements for the programming ability of the test personnel are relatively low, which reduces the development threshold of the test script. On the other hand, it reduces the workload brought by generating the test script. To optimize the test script later, it is only necessary to modify the relevant configuration parameters in the test configuration interface, which can also reduce the workload and save development costs. Finally, test equipment can be added on demand in the test configuration interface, and there is no limit on the number of compatible test equipment, which reduces the difficulty of subsequent function expansion and adding other types of test equipment.

[0028] Please refer to Figure 1 , which shows a schematic diagram of a test system 100 according to an embodiment of the present application. The test system 100 includes a host computer 10, at least one test device 20, a test board 30, and a chip to be tested 40.

[0029] The host computer 10 is connected to at least one test device 20 and a test board 30, respectively. The host computer 10 can be interconnected with the test board via interfaces such as JTAG / UART, enabling data transmission and register reading and writing between the host computer 10, the test board 30, and the chip under test 40. The host computer 10 is interconnected with at least one test device 20 via GPIB, USB, LAN, or PXI, enabling automated control of at least one test device 20 and receiving test measurement data returned by at least one test device 20. At least one test device 20 is connected to the test board 30, respectively. The connection method between the test device 20 and the test board 30 selects different connection media based on the device type of the test device 20, providing input data to the test board 30 on the one hand, and obtaining output data from the test board 30 and the chip under test 40 on the other hand. The chip under test 40 is set on the test board 30.

[0030] The host computer 10 refers to a computer that can directly issue control commands, generally a personal computer. In an embodiment of the present application, the host computer 10 includes a first application and a second application. The first application is for the tester to set various test configuration information, including but not limited to: configuration information of the chip to be tested 10, configuration information of at least one test device 20, configuration information of this test process, performance indicators of performance parameters, etc. The first application can be an EXCEL program or a WORD program. The second application is an automatic test program, which can be pre-developed based on the Python language and its related extension packages. In some embodiments, the host computer 10 also includes a driver corresponding to at least one test device 20, and the identification and remote control of the test device 20 are realized through the driver corresponding to the test device 20.

[0031] The test equipment 20 includes equipment for testing the chip 40 to be tested, such as an oscilloscope and a temperature shock. The test equipment 20 also includes equipment that provides input to the chip 40 to be tested, such as a power supply, a signal generator, etc. The above-mentioned test equipment 20 are all programmable devices, which means that technicians can set their test conditions. The test board 30 is a device used for chip testing, which usually includes some interfaces, measuring instruments, and a power light function platform required for chip testing. The test board 30 may include a probe card, a load board, an aging test board, etc. The chip 40 to be tested may be an FPGA chip.

[0032] Please refer to Figure 2 , which shows a flow chart of a test method provided by an embodiment of the present application, the method is applied to Figure 1 The host computer in the embodiment, the method includes the following process.

[0033] S201, displaying a configuration information setting interface.

[0034] The configuration information setting interface is used to set the configuration information required for this test process, including but not limited to: configuration information of the chip under test, configuration information of the test equipment, configuration information of this test process, and configuration information of performance parameters. In the embodiment of the present application, the configuration information setting interface includes multiple configuration items. Configuration items refer to configuration parameters involved in the process of testing the chip under test. The technician can set the configuration items by filling in the corresponding setting values ​​in the edit boxes corresponding to each configuration item.

[0035] Optionally, the configuration information setting interface is a user interface of the first application. A tester generates a test template file in advance using the first application. When chip testing is subsequently required, the host computer is controlled to open the test template file and display the configuration information setting interface. When the first application is an Excel program, the test template file is an Excel file.

[0036] S202: Obtain setting values ​​corresponding to a plurality of configuration items in a configuration information setting interface to obtain a test configuration file.

[0037] The technicians can set the setting values ​​corresponding to the above multiple configuration items according to the chip functions that need to be verified in this test process and the test conditions required to implement the chip functions. After all the configuration items are set, the first application saves the above settings to obtain a test configuration file.

[0038] S203: Generate a test script based on the test configuration file.

[0039] Optionally, the host computer processes the test configuration file using the second application program to generate a test script.

[0040] S204: Run the test script to test the chip to be tested.

[0041] In some embodiments, the test script can input various stimulus signals to the chip under test to check whether the chip's output meets expectations, thereby verifying the chip's functionality. In other embodiments, the test script can measure performance indicators such as the chip's response time and processing speed to perform performance testing of the chip under test. In still other embodiments, the test script can simulate extreme environmental conditions (such as high and low temperatures, and humidity fluctuations) to test the chip's long-term stability and durability, thereby performing reliability testing of the chip under test.

[0042] To sum up, the technical solution provided by the embodiment of the present application, when testing the chip to be tested, only needs to fill in the configuration information involved in this test process in the test configuration interface to form a test configuration file, and the test configuration file will be processed by the automatic test program to automatically generate a test script, and finally the test script will be run to realize the test of the chip to be tested. This process does not require technical personnel to customize the test script, so it can reduce the difficulty of developing the test script, improve the efficiency of writing the test script, and thus improve the testing efficiency.

[0043] Please refer to Figure 3 , which shows a flow chart of a test method provided by an embodiment of the present application. Figure 1 The host computer in the embodiment, the method includes the following process.

[0044] S301, displaying a configuration information setting interface.

[0045] The configuration information setting interface includes multiple configuration items, which refer to the configuration parameters involved in the process of testing the chip to be tested.

[0046] In an embodiment of the present application, the configuration information setting interface includes a combination of one or more of the following: a first sub-interface, a second sub-interface, a third sub-interface, and a fourth sub-interface. Among them, the first sub-interface is used to configure this test process. The second sub-interface is used to configure a specified test device in at least one test device. The number of second sub-interfaces should be the same as the number of test devices connected to the test board, that is, each test device corresponds to a second sub-interface. The third sub-interface is used to configure the test environment information. The fourth sub-interface is used to configure the performance parameters involved in this test process.

[0047] In the case where the configuration information setting interface is a user interface of an Excel program, the first sub-interface, the second sub-interface, the third sub-interface and the fourth sub-interface are all interfaces corresponding to a sub-table in an Excel file. Figure 4 , which shows an interface diagram of the configuration information setting interface 400 provided by an embodiment of the present application. The work bar below the configuration information setting interface 400 includes the names of multiple sub-tables. When any sub-table is selected, the host computer displays the interface corresponding to the sub-table. The configuration information setting interface 400 includes a first sub-interface 410, a second sub-interface 420, a third sub-interface 430 and a fourth sub-interface 440. Among them, the sub-table corresponding to the first sub-interface 410 is "Test Configuration", and there are 4 sub-tables in the second sub-interface 420, and their respective corresponding sub-tables are, respectively, "Power Supply", "Signal Generator", "Oscilloscope", and "Multimeter", and the sub-table corresponding to the third sub-interface 430 is "Test Environment". The sub-table corresponding to the fourth sub-interface 440 is "Performance Indicators".

[0048] In some embodiments, the configuration information setting interface further includes at least one of a fifth sub-interface, a sixth sub-interface, and a seventh sub-interface. The fifth sub-interface is used to record the version information of the test template file and the update content corresponding to each version information. The sixth sub-interface is used to set specified functions, such as delay, interruption, etc. The seventh sub-interface is used to output test results.

[0049] Please see again Figure 4 The configuration information setting interface 400 includes a fifth sub-interface 450, a sixth sub-interface 460, and a seventh sub-interface 470. The sub-table corresponding to the fifth sub-interface 450 is "version", the sub-table corresponding to the sixth sub-interface 460 is "tools", and the sub-table corresponding to the seventh sub-interface 470 is "output template".

[0050] S302: Obtain configuration information of the chip to be tested on the first sub-interface.

[0051] The configuration information of the chip under test includes but is not limited to: chip information, serial port, onboard voltage, storage path of written files, storage path of register read and write files, and external test information. Among them, chip information includes process angle, batch number, voltage, temperature information, detailed technical parameters and feature description of the chip. The serial port includes serial port number, baud rate, CPLD serial port number, and CPLD serial port function. The written files include but are not limited to: bitstream files, PDS software files, and TCL files. Please refer to Figure 4 The first sub-interface 410 includes a first area 4110 , and the first area 4110 is used to configure the chip to be tested.

[0052] S303: When there are multiple test devices, obtain the execution order of the multiple test devices on the first sub-interface.

[0053] The technician specifies the execution order of multiple test devices in the first sub-interface according to the function or performance that needs to be verified for the chip under test. Figure 4 The first sub-interface 410 further includes a second area 4120 , which is used to configure the execution order of multiple test devices.

[0054] S304 , obtaining a target test function of a designated test device and a setting value of the target test function on the second sub-interface.

[0055] The test configuration interface has different sub-tables according to the type of each test device. Each function of the test device and its settable value are extracted to form a key-value pair, and are filled into the corresponding sub-table according to the internal functional logic of the test device. In an embodiment of the present application, the test function implemented by the specified test device is set as a drop-down sequence. After the technician selects the edit box corresponding to the specified test device, the host computer displays the drop-down sequence. The technician can select the specified test function in the drop-down sequence and fill in the corresponding setting value in the edit box corresponding to the specified test function. In addition, the technician can also customize the target test function. The host computer provides an edit box corresponding to the customized test function for the technician to customize the setting value.

[0056] Please refer to Figure 5 , which shows a schematic diagram of a second sub-interface 420 provided by an embodiment of the present application. The second sub-interface 420 is used to configure the signal generator.

[0057] S305: Obtain hardware environment information of this test process in the third sub-interface.

[0058] The hardware environment information includes the relevant information of each hardware involved in the above test system, such as model, connection method between each hardware, etc. Figure 6, which shows a schematic diagram of the third sub-interface 430 provided by an embodiment of the present application. The third sub-interface 430 includes a third area 4310, which is used to set the hardware environment information of this test process.

[0059] S306: Obtain software environment information of this test process in the third sub-interface.

[0060] The software environment information includes the relevant information of each software involved in the above test system, such as operating system, PDS version, Python version, NI software version, etc. Please refer to Figure 6 , which shows a schematic diagram of the third sub-interface 430 provided by an embodiment of the present application. The third sub-interface 430 includes a fourth area 4320, which is used to set the software environment information of this test process.

[0061] S307: Obtain performance indicators of performance parameters involved in this test process on the fourth sub-interface.

[0062] The performance index of the performance parameter refers to the expected value range of the performance parameter of the chip under test. The above performance parameters include the operating frequency of the chip under test, the duty cycle parameter of the 0th clock of the PLL output clock, etc. Figure 7 , which shows a schematic diagram of the fourth sub-interface 440 provided in an embodiment of the present application. The fourth sub-interface 440 includes two test scripts, case 1 and case 2; case 1 includes two performance parameters, freg and CLKOUT0_DUTY; case 2 includes two performance parameters, High and CLKOUT0_DUTY.

[0063] S308: Generate a test script based on the test configuration file.

[0064] S309: Run the test script to test the chip to be tested.

[0065] To sum up, the technical solution provided by the embodiment of the present application, when testing the chip to be tested, only needs to fill in the configuration information of the chip to be tested, the execution order of each test device, the configuration information of the test device, the software environment information, the hardware environment information, the performance indicators, etc. involved in this test process in the test configuration interface to form a test configuration file. The upper computer will use the automatic test program to process the test configuration file, automatically generate a test script, and finally run the test script to realize the test of the chip to be tested. This process does not require technical personnel to customize the test script, so it can reduce the difficulty of developing the test script, improve the efficiency of writing the test script, and thus improve the testing efficiency.

[0066] Please refer to Figure 8, which shows a flow chart of a method for testing a chip provided by an embodiment of the present application. Figure 1 The host computer in the embodiment, the method includes the following process.

[0067] S801, displaying a configuration information setting interface.

[0068] S802: Obtain setting values ​​corresponding to a plurality of configuration items in a configuration information setting interface to obtain a test configuration file.

[0069] S803, checking the editing specifications of the software test environment, hardware test environment, and test configuration files involved in this test process.

[0070] Software testing environment checks include checking the integrity of the relevant software and the correct version. Hardware testing environment checks include checking the communication status between the test equipment and the serial port, and checking the correct connection between the test board, test equipment, and other hardware. Test configuration file editing specifications include checking for compliance with the basic operating logic of the test equipment and the basic operating logic of the chip under test.

[0071] In addition, the host computer also needs to run the system initial state, during which it checks whether there are situations such as large currents that seriously endanger the test system and the chip under test.

[0072] S804: Generate an initial status inspection log based on the inspection result.

[0073] The initial status check log reflects the results of the above checks. If any abnormalities are found, a notification message will be issued. This notification message notifies the user of the abnormality and provides possible causes and solutions. Based on this notification message, technicians can correct the abnormality and trigger another check until the system passes.

[0074] S805 : When the initial status check log indicates that the check is passed, generate a test script based on the test configuration file.

[0075] S806: Run the test script to obtain test data.

[0076] In some embodiments, the test system further includes a current sensor, which is connected to a working circuit of the chip to be tested and is used to monitor the working current of the chip to be tested.

[0077] In this embodiment, while running the test script, the host computer also communicates with the current sensor, receiving the current detection value periodically reported by the current sensor. If the current detection value of the current sensor exceeds a preset current threshold, the test script is stopped and a first notification message is issued. This first notification message is used to notify the user of an overcurrent event during this test process. The first notification message can be displayed directly on the host computer's display interface or sent by the host computer to a technician's account or device via a designated communication system (such as email). The preset current threshold is set based on experimentation or experience to prevent high currents from damaging the chip under test and related test equipment.

[0078] In some embodiments, the test system further includes a temperature sensor, which is disposed around the chip to be tested and is used to monitor the operating temperature of the chip to be tested.

[0079] In this embodiment, while executing the test script, the host computer also communicates with the current sensor to receive the temperature value periodically reported by the temperature sensor. If the temperature value detected by the temperature sensor exceeds a preset temperature threshold, the test script is terminated and a second notification message is issued to notify the user of the overtemperature event during the test process. The second notification message can be displayed directly on the host computer's display interface or sent by the host computer to a technician's account or device via a designated communication system (e.g., email).

[0080] The preset temperature threshold is set based on experiments or experience, so as to avoid excessive temperature from burning out the chip under test and related test equipment.

[0081] S807: Compare the test data with the performance indicators of the performance parameters involved in this test process and generate a test report.

[0082] The host computer checks whether the test data is within the range indicated by the performance indicators of the aforementioned performance parameters. If the test data is within the above range, it indicates that the function or performance of the chip under test meets the requirements. If the test data is not within the above range, it indicates that the function or performance of the chip under test does not meet the requirements. The host computer can also send the test report to the technician's account or device via a designated communication system (such as email).

[0083] To sum up, the technical solution provided in the embodiment of the present application can improve the test success rate by checking the editing specifications of the software test environment, hardware test environment, and test configuration file involved in the test process before generating the test script; it can also improve the safety of the test system by performing overcurrent monitoring and overtemperature monitoring on the chip to be tested during the running of the test script.

[0084] Please refer to Figure 9 , which shows a structural block diagram of a chip test device provided by an embodiment of the present application. The chip test device includes: a file editing module 910 and an automatic testing module 920.

[0085] The file editing module 910 is used to display the configuration information setting interface, which includes multiple configuration items. The configuration items refer to the configuration parameters involved in the process of testing the chip to be tested; the setting values ​​corresponding to the multiple configuration items are obtained in the configuration information setting interface to obtain the test configuration file.

[0086] The automatic testing module 920 is configured to generate a test script based on the test configuration file and run the test script to test the chip under test.

[0087] In some embodiments, the configuration information setting interface includes a first sub-interface, which is used to configure the current test process; a file editing module 910, which is used to obtain the configuration information of the chip to be tested in the first sub-interface; or / and, when there are multiple test devices, the execution order of multiple test devices is obtained in the first sub-interface.

[0088] In some embodiments, the configuration information setting interface includes a second sub-interface, which is used to configure a specified test device among at least one test device; a file editing module 910 is used to obtain the target test function of the specified test device and the setting value of the target test function in the second sub-interface.

[0089] In some embodiments, the configuration information setting interface includes a third sub-interface, which is used to configure the test environment; a file editing module 910 is used to obtain the hardware environment information of this test process in the third sub-interface; or / and, obtain the software environment information of this test process in the third sub-interface.

[0090] In some embodiments, the configuration information setting interface includes a fourth sub-interface, which is used to configure the performance parameters involved in this test process; the file editing module 910 is used to obtain performance indicators of the performance parameters involved in this test process in the fourth sub-interface.

[0091] In some embodiments, the automatic testing module 920 is used to run a test script to obtain test data; compare the test data with performance indicators of performance parameters involved in this test process, and generate a test report.

[0092] In some embodiments, the test system also includes a current sensor, which is used to monitor the operating current of the chip to be tested; the automatic test module 920 is also used to stop running the test script and issue a first notification message during the execution of the test script if the current detection value of the current sensor is greater than a preset current threshold. The first notification message is used to notify the test process of an overcurrent event.

[0093] In some embodiments, the test system also includes a temperature sensor, which is used to monitor the operating temperature of the chip to be tested; the automatic test module 920 is also used to stop running the test script and issue a second notification message during the execution of the test script if the temperature detection value of the temperature sensor is greater than a preset temperature threshold. The second notification message is used to notify the test process of an overtemperature event.

[0094] In some embodiments, the automatic testing module 920 is further configured to check the editing specifications of the software testing environment, hardware testing environment, and test configuration files involved in this test process; and generate an initial status check log based on the check results.

[0095] To sum up, the technical solution provided by the embodiment of the present application, when testing the chip to be tested, only needs to fill in the configuration information involved in this test process in the test configuration interface to form a test configuration file, and the test configuration file will be processed by the automatic test program to automatically generate a test script, and finally the test script will be run to realize the test of the chip to be tested. This process does not require technical personnel to customize the test script, so it can reduce the difficulty of developing the test script, improve the efficiency of writing the test script, and thus improve the testing efficiency.

[0096] The present application also provides an electronic device 1000. Figure 10 , including a processor 1010 and a memory 1020, wherein the memory 1020 is used to store computer programs; the processor 1010 is used to execute the program stored in the memory 1020 to implement the method for testing the chip introduced in any embodiment of the present application.

[0097] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method for testing a chip described in any embodiment of the present application is implemented.

[0098] In specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units, hardware modules / units, or partially software modules / units and partially hardware modules / units.

[0099] For example, for each device or product applied to or integrated into a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated into a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip module, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated into a terminal, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (e.g., chip, circuit module, etc.) in the terminal. Chip, circuit module, etc.) or different components, or, at least part of the modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in hardware such as circuits.

[0100] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A method for testing a chip, characterized in that: The host computer is applied to the test system, the test system further includes at least one test device, a test board and a chip to be tested, the host computer is connected to the at least one test device and the test board respectively, the at least one test device is connected to the test board, and the chip to be tested is set on the test board. The method includes: Displaying a configuration information setting interface, wherein the configuration information setting interface includes a plurality of configuration items, wherein the configuration items refer to configuration parameters involved in the process of testing the chip under test; Obtaining setting values ​​corresponding to the plurality of configuration items in the configuration information setting interface to obtain a test configuration file; Generate a test script based on the test configuration file; Run the test script to test the chip to be tested.

2. The method according to claim 1, characterized in that The configuration information setting interface includes a first sub-interface, which is used to configure the current test process; The acquiring of the setting values ​​corresponding to the plurality of configuration items in the configuration information setting interface to obtain the test configuration file includes: Acquire configuration information of the chip to be tested on the first sub-interface; or / and, When there are multiple test devices, the execution order of the multiple test devices is obtained on the first sub-interface.

3. The method according to claim 1, characterized in that The configuration information setting interface includes a second sub-interface, and the second sub-interface is used to configure a specified test device among the at least one test device; The acquiring of the setting values ​​corresponding to the plurality of configuration items in the configuration information setting interface to obtain the test configuration file includes: The target test function of the designated test device and the setting value of the target test function are obtained in the second sub-interface.

4. The method according to claim 1, wherein The configuration information setting interface includes a third sub-interface, and the third sub-interface is used to configure the test environment; The acquiring of the setting values ​​corresponding to the plurality of configuration items in the configuration information setting interface to obtain the test configuration file includes: Obtain the hardware environment information of the test process in the third sub-interface; or / and, The software environment information of the current test process is obtained in the third sub-interface.

5. The method according to claim 1, wherein The configuration information setting interface includes a fourth sub-interface, and the fourth sub-interface is used to configure the performance parameters involved in this test process; The acquiring of the setting values ​​corresponding to the plurality of configuration items in the configuration information setting interface to obtain the test configuration file includes: The performance indicators of the performance parameters involved in the test process are obtained on the fourth sub-interface.

6. The method according to claim 5, characterized in that The step of running the test script to test the chip under test includes: Run the test script to obtain test data; The test data is compared with the performance indicators of the performance parameters involved in the test process, and a test report is generated.

7. The method according to any one of claims 1 to 6, characterized in that The test system further includes a current sensor configured to monitor the operating current of the chip under test. The method further includes: during execution of the test script, if a current detection value of the current sensor is greater than a preset current threshold, stopping the execution of the test script and issuing a first notification message, wherein the first notification message is configured to notify the test process of an overcurrent event occurring. or / and, The test system also includes a temperature sensor, which is used to monitor the operating temperature of the chip to be tested; the method also includes: during the execution of the test script, if the temperature detection value of the temperature sensor is greater than a preset temperature threshold, the test script is stopped and a second notification message is issued, wherein the second notification message is used to notify the test process of an overtemperature event.

8. The method according to any one of claims 1 to 6, characterized in that Before generating a test script based on the test configuration file, the method further includes: Check the software test environment, hardware test environment, and editing specifications of the test configuration files involved in the test process; Generates an initial status check log based on the check results.

9. A device for testing a chip, characterized in that: The device comprises: A file editing module is configured to display a configuration information setting interface, wherein the configuration information setting interface includes a plurality of configuration items, each of which is a configuration parameter involved in the process of testing the chip under test; and obtain setting values ​​corresponding to the plurality of configuration items in the configuration information setting interface to obtain a test configuration file; The automatic testing module is used to generate a test script based on the test configuration file; and run the test script to test the chip to be tested.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program or a computer instruction. When the computer program or the computer instruction is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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