Synchronous trigger capable of configuring multi-level interface based on ARM (Advanced RISC Machines) controller

Abstract

The invention provides a synchronous trigger capable of configuring a multi-level interface based on an ARM controller, and relates to the technical field of triggers, the synchronous trigger comprises an ARM controller, a multi-level input processing circuit, a multi-level output processing circuit, a multi-level input interface module, a multi-level output interface module and a FLASH storage module; the input end of the ARM controller is connected with the multi-level input processing circuit, the multi-level input processing circuit is connected with the multi-level input interface module, the output end of the ARM controller is connected with the multi-level output processing circuit, the multi-level output processing circuit is connected with the multi-level output interface module, and the ARM controller is connected with the FLASH storage module. Through a configurable hardware architecture, flexible switching and mode self-adaption of multi-level interfaces are achieved, and the problem that TTL level trigger signals are prone to being interfered by transmission distance and electromagnetic interference is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of triggers, and in particular to a synchronous trigger with a configurable multi-level interface based on an ARM controller. Background Art

[0002] In actual use, in order to synchronize the sampling behavior of the device with other hardware (such as a motorized stage), in addition to software commands, level signals (such as TTL level signals, LVCMOS level signals, etc.) can also be used to communicate between different hardware. The device can both receive and output level signals.

[0003] Typically, a TTL level signal is used at the receiving end of a device to receive a synchronous trigger signal. A level signal has two states: high and low. The information transmitted by the high-low level conversion allows the device to communicate with other hardware. The voltage difference between the high and low levels of the level signal varies depending on the device. Hardware such as cameras generally use the following types of signals: (1) rising and falling edges, which refer to the sudden change in voltage when the high and low levels are converted; and (2) the duration of the level.

[0004] However, in actual use, TTL level signals are susceptible to transmission distance limitations and electromagnetic interference. Generally, when designing a synchronization signal interface, it is necessary to convert TTL level signals into differential signals, which have strong anti-interference capabilities. Summary of the Invention

[0005] In view of this, in order to solve the problem that a single TTL level trigger signal is easily affected by transmission distance and electromagnetic interference, the purpose of the present invention is to propose a synchronous trigger with a configurable multi-level interface based on an ARM controller. Through a configurable hardware architecture, flexible switching and mode adaptation of the multi-level interface are achieved, solving the problem that a TTL level trigger signal is easily affected by transmission distance and electromagnetic interference.

[0006] To achieve the above object, the present invention provides the following technical solutions: Based on the above objectives, in a first aspect, the present invention provides a synchronous trigger with a configurable multi-level interface based on an ARM controller, comprising an ARM controller, a multi-level input processing circuit, a multi-level output processing circuit, a multi-level input interface module, a multi-level output interface module, and a FLASH storage module; the input end of the ARM controller is connected to the multi-level input processing circuit, which is connected to the multi-level input interface module; the output end of the ARM controller is connected to the multi-level output processing circuit, which is connected to the multi-level output interface module; the ARM controller is connected to the FLASH storage module, and the FLASH storage module runs on the ARM controller; the ARM controller is used to read the default parameters stored in the FLASH when powered on, and dynamically adjust the working state according to the configuration command, and is also used to process signal conversion, mode control, and trigger signal generation; Among them, the multi-level input processing circuit includes a synchronous trigger cascade processing circuit, an LVDS trigger processing circuit, an RS422 trigger processing circuit, an RS485 trigger processing circuit, an RS232 trigger processing circuit and a TTL / CMOS trigger processing circuit; the multi-level output processing circuit includes a synchronous trigger cascade processing circuit, a synchronous software trigger processing circuit, a synchronous hardware trigger processing circuit and a synchronous trigger mode configuration circuit.

[0007] As a further solution of the present invention, the ARM controller is a GD32F103C8T6 controller or an STM32F103C8T6 controller, and the peripheral circuit of the ARM controller is designed based on the GD32F103C8T6 chip, integrating a reset module, a startup mode module, an SPWM module, a power supply filter module, a crystal oscillator module, a power supply module and an ARM core module, and is used to select trigger interfaces and trigger output forms of different level standards according to control instructions, and perform system parameter configuration through a host computer and serial port commands, and select different types of trigger input interfaces, trigger output interfaces and trigger pulse waveform characteristics.

[0008] As a further solution of the present invention, the FLASH storage module is arranged in the configuration module of the ARM core module, and is used to configure the working mode, input mode, output mode and trigger thermal characteristic parameters through a host computer or serial port command. The trigger thermal characteristic parameters include trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width.

[0009] As a further solution of the present invention, the multi-level input interface module is used to receive an external trigger signal. The multi-level input interface module supports at least six configurable level standards, including a synchronous trigger cascade input interface, an LVDS trigger input interface, an RS422 trigger input interface, an RS485 trigger input interface, an RS232 trigger input interface, and a TTL / CMOS trigger input interface, and is respectively connected to the synchronous trigger cascade processing circuit, the LVDS trigger processing circuit, the RS422 trigger processing circuit, the RS485 trigger processing circuit, the RS232 trigger processing circuit, and the TTL / CMOS trigger processing circuit of the multi-level input processing circuit.

[0010] As a further solution of the present invention, the LVDS trigger input interface adopts a DS90LV032 differential receiver chip, the RS422 trigger input interface adopts an AM26LV32IDR differential receiver chip, the RS485 trigger input interface adopts a MAX3085EESA+T differential receiver chip, and the RS232 trigger input interface adopts a MAX3232 chip; wherein, the LVDS trigger input interface is implemented based on the DS90LV032 differential receiver chip, supports a 400Mbps data transmission rate, converts the low-voltage differential signal into a 3V CMOS level, and provides open circuit and short circuit fault protection; the RS422 trigger input interface is implemented based on the AM26LV32IDR differential receiver chip, has ±200mV sensitivity and three-state output; the RS485 trigger input interface is implemented based on the MAX3085EESA+T differential receiver chip, supports ±15kV ESD protection and fail-safe output; the RS232 trigger input interface is implemented based on the MAX3232 chip, supports a 250kbit / s data rate and ±15kV The ESD-protected charge pump circuit is compatible with a single 3V to 5.5V supply.

[0011] As a further solution of the present invention, the multi-level input interface module and the multi-level output interface module include a bus driver circuit, which uses the SN74AHCT16245DGGR chip for digital signal buffering and level conversion to improve signal driving capability and integrity.

[0012] As a further solution of the present invention, the multi-level output interface module is used to output a trigger signal to the controlled device. The multi-level output interface module supports at least four configurable output forms, including a synchronous trigger cascade output interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface and a synchronous trigger mode configuration interface. The synchronous trigger cascade output interface is connected to the cascade device, the synchronous software trigger output interface and the synchronous hardware trigger output interface are connected to the controlled device, and the synchronous trigger mode configuration interface is connected to the host computer configuration software.

[0013] As a further solution of the present invention, the synchronous trigger with a configurable multi-level interface also includes a physical structure module, which includes a main control board PCB, an outer shell, a front panel, a rear panel and multiple interface components, and the interface components include an external trigger cascade signal input interface, a multi-level external trigger interface, a main control board power supply interface, a system configuration USB interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface and a synchronous trigger cascade output interface integrated on the same main control board PCB.

[0014] As a further solution of the present invention, the synchronization trigger supports four working modes, which are dynamically switched by the configuration module, wherein: Mode 1: Receiver mode, the synchronous trigger acts as an independent receiving host, receives an external trigger signal and forwards it to the controlled device through the output interface module. The external trigger signal is input through any interface of the multi-level input interface module; Mode 2: Receiver cascade mode, multiple synchronization triggers are cascaded, one of which is connected to the external trigger interface as the receiving master, and the rest are connected to the trigger cascade input interface and output interface as receiving slaves to achieve multi-device synchronization; Mode 3: Control host mode, the synchronization trigger uses the internal timer module to actively generate a trigger signal and controls the controlled device through the output interface module; Mode 4: Control host cascade mode, multiple synchronization triggers are cascaded, one of which acts as a control host to generate a trigger signal and transmit it through the cascade interface, and the rest act as slaves to receive signals, thereby realizing synchronous control of multiple devices.

[0015] As a further solution of the present invention, the configuration process of the configuration module includes: Working mode configuration, select control host working mode, receiving host working mode or receiving slave working mode; Input mode configuration, select synchronous trigger cascade input mode, LVDS trigger input mode, RS422 trigger input mode, RS485 trigger input mode, RS232 trigger input mode or TTL / CMOS trigger input mode; Output mode configuration, select synchronous trigger cascade output mode, synchronous software trigger output mode or synchronous hardware trigger output mode; Trigger thermal characteristics configuration, set trigger level, trigger mode, positive pulse selection, negative pulse selection or pulse width; After configuration is completed, the parameters are stored in the FLASH storage module.

[0016] As a further solution of the present invention, the configuration module includes a synchronous software trigger processing circuit, which uses a CH340 chip to implement the USB to serial port function for host computer communication and mode configuration; the workflow of the synchronous software trigger processing circuit includes: system power-on initialization and reading of FLASH parameters; detection of mode configuration requirements; updating of working mode, input mode, output mode or triggering thermal characteristics according to serial port or host computer commands; after entering the working state, using an internal timer to generate a trigger signal in the control host mode, and detecting and forwarding the trigger signal in the receiving host / slave mode.

[0017] Compared with the prior art, the present invention proposes a synchronous trigger with a configurable multi-level interface based on an ARM controller, which has the following beneficial effects: The present invention supports the free selection of multiple trigger input interfaces and trigger output interfaces through the software configuration of the ARM controller, and can realize dynamic switching of multi-level interfaces, solving the problem of poor compatibility of traditional TTL level interfaces, adapting to different equipment level standards, and seamlessly switching interface types in complex industrial environments without replacing hardware. In addition, to address the problems of long-distance transmission and electromagnetic interference, the present invention integrates a high-anti-interference interface. The LVDS interface supports 400Mbps high-speed transmission and converts differential signals to CMOS levels through the DS90LV032 chip, significantly reducing the impact of noise; the RS422 / RS485 interface uses AM26LV32IDR and MAX3085EESA+T chips, supports ±15kV ESD protection, ensures stable signal transmission in harsh environments, and enhances anti-interference and signal stability.

[0018] The present invention also configures waveform characteristics and mode switching parameters in real time through the host computer or serial port commands. The configuration parameters are automatically saved to the built-in FLASH of the ARM controller for FLASH parameter storage, and there is no need to repeat the settings after power failure; the four working modes of independent receiver, cascade receiver, independent control host and cascade control host cover all scenarios, and have multi-mode collaboration and cascade expansion capabilities; all interfaces are integrated into the single-board design, which reduces the size and assembly cost, automatically loads FLASH parameters when powered on in the control process, detects configuration requirements, supports real-time switching of working states, and provides highly reliable synchronous triggering solutions for intelligent manufacturing, medical instruments, automated testing and other fields.

[0019] These and other aspects of the present application will be more clearly understood in the following description of the embodiments. It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for the exemplary embodiments or related technical descriptions. The drawings are used to provide a further understanding of the present invention and constitute part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the drawings: Figure 1 The present invention is a system block diagram of a synchronous trigger with a configurable multi-level interface based on an ARM controller.

[0021] Figure 2 This is a block diagram of using a synchronous trigger with a configurable multi-level interface based on an ARM controller as a receiver according to an embodiment of the present invention.

[0022] Figure 3 This is a connection block diagram of a cascade mode using a synchronous trigger with a configurable multi-level interface based on an ARM controller as a receiver according to an embodiment of the present invention.

[0023] Figure 4 This is a connection block diagram of using a synchronous trigger with a configurable multi-level interface based on an ARM controller as a control host according to an embodiment of the present invention.

[0024] Figure 5 The present invention is a block diagram showing a connection method for using a synchronous trigger with a configurable multi-level interface based on an ARM controller as a control host in a cascade mode.

[0025] Figure 6 This is a flow chart of a configuration of a synchronous trigger cascade mode control system with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0026] Figure 7 This is a peripheral circuit diagram based on GD32F103C8T6 in a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0027] Figure 8 This is a bus driving circuit diagram based on SN74AHCT16245DGGR in a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0028] Figure 9 This is a circuit diagram of an LVDS trigger input processing circuit based on DS90LV032 in a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0029] Figure 10This is a circuit diagram of an RS422 trigger input processing circuit based on AM26LV32IDR in a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0030] Figure 11 This is a circuit diagram of an RS485 trigger input processing circuit based on MAX3085EESA+T in a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0031] Figure 12 The present invention provides a circuit diagram of an RS232 trigger input processing circuit based on MAX3232 in a synchronous trigger with a configurable multi-level interface based on an ARM controller.

[0032] Figure 13 This is a circuit diagram of synchronous software trigger processing and synchronous trigger mode configuration processing based on CH340 in a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0033] Figure 14 This is a system control flow chart of a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention.

[0034] Figure 15 This is a structural assembly diagram of a synchronous trigger with a configurable multi-level interface based on an ARM controller according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Below, the present application is further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0036] To make the purpose, technical solutions and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0037] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0038] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described, obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present application.

[0039] The flowcharts shown in the drawings are only illustrative, not necessarily including all the contents and operations / steps, and not necessarily executed in the described order. For example, some operations / steps can be decomposed, combined or partially merged, so that the actual execution order can be changed according to the actual situation.

[0040] Some embodiments of the present application will be described in detail below with reference to the drawings. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0041] In order to solve the problem that the TTL level trigger signal based on single TTL level trigger signal is easy to be affected by transmission distance and electromagnetic interference. The present application provides a synchronous trigger of configurable multi-level interface based on ARM controller, through the configurable hardware architecture, the flexible switching and mode adaptation of multi-level interface are realized, and the problem that the TTL level trigger signal is easy to be affected by transmission distance and electromagnetic interference is solved.

[0042] Referring to Figure 1 The embodiment of the present application provides a synchronous trigger of configurable multi-level interface based on ARM controller, which comprises an ARM controller, a multi-level input processing circuit, a multi-level output processing circuit, a multi-level input interface module, a multi-level output interface module and a FLASH storage module; the input end of the ARM controller is connected with the multi-level input processing circuit, the multi-level input processing circuit is connected with the multi-level input interface module, the output end of the ARM controller is connected with the multi-level output processing circuit, the multi-level output processing circuit is connected with the multi-level output interface module, the ARM controller is connected with the FLASH storage module, the FLASH storage module runs on the ARM controller, the ARM controller is used for reading the default parameters stored in the FLASH when powered on, and dynamically adjusting the working state according to the configuration command, and is also used for processing signal conversion, mode control and trigger signal generation.

[0043] The multi-level input processing circuit comprises a synchronous trigger cascade processing circuit, an LVDS trigger processing circuit, an RS422 trigger processing circuit, an RS485 trigger processing circuit, an RS232 trigger processing circuit and a TTL / CMOS trigger processing circuit; and the multi-level output processing circuit comprises a synchronous trigger cascade processing circuit, a synchronous software trigger processing circuit, a synchronous hardware trigger processing circuit and a synchronous trigger mode configuration circuit.

[0044] In the synchronous trigger of the application, the trigger interface of different level standards can be selected flexibly according to the control instruction, and different types of trigger input interfaces such as synchronous trigger cascade input interface, LVDS trigger input interface, RS422 trigger input interface, RS485 trigger input interface, RS232 trigger input interface, TTL / CMOS trigger input interface and the like can be supported. The system design can flexibly select the trigger output form according to the control instruction, and different types of trigger output interfaces such as synchronous software trigger output interface, synchronous hardware trigger trigger interface, synchronous trigger cascade output interface and the like can be supported. The system design can configure system parameters through the host computer and serial port commands, select different types of trigger input interfaces, trigger output interfaces and trigger pulse waveform characteristics. The FLASH storage module of the system design can store the configured system parameters.

[0045] In the embodiment, in order to realize the control and operation of the system, the ARM controller is a GD32F103C8T6 controller or an STM32F103C8T6 controller, the peripheral circuit of the ARM controller is designed based on the GD32F103C8T6 chip, and is integrated with a reset module, a start mode module, an SPWM module, a power supply filtering module, a crystal oscillator module, a power supply module and an ARM core module, which are used to select trigger interfaces of different level standards, trigger output forms according to control instructions, and configure system parameters through the host computer and serial port commands, select different types of trigger input interfaces, trigger output interfaces and trigger pulse waveform characteristics.

[0046] In the embodiment, the controller circuit can use the GD32F103C8T6 ARM core control chip developed by GigaDevice based on the ARM core chip, or use the STM32F103C8T6 ARM core control chip developed by ST based on the core chip. The GD32F103C8T6 controller of GigaDevice is selected in the design, and the control and timing drive of the whole system can be realized and completed. In order to realize the control of the whole system, the peripheral circuit based on the GD32F103C8T6 is designed, including a reset module, a start mode module, an SPWM module, a power supply filtering module, a crystal oscillator module, a power supply module and a GD32F103C8T6 core module, as shown in Figure 7

[0047] ​In order to realize the synchronous trigger cascade input processing circuit, the synchronous trigger cascade output processing circuit, the TTL / CMOS trigger input processing circuit, and the synchronous hardware trigger output processing circuit, the present invention can use 16245 series bus drivers such as SN74LVC16245ADGGR or SN74AHCT16245DGGR as the input and output interface chip of the digital signal.

[0048] Among them, the FLASH storage module is set in the configuration module of the ARM core module, and is used to configure the working mode, input mode, output mode and trigger thermal characteristic parameters through the host computer or serial port command. The trigger thermal characteristic parameters include trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width.

[0049] In this embodiment, the multi-level input interface module is used to receive an external trigger signal. The multi-level input interface module supports at least six configurable level standards, including a synchronous trigger cascade input interface, an LVDS trigger input interface, an RS422 trigger input interface, an RS485 trigger input interface, an RS232 trigger input interface, and a TTL / CMOS trigger input interface, and is respectively connected to the synchronous trigger cascade processing circuit, the LVDS trigger processing circuit, the RS422 trigger processing circuit, the RS485 trigger processing circuit, the RS232 trigger processing circuit, and the TTL / CMOS trigger processing circuit of the multi-level input processing circuit.

[0050] Among them, the LVDS trigger input interface adopts the DS90LV032 differential receiver chip, the RS422 trigger input interface adopts the AM26LV32IDR differential receiver chip, the RS485 trigger input interface adopts the MAX3085EESA+T differential receiver chip, and the RS232 trigger input interface adopts the MAX3232 chip; wherein, the LVDS trigger input interface is implemented based on the DS90LV032 differential receiver chip, supports 400Mbps data transmission rate, converts low-voltage differential signals into 3V CMOS level, and provides open circuit and short circuit fault protection; the RS422 trigger input interface is implemented based on the AM26LV32IDR differential receiver chip, has ±200mV sensitivity and three-state output; the RS485 trigger input interface is implemented based on the MAX3085EESA+T differential receiver chip, supports ±15kV ESD protection and fail-safe output; the RS232 trigger input interface is implemented based on the MAX3232 chip, supports 250kbit / s data rate and ±15kV The ESD-protected charge pump circuit is compatible with a single 3V to 5.5V supply.

[0051] The SN74AHCT16245DGGR selected in the design of the present invention is used as a bus driver to buffer the input and output digital signals. On the one hand, it improves the driving ability of digital signals and improves signal integrity. On the other hand, it realizes level conversion, such as Figure 8 shown.

[0052] In order to realize the LVDS trigger input processing circuit, this design can use LVDS differential receiver chips such as DS90LV032 or DS90LV048 as LVDS trigger input interface chips. The DS90LV032 selected in the design is an LVDS differential receiver chip that uses low-voltage differential signaling (LVDS) technology and supports a data transmission rate of 400Mbps (200MHz), which is suitable for high-speed point-to-point communication. It can convert low-voltage differential input signals (typical value 350mV) into 3V CMOS output levels. It supports open circuit, short circuit and terminated input fault protection. The output remains high in the event of a fault, improving system reliability. Figure 9 shown.

[0053] To implement the RS422 trigger processing circuit, this design can use RS422 differential receiver chips such as AM26LV32IDR or SN75176B as RS422 trigger input interface chips. The AM26LV32IDR used in the design is an RS422 differential receiver chip that uses low-voltage differential signaling (LVDS) technology, has a three-state output, and has a ±200mV sensitivity. The interface circuit design supports open circuit, short circuit, and terminated input fault protection. In the event of a fault, the output remains high, improving system reliability. Figure 10 shown.

[0054] In order to realize the RS485 trigger processing circuit, this design can use RS485 differential receiver chips such as MAX3085EESA+T or SN75176B as RS485 trigger input interface chips. The MAX3085EESA+T used in the design, as an RS485 differential receiver chip, has the characteristics of high reliability and low power consumption. The circuit design can realize ±15kV ESD protection, fail-safe output and multi-node support and other functions, such as Figure 11 shown.

[0055] In order to realize the RS232 trigger processing circuit, this design uses the RS232 dedicated chip MAX3232. The design chooses to use MAX3232 as an RS232 dedicated chip to receive RS232 trigger signals. The MAX3232 device consists of two line drivers, two line receivers and a dual charge pump circuit with ±15kV ESD protection between terminals (serial port connection terminals, including GND). This part of the circuit design complies with the requirements of TIA / EIA-232-F and provides an electrical interface between the asynchronous communication controller and the serial port connector. The charge pump and four small external capacitors support power supply from a single 3V to 5.5V power supply. The device operates at a data signal transmission rate of up to 250kbit / s, and the driver output slew rate is up to 30V / μs, such as Figure 12 shown.

[0056] In order to realize synchronous software trigger processing and synchronous trigger mode configuration, this design uses the USB bus adapter chip CH340 to realize the USB to serial port control function. The design chooses to use CH340 to realize the sending of synchronous software trigger and the configuration of synchronous trigger mode. Using the chip CH340, the system design uses a full-speed USB device interface, which is compatible with USBV2.0. The host computer is based on the serial port application under the Windows operating system on the computer side for compatibility design, such as Figure 13 shown.

[0057] The multi-level input interface module and the multi-level output interface module include a bus driver circuit, which uses the SN74AHCT16245DGGR chip for digital signal buffering and level conversion to improve signal driving capability and integrity.

[0058] The multi-level output interface module is used to output a trigger signal to the controlled device. The multi-level output interface module supports at least four configurable output forms, including a synchronous trigger cascade output interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface and a synchronous trigger mode configuration interface. The synchronous trigger cascade output interface is connected to the cascade device, the synchronous software trigger output interface and the synchronous hardware trigger output interface are connected to the controlled device, and the synchronous trigger mode configuration interface is connected to the host computer configuration software.

[0059] Among them, see Figure 14As shown, the synchronous trigger with a configurable multi-level interface also includes a physical structure module, which includes a main control board PCB 1, an outer shell 11, a front panel 9, a rear panel 10 and multiple interface components. The interface components include an external trigger cascade signal input interface 2, a multi-level external trigger interface 3, a main control board power supply interface 4, a system configuration USB interface 5, a synchronous software trigger output interface 6, a synchronous hardware trigger output interface 7 and a synchronous trigger cascade output interface 8 integrated on the same main control board PCB 1.

[0060] In an embodiment of the present invention, the synchronization trigger supports four working modes, which are dynamically switched by the configuration module, wherein: Mode 1: Receiver mode, the synchronous trigger acts as an independent receiving host, receives an external trigger signal and forwards it to the controlled device through the output interface module. The external trigger signal is input through any interface of the multi-level input interface module; Mode 2: Receiver cascade mode, multiple synchronization triggers are cascaded, one of which is connected to the external trigger interface as the receiving master, and the rest are connected to the trigger cascade input interface and output interface as receiving slaves to achieve multi-device synchronization; Mode 3: Control host mode, the synchronization trigger uses the internal timer module to actively generate a trigger signal and controls the controlled device through the output interface module; Mode 4: Control host cascade mode, multiple synchronization triggers are cascaded, one of which acts as a control host to generate a trigger signal and transmit it through the cascade interface, and the rest act as slaves to receive signals, thereby realizing synchronous control of multiple devices.

[0061] The synchronization trigger of the present invention can have multiple usage modes through combination. Usage mode 1, the synchronization trigger is used as a receiver. Usage mode 2, the synchronization trigger is used as a cascade mode of the receiver. Usage mode 3, the synchronization trigger is used as a control host. Usage mode 4, the synchronization trigger is used as a cascade mode of the control host. Specifically: Using mode 1, the synchronous trigger is used as a receiver. The synchronous trigger designed by this system can be used alone as a synchronous trigger signal receiving host to connect to the external trigger interface to receive the trigger signal sent externally. The interface form of the externally sent trigger signal can choose to use different types of trigger input interfaces such as LVDS trigger input interface, RS422 trigger input interface, RS485 trigger input interface, RS232 trigger input interface, TTL / CMOS trigger input interface, etc. For the controlled device, the system parameter configuration of the synchronous trigger can be used to select the software trigger, hardware trigger and trigger waveform thermal characteristics supported by the controlled device. The connection of the synchronous trigger as a receiver is as follows: Figure 2 shown.

[0062] Using mode 2, the synchronous trigger is used as the cascade mode of the receiver. The synchronous trigger designed by this system can also realize the synchronous trigger control of multiple devices through the trigger cascade interface. The synchronous trigger cascade mode is as follows Figure 2 As shown. In cascade mode, only the trigger that serves as the synchronous trigger receiving host is connected to the external trigger interface, and other synchronous triggers are connected as receiving slaves using the trigger cascade interface. For the controlled device, the system parameter configuration of the synchronous trigger can be used to select the software trigger, hardware trigger, and trigger waveform thermal characteristics supported by the controlled device. The cascade mode of the synchronous trigger as a receiver is connected as shown below. Figure 3 shown.

[0063] Using mode 3, the synchronous trigger is used as the control host. The synchronous trigger designed by this system can also be used independently. In the absence of an external trigger signal, it can be used as a control host of a synchronous trigger signal to achieve synchronous control of the controlled device. The device uses the internal timer to set the waveform thermal characteristics of the trigger signal. For the controlled device, the system parameter configuration of the synchronous trigger can be used to select the software trigger, hardware trigger and trigger waveform thermal characteristics supported by the controlled device. The connection of the synchronous trigger as a control host is as follows: Figure 4 shown.

[0064] Using mode 4, the synchronous trigger is used as the cascade mode of the control host. The synchronous trigger designed by this system can also be used independently in conjunction with the trigger cascade interface to achieve synchronous trigger control of multiple devices in the absence of an external trigger signal. The synchronous trigger control host uses the internal timer Timer to set the waveform thermal characteristics of the trigger signal, and other synchronous triggers are connected as receiving slaves using the trigger cascade interface. For the controlled device, the system parameter configuration of the synchronous trigger can be used to select the software trigger, hardware trigger and trigger waveform thermal characteristics that the controlled device can support. The connection of the synchronous trigger as the cascade mode of the control host is as follows: Figure 5 shown.

[0065] Among them, see Figure 6 As shown, the configuration process of the configuration module includes: Working mode configuration, select control host working mode, receiving host working mode or receiving slave working mode; Input mode configuration, select synchronous trigger cascade input mode, LVDS trigger input mode, RS422 trigger input mode, RS485 trigger input mode, RS232 trigger input mode or TTL / CMOS trigger input mode; Output mode configuration, select synchronous trigger cascade output mode, synchronous software trigger output mode or synchronous hardware trigger output mode; Trigger thermal characteristics configuration, set trigger level, trigger mode, positive pulse selection, negative pulse selection or pulse width; After configuration is completed, the parameters are stored in the FLASH storage module.

[0066] In this invention, the trigger control system configuration includes the following configuration interface. During initial use, the operating mode, input mode, output mode, and trigger thermal characteristics must be configured based on the device's usage scenario and operating mode. Once configured, the system configuration parameters are saved in the internal FLASH memory of the main control chip.

[0067] In this embodiment, the configuration module includes a synchronous software trigger processing circuit, which uses a CH340 chip to implement the USB to serial port function for host computer communication and mode configuration; the workflow of the synchronous software trigger processing circuit includes: system power-on initialization and reading of FLASH parameters; detection of mode configuration requirements; updating of working mode, input mode, output mode or triggering thermal characteristics according to serial port or host computer commands; after entering the working state, using an internal timer to generate a trigger signal in the control host mode, and detecting and forwarding the trigger signal in the receiving host / slave mode.

[0068] The present invention supports the free selection of multiple trigger input interfaces and trigger output interfaces through the software configuration of the ARM controller, and can realize dynamic switching of multi-level interfaces, solving the problem of poor compatibility of traditional TTL level interfaces, adapting to different equipment level standards, and seamlessly switching interface types in complex industrial environments without replacing hardware. In addition, to address the problems of long-distance transmission and electromagnetic interference, the present invention integrates a high-anti-interference interface. The LVDS interface supports 400Mbps high-speed transmission and converts differential signals to CMOS levels through the DS90LV032 chip, significantly reducing the impact of noise; the RS422 / RS485 interface uses AM26LV32IDR and MAX3085EESA+T chips, supports ±15kV ESD protection, ensures stable signal transmission in harsh environments, and enhances anti-interference and signal stability.

[0069] The synchronous trigger control flow chart of the present invention is as follows: Figure 13 As shown, the following steps are included: When the system is initially powered on, the system default operating parameters are configured by reading the internal FLASH parameters.

[0070] During the initialization phase, the designed synchronous trigger mode configuration interface will be used to detect whether there is a mode configuration that needs to be set. If no configuration is required, it will directly enter the working state; If the mode configuration is needed, the working mode, input mode, output mode and trigger thermal characteristic of the system are configured according to the configuration command sent by the synchronous trigger mode configuration interface, and after the corresponding mode configuration is completed, the system enters into the working state.

[0071] The optional working mode configuration includes: control host working mode, receiving host working mode and receiving slave working mode. The optional input mode configuration includes: synchronous trigger cascade input mode, LVDS trigger input mode, RS422 trigger input mode, RS485 trigger input mode, RS232 trigger input mode and TTL / CMOS trigger input mode. The optional output mode configuration includes: synchronous trigger cascade output mode, synchronous software trigger output mode and synchronous hardware trigger output mode. The optional trigger thermal characteristic configuration includes: trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width. All the configurations can be completed by the upper computer designed by the system or by directly sending the instruction set.

[0072] In the working state of the system, there are two main types: control host mode and receiving host / slave mode. In the control host mode, the system uses the internal timing Timer module of the ARM controller to actively generate the trigger signal according to the configuration parameters, and controls the controlled device to realize the synchronous trigger of the controlled device. In the receiving host / slave mode, the system detects the trigger signal according to the currently selected input interface and output interface, and completes the receiving and forwarding functions of the trigger signal.

[0073] The control software can be used to flexibly select different level standards of trigger interfaces according to control instructions, and can support different types of trigger input interfaces such as synchronous trigger cascade input interface, LVDS trigger input interface, RS422 trigger input interface, RS485 trigger input interface, RS232 trigger input interface, TTL / CMOS trigger input interface and the like. The control software can be used to flexibly select trigger output forms according to control instructions, and can support different types of trigger output interfaces such as synchronous software trigger output interface, synchronous hardware trigger trigger interface, synchronous trigger cascade output interface and the like. The control software can configure system parameters through the host computer and the serial port command, select different types of trigger input interfaces and trigger output interfaces. The control software can conveniently set the trigger pulse waveform characteristics, including trigger level, trigger mode, positive pulse selection, negative pulse selection, pulse width and the like. The control software can store the configured system parameters through the embedded software system design FLASH storage module. The control software can be used in combination with multiple use modes. Use mode 1: the synchronous trigger is used as a receiver. Use mode 2: the synchronous trigger is used as a cascade mode of a receiver. Use mode 3: the synchronous trigger is used as a control host. Use mode 4: the synchronous trigger is used as a cascade mode of a control host.

[0074] The waveform characteristics and mode switching parameters can be configured in real time through the host computer or the serial port command, and the configured parameters are automatically saved to the built-in FLASH of the ARM controller for FLASH parameter storage, so that repeated setting is not required after power failure. The four working modes of independent receiver, cascade receiver, independent control host and cascade control host cover all scenarios, have multi-mode coordination and cascade expansion capabilities, all interfaces are integrated in a single board design, the volume is reduced and the assembly cost is reduced, the FLASH parameters are automatically loaded in the control process, the configuration requirements are detected, the working state is supported to be switched in real time, and a high-reliability synchronous trigger solution is provided for the fields of intelligent manufacturing, medical instruments, automation testing and the like.

[0075] The above is the exemplary embodiment disclosed by the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present application defined by the claims. The functions, steps and / or actions of the method claims described herein do not need to be performed in any particular order. In addition, although the elements of the embodiments disclosed by the present application can be described or claimed in singular form, they can also be understood as plural unless explicitly limited to singular.

[0076] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0077] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to limit the scope of the disclosure of the present invention (including the claims) to these examples. Within the spirit of the present invention, the technical features of the above embodiments or different embodiments may be combined, and many other variations exist in different aspects of the above embodiments, which are not provided in detail for the sake of clarity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A synchronous trigger with a configurable multi-level interface based on an ARM controller, characterized in that: It includes an ARM controller, a multi-level input processing circuit, a multi-level output processing circuit, a multi-level input interface module, a multi-level output interface module and a FLASH storage module; the input end of the ARM controller is connected to the multi-level input processing circuit, the multi-level input processing circuit is connected to the multi-level input interface module, the output end of the ARM controller is connected to the multi-level output processing circuit, the multi-level output processing circuit is connected to the multi-level output interface module, and the ARM controller is connected to the FLASH storage module; Among them, the multi-level input processing circuit includes a synchronous trigger cascade processing circuit, an LVDS trigger processing circuit, an RS422 trigger processing circuit, an RS485 trigger processing circuit, an RS232 trigger processing circuit and a TTL / CMOS trigger processing circuit; the multi-level output processing circuit includes a synchronous trigger cascade processing circuit, a synchronous software trigger processing circuit, a synchronous hardware trigger processing circuit and a synchronous trigger mode configuration circuit.

2. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 1, characterized in that: The ARM controller is a GD32F103C8T6 controller or an STM32F103C8T6 controller. The peripheral circuit of the ARM controller is designed based on the GD32F103C8T6 chip and integrates a reset module, a startup mode module, an SPWM module, a power filter module, a crystal oscillator module, a power supply module and an ARM core module. It is used to select trigger interfaces and trigger output forms of different level standards according to control instructions, and configure system parameters through a host computer and serial port commands to select different types of trigger input interfaces, trigger output interfaces and trigger pulse waveform characteristics.

3. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 2, characterized in that: The FLASH storage module is set in the configuration module of the ARM core module, and is used to configure the working mode, input mode, output mode and trigger thermal characteristic parameters through the host computer or serial port command. The trigger thermal characteristic parameters include trigger level, trigger mode, positive pulse selection, negative pulse selection and pulse width.

4. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 3, characterized in that: The multi-level input interface module is used to receive an external trigger signal. The multi-level input interface module supports at least six configurable level standards, including a synchronous trigger cascade input interface, an LVDS trigger input interface, an RS422 trigger input interface, an RS485 trigger input interface, an RS232 trigger input interface, and a TTL / CMOS trigger input interface, and is respectively connected to the synchronous trigger cascade processing circuit, the LVDS trigger processing circuit, the RS422 trigger processing circuit, the RS485 trigger processing circuit, the RS232 trigger processing circuit, and the TTL / CMOS trigger processing circuit of the multi-level input processing circuit.

5. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 4, characterized in that: The LVDS trigger input interface adopts the DS90LV032 differential receiver chip, the RS422 trigger input interface adopts the AM26LV32IDR differential receiver chip, the RS485 trigger input interface adopts the MAX3085EESA+T differential receiver chip, and the RS232 trigger input interface adopts the MAX3232 chip.

6. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 1, characterized in that: The multi-level input interface module and the multi-level output interface module include a bus driver circuit, which uses a SN74AHCT16245DGGR chip for digital signal buffering and level conversion.

7. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 6, characterized in that: The multi-level output interface module is used to output a trigger signal to the controlled device. The multi-level output interface module supports at least four configurable output forms, including a synchronous trigger cascade output interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface and a synchronous trigger mode configuration interface. The synchronous trigger cascade output interface is connected to the cascade device, the synchronous software trigger output interface and the synchronous hardware trigger output interface are connected to the controlled device, and the synchronous trigger mode configuration interface is connected to the host computer configuration software.

8. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 1, characterized in that: The synchronous trigger with a configurable multi-level interface also includes a physical structure module, which includes a main control board PCB, an outer shell, a front panel, a rear panel and multiple interface components. The interface components include an external trigger cascade signal input interface, a multi-level external trigger interface, a main control board power supply interface, a system configuration USB interface, a synchronous software trigger output interface, a synchronous hardware trigger output interface and a synchronous trigger cascade output interface integrated on the same main control board PCB.

9. The synchronous trigger with configurable multi-level interface based on ARM controller as claimed in claim 3, characterized in that: The synchronization trigger supports four working modes, which are dynamically switched by the configuration module, among which: Mode 1: Receiver mode, the synchronous trigger acts as an independent receiving host, receives an external trigger signal and forwards it to the controlled device through the output interface module. The external trigger signal is input through any interface of the multi-level input interface module; Mode 2: Receiver cascade mode, multiple synchronization triggers are cascaded, one of which is connected to the external trigger interface as the receiving master, and the rest are connected to the trigger cascade input interface and output interface as receiving slaves to achieve multi-device synchronization; Mode 3: Control host mode, the synchronization trigger uses the internal timer module to actively generate a trigger signal and controls the controlled device through the output interface module; Mode 4: Control host cascade mode, multiple synchronization triggers are cascaded, one of which acts as a control host to generate a trigger signal and transmit it through the cascade interface, and the rest act as slaves to receive signals, thereby realizing synchronous control of multiple devices.

10. The synchronous trigger with configurable multi-level interface based on ARM controller according to claim 9, characterized in that: The configuration process of the configuration module includes: Working mode configuration, select control host working mode, receiving host working mode or receiving slave working mode; Input mode configuration, select synchronous trigger cascade input mode, LVDS trigger input mode, RS422 trigger input mode, RS485 trigger input mode, RS232 trigger input mode or TTL / CMOS trigger input mode; Output mode configuration, select synchronous trigger cascade output mode, synchronous software trigger output mode or synchronous hardware trigger output mode; Trigger thermal characteristics configuration, set trigger level, trigger mode, positive pulse selection, negative pulse selection or pulse width; After configuration is completed, the parameters are stored in the FLASH storage module.

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