A method for accessing device registers, an electronic device, and a storage medium.

Abstract

This application relates to a method for accessing device registers, an electronic device, and a storage medium, belonging to the field of memory. The method includes: receiving a write access request from a processor, wherein the write access request includes a register address and a data field, the data field including a memory address and a data length; if the write access request is a special write access request, identifying the true intent of the special write access request; if the true intent of the special write access request is a read access, reading data with a length consistent with the data length starting from the register corresponding to the register address, and storing the read data into the memory corresponding to the memory address. This application enables one-time access to "ultra-long" data greater than 8 bytes. When multiple (e.g., more than two) registers with consecutive addresses need to be accessed, it is not necessary to access the registers in multiple steps, but can access multiple registers at once, thereby greatly improving access efficiency.

Description

Technical Field

[0001] This application belongs to the field of memory, specifically relating to a method for accessing device registers, an electronic device, and a storage medium. Background Technology

[0002] The common interface between the Central Processing Unit (CPU) and I / O (Input / Output) devices is the register. I / O devices typically provide a series of registers for hardware to complete specific tasks, query the status of task execution, and identify problems encountered during execution. Taking a network interface card (NIC) as an example, a NIC typically provides a series of status registers such as a receive counter, a send counter, a receive error counter, and a send error counter, used to query the current operating status of the NIC.

[0003] When the CPU needs to query network interface card (NIC) status information, it typically reads the NIC's status registers sequentially. Because the underlying PCI (Peripheral Component Interconnect) link of the NIC is a slower I / O bus compared to the CPU's internal bus, the CPU's access efficiency for each register access (typically 4 bytes) is low. The maximum data width of a typical CPU is generally 8 bytes (8 bytes = 64 bits), making it impossible for the CPU to access "ultra-long" data larger than 8 bytes at once. This necessitates accessing registers in multiple steps. When a large number of registers need to be accessed, this wastes a significant amount of PCI bandwidth and remains inefficient. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a method for accessing device registers, an electronic device, and a storage medium to improve the problems existing in the current register access methods when accessing a large number of registers.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, embodiments of this application provide a method for accessing device registers, the method comprising: receiving a write access request from a processor, wherein the write access request includes a register address and a data field, the data field including a memory address and a data length; if the write access request is a special write access request, identifying the true intent of the special write access request; if the true intent of the special write access request is a read access, reading data with a length consistent with the data length starting from the register corresponding to the register address, and storing the read data into the memory corresponding to the memory address.

[0007] In the above embodiments, in order to access multiple registers at once, the concept of a "special write access request" is proposed to distinguish it from a normal write access request. The data field of a "special write access request" contains different content than that of a normal write access request. The data field of a normal write access request only contains the data to be written, while the data field of a special write access request contains the memory address and data length, but does not contain the data to be written. At the same time, by using a "write instead of read" approach (the true intention of the special write access request is a read access), the device can access multiple registers at once and store the read data into the memory corresponding to the memory address. This enables the processor to access "ultra-long" data greater than 8 bytes at once, thereby greatly improving access efficiency.

[0008] In one possible implementation of the first aspect embodiment, the method further includes: if the true intent of the special write access request is a write access, reading data with a length consistent with the data length from the memory corresponding to the memory address, and performing write access on the register corresponding to the register address and subsequent registers based on the read data.

[0009] In the above embodiments, if the true intention of a special write access request is a write access, data with the same length as the data can be read directly from the memory corresponding to the memory address. Then, write access can be performed on the register corresponding to the register address and subsequent registers based on the read data, thereby achieving one-time access to multiple registers. When multiple (e.g., more than 2) consecutive registers need to be accessed, the above-mentioned "write instead of write" method can be used, eliminating the need to access registers in multiple steps, and allowing one-time access to multiple registers, thereby greatly improving access efficiency.

[0010] In one possible implementation of the first aspect embodiment, identifying the true intent of the special write access request includes: identifying whether the register address is a pre-defined special address; if the register address is a pre-defined special address, then determining that the special write access request is a read access.

[0011] In the above embodiments, a special address window can be allocated to the register that supports "write instead of read". By identifying whether the register address is a special address agreed upon, the true intention of the special write access request can be quickly determined to be a read access, thus distinguishing it from a normal write access request.

[0012] In one possible implementation of the first aspect embodiment, identifying the true intent of the special write access request includes: obtaining an operation identifier in the data field; and identifying the true intent of the special write access request based on the operation identifier.

[0013] In the above embodiments, the true intent of a special write access request can be represented by adding an operation identifier to the data field. For example, if the operation identifier is 1, the true intent is a write access; if the operation identifier is 0, the true intent is a read access (or vice versa). This allows the true intent of a special write access request to be quickly determined.

[0014] In one possible implementation of the first aspect embodiment, the method further includes: identifying whether the register address is a conventional special address; if the register address is a conventional special address, then determining that the write access request is a special write access request.

[0015] In the above embodiments, a special address window can be allocated to the register that supports "write instead of read" or "write instead of write". By identifying whether the register address is a special address as agreed, it is possible to quickly determine whether the write access request sent by the processor is a normal write access request or a "special write access request".

[0016] Secondly, embodiments of this application also provide a method for accessing device registers, comprising: generating a special write access request, wherein the special write access request includes a register address and a data field, the data field including a memory address and a data length; sending the special write access request to an I / O device, so that the I / O device executes the special write access request, reads data with a length consistent with the data length from the memory corresponding to the memory address, and performs write access on the register corresponding to the register address and subsequent registers according to the read data, or reads data with a length consistent with the data length starting from the register corresponding to the register address, and stores the read data into the memory corresponding to the memory address.

[0017] In one possible implementation of the second aspect embodiment, before generating a special write access request, the method further includes: determining that the number of registers that need to be accessed at once exceeds a target number; wherein the number of bytes corresponding to the target number of registers is less than the number of bytes corresponding to the data length.

[0018] In the above embodiments, the special write access request is used only when the number of registers to be accessed at one time exceeds the target number. If the number of registers to be accessed at one time is less than or equal to the target number, a normal read and write access is generated. This allows the device to access multiple registers at one time while being compatible with traditional access methods.

[0019] In one possible implementation of the second aspect embodiment, before sending the special write access request to the I / O device, the method further includes: if the true intent of the special write access request is a write access, storing the data to be written to the register into the memory corresponding to the memory address.

[0020] In the above embodiments, the true intent of the special write access request is a write access, which requires the data to be written to the register to be stored in the memory corresponding to the memory address in advance, so that the device can read the data from the memory corresponding to the memory address at one time after receiving the special write access request, in order to configure multiple registers.

[0021] Thirdly, embodiments of this application also provide an electronic device, including: a processor and an I / O device; the processor is configured to generate a special write access request and send the special write access request, wherein the special write access request includes a register address and a data field, and the data field includes a memory address and a data length; the I / O device is configured to receive a write access request from the processor; if the write access request is a special write access request, the true intent of the special write access request is identified; if the true intent of the special write access request is a read access, data with a length consistent with the data length is read from the register corresponding to the register address, and the read data is stored in the memory corresponding to the memory address.

[0022] Fourthly, embodiments of this application also provide an electronic device, including: a memory and a processor, the processor being connected to the memory; the memory being used to store a program; the processor being used to invoke the program stored in the memory to perform a method provided by any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment, or to perform a method provided by any possible implementation of the second aspect embodiment and / or in combination with the second aspect embodiment.

[0023] Fifthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon. When the computer program is run by a processor, it performs the method provided by any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment, or performs the method provided by any possible implementation of the second aspect embodiment and / or in combination with the second aspect embodiment.

[0024] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0026] Figure 1 A structural block diagram of an electronic device provided in an embodiment of this application is shown.

[0027] Figure 2 This illustration shows a schematic diagram of the principle of an address space corresponding to a register provided in an embodiment of this application.

[0028] Figure 3 This illustration shows a schematic diagram of the format of a data field provided in an embodiment of this application.

[0029] Figure 4 This illustration shows a schematic diagram of a write-to-read approach to accessing registers provided in an embodiment of this application.

[0030] Figure 5 A structural block diagram of an I / O device provided in an embodiment of this application is shown.

[0031] Figure 6 A flowchart illustrating a method for accessing a device register provided in an embodiment of this application is shown.

[0032] Figure 7 A flowchart illustrating another method for accessing device registers provided in an embodiment of this application is shown.

[0033] Figure 8 A structural block diagram of a device register access apparatus provided in an embodiment of this application is shown.

[0034] Figure 9 A structural block diagram of another electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0036] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0037] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0038] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0039] Given that current CPUs cannot access "ultra-long" data (greater than 8 bytes) in a single access to registers, multiple steps are required. When a large number of registers need to be accessed, this wastes significant PCI bandwidth and is inefficient. This application provides an efficient method for accessing device registers, enabling one-time access to "ultra-long" data (greater than 8 bytes). When multiple (e.g., more than two) contiguous registers need to be accessed, multiple registers can be accessed simultaneously without multiple steps, thus greatly improving access efficiency.

[0040] The following is combined with Figure 1 The electronic device involved in the device register access method provided in the embodiments of this application will be described. This electronic device includes a processor and I / O devices. The processor includes, but is not limited to, a CPU. I / O devices may include PCIe (PCI express) devices, including, but not limited to, network interface cards (NICs), graphics cards, etc. The processor included in a graphics card may be a graphics processing unit (GPU), etc. The processor included in a network interface card may be a dedicated network processor (NP), etc.

[0041] In some implementations, the electronic device also includes an RC (Root Complex), which is a key hub connecting the processor and PCIe devices. It can convert requests issued by the CPU into a format that the PCIe devices can recognize and route them to the correct PCIe devices. It can also handle DMA (Direct Memory Access) requests issued by PCIe devices to ensure that data reaches memory directly.

[0042] The processor is used to generate and send special write access requests, wherein the special write access request contains a register address and a data field, and the data field contains a memory address and a data length. It is understood that the processor can also be used to generate normal write access requests; however, normal write access requests are not the focus of this application and will not be discussed further.

[0043] In some possible implementations, the processor determines that the number of registers to be accessed at once exceeds a target number before generating a special write access request; wherein the number of bytes corresponding to the target number of registers is less than the number of bytes corresponding to the data length. In this implementation, a special write access request is only generated when the number of registers to be accessed at once exceeds the target number (which could be 2). If the number of registers to be accessed at once is less than or equal to the target number, a normal read / write access is generated.

[0044] It is understandable that if the number of registers accessed at one time is less than or equal to the target number, the "special write access" shown in this application can also be used for access.

[0045] If the true intent of a special write access request is a write access, the processor needs to store the data to be written to the register into the memory corresponding to the memory address before sending the special write access request to the I / O device.

[0046] An I / O device is used to receive write access requests from the processor. If the write access request is a special write access request, it identifies the true intent of the special write access request. If the true intent of the special write access request is a read access, it reads data with a length matching the specified data length, starting from the register corresponding to the register address, and stores the read data into the memory corresponding to the memory address. The I / O device is also used to, if the true intent of the special write access request is a write access, read data with a length matching the specified data length from the memory corresponding to the memory address, and perform write accesses on the register corresponding to the register address and subsequent registers based on the read data. In this embodiment, the I / O device is an I / O device that supports DMA functionality, capable of directly reading data from the memory corresponding to the memory address, or directly writing data to the memory corresponding to the memory address.

[0047] When writing to the register corresponding to the register address and subsequent registers based on the read data, the number of registers accessed depends on the length of the data. For example, if the data length is 24 bytes, then 6 registers can be accessed (the size of a register is usually 4 bytes).

[0048] To enable simultaneous access to multiple registers, this application proposes the concept of a "special write access request" to distinguish it from a normal write access request. A special write access request is relative to a normal write access request, and its true intent may simply be a read access (which can be termed "write instead of read").

[0049] In some possible implementations, the true intent of a special write access request can be a read access (which can be called "write instead of read") or a write access (which can be called "write instead of write"), depending on the operation identifier carried in the data field. The true intent of a normal write access request, however, is simply a write access, and its principle differs from that of "write instead of write".

[0050] The data format for a special write access request is the same as that for a normal write access request, both including a write identifier, a register address, and a data field of a specified length. The differences are: the register address is different from that of a normal write access request, the content of the data field is different, and the specified length is different. The specified length of the data field in a normal write access request is less than or equal to 8 bytes, while the specified length of the data field in a special write access request is equal to 8 bytes.

[0051] Normal write access requests use normal register addresses, while special write access requests use pre-agreed special register addresses. These special register addresses can be agreed upon beforehand between the processor and the PCIe device. For registers that support "write-for-read" or "write-for-write" operations, a special address window can be allocated. Only registers falling within this address window will be accessed via "write-for-read" or "write-for-write," while the remaining address space maintains normal register read / write behavior. In short, registers supporting "write-for-read" or "write-for-write" operations can have two addresses: one for normal read / write operations (e.g., normal register address space) and one for special write access operations (e.g., special register address space). Figure 2 As shown, R0, R1, ... R85 are all registers of the I / O device. Registers R80 and later support "write instead of read" or "write instead of read". In addition to normal register addresses, they also have special register addresses.

[0052] A normal write access request's data field contains only the data to be written. For example, a normal write access request's data field is 4 bytes, all of which is the data to be written. A special write access request's data field contains the memory address and data length, but may not contain the data to be written. Furthermore, in some possible implementations, the data field of a special write access request may also include an operation identifier (such as an op identifier). This operation identifier is used to identify the true intent of the special write access request. For example, if the operation identifier is 1, the true intent is a write access (write); if the operation identifier is 0, the true intent is a read access (read), and vice versa.

[0053] In one implementation, the content of the data field in the special write access request is as follows: Figure 3 As shown, the OP identifier is used to indicate the true intent of a special write access request, pa represents the memory address, and size (size) represents the data length.

[0054] When an I / O device identifies whether a write access request sent by the processor is a special write access request, one possible implementation is to identify whether the register address in the write access request is a pre-defined special address; if the register address is a pre-defined special address, then the write access request is determined to be a special write access request, otherwise it is a normal write access request.

[0055] When an I / O device identifies the true intent of a special write access request, in one possible implementation, if the true intent of the special write access request is only a read access, it can identify whether the register address is a pre-defined special address; if the register address is a pre-defined special address, then the special write access request is determined to be a read access.

[0056] In another possible implementation, if the operation identifier in the data field is specifically obtained, the true intent of the special write access request can be identified based on the operation identifier. For example, if the operation identifier is 1, the true intent is a write access, and if the operation identifier is 0, the true intent is a read access.

[0057] To facilitate understanding, examples are provided below. Figure 4As shown, R0, R1, ..., R85 are all registers of the I / O device. When the processor needs to obtain data from the six registers R80, R81, ..., R85, a normal read access would require three read operations. Since the processor's maximum data width is 8 bytes and each register's data length is 4 bytes, a traditional read operation can only access a maximum of two registers. To access all six registers, three read operations are required. However, using the "write-instead-of-read" method described in this application, only one access operation is needed to obtain the data from these six registers. The processor needs to convert the original read operation into a special write access operation by sending a special write access request.

[0058] in, Figure 4 In a special write access request, `write` indicates a write flag, `R80` is the register address, and `64bitsdate` represents a 64-bit (8-byte) data field. The data format of a normal write access request also includes... Figure 4 The write flag, R8 register address, and specified length (usually less than or equal to 8 bytes) shown indicate that in a normal write access request, the date field contains all the data to be written, while in a special write access request, the data field format is as follows: Figure 3 As shown, the `op` field is set to 0 to tell the device that this is actually a "read" operation. `size` indicates the length of the data to be read, such as 24 bytes. `pa` is a physical address of a block of CPU main memory used to store the read content. When the device receives this "special write" request, it can parse the 64-bit `data` field to reconstruct the processor's true intention: to read the six registers starting at R80. The device will then directly write the contents of R80 to R85 into the CPU main memory identified by `pa`, thereby greatly improving register access efficiency.

[0059] The aforementioned I / O devices can be graphics cards or network cards, such as... Figure 5 As shown, the I / O device may include: a read / write controller, registers, and a DMA controller. The read / write controller can access registers directly or through the DMA controller. The read / write controller is mainly responsible for normal read and write access to registers, while the DMA controller mainly handles special write access, namely, the aforementioned "write-instead-of-write" or "write-instead-of-read". It is responsible for reading data from the memory corresponding to the memory address and performing write access to the register corresponding to the register address and subsequent registers based on the read data, or directly writing the data read from the register to the memory corresponding to the memory address.

[0060] For example, a read / write controller receives write access requests from the processor. If the write access request is a special write access request, it identifies the true intent of the special write access request. If the true intent of the special write access request is a read access, the read / write controller, through the DMA controller, reads data of the same length as the data from the register corresponding to the register address, and stores the read data into the memory at the corresponding memory address. If the true intent of the special write access request is a write access, the read / write controller, through the DMA controller, reads data of the same length as the data from the memory at the corresponding memory address, and performs write accesses on the register corresponding to the register address and subsequent registers based on the read data.

[0061] In one possible implementation, when the read / write controller identifies the true intent of a special write access request, it may identify whether the register address is a pre-defined special address; if the register address is a pre-defined special address, then the special write access request is determined to be a read access. In another possible implementation, it may obtain an operation identifier from a data field and identify the true intent of the special write access request based on the operation identifier.

[0062] The read / write controller can identify whether a received write access request is a special write access request by recognizing whether the register address is a pre-defined special address; if the register address is a pre-defined special address, then the write access request is determined to be a special write access request.

[0063] This application also provides a method for accessing device registers of I / O devices, which will be described below in conjunction with... Figure 6 The method will be explained.

[0064] S1: Receive write access requests from the processor.

[0065] Write access requests from the processor can be normal write access requests or special write access requests. If it is a special write access request, the write access request includes a register address and a data field, and the data field includes the memory address and the data length.

[0066] Upon receiving a write access request from the processor, it can identify whether the register address is a pre-defined special address. If the register address is a pre-defined special address, then the write access request is determined to be a special write access request.

[0067] S2: If the write access request is a special write access request, then identify the true intent of the special write access request.

[0068] If the write access request is a special write access request, then identify the true intent of the special write access request.

[0069] In one possible implementation, the process of S2 includes: identifying whether the register address is a pre-defined special address; if the register address is a pre-defined special address, then determining that the special write access request is a read access. It should be noted that in this implementation, the true intent of the special write access request is only a read access.

[0070] In one possible implementation, the process of S2 includes: obtaining the operation identifier from the data field; and identifying the true intent of a specific write access request based on the operation identifier. For example, if the operation identifier is 1, the true intent is a write access; if the operation identifier is 0, the true intent is a read access.

[0071] S3: If the true intention of the special write access request is a read access, start from the register corresponding to the register address, read data with a length consistent with the data length, and store the read data into the memory corresponding to the memory address.

[0072] If the true intent of a special write access request is a read access, then data of the same length as the data is read from the register corresponding to the register address, and the read data is stored in the memory at the corresponding memory address. For example, with Figure 4 For example, starting from R80, a data length of 24 bytes is read. Since the size of each register is 4 bytes, the device will read the contents of R80 to R85 and store the read data into the memory corresponding to the memory address.

[0073] If the true intent of the special write access request is a write access, the method further includes: reading data of the same length as the data length from the memory corresponding to the memory address, and performing write access on the register corresponding to the register address and subsequent registers based on the read data. Let's take... Figure 4 For example, assuming the data length is 24 bytes, 24 bytes of data will be read from memory. Then, the registers corresponding to the read register addresses and subsequent registers will be written to based on the read data. Since each register is 4 bytes in size, the device will write to the contents of R80 to R85 based on the read data.

[0074] This application also provides a method for accessing device registers that can be applied to the aforementioned processor, as described below. Figure 7 This access method is explained.

[0075] S10: Generate a special write access request.

[0076] A special write access request includes a register address and a data field, where the data field contains the memory address and data length. In some possible implementations, the data field may also include an OP identifier.

[0077] In one possible implementation, before generating a special write access request, the method further includes: determining that the number of registers that need to be accessed at once exceeds a target number; wherein the number of bytes corresponding to the target number of registers is less than the number of bytes corresponding to the data length.

[0078] S20: Send the special write access request to the IO device so that the IO device executes the special write access request.

[0079] After generating a special write access request, a special write access request is sent to the I / O device so that the I / O device can execute the special write access request, read data with the same length as the data from the memory corresponding to the memory address, and perform write access on the register corresponding to the register address and subsequent registers according to the read data, or read data with the same length as the data from the register corresponding to the register address and store the read data in the memory corresponding to the memory address.

[0080] In one possible implementation, before sending the special write access request to the I / O device, the method further includes: if the true intent of the special write access request is a write access, storing the data to be written to the register into the memory corresponding to the memory address.

[0081] The access method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned electronic device embodiment. For the sake of brevity, any part not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned electronic device embodiment.

[0082] This application also provides a device register access device, such as... Figure 8 As shown, the access device includes a generation module and a sending module. In one possible implementation, the access device further includes a writing module.

[0083] A generation module is used to generate a special write access request, wherein the special write access request includes a register address and a data field, and the data field includes a memory address and a data length.

[0084] The sending module is used to send the special write access request to the I / O device so that the I / O device executes the special write access request.

[0085] The write module is used to store the data to be written to the register into the memory corresponding to the memory address if the true intent of the special write access request is a write access.

[0086] In one possible implementation, the generation module is further configured to determine, before generating a special write access request, that the number of registers to be accessed at one time exceeds a target number; wherein the number of bytes corresponding to the target number of registers is less than the number of bytes corresponding to the data length.

[0087] like Figure 9 As shown, Figure 9 This diagram illustrates a structural block diagram of an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0088] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, which include at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the software functional modules or computer programs stored in the memory 220. For example, the processor 240 is used to execute the aforementioned device register access method.

[0089] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0090] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.

[0091] Among them, the aforementioned electronic devices 200 include, but are not limited to, mobile phones, tablets, computers, servers, etc.

[0092] This application also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which, when run by a computer such as the electronic device 200 described above, executes the device register access method described above.

[0093] This application also provides a computer program product, which includes a computer program that, when executed by a computer, performs the device register access method described above.

[0094] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0096] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0097] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for accessing PCIe device registers, characterized in that, The method includes: Receive a write access request from the processor, wherein the write access request includes a register address and a data field, the data field including a memory address and a data length; If the write access request is a special write access request, then the true intent of the special write access request is identified, wherein the register address in the special write access request is a special address agreed upon in advance between the processor and the PCIe device; If the true intent of the special write access request is a read access, start from the register corresponding to the register address, read data with a length consistent with the data length, and store the read data into the memory corresponding to the memory address.

2. The method according to claim 1, characterized in that, The method further includes: If the true intent of the special write access request is a write access, read data with a length consistent with the data length from the memory corresponding to the memory address, and perform write access on the register corresponding to the register address and subsequent registers based on the read data.

3. The method according to claim 1, characterized in that, Identifying the true intent of the specific write access request includes: Identify whether the register address is a conventional special address; if the register address is a conventional special address, then determine that the special write access request is a read access.

4. The method according to claim 1, characterized in that, Identifying the true intent of the specific write access request includes: Retrieve the operation identifier from the data field; The true intent of the special write access request is identified based on the operation identifier.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: Identify whether the register address is a pre-defined special address; If the register address is a special address as agreed upon, then the write access request is determined to be a special write access request.

6. A method for accessing PCIe device registers, characterized in that, include: Generate a special write access request, wherein the special write access request includes a register address and a data field, the data field includes a memory address and a data length, wherein the register address in the special write access request is a special address agreed upon in advance between the processor and the PCIe device; Send the special write access request to the PCIe device so that the PCIe device executes the special write access request, reads data with the same length as the data length from the memory corresponding to the memory address, and performs write access to the register corresponding to the register address and subsequent registers according to the read data, or reads data with the same length as the data length starting from the register corresponding to the register address and stores the read data into the memory corresponding to the memory address.

7. The method according to claim 6, characterized in that, Before generating a special write access request, the method further includes: The number of registers that need to be accessed at once exceeds the target number; wherein the number of bytes corresponding to the target number of registers is less than the number of bytes corresponding to the data length.

8. The method according to claim 6, characterized in that, Before sending the special write access request to the PCIe device, the method further includes: If the true intent of the special write access request is a write access, the data to be written to the register will be stored in the memory corresponding to the memory address.

9. An electronic device, characterized in that, include: The processor is configured to generate a special write access request and send the special write access request, wherein the special write access request includes a register address and a data field, the data field includes a memory address and a data length, and the register address in the special write access request is a special address agreed upon in advance between the processor and the PCIe device. The PCIe device is used to receive write access requests from the processor; if the write access request is a special write access request, the true intent of the special write access request is identified; if the true intent of the special write access request is a read access, data with a length consistent with the data length is read from the register corresponding to the register address, and the read data is stored in the memory corresponding to the memory address.

10. An electronic device, characterized in that, include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-5, or to execute the method as described in any one of claims 6-8.

11. A computer-readable storage medium, characterized in that, It stores a computer program thereon, which, when executed by a processor, performs the method as described in any one of claims 1-5, or performs the method as described in any one of claims 6-8.

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