Data transmission method and device based on accelerator card

Abstract

The invention relates to the technical field of computer hardware acceleration and data processing, and discloses a data transmission method and device based on an accelerator card, and the method comprises the steps: collecting an original data stream of external equipment, carrying out the real-time feature analysis of the original data stream through a mode recognition engine, obtaining space-time related features, and carrying out the real-time feature analysis; performing binary coding on the space-time correlation features to obtain feature mark data; according to the instantaneous bandwidth of the M.2 interface and the load state of the AI chip, compressing the feature mark data into optimized compressed data by using a dynamic compression engine; inputting the optimized compressed data into a heterogeneous computing distributor so as to distribute a path selection instruction for the optimized compressed data through the heterogeneous computing distributor according to the feature marking type of the optimized compressed data; and according to the path selection instruction, completing data transmission of the optimized compressed data through the heterogeneous computing distributor to obtain a data transmission result. According to the method, the final data transmission result can meet the space-time consistency requirement of high-precision AI reasoning.

Description

Technical Field

[0001] The present invention relates to a data transmission method and device based on an accelerator card, belonging to the technical field of computer hardware acceleration and data processing. Background Art

[0002] Accelerator-based data transmission methods are a core technology for improving the performance of heterogeneous computing systems. M.2 accelerator cards serve as hardware hubs connecting external devices and AI chips, providing high-throughput data transmission capabilities through channels. In scenarios such as AI inference and real-time video analysis, massive amounts of raw data generated by external devices (such as sensors and cameras) need to be pre-processed by the accelerator card before being efficiently transmitted to the AI ​​chip. However, traditional transmission solutions face three challenges: dynamic bandwidth fluctuations leading to data accumulation, uneven computing load on AI chips causing processing delays, and performance loss caused by mismatches between data characteristics and computing resources. Therefore, an adaptive transmission method that can dynamically coordinate interface bandwidth, chip load, and data characteristics is urgently needed to achieve low-latency, high-precision end-to-end data processing.

[0003] The existing solution uses a fixed compression algorithm and cannot respond to the instantaneous bandwidth fluctuations of the M.2 interface. When the bandwidth drops sharply, the fixed compression ratio causes data packet transmission delays, which directly causes the time window of spatiotemporal feature analysis to be misaligned, reducing the accuracy of feature extraction. Due to the lack of a real-time feature analysis engine, invalid information in the original data stream is transmitted indiscriminately, which not only squeezes the limited bandwidth, but also causes the AI ​​chip to fall into invalid calculations and weakens the recognition accuracy of effective features. If the heterogeneous computing allocator does not dynamically perceive the AI ​​chip load, high-priority tasks may be assigned to overloaded computing units. This defect, when combined with the previous two, causes feature data to miss processing time, the spatiotemporal correlation to be broken, and the final output result deviates from the real scenario.

[0004] In summary, the core contradiction of existing technologies lies in the lack of a coordinated scheduling mechanism for the triple resources of bandwidth, data, and computing. Static compression, featureless filtering, and rigid path allocation form a cascading failure chain, which can be essentially attributed to insufficient system-level accuracy. Inaccurate bandwidth adaptation reduces feature timeliness, redundant data transmission dilutes feature density, and improper load distribution distorts feature calculation logic. The synergistic effect of these three makes it difficult for the final data transmission results to meet the spatiotemporal consistency requirements of high-precision AI reasoning. Summary of the Invention

[0005] The present invention provides a data transmission method and device based on an accelerator card, the main purpose of which is to ensure that the final data transmission results meet the spatiotemporal consistency requirements of high-precision AI reasoning.

[0006] To achieve the above-mentioned purpose, the present invention provides a data transmission method based on an accelerator card, comprising: Constructing a data transmission system, wherein the data transmission system includes an external device, an M.2 accelerator card, an M.2 interface, and an AI chip, wherein the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; Collecting the original data stream of the external device, performing real-time feature analysis on the original data stream through the pattern recognition engine to obtain spatiotemporal correlation features, and binary-encoding the spatiotemporal correlation features into feature tag data; Compressing the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip; Inputting the optimized compressed data into the heterogeneous computing distributor, so as to distribute a path selection instruction to the optimized compressed data through the heterogeneous computing distributor according to a feature tag type of the optimized compressed data; According to the path selection instruction, the data transmission of the optimized compressed data is completed through the heterogeneous computing distributor to obtain a data transmission result.

[0007] Optionally, the constructing of the data transmission system includes: Prepare external devices and M.2 accelerator cards; Deploying a pattern recognition engine in the front-end area of ​​the M.2 accelerator card; Deploying a dynamic compression engine in the middle area of ​​the M.2 accelerator card; Deploy a heterogeneous computing distributor in the back-end control area of ​​the M.2 accelerator card; Integrating an AI chip on the M.2 accelerator card; Constructing an M.2 interface connecting the external device and the M.2 accelerator card; A data transmission system is determined by the external device, the M.2 accelerator card, the M.2 interface, the AI ​​chip, the pattern recognition engine, the dynamic compression engine and the heterogeneous computing allocator.

[0008] Optionally, collecting the original data stream of the external device includes: Transmitting the original data stream of the external device to the M.2 accelerator card through the M.2 interface; The original data stream is received in the M.2 accelerator card through the M.2 interface to complete the process of collecting the original data stream of the external device.

[0009] Optionally, performing real-time feature analysis on the original data stream by the pattern recognition engine to obtain spatiotemporal correlation features includes: Using a bidirectional LSTM in the pattern recognition engine to capture inter-frame motion features of the original data stream; extracting the spatial distribution pattern of the original data stream using a convolution kernel in the pattern recognition engine; In the pattern recognition engine, the inter-frame motion features and the spatial distribution patterns are weightedly fused through an attention mechanism to obtain spatiotemporal correlation features.

[0010] Optionally, the binary encoding of the spatiotemporal correlation features into feature tag data includes: Extracting a timestamp, a feature type, and a spatial index from the spatiotemporal related features; encoding the timestamp as a 64-bit timer value; encoding the feature type as a type identifier; Encoding the spatial index as a coordinate hash value; Concatenating the 64-bit timer value, the type identifier, and the coordinate hash value to obtain a binary code; Generate a binary-coded check code using a CRC-8 check algorithm; The binary code and the check code are concatenated to obtain characteristic mark data.

[0011] Optionally, compressing the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip includes: When the instantaneous bandwidth is less than the preset bandwidth, the dynamic compression engine is used to call a tensor folding compression algorithm onboard the accelerator card of the M.2 accelerator card; While retaining the key motion vector of the coordinate hash value in the signature data, executing the tensor folding compression algorithm through the adjustable pipeline silicon chip onboard the accelerator card to reduce the dimension of the coordinate hash value in the signature data to obtain a reduced-dimensionality hash value; Based on the dimensionality reduction hash value, the process of compressing the feature-tagged data into optimized compressed data is completed; When the load state is greater than a preset load, using the dynamic compression engine to call the sparse matrix compression algorithm onboard the accelerator card; Counting the frequency of characteristic types of non-zero value elements in the characteristic tag data by using a hardware counter of the entropy coding coprocessor onboard the accelerator card; generating a priority queue of the non-zero valued elements using the feature type frequency; According to the priority queue and the Huffman tree generation rules pre-stored in the silicon chip ROM on the accelerator card, the fixed-length optimized coding table of the non-zero value elements is generated by using the Huffman coding in the sparse matrix compression algorithm; detecting zero-valued elements in the signature data; Generate a sparse coding matrix of the zero-valued elements by using run-length coding in the sparse matrix compression algorithm; The entropy coding coprocessor converts the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data.

[0012] Optionally, converting the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data by the entropy coding coprocessor includes: Obtain non-zero value elements and zero value elements in the feature tag data; After the entropy coding coprocessor receives the fixed-length optimized coding table and the sparse coding matrix, the entropy coding coprocessor uses the fixed-length optimized coding table to perform coding mapping on the non-zero value elements to obtain non-zero value codes; Performing encoding mapping on the zero-value elements using the sparse coding matrix to obtain zero-value codes; The entropy coding coprocessor is used to encapsulate the non-zero value code and the zero value code to obtain optimized compressed data.

[0013] Optionally, allocating a transmission path for the optimized compressed data by the heterogeneous computing allocator according to a feature tag type of the optimized compressed data includes: Inputting the feature tag type, the instantaneous bandwidth of the M.2 interface, and the load status of the AI ​​chip into a decision tree model of the heterogeneous computing distributor, so as to output a path selection instruction for optimizing the compressed data through the decision tree model; The path selection instruction includes a target device identifier, a transmission path identifier, a data packet identifier, and a task priority.

[0014] Optionally, completing the data transmission of the optimized compressed data through the heterogeneous computing distributor according to the path selection instruction to obtain a data transmission result includes: Parsing the path selection instruction by a control logic unit in the heterogeneous computing distributor to obtain parsed instruction information; activating the bus transmission logic corresponding to the parsed instruction information using the control logic unit; performing format conversion on the optimized compressed data according to the bus transmission logic to obtain format-converted data; Based on the target device, data packet identifier and task priority in the parsed instruction information, the format-converted data is transmitted through the bus transmission logic to obtain a data transmission result.

[0015] In order to solve the above problems, the present invention further provides a data transmission device based on an accelerator card, the device comprising: A system construction module for constructing a data transmission system, wherein the data transmission system includes an external device, an M.2 accelerator card, an M.2 interface, and an AI chip; the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; a feature encoding module, configured to collect the raw data stream of the external device, perform real-time feature analysis on the raw data stream through the pattern recognition engine to obtain spatiotemporal correlation features, and binary encode the spatiotemporal correlation features into feature tag data; a data compression module, configured to compress the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip; a path selection module, configured to input the optimized compressed data into the heterogeneous computing distributor, so as to allocate a path selection instruction to the optimized compressed data through the heterogeneous computing distributor according to a feature tag type of the optimized compressed data; The data transmission module is used to complete the data transmission of the optimized compressed data through the heterogeneous computing distributor according to the path selection instruction to obtain a data transmission result.

[0016] Compared with the problems described in the background technology, the embodiment of the present invention efficiently collects the original data stream of the external device through the M.2 interface, provides a basis for subsequent processing, is the starting point of the entire data transmission system, ensures the timely acquisition of data, and avoids problems such as processing delays caused by untimely data collection. Furthermore, the embodiment of the present invention solves the problem of "lack of real-time feature analysis engine" in the background technology through feature analysis, and can extract effective features from the original data stream in real time, filter out invalid information, reduce the amount of data for subsequent transmission and processing, improve the usefulness and processing efficiency of the data, avoid the AI ​​chip from falling into invalid calculations, and improve the recognition accuracy of effective features. Furthermore, the embodiment of the present invention generates structured feature marker data by binary encoding time-space related features, which is convenient for subsequent transmission and processing, improves the manageability and identifiability of data, and provides a convenient data format for subsequent compression and transmission operations. The embodiment of the present invention compresses the feature marker data into optimized compressed data by utilizing the dynamic compression engine, thereby overcoming the problem of "traditional transmission method" in the background technology. The embodiment of the present invention solves the problem of "the heterogeneous computing allocator fails to dynamically perceive the AI ​​chip load" in the background technology. The heterogeneous computing allocator dynamically allocates path selection instructions according to the feature tag type, thereby achieving reasonable allocation of computing resources, avoiding high-priority tasks from being allocated to overloaded computing units, and improving the overall efficiency of the system and the timeliness of data processing. The embodiment of the present invention completes data transmission by executing path selection instructions, achieving efficient and accurate data transmission, improving the reliability and accuracy of data transmission, ensuring that data can reach the target device in a timely and accurate manner, meeting the spatiotemporal consistency requirements of high-precision AI reasoning, improving the performance and effect of the entire data transmission system, and avoiding the problems of feature data missing processing time and spatiotemporal correlation being broken. Therefore, the data transmission method and device based on the accelerator card provided in the embodiment of the present invention can ensure that the final data transmission results meet the spatiotemporal consistency requirements of high-precision AI reasoning. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic flow chart of a data transmission method based on an accelerator card provided in one embodiment of the present invention; Figure 2 A schematic diagram of a sparse coding matrix for implementing the accelerator card-based data transmission device provided in one embodiment of the present invention; Figure 3A flowchart of an optimization compression data of the acceleration card-based data transmission device provided by an embodiment of the present application is shown in the figure. Figure 4 A module diagram of the acceleration card-based data transmission device provided by an embodiment of the present application is shown in the figure.

[0018] The object, functional characteristics and advantages of the present application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the present application and do not limit the present application.

[0020] Embodiments of the present application provide an acceleration card-based data transmission method. The execution subject of the acceleration card-based data transmission method includes but is not limited to at least one of electronic devices such as a server and a terminal which can be configured to execute the method provided by the embodiments of the present application. In other words, the acceleration card-based data transmission method can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0021] Embodiment 1 Referring to Figure 1 A flowchart of the acceleration card-based data transmission method provided by an embodiment of the present application is shown in the figure. In this embodiment, the acceleration card-based data transmission method includes: S1, constructing a data transmission system, wherein the data transmission system includes an external device, an M.2 acceleration card, an M.2 interface, an AI chip, the M.2 acceleration card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor.

[0022] In an embodiment of the present application, the construction of the data transmission system includes: preparing an external device and an M.2 acceleration card; deploying a pattern recognition engine in the front-end area of the M.2 acceleration card; deploying a dynamic compression engine in the middle area of the M.2 acceleration card; deploying a heterogeneous computing distributor in the back-end control area of the M.2 acceleration card; integrating an AI chip on the M.2 acceleration card; constructing an M.2 interface connecting the external device and the M.2 acceleration card; determining a data transmission system through the external device, the M.2 acceleration card, the M.2 interface, the AI chip, the pattern recognition engine, the dynamic compression engine and the heterogeneous computing distributor.

[0023] Among them, the external device refers to a data generation device connected to the M.2 accelerator card through the M.2 interface, which is used to collect raw data streams. Typical devices include high-frame rate cameras in the industrial field, CT / MRI image acquisition devices in the medical field, and lidar point cloud generators in the field of autonomous driving. High-frame rate cameras such as 4K@120fps visual sensors are connected to the accelerator card through the M.2 interface and are used to collect image data in industrial production. CT / MRI image acquisition devices transmit medical image data to the accelerator card through the M.2 interface, and lidar point cloud generators send point cloud data to the accelerator card through the M.2 interface.

[0024] Furthermore, the pattern recognition engine is deployed in the programmable logic unit in the front-end area of ​​the M.2 accelerator card, and its functions are realized based on the CLB (configurable logic block) array of FPGA (field programmable logic array). FPGA provides high flexibility and programmability, allowing users to customize hardware logic according to specific application requirements. In addition, the pattern recognition engine contains 3×3 To 7×7 adjustable convolution kernel, the convolution kernel is a matrix used for feature extraction, and its size can be adjusted according to specific application requirements to capture different features in the data. The pattern recognition engine is directly connected to the M.2 interface PHY layer through the 40Gbps on-chip network (NoC), ensuring high speed and low latency of data transmission. The PHY layer is responsible for the transmission and reception of physical signals. The pattern recognition engine is responsible for receiving the original data stream from the external device and performing real-time feature analysis. It is responsible for real-time feature analysis of the original data stream, extracting spatiotemporal correlation features, and generating feature labeling data. The specific functions include using bidirectional LSTM to capture inter-frame motion features, using convolution kernels to extract spatial distribution patterns, and weighted fusion of these features through the attention mechanism. The use of bidirectional LSTM to capture inter-frame motion features is based on the RNN unit deployed in the pattern recognition engine. Specifically, it is achieved through the programmable logic array of FPGA. The flexible hardware resources of the FPGA are used to build RNN units to process sequence data. The parallel computing capability and customizability of the FPGA enable the RNN unit to efficiently capture inter-frame motion features. The use of convolution kernels to extract spatial distribution patterns is based on the convolution kernels deployed in the pattern recognition engine. The convolution kernel is a hardware module inside the FPGA and is composed of configurable logic blocks (CLBs). By programming the size (such as 3×3 to 7×7) and parameters of the convolution kernel, the spatial distribution patterns in the data can be flexibly extracted. The weighted fusion of these features through the attention mechanism is based on the attention weight calculation unit deployed in the pattern recognition engine. This unit is also built by the FPGA's CLB array and is specifically used to perform weight calculations in the attention mechanism. It receives output features from bidirectional LSTM units and convolution kernels, calculates the weight of each feature, and then performs weighted fusion to generate more discriminative spatiotemporal correlation features.

[0025] Furthermore, the dynamic compression engine refers to a compression processing module deployed in the middle area of ​​the M.2 accelerator card, which adopts a dual-channel pipeline architecture. The lossless compression channel is based on a static pipeline of entropy coding, and the lossy compression channel is a dynamically adjustable pipeline. The lossless compression channel is a 5-level fixed pipeline, which is implemented by an onboard entropy coding ASIC. The static pipeline of entropy coding is mainly composed of a dedicated entropy coding coprocessor, which includes a control unit, a coding lookup table and a data cache. The control unit is responsible for managing the coding process, the coding lookup table is used to store predefined coding rules, and the data cache is used to temporarily store the data to be encoded. The lossy compression channel is an adjustable pipeline, which is built based on the FPGA dynamic logic area and is directly connected to the bandwidth monitoring circuit through a PHY layer probe. The bandwidth monitoring circuit is an analog-digital hybrid circuit integrated in the PHY layer of the M.2 interface. It monitors the bandwidth usage and physical layer bit error rate of the M.2 interface in real time, and provides accurate bandwidth measurement data with a measurement error of less than 3%. The system's dynamic bandwidth perception and adaptive compression functions provide critical real-time feedback. The dynamic compression engine can adaptively select a combination of compression algorithms such as tensor folding compression algorithm and sparse matrix compression algorithm based on the instantaneous bandwidth measurement value of the M.2 interface and the load status of the AI ​​chip to compress feature-tagged data into optimized compressed data. The adjustable pipeline controller dynamically adjusts the number of pipeline levels and configuration according to the instantaneous bandwidth measurement value of the M.2 interface to optimize compression performance. In addition, the dynamic compression engine also includes a tensor folding accelerator and a sparse matrix encoder. The tensor folding accelerator is responsible for performing tensor dimension folding operations and is implemented by a dedicated hardware circuit. It can reduce the dimensionality of high-dimensional data while retaining key feature information. The sparse matrix encoder is used to implement the sparse matrix compression algorithm and includes a hardware-implemented Huffman encoder and a run-length encoder. The Huffman encoder constructs a Huffman tree and generates a coding table based on the feature type distribution. The run-length encoder efficiently encodes zero-value elements.

[0026] Furthermore, the heterogeneous computing distributor is located in the back-end control area of ​​the M.2 accelerator card. Its firmware carrier is the RISC-V MCU integrated in the accelerator card main control chip. It is bidirectionally connected via the AXI-Stream bus, with the upstream connection to the dynamic compression engine output end and the downstream connection to the AI ​​chip MAC array and the host PCIe interface. It has a built-in lightweight decision tree model and a control logic unit, as well as a task scheduling unit and a task distribution bus interface. It allocates a transmission path for optimized compressed data based on information such as the feature tag type. The decision tree model is deployed in the RISC-V On the MCU, it utilizes the processing power and storage resources of the MCU. By running a lightweight decision tree algorithm on the MCU, the model can quickly make resource scheduling decisions based on the input feature vector (such as feature tag type, NPU load, PCIe bandwidth, etc.). The control logic unit is implemented by a dedicated control circuit, which includes an instruction parser and a command generator. The instruction parser is responsible for parsing the path selection instructions output by the decision tree model and extracting key information such as the target device identifier and the transmission path identifier. The command generator generates specific control commands based on the parsed instructions. The task scheduling unit is implemented based on a priority queue and a timing controller. The priority queue is used to manage tasks of different priorities, and the timing controller ensures that high-priority tasks can be processed in a timely manner. The task distribution bus interface consists of an AXI-Stream protocol multiplexer and a data format converter. The multiplexer is responsible for switching between different transmission paths, and the data format converter ensures that data can be converted between different bus protocols.

[0027] Furthermore, the M.2 interface refers to an enhanced interface module based on the M.2 physical specification, which not only includes a standard M.2 physical interface for connecting external devices and M.2 accelerator cards, but also integrates dedicated interface circuits, such as bandwidth monitoring circuits and status feedback channels. The M.2 interface provides physical connection functions and supports high-speed protocols such as PCIe 4.0×4, ensuring high-speed data transmission between external devices (such as high frame rate cameras, CT / MRI devices, lidar, etc.) and M.2 accelerator cards. The interface module contains a PHY layer circuit, which is responsible for signal conversion and transmission to ensure efficient data flow between external devices and accelerator cards. The interface module integrates a bandwidth monitoring circuit, which can measure the transmission rate and bit error rate in real time, and constructs a status feedback channel by retaining pins to achieve real-time feedback of data transmission status.

[0028] Furthermore, the AI ​​chip is integrated on an M.2 accelerator card and contains four groups of MAC arrays that can be started and stopped independently. Each group contains 2048 INT8 computing units. Its local cache is 4MB SRAM, which is divided into feature cache and weight cache. The cache allocation strategy is dynamically adjusted by the decision tree of the heterogeneous computing allocator. The MAC array is directly connected to the accelerator card HBM2 cache through silicon vias (TSV) to ensure high-speed data transmission and processing. The feature cache and weight cache are divided in 4MB SRAM. The cache allocation strategy is dynamically adjusted by the decision tree of the heterogeneous computing allocator according to computing requirements to improve cache utilization and data access efficiency.

[0029] Furthermore, the M.2 accelerator card refers to a dedicated hardware accelerator card that complies with the M.2 2280 specification and is connected to external devices through the PCIe4.0×4 interface. It integrates components such as a pattern recognition engine, a dynamic compression engine, a heterogeneous computing distributor, and an AI chip to achieve data preprocessing, compression, and transmission.

[0030] S2. Collect the original data stream of the external device, perform real-time feature analysis on the original data stream through the pattern recognition engine to obtain spatiotemporal correlation features, and binary-code the spatiotemporal correlation features into feature tag data.

[0031] The embodiment of the present invention efficiently collects the original data stream of the external device through the M.2 interface, provides a basis for subsequent processing, and is the starting point of the entire data transmission system, ensuring timely acquisition of data and avoiding problems such as processing delays caused by untimely data collection.

[0032] In one embodiment of the present invention, collecting the original data stream of the external device includes: transmitting the original data stream of the external device to an M.2 accelerator card through an M.2 interface; and receiving the original data stream in the M.2 accelerator card through the M.2 interface to complete the process of collecting the original data stream of the external device.

[0033] It should be noted that the acquisition of the original data stream of the external device mainly relies on the M.2 interface in the M.2 accelerator card. The external device is connected to the accelerator card through the M.2 interface, and the accelerator card uses the M.2 interface to receive the original data stream.

[0034] Furthermore, the embodiments of the present invention solve the problem of "lack of a real-time feature analysis engine" in the background technology through feature analysis. It can extract effective features from the original data stream in real time, filter out invalid information, reduce the amount of data subsequently transmitted and processed, improve the usefulness and processing efficiency of the data, avoid the AI ​​chip from falling into invalid calculations, and improve the recognition accuracy of effective features.

[0035] In one embodiment of the present invention, the pattern recognition engine performs real-time feature analysis on the original data stream to obtain spatiotemporal correlation features, including: using a bidirectional LSTM in the pattern recognition engine to capture the inter-frame motion features of the original data stream; using a convolution kernel in the pattern recognition engine to extract the spatial distribution pattern of the original data stream; and weightedly fusing the inter-frame motion features and the spatial distribution pattern through an attention mechanism in the pattern recognition engine to obtain spatiotemporal correlation features.

[0036] Among them, the bidirectional LSTM (Long Short-Term Memory) is a special recurrent neural network (RNN) structure that can simultaneously utilize the forward and backward information of sequence data for feature learning. It effectively captures the long-term dependencies in the sequence by introducing a gating mechanism (input gate, forget gate, and output gate). The bidirectional LSTM contains two LSTM layers, forward and reverse. The forward layer processes data in sequence order, and the reverse layer processes the data in reverse order. Finally, the outputs of the two layers are fused, so that the contextual information of the sequence can be utilized at the same time. In video analysis, for a video clip containing multiple consecutive frames, the bidirectional LSTM can simultaneously consider the impact of the previous frame on the current frame and the potential association of the subsequent frame with the current frame. For example, in a surveillance video, when analyzing the motion trajectory of a target object, the bidirectional LSTM can integrate the starting position, movement direction, and speed of the object in the previous frame, as well as the possible association of the object in the subsequent frame. movement trend, so as to more accurately predict the position and state of the object in the current frame. Furthermore, the spatial distribution pattern refers to the spatial arrangement and combination rules of pixel values ​​or features in a single image or video frame. It describes the shape, structure, texture and other spatial information of the object in the image, and reflects the layout and mutual relationship of the objects in space. For example, in an image of a product in industrial production, the spatial distribution pattern may be manifested as the contour shape, surface texture and relative positions of each component of the product. Furthermore, the attention mechanism is a neural network mechanism that simulates human visual attention. It allows the model to automatically focus on the part most relevant to the current task when processing input data, while ignoring relatively unimportant parts. The attention mechanism calculates the importance weights of the input features and performs weighted fusion of the features, so that the model can more effectively utilize key information.

[0037] Furthermore, the embodiments of the present invention generate structured feature tag data by binary encoding the time-space related features, which facilitates subsequent transmission and processing, improves the manageability and identifiability of the data, and provides a convenient data format for subsequent compression and transmission operations.

[0038] In an embodiment of the present application, the binary encoding of the spatio-temporal correlation feature into feature tag data comprises: extracting a timestamp, a feature type and a spatial index from the spatio-temporal correlation feature; encoding the timestamp into a 64-bit timer value; encoding the feature type into a type identifier; encoding the spatial index into a coordinate hash value; splicing the 64-bit timer value, the type identifier and the coordinate hash value to obtain a binary code; generating a check code of the binary code using a CRC-8 check algorithm; and splicing the binary code and the check code to obtain the feature tag data.

[0039] The timestamp is a time label corresponding to the generation of original data or feature data, usually a numerical value representing time, used to identify the position of data on the time axis, reflect the generation time or collection time of data, and help establish the order and time interval relationship of data in the time dimension. The feature type is an identifier for classifying the extracted spatio-temporal correlation feature, used to distinguish different types of features, so that subsequent data processing and analysis can take appropriate operations according to the characteristics of different features. It reflects the semantic or functional categories of features, and is a label for classifying and identifying features. For example, in the industrial vision detection scene, the feature types extracted from image data can include "edge feature", "texture feature", "shape feature" and other types. "Edge feature" represents the contour or boundary information between different regions of an object, "texture feature" describes the texture pattern of the surface of an object, and "shape feature" is used to represent the overall shape of an object. The spatial index is an encoding or numerical value used to identify the position of a feature in space, which provides a means for quickly locating and referencing the position of a feature in space distribution, and can help establish the mapping relationship between the feature and the spatial position, facilitating the organization, query and processing of features in the spatial dimension. For example, in a two-dimensional image, the spatial index can be a pixel coordinate. The data structure of the feature tag data is [HEADER (16bit)] [timestamp (64bit)] [feature type (4bit)] [spatial index (16bit)] [CRC (8bit)].

[0040] Optionally, the process of encoding the timestamp into a 64-bit timer value is to encode the timestamp into a 64-bit high-precision timer value (precision 1μs) through a binary structured coding method. Furthermore, the process of encoding the feature type into a type identifier refers to encoding the feature type into a 4-bit type identifier (0x01-0x0F corresponds to different features). Furthermore, the process of encoding the spatial index into a coordinate hash value refers to encoding the spatial index into a 16-bit coordinate hash value (5 bits each for X / Y / Z axes, 1 bit reserved). Furthermore, the process of generating the binary-coded check code using a CRC-8 check algorithm refers to generating an 8-bit check code using a CRC-8 check algorithm.

[0041] S3. Compress the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip.

[0042] The embodiment of the present invention utilizes the dynamic compression engine to compress the feature marker data into optimized compressed data, thereby overcoming the shortcoming of "traditional transmission schemes using fixed compression algorithms" in the background technology. It can adaptively select the compression algorithm according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip, thereby improving bandwidth utilization, avoiding data accumulation and transmission delays caused by bandwidth fluctuations, and ensuring the efficiency and adaptability of data transmission, and ensuring the accuracy of spatiotemporal feature analysis.

[0043] In one embodiment of the present invention, the dynamic compression engine is used to compress the feature tag data into optimized compressed data according to the instantaneous bandwidth of the M.2 interface and the load state of the AI ​​chip, including: when the instantaneous bandwidth is less than the preset bandwidth, the dynamic compression engine is used to call the tensor folding compression algorithm in the accelerator card onboard of the M.2 accelerator card; while retaining the key motion vector of the coordinate hash value in the feature tag data, the tensor folding compression algorithm is executed by the adjustable pipeline silicon chip onboard the accelerator card to perform dimensionality reduction processing on the coordinate hash value in the feature tag data to obtain a reduced dimensionality hash value; based on the reduced dimensionality hash value, the process of compressing the feature tag data into optimized compressed data is completed; when the load state is greater than the preset load, the tensor folding compression algorithm is used to perform dimensionality reduction processing on the coordinate hash value in the feature tag data to obtain a reduced dimensionality hash value. The dynamic compression engine calls the sparse matrix compression algorithm onboard the accelerator card; counts the feature type frequency of non-zero value elements in the feature tag data through the hardware counter of the entropy coding coprocessor onboard the accelerator card; generates a priority queue of the non-zero value elements using the feature type frequency; generates a fixed-length optimized coding table of the non-zero value elements using the Huffman coding in the sparse matrix compression algorithm according to the priority queue and the Huffman tree generation rules pre-stored in the silicon chip ROM onboard the accelerator card; detects zero value elements in the feature tag data; generates a sparse coding matrix of the zero value elements using the run-length coding in the sparse matrix compression algorithm; and converts the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data through the entropy coding coprocessor.

[0044] See Figure 3 FIG. 1 is a flow chart of optimizing and compressing data for implementing the accelerator card-based data transmission device according to an embodiment of the present invention.

[0045] Among them, the preset bandwidth refers to a bandwidth threshold pre-set by the system according to the application scenario and performance requirements, which is used to determine whether the transmission capacity of the current network or interface meets the basic requirements of data transmission. For example, in a live video scenario, if you want to ensure smooth transmission of video with 720p resolution and 30fps frame rate, the preset bandwidth may be set to 5Mbps. If the actual available bandwidth is higher than this value, higher-quality video can be transmitted normally. If it is lower than this value, the system may trigger a bandwidth optimization strategy, such as reducing the video resolution or frame rate. Furthermore, the onboard acceleration card refers to the hardware components and circuits integrated on the M.2 acceleration card, which are used to realize functions such as data processing, compression and transmission acceleration. For example, the dynamic compression engine on the M.2 acceleration card , adjustable pipeline silicon chips and silicon chip ROM for storing Huffman tree generation rules, etc., are all components on the accelerator card board. The tensor folding compression algorithm is an algorithm for compressing high-dimensional data (such as images, videos, etc.). It reduces data redundancy by performing tensor decomposition and dimension folding on the data, and realizes efficient data representation and compression. For example, when processing 4K resolution video data, the tensor folding compression algorithm can fold the spatial and temporal dimensions in the video frame to reduce the amount of data, thereby reducing the transmission bandwidth requirement without significantly reducing the video quality. The key motion vector refers to the vector information that can accurately describe the motion state and trajectory of the object in the video sequence. These vectors usually contain the object's motion. Key features such as the direction, speed and position change of movement. For example, in a football game, when tracking the movement trajectory of the football, the key motion vector can describe the movement direction (such as from left to right, forward, etc.), movement speed (such as the number of pixels moved per second) and position change (such as moving from the center of the picture to the upper right corner) of the football in several consecutive frames. The preset load is a load threshold pre-set by the system according to the performance and application scenario of the AI ​​chip. It is used to determine whether the current computing task of the AI ​​chip is too heavy, so as to decide whether it is necessary to adjust the task allocation or start the load balancing strategy. For example, in the image recognition task, if the computing resources of the AI ​​chip are occupied by more than 80%, the preset load may be set to 80%. When the actual load exceeds this value, the system It may trigger a strategy of queuing tasks or assigning them to other computing units to ensure timely processing of tasks. The hardware counter is a special counting unit integrated in a chip or hardware circuit, which is used to quickly count the number of times a specific event or data occurs. For example, in an entropy coding coprocessor, the hardware counter can be used to count the frequency of occurrence of different feature types (such as high dynamic range data, low latency sensitive data, etc.) in feature-tagged data, providing a basis for subsequent Huffman coding. The non-zero value element refers to an element with a non-zero value in a data set or matrix. In a sparse matrix, the non-zero value element usually contains key information, and the distribution and value of the non-zero value element are of great significance for data compression and processing. For example, in a matrix representing an image,Most pixel values ​​may be zero (such as a black background), while non-zero value elements represent objects in the image (such as white text or patterns). These non-zero value elements contain key information of the image and need to be effectively encoded and stored. The feature type frequency refers to the number of times or proportions of different feature types appear in the feature labeling data. It reflects the distribution of various features in the data and provides important statistical information for subsequent data processing and compression. For example, in a video analysis scenario, if the feature types include "people", "vehicles", "buildings", etc., after statistics, the "people" feature appears 50 times in a certain video clip, the "vehicle" feature appears 30 times, and the "building" feature appears 20 times, then Their feature type frequencies are 50%, 30% and 20% respectively. The priority queue is a data structure used to store and manage tasks or data items with different priorities. In data processing and task scheduling, the priority queue can ensure that high-priority tasks or data items are processed before low-priority items. For example, in an AI reasoning task, if there is a task queue containing "real-time target detection", "image classification" and "video summary generation" tasks, their priorities are high, medium and low respectively. The priority queue will process the "real-time target detection" task first, then the "image classification" task, and finally the "video summary generation" task. The silicon chip ROM (Read-Only Memory) is a read-only memory integrated in the chip, which is used to store fixed data or program code pre-written in the chip manufacturing process. In the M.2 accelerator card, the silicon ROM can be used to store key algorithm parameters such as the Huffman tree generation rules. For example, in the sparse matrix compression algorithm module of the M.2 accelerator card, the silicon ROM stores the Huffman tree generation rules, including the algorithm steps and data structure definitions of Huffman coding. These rules are called by the hardware circuit during the compression process to generate the Huffman coding table. The Huffman tree generation rules are a set of algorithms and logics used to construct a Huffman tree according to the frequency distribution of the data. The Huffman tree is a binary tree structure used to implement Huffman coding. It can assign codes of different lengths to data elements of different frequencies, thereby realizing data compression. Lossless compression of data. For example, when constructing a Huffman tree based on the frequency distribution of feature types, the frequency of each feature type is first counted. Then, according to the principle of the greedy algorithm, the two feature types with the lowest frequency are merged into a new node, and this process is repeated until a complete binary tree is constructed. Finally, the leaf node represents the original feature type, and the non-leaf node represents the frequency after the merger. The path between each node determines the length and specific coding value of the Huffman code. The fixed-length optimized coding table is a table that maps data elements to fixed-length codes. In data compression, by using the fixed-length optimized coding table, the original data can be converted into a shorter coding representation, thereby reducing the amount of data and improving transmission and storage efficiency. For example, in the compression of feature-tagged data, assuming that there are four feature types,They are "A", "B", "C", and "D", and their occurrence frequencies are 40%, 30%, 20%, and 10%, respectively. The fixed-length optimized coding table constructed according to the Huffman tree generation rule may map "A" to "00", "B" to "01", "C" to "10", and "D" to "11". Through this fixed-length coding table, each feature type is represented as a two-bit code. The zero-value element refers to an element with a value of zero in a data set or matrix. In a sparse matrix, zero-value elements usually account for a large proportion. Efficiently encoding these elements can significantly reduce the overhead of data storage and transmission. For example, in a matrix representing an image, most pixel values ​​may be zero (such as a black background). These zero-value elements can be compressed using methods such as run-length encoding to reduce the amount of data and improve storage and transmission efficiency. The sparse coding matrix refers to a matrix generated by compressing the zero-value elements in the original data using a specific coding method (such as run-length encoding). It retains the non-zero-value elements of the original data and their position information, while replacing continuous zero-value elements with the starting position and length, thereby achieving efficient data representation.

[0046] See Figure 2 FIG. 1 is a schematic diagram of a sparse coding matrix for implementing the data transmission device based on an accelerator card according to an embodiment of the present invention. Figure 2 In the example, it is assumed that the original data is a one-dimensional array containing a large number of zero-valued elements. The original data is 0, 0, 0, 5, 0, 8, 0, 0, 0, 0, 3, 0. The consecutive zero-valued elements are encoded by run-length encoding to generate a sparse coding matrix. For the first three consecutive zero-valued elements, they can be represented by starting position 0 and length 3. For the following zero-valued elements, the same encoding is performed to generate the final sparse coding matrix.

[0047] Optionally, the process of compressing the feature-marked data into optimized compressed data based on the dimensionality-reduced hash value refers to using the dimensionality-reduced hash value as the optimized compressed data.

[0048] In another embodiment of the present invention, the conversion of the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data by the entropy coding coprocessor includes: obtaining non-zero value elements and zero value elements in feature tag data; after the entropy coding coprocessor receives the fixed-length optimized coding table and the sparse coding matrix, using the fixed-length optimized coding table to encode and map the non-zero value elements to obtain non-zero value codes; using the sparse coding matrix to encode and map the zero value elements to obtain zero value codes; and using the entropy coding coprocessor to encapsulate the non-zero value codes and the zero value codes to obtain optimized compressed data.

[0049] Optionally, the process of using the entropy coding coprocessor to encapsulate the non-zero value code and the zero value code to obtain optimized compressed data refers to

[0050] S4. Input the optimized compressed data into the heterogeneous computing distributor, so as to allocate a path selection instruction to the optimized compressed data through the heterogeneous computing distributor according to the feature tag type of the optimized compressed data.

[0051] The embodiments of the present invention solve the problem of "if the heterogeneous computing allocator does not dynamically perceive the AI ​​chip load" in the background technology. By dynamically allocating path selection instructions according to the feature tag type through the heterogeneous computing allocator, it achieves a reasonable allocation of computing resources, avoids high-priority tasks from being allocated to overloaded computing units, and improves the overall efficiency of the system and the timeliness of data processing.

[0052] In one embodiment of the present invention, allocating a transmission path for the optimized compressed data by the heterogeneous computing allocator based on the feature tag type of the optimized compressed data includes: inputting the feature tag type, the instantaneous bandwidth of the M.2 interface, and the load status of the AI ​​chip into a decision tree model of the heterogeneous computing allocator, so as to output a path selection instruction for the optimized compressed data through the decision tree model; wherein the path selection instruction includes a target device identifier, a transmission path identifier, a data packet identifier, and a task priority.

[0053] Among them, the characteristic tag type refers to the type identifier part in the characteristic tag data, the instantaneous bandwidth refers to the maximum data transmission rate that the M.2 interface can provide at a specific moment, reflecting the actual transmission capacity of the interface at that moment, the load state refers to the computing task busyness of the AI ​​chip at a certain moment, usually expressed by the resource occupancy rate of the chip or the number of tasks being processed, and the target device identifier is used to uniquely determine the label or address of the data transmission destination to ensure that the data can be accurately sent to the designated device or component. For example, in the system, the NPU unit of the AI ​​chip has a unique target device identifier "NPU_01", and the CPU of the host has an identifier "CPU_01". These identifiers are used to determine the data recipient during data transmission. The transmission path identifier is a label used to distinguish different data transmission paths, helping the system identify and select the appropriate data transmission route. For example, when data is transmitted through the AXI bus inside the M.2 accelerator card, the corresponding transmission path identifier is "AXI_Bus_Path", while when it is sent to the host memory through the TLP message reassembly module of the M.2 interface, the transmission path identifier is "TLP_PCIE_Path". The packet identifier is a unique identifier used to distinguish different data packets, helping the receiving end to identify and reassemble data packets, ensuring the integrity and order of data transmission. For example, the binary encoding of a data packet is "10101010 01010101", and its corresponding packet identifier can be "DP_001", which is used to uniquely identify the data packet during transmission. Task priority refers to the priority processing level assigned to the task based on its importance and urgency, which determines the scheduling order of tasks in the system. For example, in a real-time target tracking task, if the target may pose a threat to security, the task will be given a high priority, such as "Priority_Level_High", to ensure that the system prioritizes the task and responds in a timely manner.

[0054] S5. According to the path selection instruction, the data transmission of the optimized compressed data is completed through the heterogeneous computing distributor to obtain a data transmission result.

[0055] The embodiment of the present invention completes data transmission by executing path selection instructions, thereby achieving efficient and accurate data transmission, improving the reliability and accuracy of data transmission, ensuring that data can reach the target device in a timely and accurate manner, meeting the spatiotemporal consistency requirements of high-precision AI reasoning, improving the performance and effectiveness of the entire data transmission system, and avoiding the problems of missed processing time of feature data and broken spatiotemporal correlation.

[0056] In one embodiment of the present invention, the data transmission of the optimized compressed data is completed through the heterogeneous computing distributor according to the path selection instruction to obtain a data transmission result, including: performing instruction parsing on the path selection instruction through the control logic unit in the heterogeneous computing distributor to obtain parsed instruction information; using the control logic unit to activate the bus transmission logic corresponding to the parsed instruction information; performing format conversion on the optimized compressed data according to the bus transmission logic to obtain format conversion data; and performing data transmission on the format conversion data through the bus transmission logic based on the target device, data packet identifier and task priority in the parsed instruction information to obtain a data transmission result.

[0057] The bus transmission logic refers to a series of rules and mechanisms that control how data is transmitted on the bus in a data transmission system. It defines the format, timing, control signals, etc. of data transmission to ensure that data can be transmitted efficiently and accurately between different devices or components according to predetermined rules. The bus transmission logic usually includes data packaging and unpacking rules, transmission priority management, error detection and correction mechanisms, etc. to ensure the reliability of data transmission.

[0058] Exemplarily, the control logic unit in the heterogeneous computing distributor parses the path selection instruction. For example, the control logic unit parses the path selection instruction and extracts key information therein, including the target device identifier (such as "NPU_Unit_1"), the transmission path identifier (such as "AXI_Bus_Path"), the data packet identifier (such as "Data_Packet_ID_1234") and the task priority (such as "Priority_Level_High"). Furthermore, the control logic unit is used to activate the bus transmission logic corresponding to the parsed instruction information. For example, according to the parsed instruction information, the control logic unit determines the specific path of data transmission. If the target device is the NPU unit of the AI ​​chip and the transmission path is the AXI bus inside the accelerator card, it will activate the corresponding AXI bus. The line transmission logic encapsulates the optimized compressed data according to the specified packet identifier, and sends the data to the NPU unit of the AI ​​chip according to the task priority information. At the same time, it updates the internal task scheduling table to record the transmission status and priority of the packet to ensure that high-priority tasks are given priority. Regarding format conversion, if the optimized compressed data has been encapsulated into a format suitable for AXI bus transmission through the entropy coding coprocessor, then it is usually not necessary to encapsulate it again. However, if the packet identifier in the path selection instruction is inconsistent with the encapsulated data format, simple format adjustments may be required to ensure that the packet identifier can be correctly identified and used. The host PCIe bus usually has its own specific data transmission format and protocol. If the encapsulation format of the optimized compressed data is inconsistent with the transmission requirements of the host PCIe bus, then format conversion is required before transmission.

[0059] Compared with the problems described in the background technology, the embodiment of the present invention efficiently collects the original data stream of the external device through the M.2 interface, provides a basis for subsequent processing, is the starting point of the entire data transmission system, ensures the timely acquisition of data, and avoids problems such as processing delays caused by untimely data collection. Furthermore, the embodiment of the present invention solves the problem of "lack of real-time feature analysis engine" in the background technology through feature analysis, and can extract effective features from the original data stream in real time, filter out invalid information, reduce the amount of data for subsequent transmission and processing, improve the usefulness and processing efficiency of the data, avoid the AI ​​chip from falling into invalid calculations, and improve the recognition accuracy of effective features. Furthermore, the embodiment of the present invention generates structured feature marker data by binary encoding time-space related features, which is convenient for subsequent transmission and processing, improves the manageability and identifiability of data, and provides a convenient data format for subsequent compression and transmission operations. The embodiment of the present invention compresses the feature marker data into optimized compressed data by utilizing the dynamic compression engine, thereby overcoming the problem of "traditional transmission method" in the background technology. The embodiment of the present invention solves the problem of "the heterogeneous computing allocator fails to dynamically perceive the AI ​​chip load" in the background technology. The heterogeneous computing allocator dynamically allocates path selection instructions according to the feature tag type, thereby achieving reasonable allocation of computing resources, avoiding high-priority tasks from being allocated to overloaded computing units, and improving the overall efficiency of the system and the timeliness of data processing. The embodiment of the present invention completes data transmission by executing path selection instructions, achieving efficient and accurate data transmission, improving the reliability and accuracy of data transmission, ensuring that data can reach the target device in a timely and accurate manner, meeting the spatiotemporal consistency requirements of high-precision AI reasoning, improving the performance and effect of the entire data transmission system, and avoiding the problems of feature data missing processing time and spatiotemporal correlation being broken. Therefore, the data transmission method and device based on the accelerator card provided in the embodiment of the present invention can ensure that the final data transmission results meet the spatiotemporal consistency requirements of high-precision AI reasoning.

[0060] Example 2: like Figure 4 FIG. 1 is a functional module diagram of a data transmission device based on an accelerator card according to the present invention.

[0061] The accelerator card-based data transmission device 400 described in the present invention can be installed in an electronic device. Depending on the functionality implemented, the accelerator card-based data transmission device may include a system construction module 401, a feature encoding module 402, a data compression module 403, a path selection module 404, and a data transmission module 405. A module, also referred to as a unit, is a series of computer program segments that can be executed by an electronic device processor and perform a fixed function, and is stored in the electronic device's memory.

[0062] In the embodiment of the present invention, the functions of each module / unit are as follows: The system construction module 401 is used to construct a data transmission system, wherein the data transmission system includes an external device, an M.2 accelerator card, an M.2 interface, and an AI chip, wherein the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; The feature encoding module 402 is used to collect the original data stream of the external device, perform real-time feature analysis on the original data stream through the pattern recognition engine to obtain spatiotemporal correlation features, and binary encode the spatiotemporal correlation features into feature tag data; The data compression module 403 is configured to compress the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip; The path selection module 404 is configured to input the optimized compressed data into the heterogeneous computing distributor, so as to allocate a path selection instruction to the optimized compressed data through the heterogeneous computing distributor according to a feature tag type of the optimized compressed data; The data transmission module 405 is configured to complete the data transmission of the optimized compressed data through the heterogeneous computing distributor according to the path selection instruction, and obtain a data transmission result.

[0063] In detail, each module in the data transmission device 400 based on the acceleration card in the embodiment of the present invention adopts the same method as above when in use. Figure 1 The data transmission method based on the acceleration card is the same technical means as described in , and can produce the same technical effects, so it will not be repeated here.

[0064] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A data transmission method based on an accelerator card, characterized in that: The method comprises: Constructing a data transmission system, wherein the data transmission system includes an external device, an M.2 accelerator card, an M.2 interface, and an AI chip, wherein the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; Collecting the original data stream of the external device, performing real-time feature analysis on the original data stream through the pattern recognition engine to obtain spatiotemporal correlation features, and binary-encoding the spatiotemporal correlation features into feature tag data; Compressing the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip; Inputting the optimized compressed data into the heterogeneous computing distributor, so as to distribute a path selection instruction to the optimized compressed data through the heterogeneous computing distributor according to a feature tag type of the optimized compressed data; According to the path selection instruction, the data transmission of the optimized compressed data is completed through the heterogeneous computing distributor to obtain a data transmission result.

2. The data transmission method based on the accelerator card according to claim 1, characterized in that: The data transmission system is constructed, including: Prepare external devices and M.2 accelerator cards; Deploying a pattern recognition engine in the front-end area of ​​the M.2 accelerator card; Deploying a dynamic compression engine in the middle area of ​​the M.2 accelerator card; Deploy a heterogeneous computing distributor in the back-end control area of ​​the M.2 accelerator card; Integrating an AI chip on the M.2 accelerator card; Constructing an M.2 interface connecting the external device and the M.2 accelerator card; A data transmission system is determined by the external device, the M.2 accelerator card, the M.2 interface, the AI ​​chip, the pattern recognition engine, the dynamic compression engine and the heterogeneous computing allocator.

3. The data transmission method based on the accelerator card according to claim 1, characterized in that: The collecting of the original data stream of the external device includes: Transmitting the original data stream of the external device to the M.2 accelerator card through the M.2 interface; The original data stream is received in the M.2 accelerator card through the M.2 interface to complete the process of collecting the original data stream of the external device.

4. The data transmission method based on the accelerator card according to claim 1, characterized in that: The performing real-time feature analysis on the original data stream by the pattern recognition engine to obtain spatiotemporal correlation features includes: Using a bidirectional LSTM in the pattern recognition engine to capture inter-frame motion features of the original data stream; extracting the spatial distribution pattern of the original data stream using a convolution kernel in the pattern recognition engine; In the pattern recognition engine, the inter-frame motion features and the spatial distribution patterns are weightedly fused through an attention mechanism to obtain spatiotemporal correlation features.

5. The data transmission method based on the accelerator card according to claim 1, characterized in that: The step of binary-encoding the spatiotemporal correlation features into feature tag data includes: Extracting a timestamp, a feature type, and a spatial index from the spatiotemporal related features; encoding the timestamp as a 64-bit timer value; encoding the feature type as a type identifier; Encoding the spatial index as a coordinate hash value; Concatenating the 64-bit timer value, the type identifier, and the coordinate hash value to obtain a binary code; Generate a binary-coded check code using a CRC-8 check algorithm; The binary code and the check code are concatenated to obtain characteristic mark data.

6. The data transmission method based on the accelerator card according to claim 1, characterized in that: The method of compressing the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip includes: When the instantaneous bandwidth is less than the preset bandwidth, the dynamic compression engine is used to call a tensor folding compression algorithm onboard the accelerator card of the M.2 accelerator card; While retaining the key motion vector of the coordinate hash value in the signature data, executing the tensor folding compression algorithm through the adjustable pipeline silicon chip onboard the accelerator card to reduce the dimension of the coordinate hash value in the signature data to obtain a reduced-dimensionality hash value; Based on the dimensionality reduction hash value, the process of compressing the feature-tagged data into optimized compressed data is completed; When the load state is greater than a preset load, using the dynamic compression engine to call the sparse matrix compression algorithm onboard the accelerator card; Counting the frequency of characteristic types of non-zero value elements in the characteristic tag data by using a hardware counter of the entropy coding coprocessor onboard the accelerator card; generating a priority queue of the non-zero valued elements using the feature type frequency; According to the priority queue and the Huffman tree generation rules pre-stored in the silicon chip ROM on the accelerator card, the fixed-length optimized coding table of the non-zero value elements is generated by using the Huffman coding in the sparse matrix compression algorithm; detecting zero-valued elements in the signature data; Generate a sparse coding matrix of the zero-valued elements by using run-length coding in the sparse matrix compression algorithm; The entropy coding coprocessor converts the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data.

7. The data transmission method based on the accelerator card according to claim 6, characterized in that: The converting the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data by the entropy coding coprocessor includes: Obtain non-zero value elements and zero value elements in the feature tag data; After the entropy coding coprocessor receives the fixed-length optimized coding table and the sparse coding matrix, the entropy coding coprocessor uses the fixed-length optimized coding table to perform coding mapping on the non-zero value elements to obtain non-zero value codes; Performing encoding mapping on the zero-value elements using the sparse coding matrix to obtain zero-value codes; The entropy coding coprocessor is used to encapsulate the non-zero value code and the zero value code to obtain optimized compressed data.

8. The data transmission method based on the accelerator card according to claim 1, characterized in that: Allocating a transmission path for the optimized compressed data by the heterogeneous computing allocator according to the feature tag type of the optimized compressed data includes: Inputting the feature tag type, the instantaneous bandwidth of the M.2 interface, and the load status of the AI ​​chip into a decision tree model of the heterogeneous computing distributor, so as to output a path selection instruction for optimizing the compressed data through the decision tree model; The path selection instruction includes a target device identifier, a transmission path identifier, a data packet identifier, and a task priority.

9. The data transmission method based on the accelerator card according to claim 1, characterized in that: The completing the data transmission of the optimized compressed data through the heterogeneous computing distributor according to the path selection instruction to obtain a data transmission result includes: Parsing the path selection instruction by a control logic unit in the heterogeneous computing distributor to obtain parsed instruction information; activating the bus transmission logic corresponding to the parsed instruction information using the control logic unit; performing format conversion on the optimized compressed data according to the bus transmission logic to obtain format-converted data; Based on the target device, data packet identifier and task priority in the parsed instruction information, the format-converted data is transmitted through the bus transmission logic to obtain a data transmission result.

10. A data transmission device based on an accelerator card, characterized in that: The device comprises: A system construction module for constructing a data transmission system, wherein the data transmission system includes an external device, an M.2 accelerator card, an M.2 interface, and an AI chip; the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; a feature encoding module, configured to collect the raw data stream of the external device, perform real-time feature analysis on the raw data stream through the pattern recognition engine to obtain spatiotemporal correlation features, and binary encode the spatiotemporal correlation features into feature tag data; a data compression module, configured to compress the signature data into optimized compressed data using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip; a path selection module, configured to input the optimized compressed data into the heterogeneous computing distributor, so as to allocate a path selection instruction to the optimized compressed data through the heterogeneous computing distributor according to a feature tag type of the optimized compressed data; The data transmission module is used to complete the data transmission of the optimized compressed data through the heterogeneous computing distributor according to the path selection instruction to obtain a data transmission result.

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