RGMII interface MAC layer docking delay method based on clock inversion technology

Abstract

The invention discloses an RGMII interface MAC layer butt joint time delay method based on a clock inversion technology, which comprises the following steps: when MAC layers of two chips communicate through an RGMII interface, performing phase inversion and clock channel switching on built-in clock inverting amplifiers of the chips to realize clock phase inversion and RGMII time sequence adjustment; a normal CLK channel is switched to CLK 180, namely, the clock phase shifts 180 degrees. According to the invention, by inverting the chip built-in clock inverting amplifier, the time sequence of the RGMII interface is improved, and the problem of RGMII communication packet loss is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic information, in particular to a MAC layer docking delay method based on clock inversion technology RGMII interface. BACKGROUND

[0002] RGMII (Reduced Gigabit Media Independent Interface) is Reduced GMII (Gigabit Media Independent Interface). Data bit width: RGMII uses a 4-bit data interface, supports using the rising edge and falling edge of the clock to transmit data at 1000 Mbps rate, and only uses a single clock edge to transmit data at 10 Mbps and 100 Mbps rate; Clock frequency: at 1000 Mbps rate, the clock frequency is 125 MHz; at 100 Mbps rate, the clock frequency is 25 MHz; at 10 Mbps rate, the clock frequency is 2.5 MHz;‌‌ Currently, the RGMII communication protocol has a delay requirement between the clock and the data. Most application scenarios MAC (Media Access Controller) interface PHY (Physical Layer), the mainstream PHY chip on the market will have a delay function, which can set the related register to adjust the delay parameter between the RGMII clock and the data signal, and meet the communication timing requirements. A small number of application scenarios MAC interface MAC, some chips consider cost reduction, and the MAC side has no delay function. At this time, delay design needs to be added.

[0003] Currently, there are two ways to delay: 1) RC delay, which can realize 1000\100\10 Mbps application, and the delay can be adjusted by RC parameters; but it needs to add RC peripheral circuit, in order to maintain the driving ability, it needs two-stage amplification, which will increase the cost, and needs to be considered at the beginning of the design. 2) Increase the delay by the length of the board-level wiring; but the minimum wiring length to realize RGMII delay is 15 cm (6 inch / ps), which occupies the PCB space, and affects the signal integrity, and the delay parameter cannot be adjusted. SUMMARY

[0004] The purpose of the present application is to overcome the defects of the prior art, and provide a MAC layer docking delay method based on clock inversion technology RGMII interface, which improves the RGMII interface timing by inverting the built-in clock inverter amplifier, and solves the problem of RGMII communication packet loss.

[0005] The purpose of the present invention is achieved as follows: A RGMII interface MAC layer docking delay method based on clock inversion technology, comprising: when the MAC layers of two chips communicate through the RGMII interface, the built-in clock inversion amplifier of the chip is inverted, the clock channel is switched, and the clock inversion is realized to adjust the RGMII timing.

[0006] Furthermore, the inverting of the built-in clock inverting amplifier of the chip and switching the clock channel specifically includes: switching the normal CLK channel to CLK_180, ie, shifting the clock phase by 180°.

[0007] Furthermore, the chip clock is reversed by modifying the value of TX_CLK_CONFIG in the program.

[0008] Furthermore, the chip includes a transmitting clock TX_CLX and a receiving clock RX_CLX; the reverse clock of the transmitting clock TX_CLX is TX_CLX_180; the reverse clock of the receiving clock RX_CLX is RX_CLX_180.

[0009] Furthermore, the implementation of clock inversion to adjust RGMII timing specifically includes: inverting the clock inversion amplifier built into the chip to generate clock delay data Tdelay, where the value of Tdelay is not equal to 0ns, thereby implementing RGMII communication between chips.

[0010] Furthermore, the clock delay data Tdelay specifically includes: at the RGMII gigabit rate, the clock is 125M, the period is 8ns, the sampling is for both rising and falling edges, 1ns≦Tdelay≦2.6ns; at the RGMII 100M rate, the clock is 25M, the period is 40ns, the sampling is for rising edge sampling, 1ns≦Tdelay; at the RGMII 10M rate, the clock is 2.5M, the period is 400ns, the sampling is for rising edge sampling, 1ns≦Tdelay.

[0011] Furthermore, when the MAC layers of the two chips communicate through the RGMII interface, the RGMII interface sends and receives two sets of signals independently of each other, sends or receives data signals with reference to the same set of clock signal edges, and performs clock phase adjustment based on the sending or receiving clocks of the two chips.

[0012] Furthermore, the clock phase adjustment based on the transmit or receive clocks of the two chips specifically includes: a) inverting the transmit clock TX_CLX and the receive clock RX_CLX of chip one; b) inverting the transmit clock TX_CLX and the receive clock RX_CLX of chip two; c) inverting the transmit clock TX_CLX of chip one and the receive clock RX_CLX of chip two; d) inverting the transmit clock TX_CLX of chip two and the receive clock RX_CLX of chip one.

[0013] Furthermore, the chip 1 has a clock inverting amplifier inside.

[0014] Furthermore, the chip 2 has a clock inverting amplifier inside.

[0015] The present invention adopts the above technical solution, and compared with the prior art, the beneficial effects are as follows: the present invention uses clock inversion technology to realize the delay of RGMII clock and data signals, and realizes the RGMII communication 100 / 10Mbps solution; in specific cases, it can also solve the 1000Mbps communication delay requirement; the RGMII interface MAC layer docking delay method of the present invention can improve the RGMII timing by inverting the clock of the chip's built-in clock inversion amplifier without adding peripheral circuits and without winding wires. When RGMII MAC is connected to MAC, when the MACs on both sides do not have a delay function, the inverted clock is used to generate delayed data, thereby realizing normal RGMII communication and solving the problem of RGMII communication packet loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a circuit diagram of a chip with a built-in clock inversion function in the present invention.

[0017] Figure 2 This is a timing diagram of the RGMII clock inversion at 100 Mbps of the present invention.

[0018] Figure 3 This is a timing diagram of the RGMII gigabit rate of the present invention after clock inversion.

[0019] Figure 4 Schematic diagram of the combination of four clock adjustment methods of the present invention.

[0020] Figure 5 This is a timing diagram without clock inversion in an embodiment of the present invention.

[0021] Figure 6 This is a timing diagram of clock inversion in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] A method for delaying the connection of the MAC layer of the RGMII interface based on clock inversion technology comprises: when the MAC layers of two chips communicate through the RGMII interface, inverting the built-in clock inversion amplifier of the chip, switching the clock channel, and realizing clock inversion to adjust the RGMII timing.

[0023] Invert the built-in clock inverting amplifier of the chip, switch the clock channel, switch the normal CLK channel to CLK_180, even if the clock phase is shifted by 180°; realize the clock reversal of the chip by modifying the value of TX_CLK_CONFIG in the program; Figure 1 As shown, the chip includes a transmitting clock TX_CLX and a receiving clock RX_CLX; the reverse clock of the transmitting clock TX_CLX is TX_CLX_180; the reverse clock of the receiving clock RX_CLX is RX_CLX_180.

[0024] By inverting the chip's built-in clock inverting amplifier, clock delay data Tdelay is generated. The value of Tdelay is not equal to 0ns, thereby realizing RGMII communication between chips.

[0025] At RGMII 100M rate, the clock is 25M, the period is 40ns, the sampling is rising edge sampling, 1ns ≦ Tdelay; the transmission rate is 100Mbps = 25M (sampling clock) * 1 (single edge sampling) * 4 (data bits); If the chips on both sides of the RGMII MAC connection do not have a delay function, the Tdelay value is approximately 0ns, and the MCAs on both sides cannot communicate through RGMII. At this time, the communication rate on both sides can be set to 100Mbps, the clock can be changed to 25M, and the clocks of the sending TX and receiving RX can be inverted. This can be achieved as follows: Figure 2 After inverting the 25M clock, Tdelay≈20ns, which meets the requirement of 100Mbps 1ns≦Tdelay, and RGMII can communicate normally. At the RGMII 10M rate, the clock is 2.5M, the period is 400ns, the sampling is rising edge sampling, and 1ns≦Tdelay; after clock inversion, the 10Mbps communication timing requirements can be met in the same way.

[0026] At the RGMII gigabit rate, the clock is 125M, the period is 8ns, the sampling is for both rising and falling edges, 1ns ≤ Tdelay ≤ 2.6ns; the transmission rate is 1000Mbps = 125M (sampling clock) * 2 (double-edge sampling) * 4 (data bits); The clock inversion method is only applicable in some special scenarios for 1000Mbps communication, for example, the initial Tdelay=3ns, the RGMII cannot normally communicate, after inversion, Tdelay=1ns, the RGMII can normally communicate, and the timing change is as shown in Figure 3 .

[0027] When the MAC layers of the two chips communicate through the RGMII interface, the specific steps include that the RGMII interface sends and receives two groups of signals independently, the sending or receiving data signal is referenced to the same group of clock signal edges, and the clock phase is adjusted according to the sending or receiving clock of the two chips; as shown in Figure 4 , the clock phase adjustment according to the sending or receiving clock of the two chips specifically includes: a) inverting the sending clock TX_CLX and the receiving clock RX_CLX of chip one; b) inverting the sending clock TX_CLX and the receiving clock RX_CLX of chip two; c) inverting the sending clock TX_CLX of chip one and the receiving clock RX_CLX of chip two; and d) inverting the sending clock TX_CLX of chip two and the receiving clock RX_CLX of chip one.

[0028] Embodiment: In the automobile gateway project, the functions of TBOX and gateway are integrated, RGMII communication is required between the 4G module and the SOC chip, and the network routing function is realized by the SOC; The two chips respectively use S32G398A of NXP and AG35CET of Yida, the communication between the two chips uses the RGMII interface, and neither of the two chips supports RGMII CLK delay; as shown in Figure 5 , the actual measurement of 4G_RGMII_TX_CLK and 4G_RGMII_TXD0 of RGMII is performed, RGMII is set to 100M rate, the period is 40ns, the delay is measured, and the actual measurement Tdelay is approximately equal to 0ns, which is less than 1ns, and does not meet the communication specification.

[0029] Both the two chips internally have a clock inversion amplifier, by modifying the TX and RX clk_sel parameters, the AG35CET clock configuration can be changed to inversion, which meets the RGMII timing; the RGMII interface clock configuration modification before AG35CET chip is TX_CLK_CONFIG=<0x0>; the code after modification is TX_CLK_CONFIG=<0x10000>; as shown in Figure 6As shown, the upper signal 1 is 4G_RGMII_TX_CLK, and the lower signal 2 is 4G_RGMII_TXD0; actual measurement can show that the rising edge of data is at the falling edge of the clock signal, which is equivalent to a delay of half a period, about 20ns Tdelay>1ns, satisfying the RGMII communication specification; actual test of 100M bandwidth test shows that the packet loss rate is 0%.

[0030] If the internal clock of the chip does not have a clock inverting amplifier, an IC scheme without a clock inverting function needs to be used, and an inverting amplifier circuit needs to be added outside the IC RGMII interface, which is a commonly used circuit, and no special description is made this time.

[0031] The application provides a clock inverting technology-based RGMII interface MAC layer docking delay method, in the case of MAC docking of the RGMII interface, and in the case that neither of the two MACs has a delay function, the built-in clock inverting amplifier of the chip is inverted, the clock channel is switched, the clock inverting adjusts the RGMII timing, and the communication of the RGMII is realized.

[0032] The application is not limited to the above-mentioned embodiments, and based on the technical solutions disclosed in the application, those skilled in the art can make some substitutions and deformations to some technical features according to the disclosed technical content without creative labor, and these substitutions and deformations are all within the protection scope of the application.

Claims

1. A method for delaying the connection of the RGMII interface MAC layer based on clock inversion technology, characterized in that: include: When the MAC layers of two chips communicate through the RGMII interface, the built-in clock inversion amplifier of the chip is inverted, the clock channel is switched, and the clock inversion is implemented to adjust the RGMII timing.

2. The method for delaying the RGMII interface MAC layer connection based on clock inversion technology according to claim 1, characterized in that: The inverting of the built-in clock inverting amplifier of the chip and switching the clock channel specifically include: switching the normal CLK channel to CLK_180, ie, shifting the clock phase by 180°.

3. The method for delaying the RGMII interface MAC layer connection based on clock inversion technology according to claim 2, characterized in that: The chip clock is reversed by modifying the value of TX_CLK_CONFIG in the program.

4. The method for delaying the RGMII interface MAC layer connection based on clock inversion technology according to claim 2, characterized in that: The chip includes a transmitting clock TX_CLX and a receiving clock RX_CLX; the reverse clock of the transmitting clock TX_CLX is TX_CLX_180; the reverse clock of the receiving clock RX_CLX is RX_CLX_180.

5. The method for delaying the RGMII interface MAC layer connection based on clock inversion technology according to claim 1, characterized in that: The implementation of clock inversion to adjust RGMII timing specifically includes: inverting the clock inversion amplifier built into the chip to generate clock delay data Tdelay, where the value of Tdelay is not equal to 0ns, thereby implementing RGMII communication between chips.

6. The method for delaying the RGMII interface MAC layer connection based on clock inversion technology according to claim 5, characterized in that: The clock delay data Tdelay specifically includes: at RGMII gigabit rate, the clock is 125M, the period is 8ns, the sampling is both the rising edge and the falling edge, 1ns≦Tdelay≦2.6ns; At RGMII 100M rate, the clock is 25M, the period is 40ns, the sampling is rising edge sampling, and 1ns≦Tdelay; At the RGMII 10M rate, the clock is 2.5M, the period is 400ns, the sampling is rising edge sampling, and 1ns≦Tdelay.

7. The method for delaying the connection of the RGMII interface MAC layer based on clock inversion technology according to claim 1, characterized in that: The MAC layers of the two chips communicate through the RGMII interface. Specifically, the RGMII interface sends and receives two sets of signals independently of each other, sends or receives data signals with reference to the same set of clock signal edges, and performs clock phase adjustment based on the sending or receiving clocks of the two chips.

8. The method for delaying the connection of the RGMII interface MAC layer based on the clock inversion technology according to claim 7, characterized in that: The clock phase adjustment based on the transmit or receive clocks of the two chips specifically includes: a) inverting the transmit clock TX_CLX and the receive clock RX_CLX of chip one; b) inverting the transmit clock TX_CLX and the receive clock RX_CLX of chip two; c) inverting the transmit clock TX_CLX of chip one and the receive clock RX_CLX of chip two; d) inverting the transmit clock TX_CLX of chip two and the receive clock RX_CLX of chip one.

9. The method for delaying RGMII interface MAC layer connection based on clock inversion technology according to claim 8, characterized in that: The chip 1 has a clock inverting amplifier inside.

10. The method for delaying RGMII interface MAC layer connection based on clock inversion technology according to claim 8, characterized in that: The chip 2 has a clock inverting amplifier inside.

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