Wafer image processing method and device and storage medium

Abstract

The invention provides a wafer image processing method, a wafer image processing device and a computer readable storage medium. The wafer image processing method comprises the following steps: acquiring a wafer image to be processed through an imaging module; the wafer image comprises a wafer and at least one interference point caused by the imaging module; obtaining interference point data of the imaging module; and identifying the wafer image according to the interference point data so as to determine the wafer edge of the wafer. According to the invention, the interference point data of the imaging module can be acquired in advance, and the wafer image is filtered based on the interference point data to determine the wafer edge, so that the accuracy of the wafer edge information is improved, and the accuracy of the wafer center position, radius and gap relative angle calculated based on the wafer edge information is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor device processing, and in particular, to a wafer image processing method, a wafer image processing device, and a computer readable storage medium. BACKGROUND

[0002] In the image processing process of semiconductor device processing technology, edge detection algorithm occupies an important position. In a complete image recognition process, the edge detection algorithm is first needed to find the edge contour of the target, then the target contour is extracted, and finally the target is positioned according to the edge contour of the target. In the wafer alignment process, the edges of the upper and lower wafers are first collected by the imaging module, and the center position and the relative angle of the gap of the wafer are determined according to the edge information to determine the wafer position, so as to position and align it. Therefore, the more accurate the edge position information of the wafer detected by the edge detection algorithm, the more accurate the determined center position of the wafer. However, in the real scene, the wafer image to be recognized not only has the edge information of the wafer, but also has noise, speckle and other interference edges. These interference edges are mainly caused by the non-uniform illumination in the imaging module, which leads to the noise edges in the image, and the speckle edges caused by the particles and scratches on the imaging module. The existence of these interference edges leads to the reduction of the accuracy of the extracted wafer edge, and further leads to the reduction of the accuracy of the determined wafer position information.

[0003] In order to overcome the above-mentioned defects existing in the prior art, the present application provides an improved wafer image processing method, which can improve the accuracy of the wafer edge information, and thus improve the accuracy of the wafer center position, radius and gap relative angle calculated based on the wafer edge information. SUMMARY

[0004] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0005] In order to overcome the above-mentioned defects existing in the prior art, the present application provides a wafer image processing method, a wafer image processing device and a computer readable storage medium, which can obtain the interference point data of the imaging module in advance, filter the wafer image based on the interference point data, determine the wafer edge, improve the accuracy of the wafer edge information, and thus improve the accuracy of the wafer center position, radius and gap relative angle calculated based on the wafer edge information.

[0006] Specifically, the wafer image processing method provided in accordance with the first aspect of the present invention includes the following steps: acquiring a wafer image to be processed via an imaging module, wherein the wafer image includes a wafer and at least one interference point caused by the imaging module; acquiring interference point data from the imaging module; and identifying the wafer image based on the interference point data to determine the wafer edge of the wafer.

[0007] Furthermore, in some embodiments of the present invention, the step of identifying the wafer image based on the interference point data to determine the wafer edge of the wafer includes: extracting a first edge from the wafer image, wherein the first edge includes the wafer edge and interference edges of each of the interference points; calculating a pixel gradient value of the first edge, and identifying at least one interference edge in the wafer image based on the pixel gradient value and the interference point data; and removing the at least one interference edge from the wafer image to determine the wafer edge.

[0008] Furthermore, in some embodiments of the present invention, the step of calculating the pixel gradient value of the first edge and identifying at least one interference edge in the wafer image based on the pixel gradient value and the interference point data further includes: splitting the first edge into multiple sub-edges, and calculating the pixel gradient value of each sub-edge respectively; and in response to the pixel gradient value being less than a preset pixel threshold, determining that the corresponding sub-edge is the interference edge.

[0009] Furthermore, in some embodiments of the present invention, the step of separately calculating the pixel gradient value of each sub-edge includes: calculating the contrast between the pixel points on each sub-edge and the pixel points in its neighborhood along a direction perpendicular to each sub-edge; and calculating the pixel gradient value of the sub-edge based on the contrast between all pixel points on the sub-edge and the pixel points in its neighborhood.

[0010] Furthermore, in some embodiments of the present invention, the step of removing the at least one interfering edge from the wafer image to determine the wafer edge also includes: determining the polarity of the sub-edge in response to the pixel gradient value being greater than the pixel threshold; and determining that the corresponding sub-edge is the wafer edge in response to the polarity being the same as a preset wafer polarity.

[0011] Furthermore, in some embodiments of the present invention, the step of obtaining interference point data from the imaging module includes: obtaining a background image via the imaging module, the background image including at least one interference point caused by the imaging module; extracting a second edge from the background image, the second edge including an interference edge of each of the interference points; and calculating a pixel gradient value of the second edge and, based on the pixel gradient value, determining each of the interference edges to form the interference point data.

[0012] Furthermore, in some embodiments of the present invention, before extracting the second edge in the background image, the following steps are also included: processing the background image with a filtering algorithm to filter out noise in the background image; performing dilation and erosion processing on the background image to smooth the edges of the interference points and fill the internal holes of the interference points; and converting the background image into a binary image.

[0013] Furthermore, in some embodiments of the present invention, the wafer includes a notch for positioning, and the processing method also includes the following steps: calculating the center position, radius and relative angle of the notch of the wafer based on the edge of the wafer; and positioning the wafer based on the center position, radius and relative angle of the notch of the wafer.

[0014] Furthermore, the wafer image processing apparatus provided in accordance with a second aspect of the present invention includes a memory and a controller. The controller is configured to: acquire a wafer image to be processed via an imaging module; the wafer image includes the wafer and at least one interference point caused by the imaging module; acquire interference point data from the imaging module; and identify the wafer image based on the interference point data to determine the wafer edge of the wafer.

[0015] Furthermore, in some embodiments of the present invention, the controller is connected to a plurality of imaging modules, each of which is distributed around the wafer and configured to respectively capture wafer images of corresponding areas of the wafer.

[0016] Furthermore, the computer-readable storage medium provided in accordance with the third aspect of the present invention stores computer instructions, which, when executed by a processor, implement the wafer image processing method provided in accordance with the first aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above features and advantages of the present invention will be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or characteristics may have the same or similar reference numerals.

[0018] Figure 1 A schematic structural diagram of a wafer image processing device provided according to some embodiments of the present invention is shown.

[0019] Figure 2 A schematic flow chart of a wafer image processing method according to some embodiments of the present invention is shown.

[0020] Figure 3 Schematic diagram of a wafer image provided according to some embodiments of the present invention is shown.

[0021] Figure 4 A schematic diagram of splitting into sub-edges according to some embodiments of the present invention is shown.

[0022] Figure 5 A schematic diagram of calculating pixel gradient values ​​of sub-edges provided according to some embodiments of the present invention is shown.

[0023] Figure 6 A schematic diagram of identifying interference edges according to some embodiments of the present invention is shown.

[0024] Figure 7 A schematic diagram of identifying interference edges according to some embodiments of the present invention is shown.

[0025] Figure 8 A schematic diagram of identifying interference edges according to some embodiments of the present invention is shown. DETAILED DESCRIPTION

[0026] The following specific embodiments illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this embodiment. On the contrary, the purpose of introducing the invention in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description.

[0027] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0028] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood to refer to the orientations depicted in that section and the accompanying drawings. These relative terms are used solely for convenience of description and do not necessarily imply that the devices described herein must be manufactured or operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0029] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various components, regions, layers, and / or portions, these components, regions, layers, and / or portions should not be limited by these terms, and these terms are merely used to distinguish different components, regions, layers, and / or portions. Thus, a first component, region, layer, and / or portion discussed below may be referred to as a second component, region, layer, and / or portion without departing from some embodiments of the present invention.

[0030] As mentioned above, during the wafer alignment process, the edges of the upper and lower wafers are first collected through the imaging module, and the center position of the wafer and the relative angle of the notch are determined based on the edge information to determine the wafer position for positioning and alignment. Therefore, the more accurately the edge position information of the wafer is detected by the edge detection algorithm, the more accurate the final center position of the wafer will be. However, in real scenarios, the wafer image to be identified contains not only the edge information of the wafer, but also interference edges such as noise and spots. These interference edges are mainly due to the uneven illumination in the imaging module, which causes the image to contain noise edges, as well as spot edges caused by particles, scratches, etc. on the imaging module. The presence of these interference edges reduces the accuracy of the extracted wafer edges, which in turn reduces the accuracy of the determined wafer position information.

[0031] In order to overcome the above-mentioned defects of the prior art, the present invention provides a wafer image processing method, a wafer image processing device and a computer-readable storage medium, which can obtain interference point data of the imaging module in advance and filter the wafer image based on the interference point data to determine the wafer edge, thereby improving the accuracy of the wafer edge information, thereby improving the accuracy of the wafer center position, radius and relative angle of the notch calculated based on the wafer edge information.

[0032] In some non-limiting embodiments, the wafer image processing device provided in the second aspect of the present invention can be implemented based on the wafer image processing method provided in the first aspect of the present invention.

[0033] In some non-limiting embodiments, the wafer image processing apparatus provided in the second aspect of the present invention includes a memory and a controller. The memory includes, but is not limited to, the computer-readable storage medium provided in the third aspect, having computer instructions stored thereon. The controller is connected to the memory and configured to execute the computer instructions stored in the memory to implement the wafer image processing method provided in the first aspect of the present invention.

[0034] Please refer to Figure 1 . Figure 1 A schematic structural diagram of a wafer image processing device provided according to some embodiments of the present invention is shown.

[0035] In some embodiments, the controller is connected to a plurality of imaging modules 11. Here, the imaging modules 11 are distributed around the wafer 12 and are used to respectively capture wafer images of corresponding areas of the wafer 12.

[0036] Further, in Figure 1 In the illustrated embodiment, the controller is connected to four imaging modules 11. The four imaging modules 11 are distributed around the wafer 13, wherein three imaging modules 11 are used to capture edge images of the wafer 12, and the other imaging module 11 is used to capture notch information at the edge of the wafer 12.

[0037] In addition, in some preferred embodiments, technicians can adjust the imaging parameters of the imaging module according to the semiconductor processing environment. Specifically, based on the current imaging scenario, the image size is 2448×2048 pixels, the starting point coordinates of the ROI are generally (10, 900), the width is 2400, the height is 1000, and the indentation value is 5. If the imaging module 11 is replaced with 1920×1200 pixels, only the ROI area of ​​the algorithm needs to be changed to adapt to the new imaging scenario. Here, the width of the ROI area plus the initial point X is less than the image width. The height of the ROI area plus the initial point Y is less than the image height.

[0038] The following will describe the working principle of the above-mentioned wafer image processing device in conjunction with some embodiments of the wafer image processing method. Those skilled in the art will understand that the embodiments of these wafer image processing methods are only some non-restrictive implementation methods provided by the present invention, which are intended to clearly demonstrate the main concept of the present invention and provide some specific solutions that are convenient for the public to implement, rather than limiting all functions or all working modes of the wafer image processing device. Similarly, the wafer image processing device is also only a non-restrictive implementation method provided by the present invention, and does not constitute a limitation on the execution subject and execution order of each step in these wafer image processing methods.

[0039] Specifically, in some non-limiting embodiments, the wafer image processing method provided in the first aspect of the present invention can be implemented in two stages: offline processing and online detection. A technician can first determine interference point data consisting of an interference edge of at least one interference point in the imaging module 11 during the offline processing stage, and then identify the wafer image based on the obtained interference point data during the online detection stage to determine the wafer edge of the wafer 12.

[0040] In the process of acquiring the interference point data of the imaging module 11 , the processing device may first acquire a background image via the imaging module 11 . Here, the background image includes at least one interference point caused by the imaging module 11 .

[0041] Afterwards, the processing device may extract a second edge in the background image, wherein the second edge includes interference edges of each interference point.

[0042] Furthermore, in some preferred embodiments, before extracting the second edge in the background image, the processing device may pre-process the background image.

[0043] Specifically, the processing device may first process the background image using a filtering algorithm (eg, Shen-Castan filtering algorithm) to filter noise in the background image to reduce interference of the noise on the background image, thereby facilitating subsequent further image processing.

[0044] Afterwards, the processing device may perform dilation processing and erosion processing on the background image to smooth the edges of the interference points and fill the internal holes of the interference points.

[0045] Thereafter, the processing device may convert the background image into a binary image based on a local adaptive binarization algorithm.

[0046] Furthermore, the processing device can decompose the input background image into multiple sub-images, then automatically calculate the threshold required for binarization for each sub-image using a histogram segmentation algorithm, and perform a binarization operation on each sub-image. Thereafter, the processing device can merge the multiple sub-images into a background image of the original size.

[0047] Here, the image is composed of a number of pixels, and the pixel value of each pixel ranges from 0 to 255. During the binarization process, a threshold value (for example, 128) can be set. In response to the pixel values ​​of some pixels in the image being less than the above threshold value, the pixel values ​​of these pixels are set to 0. In response to the pixel values ​​of other pixels in the image being greater than or equal to 128, the pixel values ​​of these pixels are set to 255. In this way, the pixel values ​​in the entire image are changed from the original 0 to 255 to only two pixel values, 0 or 255, to complete the image binarization operation.

[0048] Thereafter, the processing device may calculate the pixel gradient value of the second edge, and determine each interference edge according to the pixel gradient value to form interference point data.

[0049] Furthermore, in some preferred embodiments, during the process of identifying the interference edge, the processing device may first split the second edge into a plurality of sub-edges, and respectively calculate the pixel gradient value of each sub-edge.

[0050] Specifically, in the process of calculating the pixel gradient value of each sub-edge, the processing device may calculate the contrast between the pixels on each sub-edge and the pixels in its neighborhood along a direction perpendicular to each sub-edge. Thereafter, the processing device may calculate the pixel gradient value of the sub-edge based on the contrast between all pixels on the sub-edge and the pixels in its neighborhood.

[0051] Afterwards, in response to the pixel gradient value being less than a preset pixel threshold, the corresponding sub-edge is determined to be an interference edge.

[0052] By performing the above steps, a person skilled in the art can obtain interference data based on the background image, which is composed of interference edges of at least one interference point caused by imaging module 11. The person skilled in the art can then store the data on a CD, disk, network drive, or other storage medium for access and recall by the wafer image storage device during the online inspection phase.

[0053] Please refer to Figures 2 to 5 . Figure 2 A schematic flow chart of a method for processing wafer images according to some embodiments of the present invention is shown. Figure 3 Schematic diagram of a wafer image provided according to some embodiments of the present invention is shown. Figure 4A schematic diagram of splitting into sub-edges according to some embodiments of the present invention is shown. Figure 5 A schematic diagram of calculating pixel gradient values ​​of sub-edges provided according to some embodiments of the present invention is shown.

[0054] like Figure 2 As shown, a technician can use a reflective imaging method to obtain an image of a wafer to be processed via an imaging module 11. Here, the wafer image includes the wafer 12 and at least one interference point caused by the imaging module.

[0055] Afterwards, the technician can obtain the interference point data of the imaging module extracted above.

[0056] Afterwards, technicians can identify the wafer image based on the interference point data to determine the wafer edge of the wafer.

[0057] Furthermore, if Figure 3 As shown, in the process of determining the wafer edge, the processing device may first extract first edges 30-31 in the wafer image. Here, the first edges include the wafer edge and interference edges of each interference point.

[0058] Thereafter, the processing device may calculate a pixel gradient value of the first edge, and identify at least one interfering edge in the wafer image based on the pixel gradient value and the interference point data.

[0059] In addition, Figure 4 In the illustrated embodiment, during the process of identifying interference edges, the processing device may preferably first split the first edges 30 - 31 into multiple sub-edges 40 - 41 and respectively calculate the pixel gradient value of each sub-edge 40 - 41 .

[0060] Specifically, if Figure 5 As shown, in the process of calculating the pixel gradient value of each sub-edge, the processing device can calculate the contrast between the pixel points on each sub-edge and the pixels in its neighborhood along a direction perpendicular to each sub-edge. Thereafter, the processing device can calculate the pixel gradient value of the sub-edge based on the contrast between all pixels on the sub-edge and the pixels in its neighborhood.

[0061] Thereafter, in response to the pixel gradient value being less than a preset pixel threshold (eg, 20), the processing device may determine that the corresponding sub-edge is an interference edge.

[0062] Conversely, in response to the pixel gradient value being greater than the pixel threshold, the processing device may further determine the polarity of the sub-edge.

[0063] Next, in response to the polarity being the same as the preset wafer polarity, the corresponding sub-edge is determined to be a wafer edge. Specifically, along the Y direction of the wafer image, the preset wafer polarity changes from bright to dark, while other edges do not have this polarity. Therefore, this feature is used to further confirm whether the corresponding sub-edge is a wafer edge.

[0064] Thereafter, the processing device may remove at least one interfering edge from the wafer image to determine the wafer edge.

[0065] Please refer to further Figures 6 to 8 . Figure 6 A schematic diagram of identifying interference edges according to some embodiments of the present invention is shown. Figure 7 A schematic diagram of identifying interference edges according to some embodiments of the present invention is shown. Figure 8 A schematic diagram of identifying interference edges according to some embodiments of the present invention is shown.

[0066] exist Figures 6 to 8 In the illustrated embodiment, the processing device may first extract all first edges in the wafer image and mark them blue. The processing device may then directly extract the interference point data acquired during the offline processing phase or re-identify the interference point data in the wafer image to mark the corresponding interference edges red and the extracted wafer edges green.

[0067] Specifically, when distinguishing the interfering edge from the wafer edge in the first edge, technicians can number all edges from top to bottom based on the image coordinates. Here, edge number 0 includes the wafer edge. To improve algorithm efficiency, technicians can preferably only perform optimization operations such as noise and speckle removal on the edge with index 0.

[0068] In addition, Figure 1 In the illustrated embodiment, the wafer 12 includes a notch for positioning, and the relative angle of the notch is used to determine the orientation of the wafer 12. After determining the wafer edge, the processing device can calculate the center position, radius, and relative angle of the notch of the wafer 12 based on the wafer edge.

[0069] Afterwards, the processing device can position the wafer according to the center position, radius and relative angle of the notch of the wafer.

[0070] Please further refer to Table 1. Table 1 shows a comparison table of the center position, radius and relative angle of the notch of a wafer provided according to some embodiments of the present invention.

[0071] Table 1 Comparison of wafer center position, radius and relative angle of the notch

[0072]

[0073]

[0074] As shown in Table 1, after removing the interference point data in the wafer image, the accuracy of the horizontal and vertical coordinates of the wafer center position is significantly higher. Here, in the imaging module of the wafer image processing device provided by the second aspect of the present invention, after calibration, 1 pixel = 3 μm.

[0075] In summary, the above-mentioned wafer image processing method, wafer image processing device and computer-readable storage medium provided by the present invention can all obtain the interference point data of the imaging module in advance and filter the wafer image based on the interference point data to determine the wafer edge, which is used to improve the accuracy of the wafer edge information, thereby improving the accuracy of the wafer center position, radius and relative angle of the notch calculated based on the wafer edge information.

[0076] Although the above methods are illustrated and described as a series of acts for simplicity of explanation, it is to be understood and appreciated that these methods are not limited by the order of the acts, as some acts may occur in a different order and / or concurrently with other acts from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art according to one or more embodiments.

[0077] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read and write information from / to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside in a user terminal as discrete components.

[0078] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Any connection is also properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0079] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for processing a wafer image, characterized in that: The following steps are involved: Acquiring an image of a wafer to be processed via an imaging module, wherein the wafer image includes the wafer and at least one interference point caused by the imaging module; Acquiring interference point data of the imaging module; as well as The wafer image is identified according to the interference point data to determine a wafer edge of the wafer.

2. The processing method according to claim 1, characterized in that The step of identifying the wafer image according to the interference point data to determine the wafer edge of the wafer includes: Extracting a first edge in the wafer image, wherein the first edge includes the wafer edge and interference edges of each of the interference points; calculating a pixel gradient value of the first edge, and identifying at least one interference edge in the wafer image based on the pixel gradient value and the interference point data; and The at least one interfering edge is removed from the wafer image to determine the wafer edge.

3. The processing method according to claim 2, characterized in that The step of calculating the pixel gradient value of the first edge and identifying at least one interference edge in the wafer image based on the pixel gradient value and the interference point data further includes: Splitting the first edge into multiple sub-edges, and calculating the pixel gradient value of each sub-edge respectively; and In response to the pixel gradient value being less than a preset pixel threshold, the corresponding sub-edge is determined to be the interference edge.

4. The processing method according to claim 3, characterized in that The step of respectively calculating the pixel gradient value of each sub-edge comprises: Calculating the contrast between a pixel point on each sub-edge and a pixel point in its neighborhood along a direction perpendicular to each sub-edge; and The pixel gradient value of the sub-edge is calculated based on the contrast between all pixels on the sub-edge and pixels in its neighborhood.

5. The processing method according to claim 3, characterized in that The step of removing the at least one interfering edge from the wafer image to determine the wafer edge further comprises: In response to the pixel gradient value being greater than the pixel threshold, determining a polarity of the sub-edge; and In response to the polarity being the same as a preset wafer polarity, the corresponding sub-edge is determined to be the wafer edge.

6. The processing method according to claim 1, wherein The step of obtaining interference point data of the imaging module includes: Acquiring a background image via the imaging module, wherein the background image includes at least one interference point caused by the imaging module; extracting a second edge in the background image, wherein the second edge includes an interference edge of each of the interference points; and The pixel gradient value of the second edge is calculated, and each of the interference edges is determined according to the pixel gradient value to form the interference point data.

7. The processing method according to claim 6, characterized in that Before extracting the second edge in the background image, the method further includes the following steps: Processing the background image using a filtering algorithm to filter noise in the background image; Performing dilation and erosion processing on the background image to smooth the edges of the interference points and fill the internal holes of the interference points; and The background image is converted into a binary image.

8. The processing method according to claim 1, wherein The wafer includes a notch for positioning, and the processing method further includes the following steps: Calculating the center position, radius, and relative angle of the notch of the wafer according to the wafer edge; and The wafer is positioned according to the center position and radius of the wafer and the relative angle of the notch.

9. A wafer image processing device, characterized in that: include: Memory; A controller is configured to: acquire an image of a wafer to be processed via an imaging module, wherein the wafer image includes a wafer and at least one interference point caused by the imaging module; acquire interference point data of the imaging module; and identify the wafer image based on the interference point data to determine the wafer edge of the wafer.

10. The processing device according to claim 9, characterized in that The controller is connected to a plurality of imaging modules, wherein the imaging modules are distributed around the wafer and are used to respectively capture wafer images of corresponding areas of the wafer.

11. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the wafer image processing method according to any one of claims 1 to 8 is implemented.

Images