Silicon wafer edge defect detection method and device under special chamfering process

Abstract

The invention discloses a silicon wafer edge defect detection method and device under a special chamfering process, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: obtaining a defect-free silicon wafer edge image under a special chamfering process, and obtaining an edge feature tensor through space unification, channel splicing and residual compression by taking the multi-layer and multi-scale features of the defect-free silicon wafer edge image in pre-training WideResNet50 as supervision; training and freezing an automatic encoder by taking the tensor as a target, and training a convolutional neural network by taking the output of the encoder as supervision; then, respectively carrying out edge defect detection on the to-be-detected image by utilizing an automatic encoder with frozen parameters and a trained convolutional neural network to obtain two groups of defect feature maps; generating defect feature maps by calculating pixel-by-pixel differences of the two groups of feature maps in channel, width and height dimensions, and mapping the defect feature maps into defect scores; and highlighting and positioning a defect area according to the defect score, and outputting a silicon wafer edge defect detection result. The method effectively solves the problem of insufficient industrial field defect labels.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method and device for detecting edge defects of silicon wafers under a special chamfering process. Background Art

[0002] Silicon wafer edge chamfering is a key mechanical process in semiconductor wafer manufacturing. In the initial stage, after the silicon ingot is cut into wafers, the wafer edges are usually sharp and rough, which not only affects the subsequent processing steps, but also increases the risk of wafer breakage. Through chamfering, these rough edges will be reshaped into smooth arc surfaces, thereby enhancing the mechanical strength of the wafer edge, effectively preventing cracks caused by stress generated during transportation, cleaning or heat treatment, and laying a solid foundation for subsequent polishing, high-temperature oxidation and other processes. Although edge chamfering is crucial to improving the overall quality of silicon wafer manufacturing, the process itself may introduce new defects. In the process of detecting edge defects of silicon wafers after edge chamfering, the size of silicon wafer defects varies greatly, ranging from large cracks to small scratches, posing a huge challenge to defect detection.

[0003] Existing technologies struggle to collect and annotate comprehensive data covering all possible defects due to the high diversity of silicon wafer edge defects and the potential for rare, previously unseen defects in silicon wafer production lines. Existing supervised learning detection algorithms struggle to address these challenges, resulting in silicon wafer defect detection accuracy insufficient to meet practical engineering requirements.

[0004] Therefore, there is an urgent need for a silicon wafer edge defect detection method that can effectively improve the accuracy of silicon wafer defect detection without the need for image labels. Summary of the Invention

[0005] Based on this, it is necessary to provide a method and device for detecting edge defects of silicon wafers under a special chamfering process to address the above technical problems.

[0006] The present invention adopts the following technical solutions: The present invention provides a method for detecting silicon wafer edge defects under a special chamfering process, comprising: Acquire defect-free silicon wafer edge images using a special double 45-degree edge chamfering process; Using a pre-trained WideResNet50 network as the backbone network, we extract multiple multi-scale feature maps from the first and second residual modules of a defect-free silicon wafer edge image. We unify the spatial dimensions of the multi-scale feature maps and concatenate them along the channel dimension. We then perform residual feature compression on the concatenated multi-scale feature maps to obtain a silicon wafer edge feature tensor. The silicon wafer edge feature tensor is used as the first supervision target to train an autoencoder, and all parameters of the trained autoencoder are frozen. The autoencoder with frozen parameters is used to process defect-free silicon wafer images to obtain an output feature map. The output feature map is used as the second supervision target to train a convolutional neural network. Edge defect detection is performed on the silicon wafer image to be tested using an autoencoder with frozen parameters and a trained convolutional neural network, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; the silicon wafer edge defect detection result is determined based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0007] Preferably, obtaining a defect-free silicon wafer edge image under a special chamfering process specifically includes: After the wafer is adsorbed and positioned in the center and horizontally aligned and angularly oriented, the wafer edge is stably illuminated by a ring light source; Using dual CCD linear array cameras symmetrically arranged on the upper and lower sides of the wafer and scanning at a fixed frequency, high-resolution images of the upper and lower 45-degree edges of the silicon wafer after chamfering are continuously acquired to obtain defect-free silicon wafer edge images.

[0008] Preferably, residual feature compression is performed on the spliced ​​multi-scale feature map to obtain a silicon wafer edge feature tensor, specifically including: The spliced ​​multi-scale feature maps are activated sequentially through 1×1 convolution, batch normalization, and ReLU activation function to obtain the first silicon wafer edge feature tensor; The spliced ​​multi-scale feature map is sequentially passed through 3×3 convolution, batch normalization, ReLU activation function activation, 3×3 convolution and batch normalization to obtain the second silicon wafer edge feature tensor; The first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor are spliced ​​to obtain a silicon wafer edge feature tensor.

[0009] Preferably, the spatial sizes of the multi-scale feature maps are unified by a bilinear interpolation method.

[0010] Preferably, the loss function used when training the convolutional neural network is: ; Where, L AS is the loss function for training convolutional neural networks, C, W, H are the number of channels, width, and height of the feature map, respectively. S ( I ) is the output of the convolutional neural network, A ( I ) is the output feature map of the automatic encoder after freezing the parameters, μ c A is the channel mean of the autoencoder output feature, σ c A The channel-wise standard deviation of the autoencoder output features.

[0011] Preferably, determining the silicon wafer edge defect detection result according to the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map specifically includes: Calculating pixel-by-pixel differences between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in channel, width, and height dimensions and mapping them into defect scores; According to the defect score, an edge defect feature map of the silicon wafer image to be tested is determined; according to the edge defect feature map, a silicon wafer edge defect detection result is determined.

[0012] Preferably, the calculation formula for mapping the pixel-by-pixel differences between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions into defect scores is: ; ; Where M AS is the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in channel, width, and height dimensions, S AS is the defect score of the silicon wafer image to be detected, C, W, and H are the number of channels, width, and height of the silicon wafer edge defect feature map, respectively. S(I) and A(I) are the outputs of the convolutional neural network and the autoencoder, respectively, i.e., the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map. μ A is the channel mean of the autoencoder output feature, σ A The channel-wise standard deviation of the autoencoder output features.

[0013] Preferably, determining an edge defect feature map of the silicon wafer image to be tested based on the defect score specifically includes: When the defect score is greater than a preset threshold, it indicates that the silicon wafer image to be tested has edge defects, and the image is determined as an edge defect feature map; otherwise, it indicates whether the silicon wafer image to be tested has edge defects.

[0014] Preferably, the defective portion of the silicon wafer edge defect feature map is highlighted in white, and the remaining portion is black; and determining the silicon wafer edge defect detection result according to the silicon wafer edge defect feature map specifically includes: According to the high-light positioning area of the defect part of the silicon wafer edge defect feature map, the position, size and shape of the high-light positioning area on the silicon wafer edge defect feature map are counted, that is, the silicon wafer edge defect detection result.

[0015] The application provides a silicon wafer edge defect detection device under a special chamfering process. The data acquisition module is configured to acquire an edge image of a defect-free silicon wafer under a double-45-degree edge special chamfering process. The feature compression module is configured to use a pre-trained WideResNet50 network as a backbone network to extract a plurality of multi-scale feature maps output by a first group of residual modules and a second group of residual modules in the backbone network. The model training module is configured to use the silicon wafer edge feature tensor as a first supervision target to train an auto-encoder and freeze all parameters of the trained auto-encoder. The defect detection module is configured to use the frozen auto-encoder and the trained convolutional neural network to respectively perform edge defect detection on a to-be-tested silicon wafer image to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map.

[0016] The application provides a computer-readable storage medium, which stores a computer program.

[0017] The application provides a computer device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor.

[0018] The above at least one technical solution adopted by the application can achieve the following beneficial effects: In a silicon wafer edge defect detection method under a special chamfering process provided by the present invention, the autoencoder can reconstruct the defective parts of the abnormal image on the test set, while the reconstruction ability of the convolutional neural network cannot generalize unknown abnormal patterns. The comparison of the output feature maps of the two can detect defects. When any defect labels are unknown in advance, it is still possible to efficiently and accurately distinguish defective images from normal images, and output a defect feature map. The feature map contains the position, size, and shape of the defect, and can detect defects of different scales at the same time. When only normal silicon wafer images are used for model training, abnormal silicon wafer images and defect information of different shapes and sizes can still be efficiently and reliably detected, realizing unsupervised detection of silicon wafer edge defects, effectively solving the problem of insufficient silicon wafer edge defect labels under the industrial on-site chamfering process, thereby effectively improving the accuracy of silicon wafer defect detection under the chamfering process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 A schematic flow chart of a method for detecting silicon wafer edge defects under a special chamfering process provided by the present invention; Figure 2 A schematic diagram of residual feature compression for a silicon wafer edge defect detection method under a special chamfering process provided by the present invention; Figure 3 A schematic diagram of the training of a convolutional neural network and an autoencoder for a method of detecting silicon wafer edge defects under a special chamfering process provided by the present invention; Figure 4 A schematic diagram of a device for detecting silicon wafer edge defects under a special chamfering process provided by the present invention; Figure 5 A schematic diagram of a computer device for implementing a method for detecting silicon wafer edge defects under a special chamfering process provided by the present invention. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments of the present invention and corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in the specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0022] In high-precision semiconductor manufacturing, the widely used chamfering method is a double 45-degree edge chamfering process. In this process, chamfering is performed on the approximately 45-degree inclined bevel between the top surface and the edge of the wafer and between the bottom surface and the edge, ensuring smooth transition around the edge of the wafer.

[0023] The existing silicon wafer chamfered edge defect detection in the industry relies on manual inspection, which is low in efficiency and difficult to guarantee accuracy. Based on computer vision and deep learning technology in artificial intelligence, the present application provides an efficient and reliable digital solution for unsupervised defect detection of high-resolution wafer edge images, showing strong abnormal detection, positioning and segmentation capabilities. At the same time, the lightweight characteristics of this scheme make it easy to deploy on industrial production lines. The unsupervised AI characteristics of this scheme make it independent of existing defect labels, allowing it to detect rare or unseen defects, solving the challenges of data size and label scarcity.

[0024] Existing intelligent defect recognition technology cannot use a single framework to cover both large and small defects, often requiring more complex model architectures to handle different defect sizes, resulting in large model parameter quantities and difficulty in deploying on the edge of industrial scenarios.

[0025] The following describes the technical solutions provided by the embodiments of the present application in detail in conjunction with the drawings.

[0026] Figure 1 The present application is a special chamfering process for silicon wafer edge defect detection method flowchart, specifically including the following steps: S101: Obtain a defect-free silicon wafer edge image under a double 45-degree edge special chamfering process.

[0027] Optionally, the defect-free silicon wafer edge image under the special chamfering process is obtained, specifically including: after the wafer is adsorbed and positioned in the center and horizontal calibration and angle orientation, the edge of the wafer is stably illuminated by a ring light source; using a double-CCD line array camera arranged symmetrically on the top and bottom of the wafer and scanned at a fixed frequency, high-resolution images of the 45-degree edges on the top and bottom of the silicon wafer after chamfering are continuously obtained, obtaining a defect-free silicon wafer edge image under a special chamfering process.

[0028] Specifically, the required image data is collected using a silicon wafer edge imaging system. The system ensures the accuracy of the wafer in terms of center positioning, horizontal calibration and angle orientation through the cooperation of the wafer suction platform and the groove alignment module. The system operates under stable lighting conditions provided by a ring-shaped light source and uses a double-CCD line array camera arranged symmetrically above and below to perform fixed frequency scanning, which can capture high-resolution images of the 45-degree edges of the wafer after chamfering. First, the edge images of 8 non-defective wafers are collected, each wafer containing about 150 high-resolution images (768x10000 pixels), and finally forming 8 non-defective data sets. Two of them are used for the information distillation step of transferring knowledge from the backbone network to the autoencoder network, and the other two are used for training the autoencoder-convolutional neural network architecture. The remaining 4 non-defective data sets, together with another 4 data sets each containing about 150 wafer manufacturing process image data sets containing defects, constitute 4 test sets for model performance evaluation. This design strictly implements the separation mechanism of distillation, training and testing, ensuring the reliability of model performance evaluation.

[0029] S102: using a pre-trained WideResNet50 network as a backbone network, extracting a plurality of multi-scale feature maps output by a first group of residual modules and a second group of residual modules of the non-defective silicon wafer edge image in the backbone network; uniform the spatial size of the multi-scale feature maps, and then splice along the channel dimension, and perform residual feature compression on the spliced multi-scale feature maps to obtain a silicon wafer edge feature tensor.

[0030] The spatial size of the multi-scale feature map is unified by a bilinear interpolation method Optionally, the spliced multi-scale feature map is subjected to residual feature compression to obtain a silicon wafer edge feature tensor, specifically including: the spliced multi-scale feature map is sequentially subjected to 1x1 convolution, batch normalization and ReLU activation function activation to obtain a first silicon wafer edge feature tensor; the spliced multi-scale feature map is sequentially subjected to 3x3 convolution, batch normalization, ReLU activation function activation, 3x3 convolution and batch normalization to obtain a second silicon wafer edge feature tensor; the first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor are spliced to obtain a silicon wafer edge feature tensor.

[0031] Specifically, the WideResNet50 residual network is used as the backbone network, and the output of the intermediate layer of the network is used to train the autoencoder network, as shown in Figure 2As shown, the knowledge distillation is realized from the rich feature information of the backbone network to the auto-encoder network with relatively simple architecture. All input images in this step are defect-free images. This processing step is specifically: extracting the target intermediate layers of the backbone network, taking the 1st and 2nd layers as examples. Using bilinear interpolation, the size of the output feature map is unified; the feature maps of different intermediate layers after size adjustment are spliced along the channel dimension, and the spliced data are input into the feature compression module as shown. Figure 2 As shown, the feature compression module includes a residual structure composed of a 1x1 convolution block and a 3x3 convolution block, which can improve the representation quality of the intermediate features and enhance the stability of the subsequent training; the target of the auto-encoder in this step is to learn the intermediate layers of the backbone network after the feature compression module, and the loss function adopts mean square error (MSE); the target of the auto-encoder in this step is to learn the intermediate layers of the backbone network after the feature compression module, and the loss function adopts mean square error (MSE).

[0032] S103: Taking the silicon wafer edge feature tensor as the first supervised target, training the auto-encoder, and freezing all parameters of the trained auto-encoder; using the auto-encoder with frozen parameters to process the defect-free silicon wafer image to obtain an output feature map; taking the output feature map as the second supervised target, training the convolutional neural network.

[0033] Optionally, the loss function used when training the convolutional neural network is: ; In the formula, L AS is the loss function for training the convolutional neural network, C, W, H is the channel number, width, and height of the feature map, respectively, S is the output of the convolutional neural network, I is the output feature map of the auto-encoder with frozen parameters, A I μ c A is the channel mean of the output feature of the auto-encoder, σ c A is the channel standard deviation of the output feature of the auto-encoder.

[0034] S104: Using the auto-encoder with frozen parameters and the trained convolutional neural network to respectively detect edge defects of a to-be-tested silicon wafer image to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; determining a silicon wafer edge defect detection result according to the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0035] ​​Optionally, based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map, the silicon wafer edge defect detection result is determined, specifically including: calculating the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width and height dimensions and mapping them into defect scores; based on the defect scores, determining the edge defect feature map of the silicon wafer image to be tested; based on the edge defect feature map, determining the silicon wafer edge defect detection result.

[0036] Optionally, a calculation formula for pixel-by-pixel differences between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in channel, width, and height dimensions is: ; ; Where M AS is the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in channel, width, and height dimensions, S AS is the defect score of the silicon wafer image to be detected, C, W, and H are the number of channels, width, and height of the silicon wafer edge defect feature map, respectively. S(I) and A(I) are the outputs of the convolutional neural network and the autoencoder, respectively, i.e., the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map. μ A is the channel mean of the autoencoder output feature, σ A The channel-wise standard deviation of the autoencoder output features.

[0037] Optionally, the silicon wafer edge defect detection result includes: the position, size and shape of the defect on the image of the silicon wafer to be tested.

[0038] Optionally, based on the defect score, an edge defect feature map of the silicon wafer image to be tested is determined, specifically including: when the defect score is greater than a preset threshold, it indicates that there is an edge defect in the silicon wafer image to be tested, and the image is determined as an edge defect feature map; otherwise, it indicates whether there is an edge defect in the silicon wafer image to be tested.

[0039] Specifically, because this solution is unsupervised learning, there's no fixed defect score threshold. The model's evaluation criteria are based on the Area Under the Receiver Operating Characteristic (AUROC) curve. In practice, the point on the ROC curve with the shortest distance to the upper left corner is used as the optimal threshold for determining whether an image is defective or not during inference. This value varies depending on the dataset.

[0040] Defect recognition is performed using an autoencoder-convolutional neural network comparative learning architecture. A model with strong image reconstruction capabilities, such as an autoencoder, is introduced for comparative learning with a conventional convolutional neural network, which has relatively weak reconstruction capabilities. For an autoencoder trained with knowledge distillation, even when processing abnormal inputs, its output feature maps remain consistent with those generated by normal samples. However, conventional convolutional neural networks lack the ability to generalize to unknown abnormal patterns due to their weak reconstruction capabilities. Therefore, when processing abnormal images, the outputs of the autoencoder and the convolutional neural network will differ significantly, and this difference can be used as a basis for abnormality detection, such as Figure 3 Figure 2 shows the parameters of the autoencoder network after freezing knowledge distillation. The network parameters remain unchanged throughout this step. Using a normal, defect-free silicon wafer edge image as input, the channel-wise mean and standard deviation of the autoencoder output feature map are first calculated and normalized. The convolutional neural network is trained using the processed autoencoder output feature map as the target.

[0041] Specifically, the trained autoencoder-convolutional neural network contrastive learning architecture can be used for image defect detection. Given a test dataset of silicon wafer edge images containing a mixture of normal and defective images, the architecture can distinguish between normal and defective images and highlight the defective areas. In the defect feature map, defective areas on the silicon wafer edge are highlighted in white, while the rest of the image is black. This demonstrates the location, shape, and size of the defect, and allows for segmentation between normal and defective areas.

[0042] An autoencoder-convolutional neural network (CNN) comparative learning framework. This framework uses the feature maps output by the autoencoder after distillation as the basis and trains a CNN to reconstruct these feature maps. This training step requires only normal, defect-free images, without the need for manual defect labels. After training, the autoencoder in this framework can reconstruct defect locations in abnormal images on a test set. However, the CNN's reconstruction capability cannot generalize to unknown abnormal patterns. Comparing the output feature maps of the two allows for defect detection.

[0043] This embodiment can efficiently and accurately distinguish defective images from normal images even when no defect labels are known in advance, and output a defect feature map, which includes the location, size, and shape of the defect. This method can detect defects of different sizes at the same time. In addition, since it is difficult for existing intelligent defect recognition technologies to use a set of frameworks to cover both large-scale defects and small defects, more complex model architectures are often required to cope with different defect scales. The resulting model has a large number of parameters and is difficult to deploy at the edge of industrial scenarios. To address this problem, the present invention can effectively reduce the number of parameters of the silicon wafer defect detection model by performing residual feature compression on the multi-scale feature maps of the spliced ​​silicon wafers, thereby achieving lightweight silicon wafer defect detection models.

[0044] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present invention.

[0045] The above is a method for detecting silicon wafer edge defects under a special chamfering process provided by one or more embodiments of the present invention. Based on the same idea, the present invention also provides a corresponding device for detecting silicon wafer edge defects under a special chamfering process, such as Figure 4 shown.

[0046] Figure 4 A schematic diagram of a silicon wafer edge defect detection device under a special chamfering process provided by the present invention, the device comprising: The data acquisition module 401 is used to acquire a defect-free silicon wafer edge image using a double 45-degree edge special chamfering process; The feature compression module 402 is configured to extract multiple multi-scale feature maps output by the first and second residual modules of the backbone network of the defect-free silicon wafer edge image using the pre-trained WideResNet50 network as the backbone network; unify the spatial dimensions of the multi-scale feature maps, concatenate them along the channel dimension, and perform residual feature compression on the concatenated multi-scale feature maps to obtain a silicon wafer edge feature tensor; The model training module 403 is used to train an autoencoder using the silicon wafer edge feature tensor as a first supervision target, and freeze all parameters of the trained autoencoder; process a defect-free silicon wafer image using the autoencoder with frozen parameters to obtain an output feature map; and train a convolutional neural network using the output feature map as a second supervision target; The defect detection module 404 is used to use the autoencoder with frozen parameters and the trained convolutional neural network to perform edge defect detection on the silicon wafer image to be tested, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; and determine the silicon wafer edge defect detection result based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0047] Regarding the specific definition of the silicon wafer edge defect detection device under a special chamfering process, please refer to the definition of the silicon wafer edge defect detection method under a special chamfering process mentioned above, which will not be repeated here. The various modules in the above-mentioned silicon wafer edge defect detection device under a special chamfering process can be implemented in whole or in part through software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0048] The present invention also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 1 A method for detecting silicon wafer edge defects under a special chamfering process is provided.

[0049] The present invention also provides Figure 5 The structural diagram of the computer equipment shown in FIG. Figure 5 As shown in the figure, at the hardware level, the computer device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory. Of course, it may also include other hardware required for the business. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to achieve the above Figure 1 A method for detecting silicon wafer edge defects under a special chamfering process is provided.

[0050] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware using a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes in the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

Claims

1. A method for detecting silicon wafer edge defects under a special chamfering process, characterized in that: include: Acquire defect-free silicon wafer edge images using a special double 45-degree edge chamfering process; Using a pre-trained WideResNet50 network as the backbone network, we extract multiple multi-scale feature maps from the first and second residual modules of a defect-free silicon wafer edge image. We unify the spatial dimensions of the multi-scale feature maps and concatenate them along the channel dimension. We then perform residual feature compression on the concatenated multi-scale feature maps to obtain a silicon wafer edge feature tensor. The silicon wafer edge feature tensor is used as the first supervision target to train an autoencoder, and all parameters of the trained autoencoder are frozen. The autoencoder with frozen parameters is used to process defect-free silicon wafer images to obtain an output feature map. The output feature map is used as the second supervision target to train a convolutional neural network. Edge defect detection is performed on the silicon wafer image to be tested using an autoencoder with frozen parameters and a trained convolutional neural network, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; the silicon wafer edge defect detection result is determined based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

2. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, wherein: The step of obtaining a defect-free silicon wafer edge image under a special chamfering process specifically includes: After the wafer is adsorbed and positioned in the center and horizontally aligned and angularly oriented, the wafer edge is stably illuminated by a ring light source; Using dual CCD linear array cameras symmetrically arranged on the upper and lower sides of the wafer and scanning at a fixed frequency, high-resolution images of the upper and lower 45-degree edges of the silicon wafer after chamfering are continuously acquired to obtain defect-free silicon wafer edge images.

3. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, wherein: The residual feature compression is performed on the spliced ​​multi-scale feature map to obtain the silicon wafer edge feature tensor, specifically including: The spliced ​​multi-scale feature maps are activated sequentially through 1×1 convolution, batch normalization, and ReLU activation function to obtain the first silicon wafer edge feature tensor; The spliced ​​multi-scale feature map is sequentially passed through 3×3 convolution, batch normalization, ReLU activation function activation, 3×3 convolution and batch normalization to obtain the second silicon wafer edge feature tensor; The first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor are spliced ​​to obtain a silicon wafer edge feature tensor.

4. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, wherein: The spatial sizes of the multi-scale feature maps are unified by a bilinear interpolation method.

5. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, wherein: The loss function used in training the convolutional neural network is: ； Where, L AS is the loss function for training convolutional neural networks, C, W, H are the number of channels, width, and height of the feature map, respectively. S ( I ) is the output of the convolutional neural network, A ( I ) is the output feature map of the automatic encoder after freezing the parameters, μ c A is the channel mean of the autoencoder output feature, σ c A The channel-wise standard deviation of the autoencoder output features.

6. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 1, wherein: The determining of the silicon wafer edge defect detection result based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map specifically includes: Calculating pixel-by-pixel differences between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in channel, width, and height dimensions and mapping them into defect scores; According to the defect score, an edge defect feature map of the silicon wafer image to be tested is determined; according to the edge defect feature map, a silicon wafer edge defect detection result is determined.

7. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 6, wherein: The calculation formula for mapping the pixel-by-pixel differences between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions into defect scores is: ； ； Where M AS is the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in channel, width, and height dimensions, S AS is the defect score of the silicon wafer image to be detected, C, W, and H are the number of channels, width, and height of the silicon wafer edge defect feature map, respectively. S(I) and A(I) are the outputs of the convolutional neural network and the autoencoder, respectively, i.e., the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map. μ A is the channel mean of the autoencoder output feature, σ A The channel-wise standard deviation of the autoencoder output features.

8. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 6, wherein: Determining an edge defect feature map of the silicon wafer image to be tested based on the defect score specifically includes: When the defect score is greater than a preset threshold, it indicates that the silicon wafer image to be tested has edge defects, and the image is determined as an edge defect feature map; otherwise, it indicates whether the silicon wafer image to be tested has edge defects.

9. The method for detecting silicon wafer edge defects under a special chamfering process according to claim 6, wherein: The defective portion of the silicon wafer edge defect feature map is highlighted in white, and the remaining portion is black; and determining the silicon wafer edge defect detection result based on the silicon wafer edge defect feature map specifically includes: According to the highlighted positioning area of ​​the defective part of the silicon wafer edge defect feature map, the position, size and shape of the highlighted positioning area on the silicon wafer edge defect feature map are counted, which is the silicon wafer edge defect detection result.

10. A device for detecting silicon wafer edge defects under a special chamfering process, characterized in that: include: A data acquisition module is used to obtain defect-free silicon wafer edge images using a special double 45-degree edge chamfering process; The feature compression module is used to extract multiple multi-scale feature maps output by the first and second residual modules of the backbone network of the defect-free silicon wafer edge image using the pre-trained WideResNet50 network as the backbone network; the multi-scale feature maps are unified in spatial size and then spliced ​​along the channel dimension, and residual feature compression is performed on the spliced ​​multi-scale feature maps to obtain the silicon wafer edge feature tensor; The model training module uses the silicon wafer edge feature tensor as the first supervision target to train the autoencoder and freeze all parameters of the trained autoencoder. The autoencoder with frozen parameters is used to process defect-free silicon wafer images to obtain an output feature map. The output feature map is used as the second supervision target to train the convolutional neural network. The defect detection module is used to use the autoencoder with frozen parameters and the trained convolutional neural network to perform edge defect detection on the silicon wafer image to be tested, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; and determine the silicon wafer edge defect detection result based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

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