Time sequence counter control method and circuit, electronic equipment and storage medium

Abstract

The invention provides a time sequence counter control method and circuit, electronic equipment and a storage medium, and belongs to the technical field of computer application, the method comprises the following steps: in response to an input first time sequence counting request, selecting a target time sequence counter from time sequence counters in an idle state in a counter pool; and distributing the target time sequence counter to the first time sequence counting request, so that the target time sequence counter counts a time sequence corresponding to the first time sequence counting request. The time sequence counter in the idle state in the counter pool serves as the target time sequence counter and is dynamically allocated to the input first time sequence counting request, and compared with a scheme of deploying a counter for each read-write time sequence in the prior art, the time sequence counting method does not need a large number of time sequence counters, and is beneficial to reducing the scale and cost of an integrated circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer application, and in particular to a timing counter control method, circuit, electronic device and storage medium. BACKGROUND

[0002] The timing counter is one of the core parts of a DDR memory controller, and is mainly used for checking various read / write timing requirements of the DDR memory. There are many types of read / write timing of the DDR memory, and the existing DDR memory timing device usually deploys one counter for each read / write timing to meet various read / write timing of the DDR memory. This way will lead to an increase in the circuit size, which is not conducive to circuit integration. SUMMARY

[0003] The present application provides a timing counter control method, circuit, electronic device and storage medium, which solves the defects that the existing DDR memory timing device deploys one counter for each read / write timing, leading to an increase in the circuit size, which is not conducive to circuit integration.

[0004] The present application provides a timing counter control method, which comprises: selecting a target timing counter from the timing counters in an idle state in a counter pool in response to an input first timing count request; allocating the target timing counter to the first timing count request, so that the target timing counter counts the timing corresponding to the first timing count request.

[0005] As an embodiment, after the target timing counter is allocated to the first timing count request, so that the target timing counter counts the timing corresponding to the first timing count request, the method further comprises: setting the state of the target timing counter to the idle state when the first timing count request is executed; releasing the target timing counter.

[0006] As an embodiment, the selecting a target timing counter from the timing counters in an idle state in a counter pool in response to an input first timing count request comprises: determining the request timing count type corresponding to the first timing count request in response to the input first timing count request; selecting, as the target timing counter, the timing counter corresponding to the request timing count type from the timing counters in an idle state in the counter pool, or selecting, as the target timing counter, the timing counter with a non-fixed timing count type from the timing counters in an idle state in the counter pool.

[0007] As an embodiment, selecting a time series counter with a non-fixed time series counting type from idle time series counters in the counter pool as a target time series counter includes: A timing counter with a non-fixed timing counting type and in a fixed bank matching the first timing counting request is selected from the timing counters in the idle state in the counter pool as a target timing counter.

[0008] As an embodiment, before allocating the target timing counter to the first timing count request, the method further includes: If the number of idle state timing counters is insufficient, select a first timing counter from the counter pool and reset and start the first timing counter, where the first timing counter is a counter whose timing counting type matches the first timing counting request among the busy state timing counters; The reset-enabled first timing counter is responsible for timing counting of at least two timing counting requests including the first timing counting request.

[0009] As an embodiment, before responding to the input first timing count request, the method further includes: outputting a corresponding timing counting result according to the received first query request, where the first query request is a query request generated when the DDR controller determines that a first DDR operation command needs to be executed; determining whether the first DDR operation command can be executed according to the timing counting result; The step of selecting a target timing counter from idle timing counters in a counter pool in response to the input first timing counting request includes: In response to the first timing count request generated when the first DDR operation command can be executed, the target timing counter is selected from idle timing counters in a counter pool.

[0010] As an embodiment, the timing counting result is a timing counting result of timing counting requests related to other DDR operation commands before the first DDR operation command is executed.

[0011] The present invention also provides a timing counter control circuit, comprising: A counter allocation module, configured to select a target timing counter from idle timing counters in a counter pool in response to an input first timing counting request; The counting module is configured to allocate the target timing counter to the first timing counting request, so that the target timing counter counts the timing corresponding to the first timing counting request.

[0012] The present invention also provides an electronic device, comprising the timing counter control circuit as described above; Alternatively, the electronic device includes a processor, a memory, and a computer program stored in the memory and running on the processor, and the computer program implements the timing counter control method as described above when executed by the processor.

[0013] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which implements any of the above-mentioned timing counter control methods when executed by a processor.

[0014] The present invention also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements any of the above-mentioned timing counter control methods.

[0015] The timing counter control method, circuit, electronic device, and storage medium provided by the present invention use idle timing counters in a counter pool as target timing counters and dynamically assign them to the first input timing count request. Compared with the prior art solution of deploying a counter for each read and write timing, the present invention does not require a large number of timing counters, which is conducive to reducing the scale and cost of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a flow chart of the timing counter control method provided by the present invention.

[0018] Figure 2 This is one of the structural diagrams of the timing counter control circuit provided by the present invention.

[0019] Figure 3 This is the second structural diagram of the timing counter control circuit provided by the present invention.

[0020] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0022] Typical timing requirements for DDR memory include tRCD, tRP, tRAS, tRFC, tFAW, etc.

[0023] tRCD (RAS to CAS Delay) refers to the row address strobe to column address strobe delay. Simply put, it is the time required to wait between activating a row of memory (RAS) and being able to access the column in the row (CAS).

[0024] tRP (RAS Precharge) refers to the row precharge time. Precharge is required before closing an activated memory row (in order to activate a new row). tRP is the time required to complete the precharge process.

[0025] tRAS (RAS Active Time) refers to the row valid time, which is the time from activating a row of memory (RAS) to issuing a precharge command (Precharge).

[0026] tRFC (Row Refresh Cycle Time) refers to the row refresh cycle time. DRAM needs to be refreshed periodically to retain data. tRFC is the cycle time required to refresh a row of memory.

[0027] tFAW (Four Activate Window) refers to the four activation window time. Within a certain time window (tFAW), the maximum number of rows allowed to be activated is four. This parameter is intended to prevent memory overload and ensure stable memory operation.

[0028] In the typical timing of DDR memory, taking tRP timing as an example, the data of the memory rank is divided into 16 independent storage unit banks. Among them, a rank refers to a group of DRAM chips controlled in parallel by a memory controller, which share the same chip select signal. When the memory controller issues a read or write command, it can operate in parallel on these 16 banks, thereby improving data transmission efficiency. Among them, a rank refers to a group of physical memory chips that provides a 64-bit data channel (in non-ECC memory) or a 72-bit data channel (in ECC memory). Bank allows the memory controller to operate on different banks at the same time, reducing the delay caused by waiting for a single storage unit to complete the operation.

[0029] If 4 DDR ranks are connected, 16*4=64 counters are needed to count tRP. If other timing sequences are included, the number of required timing counters may reach thousands. For integrated circuits, this is a large hardware circuit scale, which is costly and not conducive to reducing circuit area.

[0030] To address the above-mentioned drawbacks, the present invention proposes a timing counter control method, circuit, and DDR memory controller, which are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 FIG. 1 is a flow chart of the timing counter control method provided by the present invention, as shown in FIG. Figure 1 As shown, the present invention provides a timing counter control method, which includes the following steps.

[0032] Step S100 : In response to an input first timing counting request, a target timing counter is selected from idle timing counters in a counter pool.

[0033] Step S200: Allocate the target timing counter to the first timing counting request, so that the target timing counter counts the timing corresponding to the first timing counting request.

[0034] Optionally, before step S100, the present invention preliminarily constructs a counter pool using a plurality of timing counters, and the number of timing counters in the counter pool is determined according to the number of banks of the DDR memory, for example, the number of timing counters is set to one tenth of the number of banks of the DDR memory.

[0035] In other embodiments, the number of timing counters can also be determined comprehensively based on the number of banks of the DDR memory and the number of DDR operation commands. For example, the initial value is first determined based on the number of banks of the DDR memory, and then adjusted based on the number of DDR operation commands. If the number of DDR operation commands is large, the initial value is increased, otherwise, the initial value is decreased.

[0036] In other embodiments, weights may be assigned to the number of DDR memory banks and the number of DDR operation commands respectively, and the number of timing counters may be determined by multiplying the number of DDR memory banks and the number of DDR operation commands by their respective weights.

[0037] If the timing counter in the counter pool is counting, it is in the busy state; if it is not counting, it is in the idle state.

[0038] In step S100, a first timing count request is generated based on the DDR operation command. Generating these first timing count requests is a complex process that involves collaboration between the memory controller, CPU, and other system components. Simply put, this ensures that memory access operations occur at the correct time to meet the timing requirements of DDR memory.

[0039] The simplified steps of the first timing count request generation process are as follows: The CPU or other device initiates a memory access request: When the CPU needs to read data from or write data to the memory, it sends a memory access request to the memory controller, which contains the memory address to be accessed, the operation type (read or write), and other related information.

[0040] The memory controller receives the request and performs address translation: After receiving the request from the CPU, the memory controller translates the logical address sent by the CPU into a physical address, which involves table lookup and calculation to determine the specific location of the memory unit to be accessed.

[0041] The memory controller generates a first timing count request based on timing parameters: The memory controller generates a series of first timing count requests based on pre-set timing parameters (such as tRCD, tRP, tRAS, etc.) and the current memory status to control various stages of memory access operations, such as activating memory rows, selecting memory columns, and sending read and write commands.

[0042] Optionally, in step S100, in response to the input first timing count request, a target timing counter is selected from the idle state timing counters in the counter pool. Specifically, the status of each timing counter in the counter pool is monitored, such as constructing a list of idle state timing counters and a list of busy state timing counters, determining the idle state timing counters in the counter pool, and then selecting a timing counter corresponding to the type of the first timing count request from the idle state timing counters as the target timing counter.

[0043] Optionally, in step S200, the target timing counter is assigned to the first timing count request, which can be achieved by associating the flag bit of the target timing counter with the relevant information of the first timing count request.

[0044] It can be understood that the present application is different from the logic of the prior art, and instead of setting a timing counter for each DDR bank, a dynamic counter pool is established, and when a certain first timing count request needs to be counted, one of the idle timing counters is called to count, and a large number of timing counters do not need to be deployed, a small number of timing counters are used to complete a large number of first timing count requests, and the implementation size and cost of the circuit are reduced.

[0045] It should be further noted that in the timing counting process of the embodiment, the timing delay duration or period related to the timing parameters described above is counted, and the delay period can reflect the read-write process of the DDR and / or the operation of the related operation instructions. In other implementation manners, the timing counter described above can also count some special time points.

[0046] Based on the above embodiment, as an optional embodiment, after the target timing counter is assigned to the first timing count request for the target timing counter to count the timing corresponding to the first timing count request, the method further comprises: Step S300: setting the state of the target timing counter to an idle state when the first timing count request is executed.

[0047] Step S400: releasing the target timing counter.

[0048] In step S300, the target timing counter counts the timing corresponding to the first timing count request to obtain a counting result, and after obtaining the counting result, the target timing counter completes the counting and sets the state of the target timing counter to an idle state again.

[0049] In step S400, releasing the target timing counter specifically means modifying or resetting the flag bit of the target timing counter and disconnecting the target timing counter from the first timing count request.

[0050] It can be understood that after the first timing count request is executed, the state of the target timing counter is set to an idle state, and the target timing counter is released, so as to be used by other first timing count requests, thereby improving the use efficiency of the timing counter, and achieving dynamic allocation of the idle timing counter in the counter pool to the input first timing count request, that is, dynamic allocation of the timing counter is completed, so that a small number of timing counters are used to complete a large number of first timing count requests.

[0051] On the basis of the above-mentioned embodiments, as an optional embodiment, the time sequence counter is provided with at least two types of flag bits to represent whether the time sequence counter is in an idle state and the time sequence counting type that can be completed, and at least one of the flag bits of each type is non-fixed to realize dynamic allocation.

[0052] Each time sequence counter in the counter pool is provided with at least two types of flag bits to represent whether the time sequence counter is in an idle state and the time sequence counting type that can be completed, so as to allocate a target time sequence counter in an idle state and corresponding to the time sequence counting type of the first time sequence counting request to the input first time sequence counting request.

[0053] Optionally, the time sequence counter is provided with a bank flag, a rank flag, an idle flag and a type flag, the idle flag is used to represent whether the time sequence counter is in an idle state, and the type flag is used to represent the time sequence counting type that can be completed by the time sequence counter.

[0054] When the time sequence counter is counting, the idle flag is busy, and when the counting is completed, the idle flag becomes idle again.

[0055] At least one of the bank flag, the rank flag, the idle flag and the type flag is non-fixed to realize dynamic allocation.

[0056] The present application constructs a counter pool that can realize dynamic allocation, and the counter pool can not adopt the mode of full dynamic allocation, that is, the information flags of a part of time sequence counters are fixedly allocated, and the information flags of another part of time sequence counters are modifiable to realize dynamic allocation.

[0057] For example, a first time sequence counting request of a certain time sequence type can be fixedly allocated to some time sequence counters, and only the bank flag and the rank flag of the time sequence counters are modifiable. A first time sequence counting request of a certain bank flag can also be fixedly allocated to certain time sequence counters, and only the time sequence type and the rank information of the time sequence counters are modifiable.

[0058] It can be understood that the present application sets at least two types of flag bits for each time sequence counter to represent whether the time sequence counter is in an idle state and the time sequence counting type that can be completed, and sets at least one of the flag bits of each type as non-fixed, so that the time sequence counting request of different time sequence counting types can meet the real-time change requirement through the way of dynamically modifying the flag bits.

[0059] Based on the above embodiment, as an optional embodiment, the step of selecting a target timing counter from idle timing counters in a counter pool in response to the input first timing counting request includes steps S110 to S120.

[0060] Step S110 : In response to an input first timing count request, determining a requested timing count type corresponding to the first timing count request.

[0061] Step S120: Select a timing counter corresponding to the requested timing counting type from the idle timing counters in the counter pool as the target timing counter, or select a timing counter with a non-fixed timing counting type from the idle timing counters in the counter pool as the target timing counter.

[0062] Optionally, step S110 further includes, in response to the input first timing count request, determining the request timing count type, request repository information and request rank information corresponding to the first timing count request.

[0063] The request repository information and the request rank information are used to modify the flag bit corresponding to the target timing counter so that the target timing counter is associated with the first timing technology request, that is, the target timing counter is assigned to the first timing counting request.

[0064] In some optional examples of step S120, when the number of timing counters corresponding to the requested timing count type in the idle timing counters in the counter pool is sufficient, one of the timing counters can be randomly or sequentially selected as the target timing counter, or a timing counter with a non-fixed timing count type can be selected to obtain the target timing counter.

[0065] Alternatively, when there is no timing counter corresponding to the requested timing counting type among the timing counters in the idle state or the number of the timing counters is insufficient, the target timing counter may be selected from the timing counters with non-fixed timing counting types.

[0066] After determining the target timing counter, the repository flag of the target timing counter can be modified to the requested repository information, the rank flag of the target timing counter can be modified to the requested rank information, and the idle state of the target timing counter can be modified to the busy state.

[0067] It can be understood that the present invention selects a timing counter corresponding to the requested timing counting type, or a timing counter with a non-fixed timing counting type as the target timing counter, and provides a selection scheme for the target timing counter to facilitate classification management in the counter pool.

[0068] On the basis of the above-mentioned embodiments, as an optional embodiment, the step of selecting a time sequence counter of a non-fixed type from the time sequence counters in the idle state in the counter pool as the target time sequence counter comprises: From the time sequence counters in the idle state in the counter pool, a time sequence counter of a non-fixed type under a fixed bank matched with the first time sequence count request is selected as the target time sequence counter.

[0069] It can be understood that by selecting a time sequence counter of a non-fixed type under a fixed bank as the target time sequence counter, the time for selecting the target time sequence counter can be shortened, and the allocation efficiency can be improved under the condition of ensuring dynamic allocation of the time sequence counter.

[0070] On the basis of the above-mentioned embodiments, as an optional embodiment, the step of allocating the target time sequence counter to the first time sequence count request further comprises: If the number of time sequence counters in the idle state is insufficient, a first time sequence counter is selected from the counter pool and reset to start, the first time sequence counter being a time sequence counter in a busy state and of a type matched with the first time sequence count request. The first time sequence counter reset to start is used for time sequence counting of at least two time sequence count requests including the first time sequence count request.

[0071] If all the time sequence counters in the counter pool are allocated, there is no idle time sequence counter, and a new first time sequence count request enters, time sequence counters of the same type in the counter pool can be reset to start so as to count the original time delay period and the new time delay period at the same time.

[0072] It can be understood that when the number of the time sequence counters allocated dynamically is insufficient, the present application can compensate for the deficiency by merging the first time sequence count requests of the same type into the same time sequence counter, so as to reduce the number of the time sequence counters, reduce the size and cost of the DDR controller logic, and ensure smooth time sequence counting.

[0073] On the basis of the above-mentioned embodiments, as an optional embodiment, the step of responding to the input first time sequence count request further comprises: According to the received first query request, a corresponding time sequence count result is output, the first query request being a query request generated when a first DDR operation command determined by the DDR controller needs to be executed.

[0074] According to the time sequence count result, it is determined whether the first DDR operation command can be executed.

[0075] When a DDR operation command needs to be executed, the DDR controller will generate the timing query request required for this command, that is, the first query request. Then, upon receiving the first query request, this embodiment can query the timing count result related to the operation command before the request and output the timing count result.

[0076] It should be noted that the aforementioned timing count result is the timing count result of timing count requests related to other DDR operation commands before the execution of the first DDR operation command. This timing count result can be used to determine whether the DDR operation command has been executed. If the timing query results related to other DDR operation commands before the operation command are not output, it indicates that the command has not been executed. The timing count result can be continuously queried until a timing count result is found, indicating that the command has been executed.

[0077] On the other hand, when the DDR operation command is executed, a new timing count request is generated. Based on the type of the command, a first timing count request is generated to allocate and start a timing counter associated with the command to count the timing. This also facilitates querying the timing of the command when subsequent DDR operation commands are executed.

[0078] That is, the process of selecting a target timing counter from idle timing counters in the counter pool in response to the input first timing counting request may include: In response to a first timing count request generated when the first DDR operation command can be executed, a target timing counter is selected from idle timing counters in a counter pool.

[0079] In summary, it can be understood that counting result query and timing counter allocation is a cyclic process. Before a command is executed, the timing delay related to the previous operation command needs to be queried to output the timing counting result. At the same time, when the command is executed, a new timing counting request will be generated synchronously, thus ensuring the sequential execution of DDR operation commands as a whole.

[0080] The timing counter control circuit provided by the present invention is described below. The timing counter control circuit described below and the timing counter control method described above can be referenced to each other.

[0081] Figure 2 This is one of the structural diagrams of the timing counter control circuit provided by the present invention. Figure 3 This is the second structural diagram of the timing counter control circuit provided by the present invention, such as Figure 2 and Figure 3 As shown, the present invention also provides a timing counter control circuit, comprising: The counter allocation module 210 is configured to select a target timing counter from idle timing counters in a counter pool in response to an input first timing counting request; The counting module 220 is configured to allocate the target timing counter to the first timing counting request, so that the target timing counter counts the timing corresponding to the first timing counting request.

[0082] As an embodiment, it also includes: The counter releasing module is configured to set the state of the target timing counter to an idle state and release the target timing counter when the first timing counting request is executed.

[0083] As an embodiment, the timing counter is provided with at least two types of flag bits to indicate whether the timing counter is in an idle state and the type of timing counting that can be completed, and at least one of the flag bits of each type is non-fixed to achieve dynamic allocation.

[0084] As an embodiment, the counter allocation module 210 is further configured to: In response to an input first timing count request, determining a request timing count type corresponding to the first timing count request; A timing counter corresponding to the requested timing counting type is selected from the idle timing counters in the counter pool as the target timing counter, or a timing counter with a non-fixed timing counting type is selected from the idle timing counters in the counter pool as the target timing counter.

[0085] As an embodiment, the counter allocation module 210 is further configured to: A timing counter with a non-fixed timing counting type and under a fixed bank matching the first timing counting request is selected from the timing counters in the idle state in the counter pool as a target timing counter.

[0086] As an embodiment, the counter allocation module 210 is further configured to: If the number of idle state timing counters is insufficient, select a first timing counter from the counter pool and reset and start the first timing counter, where the first timing counter is a counter whose timing counting type matches the first timing counting request among the busy state timing counters; The reset-enabled first timing counter is responsible for timing counting of at least two timing counting requests including the first timing counting request.

[0087] As an embodiment, the circuit further includes: The query module is configured to output a corresponding timing counting result according to a received first query request, the first query request being a query request generated when a DDR controller determines that a first DDR operation command needs to be executed; and determine whether the first DDR operation command can be executed according to the timing counting result.

[0088] The counter allocation module 210 is further configured to select the target timing counter from timing counters in an idle state in a counter pool in response to the first timing counting request generated when the first DDR operation command can be executed.

[0089] As an embodiment, the timing counting result is a timing counting result of a timing counting request related to other DDR operation commands before execution of the first DDR operation command.

[0090] It is also necessary to continue to refer to Figure 3 , Figure 3 The counter pool, the idle query and allocation module, and the counting result output module are shown.

[0091] The idle query and allocation module is configured to select a target timing counter from timing counters in an idle state in a counter pool in response to a first timing counting request generated when the first DDR operation command is executed. Thus, the target timing counter can be allocated to the first timing counting request, so that the target timing counter counts a timing corresponding to the first timing counting request.

[0092] The counting result output module is configured to output a corresponding timing counting result according to a received first query request, the first query request being a query request generated when a DDR controller determines that a first DDR operation command needs to be executed; and determine whether the first DDR operation command can be executed according to the timing counting result.

[0093] The following describes a DDR memory controller provided by the present application, which can be correspondingly referred to the timing counter control method and the timing counter control circuit described above.

[0094] Figure 4 is a structural schematic diagram of an electronic device provided by the present application, as Figure 4 The present application further provides an electronic device including a DDR memory, a controller, and a timing counter control circuit, the controller interacting data with the DDR memory and the timing counter control circuit respectively, and being configured to generate a first timing counting request and a timing query request according to a DDR operation command to be executed, and send the first timing counting request and the timing query request to the timing counter control circuit.

[0095] The first timing count request is generated based on the DDR operation command. Generating the first timing count request is a complex process that involves the coordination between the memory controller, CPU, and other system components. Simply put, it is to ensure that memory access operations occur at the correct time to meet the timing requirements of DDR memory.

[0096] The above-mentioned timing counter control circuit is the timing counter control circuit involved in the above-mentioned embodiment.

[0097] Alternatively, the electronic device provided by the present invention is used to execute the timing counter control method described in any of the above embodiments, and has the technical effect corresponding to the timing counter control method, which will not be repeated here.

[0098] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the timing counter control method provided by the above methods, and the method includes: in response to an input first timing count request, selecting a target timing counter from the idle timing counters in the counter pool; allocating the target timing counter to the first timing count request, so that the target timing counter counts the timing corresponding to the first timing count request.

[0099] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the timing counter control method provided by the above methods, the method comprising: in response to an input first timing count request, selecting a target timing counter from the idle timing counters in the counter pool; allocating the target timing counter to the first timing count request, so that the target timing counter counts the timing corresponding to the first timing count request.

[0100] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0101] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A timing counter control method, characterized in that: include: In response to an input first timing counting request, selecting a target timing counter from idle timing counters in a counter pool; The target timing counter is allocated to the first timing counting request, so that the target timing counter counts the timing corresponding to the first timing counting request.

2. The timing counter control method according to claim 1, wherein: After allocating the target timing counter to the first timing counting request so that the target timing counter counts the timing corresponding to the first timing counting request, the method further includes: When the first timing counting request is executed, setting the state of the target timing counter to an idle state; Release the target timing counter.

3. The timing counter control method according to claim 1, wherein: The step of selecting a target timing counter from idle timing counters in a counter pool in response to the input first timing counting request includes: In response to an input first timing count request, determining a request timing count type corresponding to the first timing count request; A timing counter corresponding to the requested timing counting type is selected from the idle timing counters in the counter pool as the target timing counter, or a timing counter with a non-fixed timing counting type is selected from the idle timing counters in the counter pool as the target timing counter.

4. The timing counter control method according to claim 3, wherein: The step of selecting a time series counter with a non-fixed time series counting type from the time series counters in the idle state in the counter pool as the target time series counter includes: A timing counter with a non-fixed timing counting type and under a fixed bank matching the first timing counting request is selected from the timing counters in the idle state in the counter pool as a target timing counter.

5. The timing counter control method according to claim 1, wherein: Before allocating the target timing counter to the first timing count request, the method further includes: If the number of idle state timing counters is insufficient, select a first timing counter from the counter pool and reset and start the first timing counter, where the first timing counter is a counter whose timing counting type matches the first timing counting request among the busy state timing counters; The reset-enabled first timing counter is responsible for timing counting of at least two timing counting requests including the first timing counting request.

6. The timing counter control method according to claim 1, wherein: Before responding to the input first timing count request, the method further includes: outputting a corresponding timing counting result according to the received first query request, where the first query request is a query request generated when the DDR controller determines that a first DDR operation command needs to be executed; determining whether the first DDR operation command can be executed according to the timing counting result; The step of selecting a target timing counter from idle timing counters in a counter pool in response to the input first timing counting request includes: In response to the first timing count request generated when the first DDR operation command can be executed, the target timing counter is selected from idle timing counters in a counter pool.

7. The timing counter control method according to claim 6, wherein: The timing counting result is a timing counting result of timing counting requests related to other DDR operation commands before the first DDR operation command is executed.

8. A timing counter control circuit, characterized in that: include: A counter allocation module, configured to select a target timing counter from idle timing counters in a counter pool in response to an input first timing counting request; The counting module is configured to allocate the target timing counter to the first timing counting request, so that the target timing counter counts the timing corresponding to the first timing counting request.

9. An electronic device, characterized in that: comprising the timing counter control circuit according to claim 8; Alternatively, the electronic device includes a processor, a memory, and a computer program stored in the memory and running on the processor, and when the computer program is executed by the processor, the timing counter control method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the timing counter control method according to any one of claims 1 to 7 is implemented.

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