Broadband low-distortion phase compensation type vector modulation phase shifter system

Abstract

The invention discloses a broadband low-distortion phase compensation type vector modulation phase shifter system, and belongs to the technical field of radio frequency integrated circuits. The system comprises an orthogonal shunt module for decomposing an input radio frequency signal into an in-phase (I) signal and an orthogonal (Q) signal; the biphase variable gain amplifier module adopts a five-stage binary weighted parallel unit and a polarity switching circuit, and realizes 0-360 degree (2.8125 degree stepping) phase adjustment and + / -15dB gain control through digital control words; and the common base synthesis module and the LC matching network are used for current vector synthesis and broadband impedance matching. Through the modes of degenerated resistance phase compensation, a low parasitic capacitance common base structure and the like, the RMS phase error can be smaller than 3.5 degrees, the RMS gain error is smaller than 0.75 dB, the insertion loss range is-3-0.5 dB within the frequency band of 7-17GHz, a transmitting channel P1dB is supported to be larger than 6dBm under the working frequency of 12GHz, the radio-frequency signal processing precision and stability are remarkably improved, and the application range is wide. The method is suitable for a high-precision beam forming system of a phased array radar and millimeter wave communication system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency integrated circuit, in particular to a wideband vector modulation phase shifter system based on phase compensation technology, which is suitable for phased array radar system, wireless millimeter wave communication and other radio frequency signal processing scenarios. BACKGROUND

[0002] In modern wireless systems such as phased array radar and millimeter wave communication, phase shifters are the core modules for beamforming and amplitude-phase modulation. Traditional vector modulation phase shifters mostly use a variable gain architecture based on current scaling, which changes the I / Q signal weight by adjusting the in-phase (I) and quadrature (Q) branch bias current. However, there are the following problems:

[0003] 1. Bias current variation causes transistor operating point drift, resulting in severe amplitude / phase distortion;

[0004] 2. Parasitic capacitance effect is intensified in small current state, and phase consistency changes significantly with gain;

[0005] 3. Input impedance fluctuates significantly during gain adjustment, affecting the accuracy of quadrature signal synthesis.

[0006] 4. Existing phase compensation techniques can reduce phase deviation, but will compress the gain adjustment range.

[0007] 5. The output impedance of the variable gain amplifier (VGA) in the traditional architecture changes with gain, causing load effect.

[0008] In recent years, although there have been improved schemes based on current steering technology, there are still significant shortcomings in maintaining constant input impedance, achieving full phase quadrant operation, and phase consistency in wide dynamic range. The present application proposes innovative system architecture and module design to improve the performance of wideband (7-17 GHz) phase shifter systems on a 0.18 μm SiGe BiCMOS process platform. SUMMARY

[0009] The purpose of the present application is to improve the traditional VGA architecture and provide a wideband low-distortion phase compensation vector modulation phase shifter system to solve the technical problems of insufficient phase control accuracy, amplitude-phase distortion (AM / PM), and poor wideband matching in the prior art.

[0010] To solve the above technical problems, the technical solution provided by the present application is a wideband low-distortion phase compensation vector modulation phase shifter system, which includes:

[0011] The orthogonal split module adopts an orthogonal filter to decompose the input radio frequency signal into two orthogonal signals of in-phase (I) and quadrature (Q), so that the output orthogonal signals pass through an I-path digitally controlled current switching switch and a Q-path digitally controlled current switching switch with gain. The design adopts an all-pass RLC filter to realize this. The orthogonal filter is designed to work at a center frequency of 12 GHz, and the voltage transmission coefficient is about 3 dB. Because the bandwidth of the filter is determined by the quality factor of the integral inductor, a low-Q inductor is used in this design to achieve a wide working frequency band. At the same time, the inductance is determined by the input impedance matching to maximize the insertion loss. The actual measurement shows that the phase imbalance between the generated orthogonal vectors I+ and Q+ and I- and Q- is less than 2°, and the amplitude imbalance is less than 0.5 dB in the 12 GHz frequency band.

[0012] The dual-phase variable gain amplifier module is connected to the I / Q two-way output ends of the orthogonal split module, each of which is composed of 5 levels of binary weighted parallel units, and the current path and output polarity are switched through a digital control word to realize 0-360° phase adjustment and ±15 dB gain control. The current steering topology is adopted, and a degeneration resistor (R deg ) is connected in series at the emitter of the differential pair to maintain constant input impedance and suppress phase change during gain adjustment. deg The dual-phase variable gain amplifier module adopts the current steering topology, and a degeneration resistor (R B ) with a resistance of 50-200 Ω is connected in series at the emitter of the differential pair to maintain constant input impedance and suppress phase shift during gain adjustment.

[0013] The common base amplification stage base bias voltage generation module adopts an on-chip low dropout linear regulator (LDO) to provide a stable base bias voltage V B . The design is 1.2-1.5 V (lower than the power supply voltage 3.3 V), which ensures that the transistor works in the active region. At the same time, the circuit V B is generated by a bandgap reference source, with a temperature drift coefficient of <50 ppm / ℃, which ensures its temperature stability.

[0014] The common base synthesis module and the LC matching network are connected to the output end of the common base synthesis module, which completes the wideband impedance matching, including parallel inductor components (0.5-2 nH adjustable) and series capacitor components (50-200 fF adjustable), and realizes a wideband matching with a standing wave ratio <1.5 in the 7-17 GHz frequency band.

[0015] The common base synthesis module and the LC matching network are connected to the output end of the common base synthesis module, which completes the wideband impedance matching, including parallel inductor components (0.5-2 nH adjustable) and series capacitor components (50-200 fF adjustable), and realizes a wideband matching with a standing wave ratio <1.5 in the 7-17 GHz frequency band.

[0016] In one embodiment of the present invention, each stage of the parallel unit of the dual-phase variable gain amplifier module includes:

[0017] A transconductance amplifier is used to convert an input voltage signal into a current signal, and includes an I-channel transconductance amplifier and a Q-channel transconductance amplifier, the two having symmetrical structures.

[0018] A current switching switch, controlled by a digital control word (5-bit amplitude + 1-bit polarity), for selectively directing the current signal to a power supply or an output node;

[0019] The differential pair emitters are connected through the R deg Connect to a public node;

[0020] A base voltage regulating circuit for controlling the current sharing ratio of the differential pair;

[0021] wherein R deg The resistance value is selected so that the current density across the input conduit remains constant, and the RMS phase error is less than 3.5° in the 7-17 GHz operating frequency band.

[0022] R deg The relationship between resistance and phase error is quantified experimentally, and the formula is:

[0023]

[0024] Where Δφ is the phase error (°), R deg is the degraded resistance (Ω), k and C are experimental constants (k≈120, C≈1.5). For example, when R deg =120Ω, Δφ≈2.5°; when R deg =50Ω, Δφ≈3.0°. Optimize R deg The resistance value can be increased to 120Ω to minimize the phase error to less than 2.5°. Figure 7 As shown, R deg Increasing the resistance value improves phase continuity and reduces RMS phase error.

[0025] In one embodiment of the present invention, the input end of the I-way transconductance amplifier receives the I-way orthogonal signal of the orthogonal branch module, and the output end is connected to the I-way degeneration resistor R through the emitter. deg , while the I-way degeneration resistor R deg It is coupled with the I-channel digitally controlled current switch in the transconductor; similarly, the input end of the Q-channel transconductance amplifier receives the Q-channel orthogonal signal of the orthogonal branch module, and the output end is connected to the Q-channel degeneration resistor R through the emitter. deg , while the Q-path degeneration resistance R degThe transconductance tube is coupled with a Q-path numerical control current switch; a degeneration resistance stabilizes the emitter current of the transconductance tube, and indirectly ensures the phase consistency of the collector output current; and the current switch switches the stable current at the collector side, thereby realizing low-distortion gain / phase control.

[0026] In one embodiment of the present application, the common-base synthesis module specifically comprises:

[0027] A current summation node for vector superposition of the I / Q two-way output current signals;

[0028] A common-base amplification stage with a fixed base electrode through a bias voltage and a collector connected to the LC matching network;

[0029] The common-base structure reduces the output end parasitic capacitance to below 0.5 pF, supporting 7-17 GHz wideband operation.

[0030] In one embodiment of the present application, the LC matching network comprises:

[0031] A parallel inductance component with an adjustable inductance value in the range of 0.5-2 nH;

[0032] A series capacitance component with an adjustable capacitance value in the range of 50-200 fF;

[0033] Configured to realize a wideband matching with a standing wave ratio less than 1.5 in the 7-17 GHz frequency band.

[0034] In one embodiment of the present application, the digital control word adopts a 6-bit control signal, wherein:

[0035] A 5-bit amplitude control word corresponds to 32 gain states, realizing a ±15 dB gain adjustment range;

[0036] A 1-bit polarity control word realizes signal inversion, supporting four-quadrant phase control.

[0037] In one embodiment of the present application, the system realizes the following in the 7-17 GHz operating frequency band:

[0038] An RMS phase error less than 3.5°;

[0039] An RMS gain error less than 0.75 dB;

[0040] An insertion loss range of -3-0.5 dB.

[0041] The AM / PM distortion suppression effect was quantified by comparing before and after compensation. Without compensation, gain adjustment causes a phase shift of up to 15° (±15dB range); after compensation, the phase shift is reduced to within 3.5°. Specific data: At 12GHz, the AM / PM distortion before compensation is 8° / dB, and after compensation it is reduced to 0.5° / dB, verifying the degeneration resistor R deg The inhibitory effect. Figure 7 As shown, the RMS phase error is <3.5° in the entire frequency band.

[0042] In one embodiment of the present invention, the system is implemented using a 0.18 μm SiGe BiCMOS process, wherein:

[0043] The transistor size of the dual-phase variable gain amplifier module is scaled in binary proportions, with the minimum unit cross-duct size being 0.2μm×10μm and a width-to-length ratio of 1:50;

[0044] R deg Made of polysilicon material, the resistance is adjustable from 50-200Ω.

[0045] The key parameters of the SiGe HBT transistor in the process used include β value (current gain) of 80-120, f T (cut-off frequency) is 200GHz, the base resistance R b The W / L ratio across the conduit is optimized to 1:50 (e.g., the smallest unit is 0.2μm×10μm), ensuring constant current density and reducing the impact of process variation.

[0046] In one embodiment of the present invention, the system implements in the transmission channel:

[0047] The output 1dB compression point power is greater than 6dBm at 12GHz operating frequency;

[0048] Saturated output power exceeds 13dBm;

[0049] The third-order intercept point is higher than 20dBm.

[0050] The beneficial effects of the present invention are:

[0051] 1. Phase stability: The VGA uses a fixed current density design to avoid AM / PM distortion caused by bias current scaling, and the root mean square (RMS) phase error is less than 3.5° in the 7-17 GHz frequency band.

[0052] 2. Broadband compatibility: Common base reduces output parasitic capacitance and supports 7-17GHz broadband operation;

[0053] 3. Quantifying the AM / PM effect: After compensation, the phase shift is reduced from 10-15° before compensation to 2-3.5°.

[0054] 4. Quadrature control accuracy: the VGA adopts degeneration resistance phase compensation, the RMS phase error is less than 3.5° and the RMS gain error is less than 0.75dB in the gain adjustment range of ±15dB;

[0055] 5. Power linearity: the output P1dB of the transmitting channel is greater than 6dBm and the saturated output power is more than 13dBm at the working frequency of 12GHz, which is suitable for high dynamic range scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 is the schematic diagram of the phase shifter system of the present application;

[0057] Figure 2 is the core circuit schematic diagram of the dual-phase VGA module;

[0058] Figure 3 is the core circuit schematic diagram of the quadrature filter module;

[0059] Figure 4 is the core circuit schematic diagram of the common-base combiner and LC matching network;

[0060] Figure 5 is the test result diagram of the phase shifter receiving / transmitting mode insertion and return loss;

[0061] Figure 6 is the characteristic diagram of the RMS phase error and RMS gain error variation of the phase shifter in the effective working frequency range;

[0062] Figure 7 is the relative phase error distribution diagram of the phase shifter in the full phase state;

[0063] The labels of the components in the drawings are as follows: 1, quadrature branch module, 2, dual-phase variable gain amplifier module, 3, common-base combiner and LC matching network, 4, binary weighted parallel unit, 5, I-path digitally controlled current switching switch, 6, Q-path digitally controlled current switching switch, 7, I-path transconductance amplifier, 8, Q-path transconductance amplifier, 9, I-path degeneration resistance R deg , 10, Q-path degeneration resistance R deg . DETAILED DESCRIPTION

[0064] The preferred embodiments of the present application are described in detail below with reference to the drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the protection scope of the present application is more clearly defined.

[0065] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The embodiment of the present invention provides a broadband low-distortion phase-compensated vector modulation phase shifter system, comprising:

[0066] Orthogonal branch module: uses an orthogonal filter to decompose the input signal into I and Q signals; at the same time, it adopts an all-pass RLC filter structure and achieves insertion loss (<1dB) and phase balance (<±2°) indicators.

[0067] Bi-phase variable gain amplifier module (bi-phase VGA module): Each circuit consists of 5-level binary weighted parallel units, which achieve 0-360° phase adjustment and ±15dB gain control by digitally controlling the current path and polarity.

[0068] Based on the current steering topology, a degeneration resistor (R deg ), maintain the input impedance constant and suppress phase deviation;

[0069] Common base synthesis module and LC matching network. The common base synthesis module sums the I / Q signal currents and inputs them into the common base amplifier stage to reduce the parasitic capacitance at the output end and complete broadband impedance matching through the LC matching network.

[0070] The LC matching network is connected to the output end of the common base synthesis module to complete broadband impedance matching. It includes a parallel inductor component (adjustable from 0.5 to 2 nH) and a series capacitor component (adjustable from 50 to 200 fF), achieving broadband matching with a standing wave ratio of <1.5 in the 7-17 GHz frequency band.

[0071] Furthermore, each parallel unit of the dual-phase variable gain amplifier module includes: a transconductance amplifier, which converts the input voltage into a current signal; a digitally controlled current switch, which is controlled by a digital control word to select the current to be directed to the power supply or the output node; a differential pair emitter through R deg The common node is connected and combined with the base voltage regulation circuit to maintain the transistor current density constant, so that the RMS phase error in the 7-17GHz frequency band is less than 3.5°.

[0072] The system achieves the following in the 7-17 GHz frequency band: RMS phase error <3.5° and RMS gain error <0.75 dB; insertion loss range -3 dB to +0.5 dB; transmit channel output P1dB >6 dBm at 12 GHz, and saturated output power >13 dBm.

[0073] Specific implementation verification data includes:

[0074] 1. Temperature stability: From -55°C to 105°C, the RMS phase error variation is <0.5°, and the RMS gain error variation is <0.2dB (verifying robustness over the full temperature range).

[0075] 2. Process angle fluctuation: Under the FF / SS / TT process angles, the maximum phase error deviation is 1.5° and the maximum gain error deviation is 0.3dB (based on 0.18μm SiGe BiCMOS process).

[0076] 3. Harmonic distortion: At 12GHz, 0dBm input, the second harmonic HD2 <-50dBc, the third harmonic HD3 <-55dBc.

[0077] 4. Control word response time: Digital control word switching delay <10ns (SPI interface test).

[0078] The 0.18μm SiGe BiCMOS process is used, where the trans-pipeline size of the dual-phase variable gain amplifier module is scaled in binary proportion, with the minimum unit being 0.2μm×10μm; deg Polysilicon material is used to achieve adjustable resistance.

[0079] Specific vector modulation based phase shifter system architecture, such as Figure 1 As shown in the figure, in the phase shifter system architecture, the orthogonal filter adopts a 90° hybrid coupling circuit design to decompose the input signal into I and Q orthogonal components; the dual-phase VGA contains 5 levels of binary-weighted current switching units, each of which switches the current flow direction through a digital signal to achieve 0-360° phase adjustment (2.8125° step) and ±15dB gain adjustment range; the current summing unit adopts a common-base NPN transistor amplifier, whose low input impedance characteristics compensate for the VGA output impedance variation, and the LC network (the inductance value is adjustable in the range of 0.5-2nH, and the capacitance value is adjustable in the range of 50-200fF) achieves optimal matching in the 7-17GHz broadband range.

[0080] Specific phase compensation VGA module, such as Figure 2 As shown in Figure 1, the dual-phase VGA consists of five binary-weighted parallel units, each of which contains a gm-stage transconductance amplifier and a current switching switch. The digital control word (5-bit amplitude control word + 1-bit polarity control word) controls the current flow in each branch to the power supply or output node, and switches the output polarity to support four-quadrant operation. The emitter of the VGA's differential pair amplifier is connected to R deg (Adjustable within the range of 50-200Ω), the current distribution ratio is adjusted by the base voltage. degThe design suppresses phase shifts caused by current density variations while maintaining a constant input current density across the conduit. The design achieves an RMS phase error of less than 3.5° and an RMS gain error of less than 0.75dB over a ±15dB gain adjustment range.

[0081] Specific orthogonal filter modules, such as Figure 3 Its one-sided transfer function can be expressed as:

[0082]

[0083] where ω n is the undamped natural angular frequency, Q is the quality factor, which can be expressed as:

[0084]

[0085] R1, L1 and C1 are the resistance of the resistor, the inductance of the inductor and the capacitance of the capacitor in the filter respectively.

[0086] This orthogonal filter is designed to operate at a center frequency of 12 GHz, with a voltage transfer coefficient of approximately 3 dB. Because the filter bandwidth is determined by the quality factor of the integrating inductor, a low-Q inductor is used to achieve a wide operating frequency band. The inductor's value is determined by input impedance matching to minimize insertion loss. Measured phase imbalances between the generated orthogonal vectors I+ and Q+, as well as I- and Q-, are less than 2°, and amplitude imbalances are less than 0.5 dB at 12 GHz.

[0087] Specific common base synthesis module and LC matching network, such as Figure 4 The output differential to the common load consists of a pair of common base transistors Q1 and Q2, which sum the two vector current modes, as shown in Figure 5 As shown in Figure 2 , the common-base transistors also act as a buffer, reducing parasitics and increasing bandwidth. They also form a matching network with the subsequent shunt inductors L1 / L3 and L2 / L4, and the series capacitors C1 and C2 at the output, respectively, to match the output impedance of the entire phase shifter to 50Ω. Simulations have verified that this design achieves broadband matching with a standing wave ratio (SWR) of less than 1.5 within the 7-17 GHz frequency band.

[0088] At the same time, the specific system integration and testing, in which the system is implemented using 0.18μm SiGe BiCMOS process, the core circuit area is 0.49mm×0.45mm. Figure 5 As shown in the figure, within the 7-17GHz frequency band, the insertion loss range is -3-0.5dB and the return loss is better than -15dB. Figure 6As shown, the RMS phase error is less than 3.5° and the RMS gain error is less than 0.75dB. Figure 7 As shown in Figure 1, the design supports 2.8125° step adjustment with no phase crossover across the entire frequency band. The wide bandwidth, low distortion, and compact size of this phase shifter system make it suitable for large-scale array applications.

[0089] Specific reliability verification design includes:

[0090] 1.ESD protection structure:

[0091] Integrate two-level protection circuits on I / O ports:

[0092] The first stage adopts a gate-grounded NMOS structure with a trigger voltage of 12V and a static discharge of >2kV HBM (Human Body Model);

[0093] The second stage uses a diode clamp (anode connected to the RF line, cathode connected to VDD), with a clamping voltage of 3.3V±10%.

[0094] Series polysilicon resistors (200Ω) and parallel diodes are added to sensitive internal modules (such as transductors) to ensure ESD protection meets the JESD22-A114F Class 2 standard (>2kV HBM).

[0095] 2.Aging test:

[0096] High temperature operating life (HTOL): 500 hours of continuous operation at 105°C. Test conditions:

[0097] Input power: 0dBm@12GHz, phase control word full state cyclic switching;

[0098] Results: RMS phase error drift <0.3°, gain error drift <0.15dB, output P1dB drop <0.2dB.

[0099] Temperature Cycling (TCT): -55°C to 105°C 200 times, results:

[0100] Insertion loss variation <±0.1dB, return loss remains <-15dB;

[0101] No structural cracking or solder joint failure (verified by SEM).

[0102] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A broadband low-distortion phase-compensated vector modulation phase shifter system, characterized in that include: The orthogonal branching module (1) uses an orthogonal filter to decompose the input radio frequency signal into two orthogonal signals, namely, in-phase (I) and quadrature (Q), so that the output quadrature signals are respectively amplified by the I-channel digitally controlled current switching switch (5) and the Q-channel digitally controlled current switching switch (6); A dual-phase variable gain amplifier module (2) is respectively connected to the I / Q output ends of the orthogonal branch module (1), each path being composed of five-level binary weighted parallel units (4), and realizing 0-360° phase adjustment and ±15dB gain control by switching the current path and output polarity through digital control words; the dual-phase variable gain amplifier module (2) adopts a current-steering topology, and a degeneration resistor is connected in series with the differential emitter; A common base synthesis module and an LC matching network (3), wherein the common base synthesis module is used to perform current mode summation on the I / Q two-way signal and then input the sum into the common base amplifier stage; An LC matching network is connected to the output end of the common base synthesis module, which includes a parallel inductor component and a series capacitor component to achieve broadband matching with a standing wave ratio of <1.5 in the 7-17 GHz frequency band.

2. The system according to claim 1, wherein: Each stage of the parallel unit of the dual-phase variable gain amplifier module (2) comprises: A transconductance amplifier, used for converting an input voltage signal into a current signal, comprising an I-channel transconductance amplifier (7) and a Q-channel transconductance amplifier (8), the structures of which are symmetrically arranged; a current switching switch, controlled by a digital control word, for selectively directing the current signal to a power supply or an output node; The differential pair emitters are connected through the R deg Connect to a public node; A base voltage regulating circuit for controlling the current sharing ratio of the differential pair; wherein R deg The resistance value is selected so that the current density across the input conduit remains constant. After compensation in the 7-17 GHz operating frequency band, the phase shift is reduced from 10-15° before compensation to 2-3.5°.

3. The system according to claim 2, characterized in that The input end of the I-way transconductance amplifier (7) receives the I-way orthogonal signal of the orthogonal branch module (1), and the output end is connected to the I-way degeneration resistor R through the emitter. deg (9), at the same time, the I-way degeneration resistance R deg (9) coupled with the I-way digitally controlled current switching switch (5) in the transconductor; Similarly, the input end of the Q-path transconductance amplifier (8) receives the Q-path orthogonal signal of the orthogonal branch module (1), and the output end is connected to the Q-path degeneration resistor R through the emitter. deg (10), and the Q-path degeneration resistance R deg (10) is coupled with the Q-path digitally controlled current switching switch (6) in the transconductor.

4. The system according to claim 1, wherein: The common base synthesis module (3) specifically includes: The current summing node is used to perform vector superposition on the I / Q output current signals; A common base amplifier stage, the base of which is fixed by a bias voltage, and the collector is connected to the LC matching network (4); wherein the common base structure reduces the output end parasitic capacitance to below 0.5 pF, supporting 7-17 GHz broadband operation.

5. The system according to claim 1, wherein: The LC matching network (4) comprises: The inductance value of the parallel inductor component is adjustable within the range of 0.5-2nH; A series capacitor component, the capacitance of which is adjustable within the range of 50-200fF; Configured to achieve broadband matching with a standing wave ratio of less than 1.5 in the 7-17 GHz frequency band.

6. The system according to claim 1, wherein: The digital control word adopts a 6-bit control signal, wherein: 5-bit amplitude control word corresponds to 32 gain states, achieving ±15dB gain adjustment range; A 1-bit polarity control word enables signal inversion and supports four-quadrant phase control.

7. The system according to claim 1, wherein: The system operates in the 7-17 GHz frequency band and achieves: RMS phase error is less than 3.5°; RMS gain error is less than 0.75dB; Insertion loss range is -3-0.5dB.

8. The system according to claim 1, wherein: The system is implemented using a 0.18μm SiGe BiCMOS process, where: The transistor size of the dual-phase variable gain amplifier module is scaled in binary proportions, the transconduit W / L ratio is optimized to 1:50, and the minimum unit transconduit size is 0.2μm×10μm; R deg Made of polysilicon material, the resistance is adjustable from 50-200Ω.

9. The system according to claim 1, wherein: The system implements the following in the transmission channel: At 12GHz, 0dBm input, the second harmonic HD2 <-50dBc, the third harmonic HD3 <-55dBc; The output 1dB compression point power is greater than 6dBm at 12GHz operating frequency; Saturated output power exceeds 13dBm; The third-order intercept point is higher than 20dBm.

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