Cross-platform radio frequency data transmission method and system based on HC3080 chip

Abstract

The scheme discloses a cross-platform radio frequency data transmission method and system based on an HC3080 chip, belongs to the technical field of data transmission, constructs a multi-platform data interaction and control framework based on five concurrent thread tasks and three high-performance message queues, and introduces a unified cross-platform signaling protocol structure as a semantic carrier of instruction data, so that the accurate identification and processing of instructions between different platforms are ensured, cross-platform function control and high-performance data communication for a system containing the HC3080 chip are successfully realized, the application blank of the HC3080 chip in the communication support between multi-core heterogeneous systems is effectively filled, and the application range of the HC3080 chip in the high-reliability embedded communication and signal processing field is significantly expanded.

Description

Technical Field

[0001] This invention belongs to the field of data transmission technology, and in particular relates to a cross-platform radio frequency data transmission method and system based on the HC3080 chip. Background Technology

[0002] In the field of edge computing for drones, heterogeneous computing architectures are increasingly widely used. Among them, the HC3080, as a domestically produced high-performance intelligent acceleration chip, significantly improves data processing capabilities by integrating a DSP and a dedicated acceleration unit. However, at the data transmission level, the HC3080 faces different interface driver implementation logic compared to mainstream intelligent acceleration chips, resulting in direct incompatibility with the standardized interface drivers relied upon by existing AI chips.

[0003] This compatibility issue severely restricts the application effect of the HC3080 chip in multi-platform collaborative scenarios. In particular, when high-speed data interaction with FPGA processing modules and display control terminals is required, traditional solutions often need to add an additional protocol conversion layer, which not only introduces additional memory copy overhead, but also leads to increased transmission latency and decreased throughput. Summary of the Invention

[0004] The purpose of this invention is to address the above-mentioned problems by providing a cross-platform radio frequency data transmission method and system based on the HC3080 chip. Taking into account the interface driver architecture characteristics of the HC3080 chip, an innovative and targeted cross-platform data transmission solution is proposed, thereby realizing an efficient cross-platform data communication system.

[0005] A cross-platform radio frequency data transmission method based on the HC3080 chip, the method comprising: a heterogeneous communication architecture including five concurrent task modules and three message queues built into the HC3080 terminal;

[0006] The five concurrent task modules include the first task module, the second task module, the third task module, the fourth task module, and the fifth task module;

[0007] The three message queues include the first message queue, the second message queue, and the third message queue;

[0008] The first task module will write the control signaling received from the display and control system to the first message queue or the third message queue.

[0009] The second task module will write the FPGA data received from the display and control system to the third message queue;

[0010] The third task module reads the control signaling to be processed from the first message queue, executes the business logic according to the control signaling, and then distributes the processing result to the second message queue or the third message queue.

[0011] The fourth task module obtains display and control data and feedback signaling from the second message queue, and then sends the display and control data and feedback signaling back to the display and control system.

[0012] The fifth task module reads the target data from the third message queue and sends the target data to the FPGA terminal;

[0013] The display and control data is obtained by processing the radio frequency data received from the FPGA by the HC3080 terminal;

[0014] The feedback signaling is generated by the HC3080 and FPGA terminals after executing tasks based on the control signaling.

[0015] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the display and control system is used for human-computer interaction, transmitting control signals, HC internal data, and FPGA data to the HC3080, or receiving feedback signals and display and control data from the HC3080, and receiving feedback signals returned by the FPGA through the HC3080. When the second task module receives the HC internal data, it stores it.

[0016] The HC3080 terminal is used to receive signaling and data sent by the display and control system terminal and the FPGA terminal, and to process the signaling and data based on the five concurrent task modules and three message queues.

[0017] The data includes the internal data of the HC, the FPGA data, and the display and control data.

[0018] The FPGA terminal is used to execute corresponding tasks based on the target information sent by the HC3080 terminal;

[0019] The target information sent by the HC3080 terminal includes control signaling transmitted through the HC3080 terminal uploaded by the display and control system terminal, FPGA terminal data, and control signaling generated by the HC3080 terminal.

[0020] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the HC3080 terminal interacts with the display and control system terminal through the GMAC interface, and the HC3080 terminal interacts with the FPGA terminal through the SRIO interface.

[0021] The GMAC interface mentioned above adopts a dual-channel approach:

[0022] The first channel is implemented using stream sockets and uses the TCP protocol for communication, for transmitting control signaling and return signaling;

[0023] The second channel is used for data transmission and employs a cyclic write mechanism for cumulative verification.

[0024] The communication between the first task module and the display and control system uses the first channel;

[0025] The second task module communicates with the display and control system via the second channel;

[0026] The fourth task module communicates with the display and control system using the first channel and the second channel.

[0027] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the FPGA end transmits the generated return signaling and the acquired radio frequency data back to the HC3080 end through the SRIO interface.

[0028] The HC3080 terminal writes the feedback signaling from the FPGA terminal into the second message queue, processes the radio frequency data, and packages the processing result and related radio frequency data into display and control data and writes it into the second message queue.

[0029] The feedback signaling and display control data located on the FPGA end of the second message queue are extracted by the fourth task module and transmitted back to the display control system end through the GMAC interface.

[0030] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the first message queue is used to buffer the control signaling transmitted through the GMAC interface and directed to the HC3080 end for subsequent processing scheduling.

[0031] The second message queue is used to cache service data sent to the display and control system via the GMAC interface, including the return signaling from the HC3080 end, the return signaling from the FPGA end, and display and control data.

[0032] The third message queue is used to cache service data sent to the FPGA via the SRIO interface, including FPGA data and control signaling directed to the FPGA.

[0033] In the aforementioned cross-platform RF data transmission method based on the HC3080 chip, this method further includes defining a cross-platform signaling protocol structure. This structure is used to encapsulate the control signaling and feedback signaling between the display and control system, the FPGA, and the HC3080, including:

[0034] The header field head1 is used to mark the start of a data frame;

[0035] The frame header field head2l, combined with the frame header field head1, forms a unique frame header identifier;

[0036] The function code field cmdl and the function code field cmdh are combined to encode a 16-bit function code, which is used to indicate the operation type.

[0037] FPGA-side global registers store FPGA-side status parameters;

[0038] The HC-side global register stores the status parameters of the HC3080.

[0039] The global register of the display and control terminal stores the status parameters of the display and control terminal;

[0040] The signaling timestamp register is used to record the timestamp of signaling generation;

[0041] Temporary data registers are used to pass intermediate calculation results or extended data;

[0042] The checksum field is used to verify the integrity of the data frame;

[0043] The tail1 and tail2 fields are used together to mark the end of a data frame.

[0044] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the HC308 terminal, the display and control system terminal, and the FPGA terminal achieve cross-platform interaction based on 128-byte signaling.

[0045] The 128-byte signaling includes the function code field, and different function code fields trigger the interaction between the HC3080 terminal and the display and control system terminal and the FPGA terminal.

[0046] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the signaling sent to the display and control system is sent through the sRk circular buffer, and the data sent to the display and control system is sent through the frame transmission buffer.

[0047] Signaling to the FPGA is sent through the pZU circular buffer, while data to the FPGA is sent through the SRIO transmit buffer and a round-robin scheduling mechanism.

[0048] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the frame transmission buffer includes multiple buffer blocks, such as four buffer blocks, with each buffer block spaced 64MB apart.

[0049] The SRIO transmit buffer includes multiple buffer blocks, such as four buffer blocks, with each buffer block spaced 8MB apart;

[0050] The sRK circular buffer has 200-300 buffer slots, each slot supporting 128 bytes of data storage;

[0051] The interactive modes for acquiring display and control data include active mode and single-frame mode;

[0052] In single-frame mode, the HC3080 terminal interacts with the FPGA terminal based on the control signaling sent by the display and control terminal to obtain radio frequency data, and returns the radio frequency data to the display and control system terminal after processing the radio frequency data;

[0053] In active mode, the display and control system initiates an initialization control signal, and the HC3080 and FPGA establish a continuous communication channel. They continuously exchange signals and data through polling or interrupt mechanisms, and when the set conditions are met, such as when there are 10 results, they return display and control data to the display and control system.

[0054] A cross-platform data transmission system based on the HC3080 chip includes a display and control system end, an FPGA end, and an HC3080 end;

[0055] The display and control system is connected to the HC3080 via a GMAC interface.

[0056] The FPGA is connected to the HC3080 via an SRIO interface.

[0057] The HC3080 terminal has a heterogeneous communication architecture consisting of five concurrent task modules and three message queues;

[0058] The five concurrent task modules include the first task module, the second task module, the third task module, the fourth task module, and the fifth task module;

[0059] The three message queues include the first message queue, the second message queue, and the third message queue;

[0060] The first task module will write the control signaling received from the display and control system to the first message queue or the third message queue.

[0061] The second task module will write the FPGA data received from the display and control system to the third message queue;

[0062] The third task module reads the control signaling to be processed from the first message queue, executes the business logic according to the control signaling, and then distributes the processing result to the second message queue or the third message queue.

[0063] The fourth task module obtains display and control data and feedback signaling from the second message queue, and then sends the display and control data and feedback signaling back to the display and control system.

[0064] The fifth task module reads the target data from the third message queue and sends the target data to the FPGA terminal;

[0065] The display and control data is obtained by processing the radio frequency data received from the FPGA by the HC3080 terminal;

[0066] The feedback signaling is generated by the HC3080 and FPGA terminals after executing tasks based on the control signaling.

[0067] The advantages of this invention are:

[0068] The system architecture provided by this solution is based on five concurrently executing thread tasks and three high-performance message queues to build a multi-platform data interaction and control framework. It also introduces a unified cross-platform signaling protocol structure as the semantic carrier of instruction data, ensuring accurate identification and processing of instructions between different platforms. It successfully realizes cross-platform functional control and high-performance data communication for systems containing HC3080 chips, effectively filling the application gap of HC3080 chips in communication support between multi-core heterogeneous systems, and significantly expanding its application scope in the fields of high-reliability embedded communication and signal processing. Attached Figure Description

[0069] Figure 1 This invention relates to a heterogeneous communication architecture for a cross-platform data transmission method based on the HC3080 chip.

[0070] Figure 2 This is a block diagram of the cross-platform system based on the HC3080 of this invention;

[0071] Figure 3 This is a flowchart of the single-frame mode data interaction process of the present invention;

[0072] Figure 4 This is a flowchart of the data interaction process in the active mode of the present invention.

[0073] Figure 5 This is a flowchart of the single-frame mode data processing result feedback process of the present invention.

[0074] Figure 6 This is a flowchart of the active mode data processing result feedback process of the present invention.

[0075] Figure reference numerals: UAV side 1; HC3080 end 11; FPGA end 12; First mission module 13; Second mission module 14; Third mission module 15; Fourth mission module 16; Fifth mission module 17; Ground side 2; Display and control system end 21. Detailed Implementation

[0076] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0077] This solution is based on the HC3080 software platform to build a cross-platform RF data processing system architecture. The implementation of this cross-platform system architecture includes system framework construction, interface function implementation, signaling control and backhaul mechanism, data reception and transmission, data stream processing flow, result storage and result backhaul. The data stream processing flow includes mode configuration, data splitting and data processing.

[0078] It should be noted that this system architecture can be used in drone systems that utilize the HC3080 chip on the drone side, such as... Figure 1 As shown, the UAV system mainly consists of a UAV side 1 and a ground side 2. The UAV side 1 has an HC3080 terminal 11 and an FPGA terminal 12, while the ground side 2 mainly has a display and control system terminal 21. This solution primarily addresses the efficient transmission and processing of radio frequency data between the HC3080 chip, the FPGA, and the display and control system. It solves the problem of severe control signaling delay caused by the incompatibility between the HC3080 chip interface driver logic and the display and control system / FPGA. It does not involve general image or video data, which is transmitted back via a separate backhaul link and is not within the scope of this solution.

[0079] like Figure 2 As shown, the details are as follows:

[0080] System framework setup

[0081] Based on the task requirements, this solution proposes an innovative software system framework design, which introduces three key message queues: the first message queue, the second message queue, and the third message queue.

[0082] And five core concurrent task modules: Task 1 13, Task 2 14, Task 3 15, Task 4 16, and Task 5 17.

[0083] Through a precisely designed message passing mechanism and task scheduling strategy, this architecture achieves efficient cross-platform data transmission capabilities. While supporting multi-threaded collaborative processing, it significantly improves system performance throughput and scalability, providing strong support for real-time interaction of radio frequency data between heterogeneous platforms.

[0084] Message queue design

[0085] The first message queue is used to receive and manage control signaling transmitted via the GMAC (Gigabit Media Access Controller) interface from the display and control system end 21 and directed to the HC3080 end 11. This includes control frame indexes and instruction information, and it is responsible for scheduling and coordinating subsequent processing flows within the framework. This ensures efficient transmission and accurate routing of control signaling, thereby improving the real-time performance and reliability of instruction execution.

[0086] The second message queue, serving as a high-speed data transmission channel for the GMAC interface, is used to cache and schedule critical business data that needs to be transmitted to the display and control system terminal 21 via the GMAC interface. This includes the feedback signaling generated by the HC3080 terminal 11 after executing tasks related to control signaling, the feedback signaling generated by the FPGA terminal 12 in response to control signaling, and display and control data. This ensures the real-time and reliable transmission of critical data, based on high-bandwidth, low-latency information push scenarios.

[0087] When the FPGA terminal 12 needs to send a signal back to the display and control system terminal 21, the signal back is written into the second message queue in the form of an interrupt response. The signal back from the FPGA terminal waits in the second message queue for the fourth task module 16 to send it back to the display and control system terminal 21.

[0088] When the system needs radio frequency (RF) data, it also obtains the RF data from the FPGA terminal 12 via an interrupt response. After processing the RF data, the HC3080 terminal 11 packages the processing result and some or all of the RF data from the currently processed RF data into display and control data and writes it into the second message queue. Those skilled in the art should know that UAVs generally have RF chips, and the RF data of the FPGA here is obtained from the RF chip, which will not be elaborated here.

[0089] The third message queue carries service data sent to the FPGA-side 12 high-performance processing module via the SRIO (Serial RapidIO) interface. This includes FPGA-side 12 data and control signaling data for the FPGA-side 12, primarily FPGA overload data. It features low latency and high throughput, ensuring stable and real-time transmission of critical data even under high load conditions, meeting the communication requirements of high-speed interconnection.

[0090] Task allocation and execution

[0091] The first task module 13 is responsible for receiving control signaling from the GMAC interface, parsing the content according to the function code of the control signaling, encapsulating it into a standardized message format, and writing it into the first message queue or the third message queue for subsequent task scheduling. This module implements the instruction entry point bridging function from the physical interface to the task scheduling system.

[0092] Specifically, the control signals received by the first task module 13 from the display and control system terminal 21 include two types. One type needs to be processed by the HC3080 itself, such as the model update instruction, which is written into the first message queue. The other type needs to be processed by the FPGA, such as the FPGA software upgrade instruction, which is written into the third message queue.

[0093] The second task module 14 is responsible for processing data received from the display and control system terminal 21 via the GMAC interface. This includes internal HC data used by the HC3080 chip itself, such as model files, and data that needs to be passed to the FPGA terminal 12, such as FPGA overload data. After receiving the internal HC data, the HC3080 terminal 11 saves these files in a specific storage space. Data received from the FPGA terminal 12 is written to the third message queue.

[0094] The third task module 15 is responsible for reading control signals to be processed from the first message queue, executing the corresponding business logic according to the function code, such as data parsing, numerical calculation, system status update, etc. The processing results are delivered to the second message queue (to be sent to the display and control system terminal 21) or the third message queue (to be sent to the FPGA terminal 12) according to their application scenarios, completing message-driven business processing and result distribution.

[0095] The third task module 15 classifies the processing results. Results that need to be sent back to the display and control system are stored in the second message queue, while results that need to be provided to the FPGA terminal 12 are stored in the third message queue.

[0096] The fourth task module 16 is used to obtain display and control data and feedback signaling from the second message queue. The feedback signaling includes feedback signaling from HC3080 and feedback signaling from FPGA. The display and control data and feedback signaling are sent to the display and control system terminal 21 through the GMAC interface to realize the data feedback and result interaction function between the UAV side 1 and the host computer.

[0097] The fifth task module 17 is responsible for reading the target message from the third message queue, which is the data to be sent to the FPGA end, such as FPGA overload data, and the control signaling to be transmitted to the FPGA end 12, including the control signaling transmitted by the display and control system end 21 through the HC3080. The information generated by the HC3080 after processing the control signaling of the display and control system end 21 can also be control signaling. The data is sent to the FPGA end 12 through the SRIO high-speed interface to realize high-speed data communication and task collaboration with the FPGA end 12.

[0098] Interface functionality implementation

[0099] The SRIO interface functionality implementation in the HC3080 system includes key operational steps such as device identifier configuration, address mapping window setting, and data buffer initialization to ensure the reliability and reachability of high-speed interconnect communication. The following is a detailed description of the HC3080 SRIO initialization process.

[0100] bslRioSetID(1,0x3333);

[0101] bslRioSetIW(1,(u64)0x40000000,(u64)0x10d0000000,8);

[0102] bslRioSetIW(1,(u64)0x10000000,(u64)0x1090000000,0);

[0103] bslRioDBInit(1,RabDBTest);

[0104] The bslRioSetID function sets a unique device ID of 0x3333 for SRIO interface channel 1. This is used to achieve device identification and target addressing in RapidIO networks, ensuring the correct routing and direction of data packets in multi-device networks.

[0105] The `bslRioSetIW` function configures the input window mapping. It maps the local physical address range (0x40000000 and 0x10000000) of SRIO interface 1 to the remote RapidIO address space (0x10d0000000 and 0x1090000000), and specifies the corresponding window attributes (window indices 8 and 0). This step completes the establishment of the address mapping table, enabling remote nodes to correctly access local memory resources via SRIO.

[0106] The `bslRioDBInit` function initializes the Doorbell buffer of SRIO interface 1 and binds the corresponding interrupt handler or callback logic `RabDBTest`. The Doorbell mechanism is a lightweight communication mechanism in SRIO used to implement event notification and signal transmission, ensuring that the system can efficiently respond to remote interrupts or event triggering requests.

[0107] The GMAC interface is implemented as the core data communication interface in this system, undertaking the task of high-speed data interaction with the display and control system. The GMAC interface conforms to the IEEE 802.3 standard specification and is located at the data link layer of the OSI seven-layer model. It is responsible for encapsulating and decapsulating data frames and communicating with the underlying PHY (Physical Layer) devices, ensuring efficient collaboration between the data link layer and the physical layer.

[0108] This system is configured with two independent socket channels based on the GMAC network interface, referred to here as the first channel and the second channel, which are respectively designed for signaling and large-scale data transmission scenarios.

[0109] The first channel is dedicated to the transmission of 128B signaling. The first task module 13 receives control signaling from the display and control system via this channel. This channel is based on stream sockets and uses the TCP protocol to ensure reliable and orderly transmission of signaling commands. Signaling typically contains critical control information and has extremely high requirements for real-time performance and accuracy. The GMAC network port, with its low latency characteristics, can quickly respond to and process these commands, ensuring the stable operation of the display and control system terminal 21.

[0110] The second channel is used for data transmission and reception. The second task module 14 uses this channel to receive internal HC data for the HC3080 itself and data from the FPGA terminal 12 transmitted from the display and control system. This channel selects the TCP protocol based on the actual situation. In full-duplex mode, the GMAC network port fully utilizes its high-speed transmission capabilities, supporting data transmission rates up to 1Gb for the FPGA, meeting the needs of large-scale, high-speed data transmission.

[0111] The fourth task module 16 communicates with the display and control system terminal 21 using the two channels mentioned above. It sends signaling back to the display and control system terminal 21 through the first channel and transmits display and control data to the display and control system terminal 21 through the second channel.

[0112] Signaling control and signaling feedback

[0113] Signaling control and feedback mechanisms form the core foundation for the collaborative operation of various functional modules in a cross-platform system. Before implementing cross-platform data transmission, this system completed a unified signaling frame structure negotiation to ensure consistency and operability of data communication between different platforms. This process defines the signaling data encapsulation format, field parsing methods, and transmission specifications, thus providing protocol support for efficient signaling transmission and accurate parsing.

[0114] In this system architecture, the three different platforms adhere to a unified data frame format definition. This format establishes logical consistency above the network or transport layer, ensuring interoperability, scalability, and protocol compatibility of signaling across multiple platforms. Through this mechanism, each platform can accurately identify and process signaling, realizing key functions such as signaling delivery, status synchronization, and processing result feedback. The data formats for the three platforms include:

[0115] The header field head1 is used to mark the start position of the data frame, assisting the receiving end in quickly synchronizing the frame boundary. The header field head12 and header1 are combined to form a unique header identifier, which enhances the reliability of frame synchronization.

[0116] The function code field cmdl and the function code field cmdh are jointly encoded into a 16-bit function code, which is used to indicate the specific operation type.

[0117] The FPGA-side 12 global registers store parameters related to the status of the FPGA-side 12 devices.

[0118] The HC-side global register is used for the status management of the HC3080;

[0119] The global register at the display and control end records the internal state of the display and control system;

[0120] The signaling timestamp register is used to record the timestamp of signaling generation;

[0121] Temporary data registers provide flexible data storage space for passing intermediate calculation results or extended data;

[0122] The signaling checksum uses either Cyclic Redundancy Check (CRC) or a simple summation algorithm to ensure the integrity of the data frame.

[0123] The tail1 and tail2 fields are combined to form the end of the frame marker.

[0124] The signaling feedback includes feedback signaling from the FPGA end (signaling 12) and the HC3080 end (signaling 11). The FPGA end (signaling 12) feedback is transmitted from the HC3080 to the display and control system end (21) via the software system framework of the HC3080 end (11). The HC3080 end (11) feedback of the display and control system signaling is based on the cmdl and cmdh function codes as follows:

[0125] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 01 and 00, the X6 and X7 bytes of the global register on the HC terminal control the return of the HC3080 terminal version 11 of the display and control system.

[0126] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 02 and 00, respectively, the global registers of the HC end are as follows: X0: X0.0 (0: Connection establishment failed at display and control system 21; 1: Connection established successfully at display and control system 21), X0.1 (0: Time-frequency AI inference disabled; 1: Time-frequency AI inference enabled), X0.2 (0: No data packet arrived at display and control system 21; 1: Data packet is about to arrive, set to 0 after data packet arrival and execute the task in the task function code, including firmware upgrade), X0.3 (0: Manual mode data acquisition and task execution; 1: Automatic mode data acquisition and task execution), X0.4 (0: Watchdog timer disabled; 1: Watchdog timer enabled), X0.5 (0: FHW detection disabled; 1: FHW detection enabled), X5: Task function code (implementing reconfigurable functions), (X5: 0x01: Algorithm single-frame mode enabled; 0x04: Algorithm active mode enabled), X6: Version number L, X7: Version number H.

[0127] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 03 and 00, respectively, the control display system terminal 21 sends data to the HC3080 terminal 11. After sending this command, the HC3080 terminal 11 sets X0.2 to 1 and returns. The control display system terminal 21 must send data to the HC3080 terminal 11. After receiving the data, the HC3080 terminal 11 replies with the 03 command, setting X0.2 to 0.

[0128] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 04 and 00, respectively, the display and control system terminal 21 acquires the TF data AI inference results, direction finding inference results, timestamps, latitude and longitude, and FHW detection results from the HC3080 terminal 11 in active mode.

[0129] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 06 and 00, respectively, X0.3 controls the selection of the inference mode of the HC3080 terminal 11 (0: active acquisition off; 1: active acquisition on).

[0130] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 07 and 00, respectively, the global register status of the 21HC terminal of the display and control system is returned.

[0131] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 08 and 00, respectively, the global register of the HC terminal is configured by the 21 signaling on the display and control system side.

[0132] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 0a and 00, respectively, the 21 signaling on the display and control system end controls the 11Srio chain reconstruction on the HC3080 end.

[0133] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 0b and 00, respectively, the 21 signaling on the display and control system side controls the activation of the 11FHW inference function on the HC3080 side.

[0134] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 0c and 00, respectively, the 21 signaling on the display and control system side controls the activation of the 11 time-frequency AI inference function on the HC3080 side.

[0135] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 0d and 00, respectively, the 21 signaling on the display and control system side controls the activation of the watchdog function on the 11th terminal of the HC3080.

[0136] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 0d and 00, respectively, the 21 signaling at the display and control system end controls the 11Yolov7 threshold reception at the HC3080 end.

[0137] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 0e and 00, respectively, the 21 signaling on the display and control system terminal controls the 11 center frequency point reception on the HC3080 terminal.

[0138] When the CMDL and CMDH of the 128-byte signaling are represented in hexadecimal as 1e and 00, respectively, the 21 signaling control on the display and control system terminal controls the 11Srio initialization on the HC3080 terminal.

[0139] The above solutions resolve the compatibility issues of signaling interaction between heterogeneous platforms, display and control systems, HC3080, and FPGA terminals, providing reliable protocol support for real-time transmission and processing of RF data.

[0140] Data reception and transmission

[0141] The 128 bytes of signaling received from the display and control system terminal 21 are stored at the starting address of the fixed address space pointed to by the pointer IMGPKG.

[0142] The feedback signaling from the FPGA terminal 12 is directly written into the memory space mapped by the SRIO interface, and the real-time performance and reliability of data reception are ensured through DMA or bus pass-through access mechanisms.

[0143] Data received from the display and control system terminal 21 is stored at the starting address of the fixed physical address space pointed to by the IMGPKG_ pointer, thereby achieving unified management of large blocks of data.

[0144] The FPGA side uses a unified memory space for SRIO mapping for 12 data and backhaul signaling, and adopts an address segmentation strategy to achieve multiplexing and isolated access for different data types.

[0145] The 128-byte signaling sent to the display and control system terminal 21 uses the sRK circular buffer as the signaling transmission buffer pool, which contains 255 buffer slots, each slot supports 128 bytes of data storage, and implements multi-frame concurrent management and ordered transmission based on the circular queue structure.

[0146] The 128-byte signaling sent to FPGA terminal 12 is also managed using a pZU circular buffer to ensure that the control information sent to FPGA terminal 12 has timing and stability.

[0147] Data sent to the display and control system terminal 21 is managed through a frame transmission buffer. Each buffer block is 64MB apart and uses a continuous linear address partitioning method to ensure isolated storage and asynchronous loading of large-scale data frames.

[0148] Data is sent to FPGA terminal 12 using SRIO send buffers, with each buffer arranged in 8MB increments. A round-robin scheduling mechanism supports concurrent push of multiple frames of data to adapt to the characteristics of high-speed, low-latency links.

[0149] Data stream processing

[0150] Data type classification

[0151] 1) Single-channel TF data: Contains only feature data (Tensor Features, or TF for AI model inference), sent from FPGA terminal 12 to HC3080 chip terminal.

[0152] 2) Single-channel TF+8-channel IQ data: It includes two parts: feature data (TF) used for neural network model inference and 8 channels of complex baseband sampling data (IQ data) used by other signal processing algorithms (such as interference identification, localization, etc.).

[0153] The interaction modes for the display and control system terminal 21 to acquire radio frequency data include active mode and single-frame mode. Single-frame mode, such as... Figure 3 As shown, the display and control system terminal 21 sends a data request control signal. After receiving the request, the HC3080 terminal 11 interacts with the FPGA terminal 12 to enable the FPGA terminal 12 to acquire radio frequency data. After the HC3080 terminal 11 processes the radio frequency data, it returns the processing result and related radio frequency data to the display and control system terminal 21.

[0154] Active mode, such as Figure 4 As shown, the display and control system terminal 21 initiates an initialization signal, and the HC3080 terminal 11 and the FPGA terminal 12 establish a continuous communication channel. Through polling or interrupt mechanisms, they continuously exchange signaling and data to achieve data streaming processing and multi-frame parallelism.

[0155] Data splitting and data processing

[0156] Data received from FPGA terminal 12 is transmitted to the HC3080 chip via the SRIO interface and directly mapped to the predefined physical address space of system memory. The system reads the received data by accessing the SRIO-mapped memory area. To extract the content of each field in the data structure, a pointer offset method is used to locate and parse the length information, data content, and other metadata of each data field according to the agreed data format specifications (such as header structure, field alignment, etc.). The specific implementation of data length field extraction is as follows:

[0157] memcpy((u8*)arr1,(u8*)0x10d0000000,52);

[0158] DisTfLen=*(u32*)((u8*)arr1+16);

[0159] InfTfOriLen=*(u32*)((u8*)arr1+20);

[0160] InfTfLen=((InfTfOriLen+2048-1) / 2048)*2048;

[0161] FhwOriLen=*(u32*)((u8*)arr1+24);

[0162] FhwLen=((FhwOriLen+2048-1) / 2048)*2048;

[0163] TLen=*(u32*)((u8*)arr1+28);

[0164] DtTfLen=*(u32*)((u8*)arr1+44);

[0165] DtIqLen=*(u32*)((u8*)arr1+48);

[0166] memcpy copies the register data of the SRIO controller to the 52-byte data frame header starting at physical address 0x10d0000000 via DMA or MMU mapping, and then copies it to the local buffer arr1 via memory mapping, avoiding the security risks caused by directly manipulating the physical address.

[0167] Extract the data segment length field with a predefined offset from the buffer using pointer offset and type casting.

[0168] Result storage and result feedback

[0169] Corresponding to the above interaction modes, the data processing results are also divided into two types: active mode results and single-frame mode results. Active mode results are stored in a 10-element buffer within the loop inference information, used for cyclically storing active mode result data. Single-frame mode results are stored in a 4-element buffer within the frame transmission buffer, and are sent back to the display and control system terminal 21 after each result is obtained. Figure 5 , Figure 6 These are the result logic diagrams for two modes.

[0170] In summary, this solution constructs a heterogeneous system communication architecture consisting of five concurrent thread tasks and three message queues, achieving functional coordination and control across multiple platforms. Furthermore, it defines a unified cross-platform signaling protocol structure to encapsulate signaling and status data, ensuring the standardization and compatibility of signaling communication between systems.

[0171] Furthermore, this solution designs and implements a thread and message queue collaborative framework based on two high-speed communication interfaces, GMAC and SRIO, forming a data communication architecture adapted to the HC3080 chip. This architecture improves system communication efficiency and scalability through task division and asynchronous messaging mechanisms. Based on a deep understanding of the FPGA receiving mechanism, a large-scale data transmission logic for the HC3080 chip is designed, employing a buffer cyclic writing and integrity verification mechanism to effectively ensure the integrity and reliability of data transmission. In addition, this solution proposes feasible and efficient data transmission and reception process implementation strategies for the GMAC and SRIO communication subsystems of the HC3080 chip, including link initialization, DMA transfer, buffer management, and signaling coordination mechanisms, comprehensively improving the performance and robustness of the communication subsystem.

[0172] Although this document frequently uses terms such as First Task Module 13, Second Task Module 14, Third Task Module 15, Fourth Task Module 16, Fifth Task Module 17, First Message Queue, Second Message Queue, and Third Message Queue, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of this invention; interpreting them as any additional limitation would contradict the spirit of this invention.

Claims

1. A cross-platform radio frequency data transmission method based on HC3080 chip, characterized in that, The method comprises that a heterogeneous communication architecture comprising five concurrent task modules and three message queues is constructed in the HC3080 end; The five concurrent task modules comprise a first task module, a second task module, a third task module, a fourth task module and a fifth task module; The three message queues comprise a first message queue, a second message queue and a third message queue; The first task module writes the control signaling received from the display control system end into the first message queue or the third message queue; The second task module writes the FPGA end data received from the display control system end into the third message queue; The third task module reads the control signaling to be processed from the first message queue, distributes the processing result to the second message queue or the third message queue after executing the business logic according to the control signaling; The fourth task module obtains the display control data and the back signaling from the second message queue, and returns the display control data and the back signaling to the display control system end; The fifth task module reads the target data from the third message queue, and sends the target data to the FPGA end; The display control data is obtained after the HC3080 end processes the radio frequency data received from the FPGA end; The back signaling is generated after the HC3080 end and the FPGA end execute the task according to the control signaling; The first message queue is used for buffering the control signaling transmitted through the GMAC interface and facing the HC3080 end, for subsequent processing flow scheduling; The second message queue is used for buffering the business data sent to the display control system end through the GMAC interface, including the back signaling of the HC3080 end, the back signaling and the display control data of the FPGA end; The third message queue is used for buffering the business data sent to the FPGA end through the SRIO interface, including the FPGA end data and the control signaling facing the FPGA end.

2. The HC3080 chip based cross-platform radio frequency data transfer method of claim 1, wherein, The display control system end is used for human-computer interaction, transmitting the control signaling, the HC internal data and the FPGA end data to the HC3080 end, or receiving the back signaling and the display control data of the HC3080 end, and receiving the back signaling returned by the FPGA end through the HC3080 end; The HC3080 end is used for receiving the signaling and the data sent by the display control system end and the FPGA end, and processing the signaling and the data based on the five concurrent task modules and the three message queues; The data comprises the HC internal data, the FPGA end data and the display control data; The FPGA end is used for executing corresponding tasks according to the target information sent by the HC3080 end; The target information sent by the HC3080 end comprises the control signaling and the FPGA end data uploaded by the display control system end and transmitted through the HC3080 end.

3. The HC3080 chip based cross-platform radio frequency data transfer method of claim 1, wherein, The HC3080 end and the display control system end interact through the GMAC interface, and the HC3080 end and the FPGA end interact through the SRIO interface; The GMAC interface adopts a double-channel mode: The first channel is realized by using a stream socket, and adopts the TCP protocol during communication, and is used for transmitting the control signaling and the back signaling; The second channel is used for transmitting data, and adopts a cyclic write mechanism for cumulative verification; The communication between the first task module and the display and control system uses the first channel; The second task module communicates with the display and control system via the second channel; The fourth task module communicates with the display and control system using the first channel and the second channel.

4. The HC3080 chip based cross-platform radio frequency data transfer method of claim 3, wherein, The FPGA terminal transmits the generated feedback signaling and acquired radio frequency data back to the HC3080 terminal via the SRIO interface. The HC3080 terminal writes the feedback signaling from the FPGA terminal into the second message queue, processes the radio frequency data, and packages the processing result and related radio frequency data into display and control data and writes it into the second message queue. The feedback signaling and display control data located on the FPGA end of the second message queue are extracted by the fourth task module and transmitted back to the display control system end through the GMAC interface.

5. The HC3080 chip based cross-platform radio frequency data transfer method of claim 1, wherein, This method also includes defining a cross-platform signaling protocol structure, which is used to encapsulate control signaling and feedback signaling between the display and control system, the FPGA, and the HC3080, including: The header field head1 is used to mark the start of a data frame; The frame header field head2l, combined with the frame header field head1, forms a unique frame header identifier; The function code field cmdl and the function code field cmdh are combined to encode a 16-bit function code, which is used to indicate the operation type. FPGA-side global registers store FPGA-side status parameters; The HC-side global register stores the status parameters of the HC3080. The global register of the display and control terminal stores the status parameters of the display and control terminal; The signaling timestamp register is used to record the timestamp of signaling generation; Temporary data registers are used to pass intermediate calculation results or extended data; The checksum field is used to verify the integrity of the data frame; The tail1 and tail2 fields are used together to mark the end of a data frame.

6. The HC3080 chip based cross-platform radio frequency data transfer method of claim 5, wherein, The HC3080 terminal, display and control system terminal, and FPGA terminal achieve cross-platform interaction based on 128-byte signaling; The 128-byte signaling includes the function code field, and different function code fields trigger the interaction between the HC3080 terminal and the display and control system terminal and the FPGA terminal.

7. The HC3080 chip based cross-platform radio frequency data transfer method of claim 6, wherein, Signaling to the display and control system is sent through the sRk circular buffer, while data to the display and control system is sent through the frame transmission buffer. Signaling to the FPGA is sent through the pZU circular buffer, while data to the FPGA is sent through the SRIO transmit buffer and a round-robin scheduling mechanism.

8. The HC3080 chip based cross-platform radio frequency data transfer method of claim 7, wherein, The frame transmission buffer includes multiple buffer blocks, with each buffer block spaced 64MB apart; The SRIO transmit buffer includes multiple buffer blocks, with each buffer block spaced 8MB apart; The sRk circular buffer has 200-300 buffer slots, each slot supporting 128 bytes of data storage; The interactive modes for acquiring display and control data include active mode and single-frame mode; In single-frame mode, the HC3080 terminal interacts with the FPGA terminal based on the control signaling sent by the display and control terminal to obtain radio frequency data, and returns the radio frequency data to the display and control system terminal after processing the radio frequency data; In active mode, the display and control system initiates an initialization control signal, and the HC3080 and FPGA establish a continuous communication channel. They continuously exchange signals and data through polling or interrupt mechanisms, and return display and control data to the display and control system when the set conditions are met.

9. A cross-platform data transfer system based on HC3080 chip, characterized in that, This includes the display and control system, the FPGA, and the HC3080. The display and control system is connected to the HC3080 via a GMAC interface. The FPGA is connected to the HC3080 via an SRIO interface. The HC3080 terminal has a heterogeneous communication architecture consisting of five concurrent task modules and three message queues; The five concurrent task modules include the first task module, the second task module, the third task module, the fourth task module, and the fifth task module; The three message queues include the first message queue, the second message queue, and the third message queue; The first task module will write the control signaling received from the display and control system to the first message queue or the third message queue. The second task module will write the FPGA data received from the display and control system to the third message queue; The third task module reads the control signaling to be processed from the first message queue, executes the business logic according to the control signaling, and then distributes the processing result to the second message queue or the third message queue. The fourth task module obtains display and control data and feedback signaling from the second message queue, and then sends the display and control data and feedback signaling back to the display and control system. The fifth task module reads the target data from the third message queue and sends the target data to the FPGA terminal; The display and control data is obtained by processing the radio frequency data received from the FPGA by the HC3080 terminal; The feedback signaling is generated by the HC3080 terminal and the FPGA terminal after executing tasks based on the control signaling; The first message queue is used to cache control signaling transmitted through the GMAC interface and directed to the HC3080 end for subsequent processing scheduling; The second message queue is used to cache service data sent to the display and control system via the GMAC interface, including the return signaling from the HC3080 end, the return signaling from the FPGA end, and display and control data. The third message queue is used to cache service data sent to the FPGA via the SRIO interface, including FPGA data and control signaling directed to the FPGA.

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