Phased array system readout electronics platform and method

Abstract

The invention relates to the technical field of readout electronics, and discloses a phased array system readout electronics platform and method, and the platform comprises a radio frequency collection module which is configured to convert a space electromagnetic wave into a radio frequency collection signal; the digital receiving module comprises a time frequency management unit and at least one signal processing unit, and the time frequency management unit is configured to send a clock output signal and a time sequence control pulse signal to each signal processing unit, so that each signal processing unit synchronously analyzes the time sequence control pulse signal according to the clock output signal; performing coarse channel processing on the radio frequency acquisition signal to obtain a plurality of channel signals; the back-end readout module is configured to generate astronomical observation data according to the channel signal. According to the invention, the clock output signal and the time sequence control pulse signal are accurately controlled to ensure the consistency and synchronism of the processing process of each signal processing unit, and meanwhile, the data processing pressure is reduced by means of coarse channelization processing, so that the power consumption of the system is effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of readout electronics, and in particular to a phased array readout electronics platform and method. Background Art

[0002] A phased array system is a system that precisely controls the phase and amplitude of multiple antenna units in the array. Multiple antenna units are arranged according to a specific pattern to form an array. By changing the phase and amplitude of the transmitted or received signal of each antenna unit, the signals interfere with each other in space, achieving flexible pointing and precise focusing of the beam. Therefore, it plays an important role in the readout electronics system in the field of radio astronomy.

[0003] In related technologies, the readout electronics system obtains astronomical detection data by analyzing the signals received by phased array and other equipment. This process involves a large amount of signal and data processing, and has problems such as low analysis efficiency and low readout accuracy. Summary of the Invention

[0004] The present application provides a phased array readout electronics platform and method, which solves the technical problems of low resolution efficiency and low readout accuracy in phased array readout electronics systems. By precisely controlling clock output signals and timing control pulse signals, the platform ensures the consistency and synchronization of the processing processes of various signal processing units. At the same time, coarse channelization processing is used to reduce the data processing pressure of the back-end readout module, facilitate further refined analysis of designated sub-channel signals, and effectively reduce system power consumption.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, embodiments of the present application provide a phased array readout electronics platform, comprising: A radio frequency acquisition module, wherein the radio frequency acquisition module is configured to acquire spatial electromagnetic waves and convert the spatial electromagnetic waves into radio frequency acquisition signals; a digital receiving module adapted to receive the RF acquisition signal, and comprising a time-frequency management unit and at least one signal processing unit, wherein the time-frequency management unit is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each of the signal processing units, respectively, so that each of the signal processing units synchronously analyzes the timing control pulse signal according to the clock output signal, and performs coarse channel processing and framing on the RF acquisition signal according to the analysis result, thereby obtaining multiple channel signals; A back-end readout module is configured to generate astronomical observation data according to the channel signal.

[0006] The phased array readout electronics platform proposed in the embodiment of the present application realizes the effective acquisition of space electromagnetic waves and signal front-end processing through the radio frequency acquisition module, providing a basis for subsequent processing. The collaborative work of the time-frequency management unit and the signal processing unit in the digital receiving module enables each signal processing unit to synchronously analyze the timing control pulse signal based on a unified clock output signal. Compared with the relevant technology, it not only improves the integration of the digital receiving module, but also ensures the synchronization of the coarse channel processing of the radio frequency acquisition signal by each signal processing unit, so that the back-end readout module can work normally, greatly improving the accuracy of astronomical observation data. In addition, the present application also uses the coarse channel processing of the radio frequency acquisition signal to reduce the data processing pressure of the back-end readout module, and is conducive to further refined analysis of the specified sub-channel signal, which not only significantly improves the working efficiency of the phased array readout electronics platform, but also effectively reduces the system power consumption and reduces the system operating cost.

[0007] Optionally, in some embodiments of the present application, the time-frequency management unit includes a clock source and a frequency synthesis subunit; Wherein, the clock source is used to generate a reference clock signal; The frequency synthesis subunit is used to generate multiple clock output signals based on the reference clock signal, wherein the number of the clock output signals is greater than the number of the signal processing units, and the multiple clock output signals are respectively in the same frequency and phase as the reference clock signal.

[0008] The frequency synthesis subunit generates multiple clock output signals with the same frequency and phase based on the reference clock signal, and the number is greater than that of the signal processing units, thereby providing each signal processing unit with a sufficient and unified clock signal source, ensuring that each signal processing unit operates at the same clock rhythm, further improving the synchronization of the coarse channel processing of the RF acquisition signal, and effectively avoiding multi-channel signal delays or phase inconsistencies caused by clock asynchrony.

[0009] Optionally, in some embodiments of the present application, the frequency synthesis subunit includes a first frequency signal distributor and a second frequency signal distributor, the input ends of the first frequency signal distributor and the second frequency signal distributor are respectively connected to the clock source, and the output ends of the first frequency signal distributor and the second frequency signal distributor are connected to the clock input end of the corresponding signal processing unit; The first frequency signal distributor and the second frequency signal distributor are used to generate a plurality of the clock output signals according to the reference clock signal.

[0010] Through the first frequency signal distributor and the second frequency signal distributor, multiple clock output signals with the same frequency and phase can be generated from a reference clock signal, which reserves space for system expansion and enhances the scalability of the system. This makes it unnecessary to redesign the clock generation module when adding signal processing units, reduces the cost and complexity of system upgrades, and greatly improves the reusability and applicability of the phased array readout electronics platform.

[0011] Optionally, in some embodiments of the present application, the clock source is further used to generate a trigger signal, and the time-frequency management unit further includes a timing control subunit; The timing control subunit is suitable for receiving the trigger signal and the clock output signal, and generating the timing control pulse signal according to the system preset control parameters in response to the trigger signal and the clock output signal, wherein the pulse width of the timing control pulse signal matches the system preset control parameters.

[0012] The timing control subunit generates a timing control pulse signal by combining the trigger signal and the clock output signal, so that the timing control pulse signal can accurately carry the relevant control information of the system's preset control parameters. It can accurately adjust the pulse width of the timing control pulse signal according to different system requirements and application scenarios. While ensuring the synchronization of the acquisition channels between signal processing units, it also realizes the multiplexing control of other functions such as inter-channel synchronous state triggering and logic reset, phase signal acquisition, etc. of the signal processing unit, thereby better adapting to different observation tasks and data processing requirements, improving the flexibility and adaptability of the phased array system readout electronics platform, and saving a lot of hardware circuit design costs.

[0013] Optionally, in some embodiments of the present application, the timing control subunit includes a programmable logic processor; The first input end of the programmable logic processor is suitable for receiving the clock output signal, the second input end of the programmable logic processor is suitable for receiving the trigger signal, and the output end of the programmable logic processor is connected to the corresponding signal processing unit to output the timing control pulse signal, wherein the output end of the programmable logic processor corresponds one-to-one to the signal processing unit.

[0014] Optionally, in some embodiments of the present application, the signal processing unit is configured to parse the pulse width of the timing control pulse signal according to the clock output signal, and perform synchronous coarse channel processing on the RF acquisition signal when the pulse width meets a preset condition.

[0015] By analyzing the pulse width of the timing-controlled pulse signal, it is ensured that each signal processing unit performs signal acquisition and coarse channel processing under the same time reference, which greatly improves the synchronization between signal processing units and effectively improves the accuracy and reliability of signal processing, thereby enabling the back-end readout module to accurately generate astronomical observation data.

[0016] Optionally, in some embodiments of the present application, the signal processing unit is an integrated chip based on a Radio Frequency System on Chip (RFSoC), and the integrated chip includes an analog-to-digital conversion subunit, which is configured to perform analog-to-digital conversion on the RF acquisition signal in response to the clock output signal and the timing control pulse signal, and obtain the converted digital acquisition signal to perform the coarse channel processing on the digital acquisition signal.

[0017] The use of an RFSoC-based integrated chip as the signal processing unit leverages its high level of integration to reduce the complexity associated with connecting multiple independent chips, lowering hardware design difficulty and cost. Furthermore, by performing coarse channel processing on the digitally acquired signals, the signal data rate is significantly reduced, thereby saving significant hardware logic resources and improving processing efficiency.

[0018] Optionally, in some embodiments of the present application, the integrated chip further includes a demodulation subunit, a filtering subunit, and a framing subunit; The demodulation subunit is configured to perform orthogonal demodulation on the digital acquisition signal and obtain a demodulated initial baseband signal; The filtering subunit is configured to perform a double decimation filter on the initial baseband signal to obtain a target baseband signal, and perform synchronous coarse channel processing on the target baseband signal through polyphase filtering and fast Fourier transform to obtain multiple subchannel signals; The framing subunit is configured to frame the sub-channel signals according to the computing capability of the back-end readout module to obtain the channel signal, and transmit the channel signal to the back-end readout module through the UDP protocol.

[0019] Optionally, in some embodiments of the present application, the radio frequency acquisition module includes an antenna array unit and a radio frequency front-end unit; The antenna array unit includes a plurality of mutually independent antennas, and the plurality of antennas are arranged in a planar array to collect the spatial electromagnetic waves; The RF front-end unit is configured to sequentially perform low-noise amplification processing, analog filtering processing, and gain amplification processing on the spatial electromagnetic wave, so that the amplitude of the RF acquisition signal obtained after processing is within a preset range.

[0020] In a second aspect, an embodiment of the present application provides a phased array system readout electronics method, which is applied to the platform described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 This is one of the structural diagrams of the phased array readout electronics platform proposed in the embodiments of the present application; Figure 2 This is the second structural diagram of the phased array readout electronics platform proposed in the embodiment of the present application; Figure 3 This is a schematic diagram of the structure of the frequency synthesis subunit proposed in an embodiment of the present application; Figure 4 This is a signal timing diagram of the digital receiving module proposed in the embodiment of the present application; Figure 5 This is a schematic diagram of the structure of the timing control subunit proposed in an embodiment of the present application; Figure 6 A schematic diagram of the signal flow of the timing control subunit proposed in an embodiment of the present application; Figure 7 This is a schematic diagram of the structure of the signal processing unit proposed in an embodiment of the present application; Figure 8 This is a schematic diagram of the structure of the integrated chip proposed in the embodiment of the present application; Figure 9 A schematic diagram of the structure of a computer device proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0024] A phased array system precisely controls the phase and amplitude of multiple antenna elements in an array. These elements are arranged in a specific pattern to form an array. By varying the phase and amplitude of the transmitted or received signals from each element, the signals interfere with each other in space, achieving flexible beam pointing and precise focusing. Compared to traditional mechanically scanned antenna elements, phased array systems can rapidly change beam pointing through electronic scanning, enabling observations of different sky regions in a short period of time. They can also simultaneously form multiple beams for simultaneous observations of multiple targets, offering exceptional observation flexibility. Phased array feeds can also expand the field of view, while digital beam combining techniques enable a wider field of view and faster observation speeds. In terms of resolution, precise control of the phase and amplitude of antenna elements, combined with interferometry, can achieve higher resolution than single-aperture telescopes, facilitating the study of fine celestial structure. Furthermore, phased array systems, composed of multiple independent antenna elements, are relatively inexpensive to construct and maintain. Failure of a single antenna element does not affect the overall observational functionality, making them crucial for readout electronics in radio astronomy.

[0025] The readout electronics system analyzes the signals received by phased array devices to obtain astronomical detection data. In some application scenarios, a system architecture that combines an independent analog-to-digital converter (ADC) with the field programmable gate array (FPGA) of the acquisition board is usually adopted. Data transmission between the various acquisition channels of the acquisition board is achieved through high-speed serial interface protocols such as J204B.

[0026] As the sensitivity and resolution requirements for radio astronomical observations continue to increase, the number of acquisition channels required for phased array readout electronics systems has increased dramatically. However, in related technologies, on the one hand, due to the limitations of semiconductor process technology, the synchronization between the various acquisition channels in the above-mentioned data transmission scheme is determined by the quality of the external clock signal and trigger signal. As the number of channels increases, the synchronization between the acquisition channels is more susceptible to transmission delays and signal jitter, which in turn leads to reduced synchronization. On the other hand, the separate architecture of independent ADCs and FPGAs lengthens the signal transmission path, increases the delay difference between channels, and makes it difficult to ensure high-precision signal synchronization. Therefore, related technologies have the problems of low resolution efficiency and low readout accuracy, making it difficult to meet the needs of high-precision astronomical observations.

[0027] To address the above issues, this specification provides a phased array readout electronics platform that can be applied to phased array systems. Phased array systems can be used in a variety of fields, including radio astronomy, radar, ultrasonic detection and imaging, and meteorological detection. In radio astronomy, phased array systems can be used to construct phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band radio frequency signals. It is understood that, after adaptive modification, this application can also be used in other systems or devices for multi-channel signal acquisition, such as multi-channel data acquisition systems, high-frequency trading systems, or automated test systems.

[0028] Figure 1 FIG. 1 is a schematic diagram of a phased array readout electronics platform according to an embodiment of the present application. Figure 1 As shown, the platform includes a radio frequency acquisition module 100 , a digital receiving module 200 and a back-end readout module 300 .

[0029] The RF acquisition module 100 is configured to collect electromagnetic waves from space and convert them into RF acquisition signals. Specifically, the RF acquisition module 100 processes the received electromagnetic waves through a series of signal processing steps, such as amplification and filtering, to convert these weak electromagnetic waves into RF acquisition signals with specific parameters such as frequency range and amplitude. This allows the subsequent digital receiving module 200 to effectively process the RF acquisition signals, thereby providing appropriate input signals for the normal operation of the entire phased array system's readout electronics platform.

[0030] The digital receiving module 200 is suitable for receiving RF acquisition signals, and the digital receiving module 200 includes a time-frequency management unit 210 and at least one signal processing unit 220, wherein the time-frequency management unit 210 is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each signal processing unit 220 respectively, so that each signal processing unit 220 synchronously analyzes the timing control pulse signal according to the clock output signal, and performs coarse channel processing and framing on the RF acquisition signal according to the analysis result through the signal processing unit 220 to obtain multiple channel signals.

[0031] Specifically, the digital receiving module 200 generates a clock output signal Ex_Refclk through the time-frequency management unit 210 to provide a unified working clock source for each signal processing unit 220. In addition, the time-frequency management unit 210 also sends a timing control pulse signal to the signal processing unit 220. Each signal processing unit 220 performs synchronous analysis of the timing control pulse signal based on the clock output signal with the same frequency and phase, and each signal processing unit 220 includes multiple acquisition channels, so that each signal processing unit 220 performs one of the following operations: inter-channel synchronization state triggering operation, logic reset operation or phase acquisition operation according to the analysis result. In the case where the analysis result triggers the channel acquisition operation, each signal processing unit 220 starts to perform multi-channel acquisition and coarse channel processing of the RF acquisition signal to obtain multiple sub-channel signals, and then frames the multiple sub-channel signals to obtain multiple channel signals.

[0032] The back-end readout module 300 is configured to generate astronomical observation data based on the channel signals. Specifically, it receives the channel signals processed by the digital receiving module 200 and performs subsequent processing such as digital beamforming, radio frequency interference cancellation, fine channelization, and neutral hydrogen / Fast Radio Burst (FRB) searches. Ultimately, it outputs scientific astronomical observation data, which includes important information such as the position, velocity, and radiation intensity of celestial bodies, providing critical data support for astronomical research.

[0033] Therefore, the phased array readout electronics platform provided in this embodiment realizes the effective acquisition of space electromagnetic waves and signal front-end processing through the RF acquisition module 100, providing a basis for subsequent processing. The coordinated work of the time-frequency management unit 210 and the signal processing unit 220 in the digital receiving module 200 enables each signal processing unit 220 to synchronously analyze the timing control pulse signal based on a unified clock output signal. Compared with the relevant technology, it not only improves the integration of the digital receiving module 200, but also ensures the synchronization of the coarse channel processing of the RF acquisition signal by each signal processing unit 220, so that the back-end readout module 300 can work normally, greatly improving the accuracy of astronomical observation data. In addition, the present application also uses the coarse channel processing of the RF acquisition signal to reduce the data processing pressure of the back-end readout module, and is conducive to further refined analysis of the specified sub-channel signal, which not only significantly improves the working efficiency of the phased array readout electronics platform, but also effectively reduces power consumption and reduces system operating costs.

[0034] In some embodiments of the present application, Figure 2 As shown, the RF acquisition module 100 includes an antenna array unit 110 and a RF front-end unit (Analog Front End, AFE) 120; The antenna array unit 110 includes multiple independent antennas, and the multiple antennas are arranged in a planar array to collect space electromagnetic waves; The RF front-end unit 120 is configured to sequentially perform low-noise amplification processing, analog filtering processing, and gain amplification processing on the spatial electromagnetic wave, so that the amplitude of the RF acquisition signal obtained after processing is within a preset range.

[0035] Specifically, the antenna array unit 110 is composed of large-scale independent antennas, which adopt a planar array layout and can cover radio signals in a specific frequency band. They are responsible for the efficient reception of electromagnetic waves in space and provide original signal input for the platform.

[0036] The RF front-end unit 120 integrates a low-noise amplifier, a bandpass filter, a gain amplifier, and a distribution network. Since the spatial electromagnetic waves transmitted from the antenna array typically have extremely low signal power, they are easily interfered with by various types of noise during subsequent processing, resulting in signal quality degradation. The low-noise amplifier boosts the power of weak signals while minimizing the noise introduced by itself. The bandpass filter receives the signal processed by the low-noise amplifier and can accurately set a specific frequency range. Only signals within this range can pass smoothly, while signals of other frequencies are effectively suppressed, thereby further improving the signal-to-noise ratio. The gain amplifier receives the signal processed by the bandpass filter and performs gain amplification on the signal to obtain an analog RF signal. The analog RF signal is then sent to the corresponding signal processing unit 220 in the digital receiving module 200, thereby amplifying the weak spatial electromagnetic waves received by the antenna array to a range that can be processed by each signal processing unit 220 in the digital receiving module 200, while maintaining a high signal-to-noise ratio.

[0037] In some embodiments of the present application, Figure 2 As shown, the time-frequency management unit 210 includes a clock source 211 and a frequency synthesis subunit 212, wherein the clock source 211 is used to generate a reference clock signal, and the frequency synthesis subunit 212 is used to generate multiple clock output signals based on the reference clock signal, wherein the number of clock output signals is greater than the number of signal processing units 220, and the multiple clock output signals are respectively at the same frequency and in the same phase as the reference clock signal.

[0038] Specifically, in this embodiment of the present application, clock source 211 is a rubidium atomic clock standard source. This rubidium atomic clock standard source has GPS and Beidou satellite discipline capabilities. It receives GPS and Beidou satellite signals and synchronizes the output frequency of its rubidium oscillator to these signals, thereby providing a 10 MHz high-precision reference clock signal. Furthermore, clock source 211 is used to generate a trigger signal, which in this embodiment is a 1 pps (pulse per second) pulse.

[0039] The frequency synthesis subunit 212 is suitable for receiving the 10MHz reference clock signal generated by the clock source 211, and splitting the reference clock signal into multiple clock output signals Ex_Refclk with the same source, frequency and phase, thereby providing a stable external clock for the digital receiving module 200 and ensuring that the input clock of each signal processing unit 220 is synchronized.

[0040] Therefore, in the embodiment of the present application, the frequency synthesis subunit 212 generates multiple clock output signals Ex_Refclk with the same frequency and phase based on the reference clock signal, and the number is greater than the number of signal processing units 220, thereby providing a sufficient and unified clock signal source for each signal processing unit 220, ensuring that each signal processing unit 220 operates at the same clock rhythm, further improving the synchronization of the coarse channel processing of the RF acquisition signal, and effectively avoiding the multi-channel signal delay or phase inconsistency problem caused by clock asynchrony.

[0041] Furthermore, in some embodiments of the present application, Figure 3 As shown, the frequency synthesis subunit 212 includes a first frequency signal distributor 2121 and a second frequency signal distributor 2122. The input terminals of the first frequency signal distributor 2121 and the second frequency signal distributor 2122 are respectively connected to the clock source 211, and the output terminals of the first frequency signal distributor 2121 and the second frequency signal distributor 2122 are respectively connected to the clock input terminals of the corresponding signal processing unit 220. The first frequency signal distributor 2121 and the second frequency signal distributor 2122 are used to generate multiple clock output signals Ex_Refclk based on the reference clock signal.

[0042] Specifically, a frequency signal distributor is a radio frequency signal distribution and amplification device that distributes a frequency standard signal into multiple co-frequency signal outputs. In one embodiment of the present application, the 10 MHz reference clock signal output by the clock source 211 is input into the input terminals of the first frequency signal distributor 2121 and the second frequency signal distributor 2122, respectively. The first frequency signal distributor 2121 and the second frequency signal distributor 2122 are respectively used to distribute the 10 MHz reference clock signal into 16 clock output signals Ex_Refclk. That is, the frequency synthesis subunit 212 can split the reference clock signal into 32 co-source, co-frequency, and co-phase clock output signals Ex_Refclk1 to Ex_Refclk32, and respectively connect 28 of the clock output signals Ex_Refclk to the corresponding 28 signal processing units 220.

[0043] It should be noted that Figure 3Only two frequency signal distributors are used to generate 32 clock output signals Ex_Refclk1 to Ex_Refclk32 as an example of an embodiment of the present application. Similarly, the digital receiving module 200 includes 28 signal processing units 220 which is only an example of an embodiment of the present application and is not used to limit the present application.

[0044] Thus, it can be seen that the embodiment of the present application utilizes a frequency signal distributor to generate multiple clock output signals Ex_Refclk with the same frequency and phase, and the number of clock output signals Ex_Refclk is redundant with respect to the signal processing unit 220. On the one hand, this reserves space for system expansion and enhances the scalability of the system. This eliminates the need to redesign the clock generation module when, for example, a signal processing unit 220 needs to be added, thereby reducing the cost and complexity of system upgrades. On the other hand, during actual operation, if a clock output signal Ex_Refclk fails or is interfered with, other redundant clock output signals Ex_Refclk can immediately replace it, ensuring that the signal processing unit 220 can still obtain a stable clock signal, maintaining normal system operation, and improving the reliability and fault tolerance of the system. Therefore, the reusability and applicability of the phased array readout electronics platform are greatly improved.

[0045] In some embodiments of the present application, Figure 2 As shown, the time-frequency management unit 210 further includes a timing control subunit 213, wherein the timing control subunit 213 is adapted to receive a trigger signal and a clock output signal Ex_Refclk, and generate a timing control pulse signal SYNC_OUT according to a system preset control parameter in response to the trigger signal and the clock output signal Ex_Refclk, wherein the pulse width of the timing control pulse signal SYNC_OUT matches the system preset control parameter.

[0046] Specifically, the timing control subunit 213 has the above-mentioned system preset control parameters built in. The system preset control parameters are determined during the debugging phase of the entire readout electronics platform. The system preset control parameters can be used to determine the timing of the rising and falling edges of the timing control pulse signal SYNC_OUT, thereby realizing pulse width control of the timing control pulse signal SYNC_OUT.

[0047] Furthermore, the timing control subunit 213 starts to generate the timing control pulse signal SYNC_OUT according to the system preset control parameters when receiving the 1pps trigger signal, wherein the timing control subunit 213 uses the different pulse widths of the timing control pulse signal SYNC_OUT to represent the control information contained in the system preset control parameters. Figure 4As shown, when the pulse width of the timing control pulse signal SYNC_OUT corresponds to 3 cycles of the clock output signal Ex_Refclk, the timing control pulse signal SYNC_OUT represents the synchronization state trigger control function of the acquisition channel; when the pulse width of the timing control pulse signal SYNC_OUT corresponds to 2 cycles of the clock output signal Ex_Refclk, the timing control pulse signal SYNC_OUT represents the logic reset control function of the acquisition channel; when the pulse width of the timing control pulse signal SYNC_OUT corresponds to 1 cycle of the clock output signal Ex_Refclk, the timing control pulse signal SYNC_OUT represents the phase signal acquisition function of the acquisition channel.

[0048] The timing control subunit 213 then sends the timing control pulse signal SYNC_OUT to each signal processing unit 220 . The signal processing unit 220 counts the pulse width of the timing control pulse signal SYNC_OUT using the counting signal count to parse out the specific function represented by the timing control pulse signal SYNC_OUT.

[0049] Therefore, the timing control subunit 213 generates a timing control pulse signal SYNC_OUT by combining the trigger signal, the system preset control parameters and the clock output signal Ex_Refclk, so that the timing control pulse signal SYNC_OUT can accurately carry the relevant control information of the system preset control parameters, and can accurately adjust the pulse width of the timing control pulse signal SYNC_OUT according to different system requirements and application scenarios. While ensuring the channel synchronization between the signal processing units 220, it also realizes the multiplexing control of the acquisition channel synchronization state trigger and logic reset, phase signal acquisition and other functions of the signal processing unit, thereby better adapting to different observation tasks and data processing requirements, improving the flexibility and adaptability of the phased array system readout electronics platform, and saving a lot of hardware circuit design costs.

[0050] Furthermore, in some embodiments of the present application, Figure 5 The hardware structure of the timing control subunit 213 is shown as follows: Figure 5 As shown, the timing control subunit 213 includes a programmable logic processor 2131, a first input end of the programmable logic processor 2131 is suitable for receiving the clock output signal Ex_Refclk, a second input end of the programmable logic processor 2131 is suitable for receiving a trigger signal, and an output end of the programmable logic processor 2131 is connected to the corresponding signal processing unit 220 to output the timing control pulse signal SYNC_OUT, wherein the output end of the programmable logic processor 2131 corresponds one-to-one to the signal processing unit 220.

[0051] Specifically, the timing control subunit 213 includes a programmable logic processor 2131 on the programmable logic (PL) side and a state manager 2132 on the processing system (PS) side. In an example of this embodiment, the state manager 2132 is a Zynq7Z020SoC series FPGA module, and the programmable logic processor 2131 is an XCKU35 series FPGA module.

[0052] also, Figure 6 The signal flow of the timing control subunit 213 is shown in FIG. Figure 6 As shown, in some embodiments of the present application, system operating parameters are also distributed through the host computer 400 for system configuration. Specifically, the state manager 2132 is connected to the switch 500 via the PS-side Gigabit Ethernet port GE, thereby communicating with the host computer 400, receiving and parsing the system operating parameters sent by the host computer 400, and then distributing the system operating parameters to each signal processing unit 220 to initialize the configuration of the system operating parameters such as the operating mode and starting frequency of the signal processing unit 220.

[0053] The state manager 2132 also interacts with the programmable logic processor 2131 through the GPIO interface. Specifically, the third input terminal of the programmable logic processor 2131 is the GPIO interface, which is connected to the state manager 2132 through the third input terminal to receive the synchronization instruction sent by the host computer 400, so that when the programmable logic processor 2131 receives the above-mentioned synchronization instruction, it responds to the 1pps trigger signal and starts to generate the timing control pulse signal SYNC_OUT with different pulse widths at different times.

[0054] Furthermore, the clock output signal Ex_Refclk generated by the frequency synthesis subunit 212 is processed by the buffer Buffer to obtain the Ex_Refclk_in signal, which is then input to the first input terminal of the programmable logic processor 2131. Simultaneously, the 1 pps trigger signal generated by the clock source 211 is input to the second input terminal of the programmable logic processor 2131. Upon receiving the 1 pps trigger signal, the programmable logic processor 2131 begins analyzing the built-in preset system control parameters and generates the timing control pulse signal SYNC_OUT based on the analysis results. For details on the generation process, please refer to the relevant description of the above embodiment.

[0055] Taking the digital receiving module 200 including 28 signal processing units 220 as an example, the programmable logic processor 2131 generates 28 timing control pulse signals SYNC_OUT1 to SYNC_OUT28 through 28 output terminals and sends them to the corresponding signal processing units 220 respectively.

[0056] Further, the state manager 2132 is also configured to acquire the unit state information of each signal processing unit 220 and upload to the host computer 400 for display, while the state manager 2132 collects the channel phase information of each signal processing unit 220 and calculates the channel phase adjustment information between each signal processing unit 220 to distribute the channel phase adjustment information to each signal processing unit 220 to achieve synchronization.

[0057] For example, the state manager 2132 polls the state information of each signal processing unit 220 through the switch 500, specifically, collects the clock lock state, UDP transmission link state, channel state information and other unit state information uploaded by the 28 signal processing units 220, and reports to the host computer 400 for system state display. In addition, the state manager 2132 collects the acquisition channel state information of each signal processing unit 220, such as phase information, etc., and further uses the phase information to calculate and converge the phase difference between all acquisition channels, and distributes the phase adjustment value as channel adjustment information to each signal processing unit 220, so that each signal processing unit 220 configures the phase of the Numerically Controlled Oscillator (NCO) based on the channel adjustment information, to realize the phase calibration and synchronous acquisition function between all acquisition channels.

[0058] In some embodiments of the present application, the signal processing unit 220 is configured to parse the pulse width of the timing control pulse signal SYNC_OUT according to the clock output signal Ex_Refclk, and perform synchronous coarse channel processing on the radio frequency acquisition signal when the pulse width meets the preset condition.

[0059] Specifically, the signal processing unit 220 receives the timing control pulse signal SYNC_OUT and internally parses it, as shown in Figure 4 The signal processing unit 220 internally counts the pulse width of the timing control pulse signal SYNC_OUT based on the clock output signal Ex_Refclk, and generates a count signal count accordingly. When the pulse width of the timing control pulse signal SYNC_OUT is equal to 3 periods of the clock output signal Ex_Refclk, that is, the rising edge of the timing control pulse signal SYNC_OUT is monitored for 3 periods, the count signal count counts to 3 after a certain delay, and a pulse SYNC is generated at the moment when the count is 3, to trigger the inter-channel synchronous acquisition operation of the signal processing unit 220 in response to the pulse SYNC.

[0060] Thus, the embodiments of the present application utilize the different pulse widths of the timing control pulse signal SYNC_OUT to implement time-sharing inter-channel synchronization state triggering operations, logic reset operations, or phase acquisition operations within the signal processing unit 220. For example, when the pulse width of the timing control pulse signal SYNC_OUT is equal to two cycles of the clock output signal Ex_Refclk, that is, when the rising edge of the timing control pulse signal SYNC_OUT is detected after two cycles, the count signal count counts to 2 after a certain delay, and a pulse Reset is generated at the moment of counting to 2. In response to the pulse Reset, the signal processing unit 220 triggers a logic reset operation of the signal processing unit 220, thereby resetting the states of the various acquisition channels of the signal processing unit 220. For another example, when the pulse width of the timing control pulse signal SYNC_OUT is equal to one cycle of the clock output signal Ex_Refclk, that is, the rising edge of the timing control pulse signal SYNC_OUT is monitored after one cycle, the counting signal count counts to 1 after a certain delay, and a pulse Catch is generated at the moment when the count reaches 1. The signal processing unit 220 responds to the pulse Catch to trigger the phase acquisition operation of the signal processing unit 220, thereby sending the phase information of each acquisition channel of the signal processing unit 220 to the state manager 2132.

[0061] Therefore, the embodiment of the present application ensures that each signal processing unit 220 performs signal acquisition and coarse channel processing under the same time reference by analyzing the pulse width of the timing control pulse signal SYNC_OUT, greatly improving the synchronization between the signal processing units 220, and effectively improving the accuracy and reliability of signal processing, thereby enabling the back-end readout module to accurately generate astronomical observation data.

[0062] Furthermore, the signal processing unit 220 is an integrated chip based on RFSoC, specifically, Figure 7 The hardware structure of the signal processing unit 220 is shown in FIG. Figure 7 As shown, the integrated chip includes an RFdc IP core and its peripheral circuits, wherein the integrated chip includes 8 acquisition channels from Ch1 to Ch8, which are used to perform high-speed, parallel, real-time and synchronous acquisition and processing of RF acquisition signals.

[0063] The peripheral circuits of each integrated chip include a phase-locked loop (PLL) for synchronizing the output signal with the input reference signal. In one embodiment of the present application, the peripheral circuits include a first PLL unit and a second PLL unit. The input of the first PLL unit is connected to the time-frequency management unit, the output of the first PLL unit is connected to the input of the second PLL unit, and the output of the second PLL unit is connected to the input of the analog-to-digital conversion subunit.

[0064] The peripheral circuit also includes a memory module (DDR) for caching and reorganizing the signals of multiple acquisition channels at multiple times when the signals are framed.

[0065] The peripheral circuit also includes a power supply module for providing the integrated chip with various voltages required for operation.

[0066] The peripheral circuit also includes four QSFP28 optical ports with a single-port communication rate of up to 100Gbps, which are used for high-speed and real-time data transmission between the signal processing unit 220 and the back-end readout module.

[0067] Figure 8 The structure of the RFdc IP core in the integrated chip is shown, wherein the integrated chip includes an analog-to-digital conversion subunit 221. The analog-to-digital conversion subunit 221 is configured to perform analog-to-digital conversion on the RF acquisition signal in response to the clock output signal Ex_Refclk and the timing control pulse signal SYNC_OUT, and obtain the converted digital acquisition signal to perform coarse channel processing on the digital acquisition signal.

[0068] Specifically, the first PLL unit is configured to generate an internal clock signal Clk based on the clock output signal Ex_Refclk and the timing control pulse signal SYNC_OUT. The second PLL unit is an RF PLL, which is configured to perform frequency multiplication sampling based on the internal reference clock Refclk output by the first PLL unit to obtain a high-frequency sampling clock Sampling clk, and distribute the high-frequency sampling clock Sampling clk to each analog-to-digital conversion sub-unit in the integrated chip to convert the RF acquisition signal into a digital acquisition signal based on the high-frequency sampling clock Samplingclk.

[0069] Furthermore, if Figure 8 As shown, the integrated chip also includes a demodulation subunit 222, a filtering subunit 223, and a framing subunit 224. The demodulation subunit 222 is configured to perform orthogonal demodulation on the digital acquisition signal and obtain a demodulated initial baseband signal. The filtering subunit 223 is configured to perform a double decimation filter on the initial baseband signal to obtain a target baseband signal, and then perform synchronous coarse channel processing on the target baseband signal through polyphase filtering and fast Fourier transform to obtain multiple subchannel signals. The framing subunit 224 is configured to frame the subchannel signals according to the computing power of the backend readout module to obtain a channel signal, and transmit the channel signal to the backend readout module via the UDP protocol.

[0070] Specifically, the digital acquisition signal output by the analog-to-digital conversion subunit 221 undergoes quadrature demodulation to remove the high-frequency NCO carrier / local oscillator frequency components, resulting in an initial baseband signal carrying phase information. The effective bandwidth of this initial baseband signal is smaller than the bandwidth of the radio signal entering the antenna array. Subsequently, the initial baseband signal undergoes two-fold (D2) decimation filtering. Specifically, after filtering the initial baseband signal through a low-pass filter (LPF), only one valid sampling point is retained for every two sampling points input into the initial baseband signal. This reduces the data rate of the target baseband signal to half that of the initial baseband signal, effectively alleviating the data processing pressure on the back-end readout module.

[0071] The target baseband signal is then processed by the filtering sub-unit 223 through the polyphase filtering of the polyphase filter bank (PFB) or the over-sampled polyphase filter bank (OPFB), and then coarse digital channelization is achieved through the fast Fourier transform (FFT). The target baseband signal can be divided into M coarse-grained sub-channel signals, where the number of sub-channel signals is determined by the number of branches of the PFB or OPFB and the number of FFT points.

[0072] The framing sub-unit 224 frames the sub-channel signals in Variable Length Data Interchange Format (VLBI) and encapsulates them using User Datagram Protocol (UDP) according to the GPU processing requirements and capabilities of the back-end readout module. The signals are then distributed via a 100Gbps UDP QSFP28 optical port to the GPU processing boards in the back-end readout module for digital beam forming (DBF), radio frequency interference (RFI) cancellation, and fine-channelization.

[0073] Therefore, the embodiments of the present application utilize an integrated chip based on an RFSoC as the signal processing unit. Leveraging its high degree of integration, this reduces the complexity associated with connecting multiple independent chips, lowering the difficulty and cost of hardware design. Furthermore, by performing coarse channel processing on the digitally acquired signals, the signal data rate is significantly reduced, thereby saving a significant amount of hardware logic resources and improving processing efficiency.

[0074] It can be seen that the digital receiving module proposed in the embodiment of the present application utilizes the RFSoC architecture to integrate ADC, FPGA and high-speed interconnection resources into a single chip, and utilizes the RFdc IP core to realize the full process of RF signal acquisition, analog-to-digital conversion and signal synchronization processing on-chip. The high integration of the RFSoC architecture not only ensures the synchronization and phase consistency of multi-channel signal acquisition through close coordination at the hardware level, reducing the delay and interference caused by inter-board transmission in the traditional discrete architecture, but also realizes the rapid conversion and preprocessing from RF signals to coarse channelized data through the efficient signal processing link on the chip, greatly improving the signal processing efficiency, and can build a highly integrated single-chip phased array unit, ultimately ensuring the accuracy and real-time nature of astronomical observation data.

[0075] Accordingly, an embodiment of the present application provides a phased array readout electronics method, which is applied to the platform described in any one of the above embodiments.

[0076] The details of the method proposed in the embodiment of the present application are the same as those in the corresponding embodiment above and will not be repeated here.

[0077] See also Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 9 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 9 A processor 10 is taken as an example.

[0078] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0079] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0080] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0081] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0082] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0083] The embodiments of the present application also provide a computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0084] An embodiment of the present application provides a computer program product, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a method according to any embodiment of the present application.

[0085] Exemplary clauses of the scope of protection of the present disclosure are as follows: Clause 1A. A phased array readout electronics platform comprising a time-frequency management unit and at least one signal processing unit; The time-frequency management unit is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each of the signal processing units respectively; The plurality of signal processing units are configured to synchronously analyze the timing control pulse signal according to the clock output signal, and perform coarse channel processing on the radio frequency acquisition signal according to the analysis result, so as to obtain astronomical observation data according to the processing result.

[0086] Item 2A. The platform of Item 1A, wherein the pulse widths of the timing control pulse signals received by each of the signal processing units are equal, and the timing control pulse signals are in phase with each other.

[0087] Item 3A. A platform according to Item 1A, wherein each of the signal processing units includes multiple acquisition channels, and the signal processing unit is further configured to derive a pulse width of the timing control pulse signal based on a period resolution of the clock output signal, so as to perform one of an inter-channel synchronization state trigger operation, a logic reset operation, or a phase acquisition operation on the multiple acquisition channels based on the pulse width.

[0088] Item 4A. A platform according to Item 3A, wherein the signal processing unit is further configured to parse the pulse width of the timing control pulse signal based on the clock output signal, and trigger the inter-channel synchronization state trigger operation when the pulse width meets a first preset condition, so as to perform synchronous coarse channel processing on the RF acquisition signal according to the inter-channel synchronization state trigger operation.

[0089] Item 5A. A platform according to Item 3A, wherein the signal processing unit is further configured to parse the pulse width of the timing control pulse signal based on the clock output signal, and trigger the logic reset operation when the pulse width meets a second preset condition, so as to reset the acquisition channel according to the logic reset operation.

[0090] Item 6A. A platform according to Item 3A, wherein the signal processing unit is further configured to parse the pulse width of the timing control pulse signal based on the clock output signal, and trigger the phase acquisition operation when the pulse width meets a third preset condition, so as to obtain the phase information of the acquisition channel according to the phase acquisition operation, so as to adjust the phase difference between all acquisition channels according to the phase information.

[0091] Clause 7A. The platform of clause 1A, wherein the time and frequency management unit comprises a clock source and a frequency synthesis subunit; The clock source is used to generate a reference clock signal; The frequency synthesis subunit is used to generate multiple clock output signals based on the reference clock signal, wherein the number of the clock output signals is greater than the number of the signal processing units, and the multiple clock output signals are respectively in the same frequency and phase as the reference clock signal.

[0092] Clause 8A. The platform of Clause 7A, wherein the frequency synthesis subunit comprises a first frequency signal distributor and a second frequency signal distributor, wherein inputs of the first frequency signal distributor and the second frequency signal distributor are respectively connected to the clock source, and outputs of the first frequency signal distributor and the second frequency signal distributor are connected to clock inputs of corresponding signal processing units; The first frequency signal distributor and the second frequency signal distributor are used to generate a plurality of the clock output signals according to the reference clock signal, and the plurality of the clock output signals have the same frequency and phase.

[0093] Clause 9A. The platform of clause 7A, wherein the clock source is further configured to generate a trigger signal, and the time-frequency management unit further comprises a timing control subunit; The timing control subunit is suitable for receiving the trigger signal and the clock output signal, and generating the timing control pulse signal according to the system preset control parameters in response to the trigger signal and the clock output signal, wherein the pulse width of the timing control pulse signal matches the system preset control parameters.

[0094] Item 10A. According to the platform described in Item 9A, the timing control subunit includes a programmable logic processor, the programmable logic processor has the system preset control parameters built in, and the first input end of the programmable logic processor is suitable for receiving the clock output signal, the second input end of the programmable logic processor is suitable for receiving the trigger signal, and the output end of the programmable logic processor is connected to the signal processing unit to output the control pulse signal, wherein the output end of the programmable logic processor corresponds one-to-one to the signal processing unit.

[0095] Clause 11A. According to the platform described in Clause 9A, the timing control subunit also includes a status manager, which is configured to periodically obtain the unit status information of each signal processing unit and upload it to the host computer for display. At the same time, the status manager is also configured to collect channel phase information of each signal processing unit, and calculate the channel phase information to obtain channel phase adjustment information between each signal processing unit, and distribute the channel phase adjustment information to each signal processing unit to achieve synchronization.

[0096] In the above clauses, the time-frequency management unit can use an IO port to time-share one of the channel synchronization status trigger operations, logic reset operations or phase acquisition operations, which not only realizes port multiplexing and saves a lot of external cables and hardware circuit design, but also ensures that the multiple acquisition channel states of multiple information processing units remain synchronized, so that each signal processing unit can synchronously analyze the timing control pulse signal based on a unified clock output signal. Compared with related technologies, it not only improves the integration of the digital receiving module, but also ensures the synchronization of the coarse channel processing of the RF acquisition signal by each signal processing unit, so that the back-end readout module can work normally, greatly improving the accuracy of astronomical observation data.

[0097] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

[0098] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0099] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are generally similar to the apparatus embodiments, so their description is relatively simple. For relevant portions, refer to the description of the method embodiments.

[0100] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

[0101] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A phased array readout electronics platform, characterized in that: The platform includes: A radio frequency acquisition module, wherein the radio frequency acquisition module is configured to acquire spatial electromagnetic waves and convert the spatial electromagnetic waves into radio frequency acquisition signals; a digital receiving module adapted to receive the RF acquisition signal, and comprising a time-frequency management unit and at least one signal processing unit, wherein the time-frequency management unit is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each of the signal processing units, respectively, so that each of the signal processing units synchronously analyzes the timing control pulse signal according to the clock output signal, and performs coarse channel processing and framing on the RF acquisition signal according to the analysis result, thereby obtaining multiple channel signals; A back-end readout module is configured to generate astronomical observation data according to the channel signal.

2. The phased array readout electronics platform according to claim 1, characterized in that: The time-frequency management unit includes a clock source and a frequency synthesis subunit; Wherein, the clock source is used to generate a reference clock signal; The frequency synthesis subunit is used to generate multiple clock output signals based on the reference clock signal, wherein the number of the clock output signals is greater than the number of the signal processing units, and the multiple clock output signals are respectively in the same frequency and phase as the reference clock signal.

3. The phased array readout electronics platform according to claim 2, characterized in that: The frequency synthesis subunit includes a first frequency signal distributor and a second frequency signal distributor, wherein the input ends of the first frequency signal distributor and the second frequency signal distributor are respectively connected to the clock source, and the output ends of the first frequency signal distributor and the second frequency signal distributor are connected to the clock input end of the corresponding signal processing unit; The first frequency signal distributor and the second frequency signal distributor are used to generate a plurality of the clock output signals according to the reference clock signal.

4. The phased array readout electronics platform according to claim 2, characterized in that: The clock source is further used to generate a trigger signal, and the time-frequency management unit further includes a timing control subunit; The timing control subunit is suitable for receiving the trigger signal and the clock output signal, and generating the timing control pulse signal according to the system preset control parameters in response to the trigger signal and the clock output signal, wherein the pulse width of the timing control pulse signal matches the system preset control parameters.

5. The phased array readout electronics platform according to claim 4, characterized in that: The timing control subunit includes a programmable logic processor; The first input end of the programmable logic processor is suitable for receiving the clock output signal, the second input end of the programmable logic processor is suitable for receiving the trigger signal, and the output end of the programmable logic processor is connected to the corresponding signal processing unit to output the timing control pulse signal, wherein the output end of the programmable logic processor corresponds one-to-one to the signal processing unit.

6. The phased array readout electronics platform according to claim 1, characterized in that: The signal processing unit is configured to analyze the pulse width of the timing control pulse signal according to the clock output signal, and perform synchronous coarse channel processing on the radio frequency acquisition signal when the pulse width meets a preset condition.

7. The phased array readout electronics platform according to claim 6, characterized in that: The signal processing unit is an integrated chip based on RFSoC, which includes an analog-to-digital conversion subunit. The analog-to-digital conversion subunit is configured to perform analog-to-digital conversion on the RF acquisition signal in response to the clock output signal and the timing control pulse signal, and obtain the converted digital acquisition signal to perform the coarse channel processing on the digital acquisition signal.

8. The phased array readout electronics platform according to claim 7, characterized in that: The integrated chip also includes a demodulation subunit, a filtering subunit and a framing subunit; The demodulation subunit is configured to perform orthogonal demodulation on the digital acquisition signal and obtain a demodulated initial baseband signal; The filtering subunit is configured to perform a double decimation filter on the initial baseband signal to obtain a target baseband signal, and perform synchronous coarse channel processing on the target baseband signal through polyphase filtering and fast Fourier transform to obtain multiple subchannel signals; The framing subunit is configured to frame the sub-channel signals according to the computing capability of the back-end readout module to obtain the channel signal, and transmit the channel signal to the back-end readout module through the UDP protocol.

9. The phased array readout electronics platform according to any one of claims 1 to 8, characterized in that: The radio frequency acquisition module includes an antenna array unit and a radio frequency front-end unit; The antenna array unit includes a plurality of mutually independent antennas, and the plurality of antennas are arranged in a planar array to collect the spatial electromagnetic waves; The RF front-end unit is configured to sequentially perform low-noise amplification processing, analog filtering processing, and gain amplification processing on the spatial electromagnetic wave, so that the amplitude of the RF acquisition signal obtained after processing is within a preset range.

10. A phased array readout electronics method, characterized in that: Applicable to the platform according to any one of claims 1 to 9.

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