Preparation method of semiconductor device
By defining a photoresist layer and forming a lightly doped region in the polysilicon pattern area, combined with APF and DARC layers, the problem of uneven etching selectivity is solved and the production yield of SRAM devices is improved.
Patent Information
- Application Number
- CN202510884819.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-28
- Publication Date
- 2025-10-10
AI Technical Summary
In the preparation of semiconductor devices, especially SRAM devices, a thick silicon nitride layer used as an ion implantation barrier leads to uneven etching selectivity, affecting device electrical properties and causing a decrease in production yield.
A photoresist layer is defined in the polysilicon graphic area and a first lightly doped region is formed. After removing the photoresist layer, a polysilicon layer, an APF layer, and a DARC layer are formed, avoiding the use of a silicon nitride layer as a barrier layer. APF and DARC layers are introduced on the polysilicon layer to optimize the film layer combination and improve etching selectivity and uniformity.
The production yield of devices has been improved, the electrical mismatch problem has been reduced, and the production yield of SRAM devices has been increased by about 15%.
Smart Images
Figure CN120769495A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art
[0002] At present, in the preparation of semiconductor devices, especially in the preparation of SRAM (static random access memory) with an operating voltage of 6V to 10V, a polysilicon layer is generally deposited on a substrate, and then a silicon oxide layer and a silicon nitride layer are formed on the polysilicon layer in sequence. The silicon nitride layer serves as a barrier layer for the subsequent ion implantation process. The thickness of the silicon nitride layer is relatively thick, about Then, the polysilicon layer is etched. After the polysilicon layer is etched, ion implantation is performed on the substrate on both sides of the patterned polysilicon layer to form lightly doped regions. The lightly doped regions extend below the edge of the patterned polysilicon layer. When performing ion implantation to form the lightly doped regions, the ion implantation energy is relatively high. To prevent penetration of the patterned polysilicon layer, the silicon nitride layer serves as a barrier during the ion implantation process. However, a thicker silicon nitride layer increases the etch selectivity of the polysilicon layer, making it difficult to control the etching process of the polysilicon layer and prone to problems such as uneven etching. This can lead to electrical mismatch in the SRAM device, affecting the production yield of the SRAM device. Summary of the Invention
[0003] The object of the present invention is to provide a method for preparing a semiconductor device, thereby improving the production yield of the device.
[0004] In order to achieve the above object, the present invention provides a method for preparing a semiconductor device, comprising:
[0005] Providing a substrate, and defining a polysilicon pattern area on the substrate;
[0006] A patterned photoresist layer is formed on the substrate, wherein a projection of the patterned photoresist layer on the substrate is located within the polysilicon pattern region, and a distance is provided between an edge of the patterned photoresist layer and an edge of the polysilicon pattern region along a first direction;
[0007] Using the patterned photoresist layer as a mask, performing an ion implantation process on the substrate to form a first lightly doped region;
[0008] removing the patterned photoresist layer, and sequentially forming a polysilicon layer, an APF layer, and a DARC layer on the substrate; and
[0009] The polysilicon layer is patterned to form a patterned polysilicon layer, wherein a projection of the patterned polysilicon layer on the substrate coincides with the polysilicon pattern region, and the first lightly doped region extends below an edge of the patterned polysilicon layer.
[0010] Optionally, along the first direction, there is a distance between two edges of the patterned photoresist layer and an edge of the polysilicon pattern area.
[0011] Optionally, along the first direction, the distances between two edges of the patterned photoresist layer and the edge of the polysilicon pattern area are the same.
[0012] Optionally, a distance between an edge of the patterned photoresist layer and an edge of the polysilicon pattern region along the first direction is 0.02 μm to 0.05 μm.
[0013] Optionally, the thickness of the APF layer is The thickness of the DARC layer is
[0014] Optionally, an oxide layer is formed between the polysilicon layer and the APF layer.
[0015] Optionally, the thickness of the oxide layer is
[0016] Optionally, before forming the patterned photoresist layer, the method further includes performing ion implantation on the substrate to form a second lightly doped region.
[0017] Optionally, the first lightly doped region and the second lightly doped region have different doping types.
[0018] Optionally, the operating voltage of the semiconductor device is 6V to 10V.
[0019] The method for preparing a semiconductor device provided by the present invention includes: providing a substrate, defining a polysilicon pattern area on the substrate; forming a patterned photoresist layer on the substrate, wherein the projection of the patterned photoresist layer on the substrate is located in the polysilicon pattern area, and an edge of the patterned photoresist layer along a first direction is spaced apart from an edge of the polysilicon pattern area; using the patterned photoresist layer as a mask, performing an ion implantation process on the substrate to form a first lightly doped region; removing the patterned photoresist layer, and sequentially forming a polysilicon layer, an APF layer, and a DARC layer on the substrate; and patterning the polysilicon layer to form a patterned polysilicon layer, wherein the projection of the patterned polysilicon layer on the substrate coincides with the polysilicon pattern area, and the first lightly doped region extends below the edge of the patterned polysilicon layer. The present invention defines a polysilicon graphic area before forming a polysilicon layer, and forms a patterned photoresist layer in the polysilicon graphic area to form a first lightly doped area. After the polysilicon layer is formed, there is no need to form a silicon nitride layer thereon as a barrier layer for ion implantation. At the same time, an APF layer and a DARC layer are introduced on the polysilicon layer to optimize the film layer combination of the process, improve the etching selectivity and uniformity during the patterning of the polysilicon layer, and thus improve the production yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 The present invention provides a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0021] Figure 2 A top view of a polysilicon pattern region defined in a method for manufacturing a semiconductor device provided in one embodiment of the present invention.
[0022] Figure 3 for Figure 2 Schematic cross-section diagram along section line A1A2.
[0023] Figure 4 A top view of a patterned photoresist layer formed in a method for manufacturing a semiconductor device provided by one embodiment of the present invention.
[0024] Figure 5 for Figure 4 Schematic cross-section diagram along section line A1A2.
[0025] Figure 6 A top view of a first lightly doped region formed in a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
[0026] Figure 7 for Figure 6 Schematic cross-section diagram along section line A1A2.
[0027] Figure 8 A top view of a polysilicon layer, an APF layer, and a DARC layer formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0028] Figure 9 for Figure 8 Schematic cross-section diagram along section line A1A2.
[0029] Figure 10 A top view of a patterned polysilicon layer formed in a method for manufacturing a semiconductor device provided in one embodiment of the present invention.
[0030] Figure 11 for Figure 10 Schematic cross-section diagram along section line A1A2.
[0031] Wherein, the accompanying drawings are marked as follows:
[0032] 10 - substrate; 20 - polysilicon patterned region; 30 - patterned photoresist layer; 40 - first lightly doped region; 50 - polysilicon layer; 52 - patterned polysilicon layer; 60 - oxide layer; 70 - APF layer; 80 - DARC layer. DETAILED DESCRIPTION
[0033] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0034] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0035] Figure 1 This is a flow chart of a method for manufacturing a semiconductor device provided in this embodiment. This embodiment provides a method for manufacturing a semiconductor device, comprising:
[0036] Step S1: providing a substrate and defining a polysilicon pattern area on the substrate;
[0037] Step S2: forming a patterned photoresist layer on the substrate, wherein a projection of the patterned photoresist layer on the substrate is located within the polysilicon pattern region, and an edge of the patterned photoresist layer along a first direction is spaced from an edge of the polysilicon pattern region;
[0038] Step S3: using the patterned photoresist layer as a mask, performing an ion implantation process on the substrate to form a first lightly doped region;
[0039] Step S4: removing the patterned photoresist layer, and sequentially forming a polysilicon layer, an APF layer, and a DARC layer on the substrate;
[0040] Step S5: patterning the polysilicon layer to form a patterned polysilicon layer, wherein a projection of the patterned polysilicon layer on the substrate coincides with the polysilicon pattern region, and the first lightly doped region extends below an edge of the patterned polysilicon layer.
[0041] Figure 2 This is a top view of a polysilicon pattern region defined in the method for manufacturing a semiconductor device provided in this embodiment. Figure 3 for Figure 2 Schematic cross-section diagram along section line A1A2.Figure 4 A plan view of forming a patterned photoresist layer in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 5 A plan view of Figure 4 A cross-sectional view along the cross-sectional line A1A2 in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 6 A plan view of forming a first lightly doped region in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 7 A plan view of Figure 6 A cross-sectional view along the cross-sectional line A1A2 in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 8 A plan view of forming a polysilicon layer, an APF layer and a DARC layer in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 9 A plan view of Figure 8 A cross-sectional view along the cross-sectional line A1A2 in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 10 A plan view of forming a patterned polysilicon layer in the method of manufacturing a semiconductor device provided in the present embodiment. Figure 11 A plan view of Figure 10 A cross-sectional view along the cross-sectional line A1A2 in the method of manufacturing a semiconductor device provided in the present embodiment. Wherein the following Figures 2-11 The method of manufacturing a semiconductor device provided in the present embodiment is described in detail.
[0042] Please refer to Figure 2 and Figure 3 , execute step S1: providing a substrate 10, wherein the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, not limited thereto. A polysilicon pattern region 20 is defined on the substrate 10 (as shown in the dashed box in the figure, the figure only simply illustrates the purpose of the present application, and does not illustrate the complete device structure, Figure 2 the dashed line and double arrow in the figure represent the lateral dimension of the polysilicon pattern region 20), and a patterned polysilicon layer is subsequently formed in the polysilicon pattern region 20. In the present embodiment, after providing the substrate 10, ion implantation can be performed on the substrate 10 to form a second lightly doped region (not shown in the figure). Figure 3 Please refer to
[0043] and Figure 4 , execute step S2: forming a patterned photoresist layer 30 on the substrate 10, and the projection of the patterned photoresist layer 30 on the substrate 10 is located within the polysilicon pattern region 20 (as shown in the dashed box in the figure, the figure only simply illustrates the purpose of the present application, and does not illustrate the complete device structure, Figure 5 Figure 4 As shown in FIG, the projection of the patterned photoresist layer 30 on the substrate 10 does not overlap with the polysilicon patterned region 20. A spacing S is defined between the edge of the patterned photoresist layer 30 along the first direction D1 and the edge of the polysilicon patterned region 20. Specifically, both edges of the patterned photoresist layer 30 along the first direction D1 and the edge of the polysilicon patterned region 20 have a spacing S, and preferably, both edges of the patterned photoresist layer 30 along the first direction D1 have the same spacing S as the edge of the polysilicon patterned region 20. The spacing S between the edge of the patterned photoresist layer 30 along the first direction D1 and the edge of the polysilicon patterned region 20 is preferably 0.02 μm to 0.05 μm. The spacing S between the edge of the patterned photoresist layer 30 along the first direction D1 and the edge of the polysilicon patterned region 20 is determined based on actual electrical parameters and is not limited thereto. Furthermore, in this embodiment, the edge of the patterned photoresist layer 30 along the second direction D2 overlaps with the edge of the polysilicon patterned region 20, but this is not limiting and may also not overlap.
[0044] Please refer to Figure 6 and Figure 7 , executing step S3: using the patterned photoresist layer 30 as a mask, performing an ion implantation process on the substrate 10 to form first lightly doped regions 41. After the ion implantation, the first lightly doped regions 41 are located in the substrate 10 on both sides of the patterned photoresist layer 30. From a top view, the edges of the first lightly doped regions 41 coincide with the edges of the patterned photoresist layer 30. In practice, the implantation process may cause the first lightly doped regions 41 to extend slightly below the edges of the patterned photoresist layer 30. The first lightly doped regions 41 and the second lightly doped regions have different doping types: one is P-type doped and the other is N-type doped.
[0045] Please refer to Figure 8 and Figure 9 , executing step S4: first removing the patterned photoresist layer; then, sequentially forming a polysilicon layer 50, an APF (Advanced Patterning Film) layer 70, and a DARC (Dielectric Anti-reflective Coating) layer 80 on the substrate 10, Figure 8 The top view shows only the top layer (DARC layer 80). An oxide layer 60 is formed between the polysilicon layer 50 and the APF layer 70. In this embodiment, the thickness of the oxide layer 60 can be The thickness of the APF layer 70 may be The thickness of the DARC layer 80 may be After the polysilicon layer 70 is formed, since the first lightly doped region 41 has already been formed, there is no need to form a silicon nitride layer on the polysilicon layer 70 as a barrier layer for ion implantation. At the same time, the APF layer 70 and the DARC layer 80 are introduced on the polysilicon layer 50, thereby optimizing the film layer combination of the process.
[0046] Please refer to Figure 10 and Figure 11 , executing step S5: patterning the polysilicon layer 50 to form a patterned polysilicon layer 52, the projection of the patterned polysilicon layer 52 on the substrate 10 coincides with the polysilicon pattern area 20 (eg Figure 10 All edges of the patterned polysilicon layer 52 overlap), and the first lightly doped region 41 extends below the edge of the patterned polysilicon layer 52 ( Figure 10 The oxide layer 60 on the patterned polysilicon layer 52 is not shown in the figure, and the patterned polysilicon layer 52 is set to be transparent to clearly indicate that the first lightly doped region 41 extends to below the edge of the patterned polysilicon layer 52). After patterning, the APF layer 70 and the DARC layer 80 are removed synchronously, and the oxide layer 60 on the patterned polysilicon layer 52 is retained. Furthermore, after the patterned polysilicon layer 52 is formed, a sidewall structure (not shown in the figure) can be formed on the sidewall of the patterned polysilicon layer 52. Since the APF layer 70 and the DARC layer 80 are introduced on the polysilicon layer 50, the etching selectivity and uniformity during the patterning of the polysilicon layer 50 can be improved, thereby improving the production yield of the device.
[0047] In this embodiment, the semiconductor device is preferably an SRAM device, and its operating voltage can range from 6V to 10V, making it a medium-voltage semiconductor device. Experimental comparisons have shown that, after optimizing the film layer combination, device failures caused by electrical mismatch in a medium-voltage 8V SRAM device, for example, are significantly reduced by approximately 15%, significantly improving device production yield.
[0048] In summary, the preparation method of the semiconductor device provided by the present invention includes: providing a substrate, defining a polysilicon graphic area on the substrate; forming a patterned photoresist layer on the substrate, and the projection of the patterned photoresist layer on the substrate is located in the polysilicon graphic area, and the edge of the patterned photoresist layer along the first direction is spaced from the edge of the polysilicon graphic area; using the patterned photoresist layer as a mask, performing an ion implantation process on the substrate to form a first lightly doped area; removing the patterned photoresist layer, and sequentially forming a polysilicon layer, an APF layer and a DARC layer on the substrate; and patterning the polysilicon layer to form a patterned polysilicon layer, the projection of the patterned polysilicon layer on the substrate coincides with the polysilicon graphic area, and the first lightly doped area extends below the edge of the patterned polysilicon layer. The present invention defines a polysilicon graphic area before forming a polysilicon layer, and forms a patterned photoresist layer in the polysilicon graphic area to form a first lightly doped area. After the polysilicon layer is formed, there is no need to form a silicon nitride layer thereon as a barrier layer for ion implantation. At the same time, an APF layer and a DARC layer are introduced on the polysilicon layer to optimize the film layer combination of the process, improve the etching selectivity and uniformity during the patterning of the polysilicon layer, and thus improve the production yield of the device.
[0049] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, and defining a polysilicon pattern area on the substrate; A patterned photoresist layer is formed on the substrate, wherein a projection of the patterned photoresist layer on the substrate is located within the polysilicon pattern region, and a distance is provided between an edge of the patterned photoresist layer and an edge of the polysilicon pattern region along a first direction; Using the patterned photoresist layer as a mask, performing an ion implantation process on the substrate to form a first lightly doped region; removing the patterned photoresist layer, and sequentially forming a polysilicon layer, an APF layer, and a DARC layer on the substrate; and The polysilicon layer is patterned to form a patterned polysilicon layer, wherein a projection of the patterned polysilicon layer on the substrate coincides with the polysilicon pattern region, and the first lightly doped region extends below an edge of the patterned polysilicon layer.
2. The method for preparing a semiconductor device according to claim 1, wherein: Along the first direction, there is a distance between two edges of the patterned photoresist layer and an edge of the polysilicon pattern area.
3. The method for preparing a semiconductor device according to claim 2, wherein: The distances between two edges of the patterned photoresist layer and the edge of the polysilicon pattern area along the first direction are the same.
4. The method for preparing a semiconductor device according to claim 1, wherein: The distance between the edge of the patterned photoresist layer and the edge of the polysilicon pattern area along the first direction is 0.02 μm to 0.05 μm.
5. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the APF layer is The thickness of the DARC layer is 6. The method for preparing a semiconductor device according to claim 1, wherein: An oxide layer is formed between the polysilicon layer and the APF layer.
7. The method for preparing a semiconductor device according to claim 6, wherein: The thickness of the oxide layer is 8. The method for preparing a semiconductor device according to claim 1, wherein: Before forming the patterned photoresist layer, the method further includes performing ion implantation on the substrate to form a second lightly doped region.
9. The method for preparing a semiconductor device according to claim 8, wherein: The first lightly doped region and the second lightly doped region have different doping types.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The operating voltage of the semiconductor device is 6V to 10V.