Chip structure, semiconductor structure and memory

Abstract

The invention provides a chip structure, a semiconductor structure and a memory, and relates to the technical field of semiconductors. The chip structure comprises a CA signal transmission module which comprises M bonding pads, the M bonding pads comprise N first bonding pads and T second bonding pads, and the first bonding pads are used for transmitting CA signals; the CA signal transmission module is provided with a central position, and the number of the bonding pads located on the two sides of the central position is the same; when N is 1, the first bonding pad is located at the central position; when N is larger than 1, the number of the first bonding pads located on the two sides of the center position is the same, and the first bonding pads located on the two sides of the center position are symmetrically arranged with respect to the center position. According to the chip structure provided by the invention, the wiring consistency of the rewiring layer can be improved during flip packaging, and the integrity of CA signal transmission is ensured.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a chip structure, a semiconductor structure and a memory. BACKGROUND

[0002] In the development of integrated circuit technology, whether it is the iteration of manufacturing process or the progress of circuit design, the goal of miniaturization is pursued while performance is continuously improved. As one of the important applications of integrated circuits, memory is also constantly pursuing performance improvement and smaller size.

[0003] In order to achieve the goal of miniaturization while continuously improving performance, a packaging method of layer stack packaging is usually used to manufacture the memory, and the chip structure located at the top layer when using layer stack packaging needs to be flip-chip connected. However, the CA signal transmission module in the current chip structure will have the problem of poor consistency of the traces of the rewiring layer and poor integrity of the CA signal transmission after flip-chip connection. SUMMARY

[0004] The purpose of the present disclosure is to provide a chip structure, a semiconductor structure and a memory, thereby at least partially overcoming the problem that the CA signal transmission module in the chip structure will have poor consistency of the traces of the rewiring layer and poor integrity of the CA signal transmission after flip-chip connection.

[0005] According to a first aspect of the present disclosure, a chip structure is provided, comprising: a CA signal transmission module, comprising M pads, wherein the M pads comprise N first pads and T second pads, and the first pads are used for transmitting CA signals; the CA signal transmission module has a center position, and the number of pads located on both sides of the center position is the same; when N is 1, the first pad is located at the center position; when N is greater than 1, the number of first pads located on both sides of the center position is the same, and the first pads located on both sides of the center position are symmetrically arranged with respect to the center position.

[0006] Optionally, when M and N are both odd numbers, and N is greater than 1, N first pads comprise one first center pad and N-1 first edge pads, the first center pad is located at the center position, and the N-1 first edge pads are symmetrically arranged with respect to the first center pad.

[0007] Optionally, when M is an odd number, N is an even number, and N is greater than 1, N first pads are symmetrically arranged with respect to the center position.

[0008] Optionally, the T second pads include a second central pad, and the second central pad is located at the center position, and the N first pads are symmetrically arranged around the second central pad.

[0009] Optionally, the second center pad is any one of a clock signal pad, a first power supply pad, and a chip select signal pad.

[0010] Optionally, when M and N are both even numbers and N is greater than 1, the N first pads include two third center pads and N-2 third edge pads, the two third center pads are adjacent to each other and are respectively located on both sides of the center position, and the N-2 third edge pads are symmetrically arranged around the center position.

[0011] Optionally, when M and N are even numbers and N is greater than 1, the T second pads include two fourth center pads, the two fourth center pads are adjacent to each other and are respectively located on both sides of the center position, and the N first pads are symmetrically arranged around the center position.

[0012] Optionally, when N is greater than 1, the M pads include multiple pad groups, and the pad group includes at most two adjacent first pads; the T second pads include a first power pad, and at least one first power pad is arranged between any two adjacent pad groups.

[0013] Optionally, T second pads include multiple first power pads, the multiple first power pads include at least two first power pads and at least two first ground pads, at least two of the first power pads are symmetrically arranged about the center position, and at least two of the first ground pads are symmetrically arranged about the center position.

[0014] Optionally, any two of the first power supply pads are separately provided, and any two of the first ground pads are separately provided.

[0015] Optionally, the chip structure further comprises: a peripheral transmission module, comprising an edge transmission pad, wherein the edge transmission pad is disposed adjacent to the CA signal transmission module;

[0016] At least two of the first power supply pads include a first edge power supply pad, the first edge power supply pad is located at the edge of the CA signal transmission module and is adjacent to the edge transmission pad, and the first edge power supply pad and the edge transmission pad transmit different types of signals; and / or, at least two of the first grounding pads include a first edge grounding pad, the first edge grounding pad is located at the edge of the CA signal transmission module and is adjacent to the edge transmission pad, and the first edge grounding pad and the edge transmission pad transmit different types of signals.

[0017] Optionally, the T second pads include at least two chip select signal pads, and one of the chip select signal pads is multiplexed as a redundant pad.

[0018] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a first chip structure; a second chip structure, which is a chip structure as described in any one of the above items, and the first chip structure and the second chip structure are the same; wherein, either the first chip structure or the second chip structure is a flip chip, and the pads in the first chip structure and the second chip structure are correspondingly connected.

[0019] According to a third aspect of the present disclosure, a memory is provided, comprising the semiconductor structure as described above.

[0020] In the technical solutions provided by some embodiments of the present disclosure, the CA signal transmission module includes M pads, the M pads include N first pads and T second pads, and the first pads are used to transmit CA signals.

[0021] When N is 1, the first pad is located at the center. After the chip structure is flipped, the first pad remains at the center. This allows the first pad of the flipped chip structure to be located at the same position as the first pad of the unflipped chip structure when the two chip structures are flipped together. This allows them to be directly connected using the redistribution layer in the unflipped chip structure, effectively shortening the length of the wiring connecting the redistribution layer to the first pad in the unflipped chip structure, improving the consistency of the redistribution layer wiring in the unflipped chip structure, and helping to improve the CA signal transmission rate and integrity.

[0022] When N is greater than 1, the number of first pads on both sides of the center position is the same, and the first pads on both sides of the center position are symmetrically arranged about the center position. In this case, after the chip structure is flipped, the first pads on both sides of the center position will still be symmetrically arranged about the center position, and the positions of the first pads of the flipped chip structure and the positions of the first pads of the unflipped chip structure will remain the same. Therefore, when the chip structure is flipped, the first pads can be directly connected using the redistribution layer in the unflipped chip structure, effectively shortening the length of the wiring connecting the first pads in the redistribution layer in the unflipped chip structure, improving the consistency of the redistribution layer wiring in the unflipped chip structure, and helping to improve the CA signal transmission rate and integrity.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0025] Figure 1 A schematic diagram showing a semiconductor structure of the related art.

[0026] Figure 2 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0027] Figure 3 A schematic diagram of a CA signal transmission module according to an embodiment of the present disclosure is shown.

[0028] Figure 4 A schematic diagram showing partial connections of a CA signal transmission module when the chip structure is flipped in an embodiment of the present disclosure is shown.

[0029] Figure 5 A schematic diagram of a CA signal transmission module according to another embodiment of the present disclosure is shown.

[0030] Figure 6 A schematic diagram showing partial connections of a CA signal transmission module when the chip structure is flipped in accordance with another embodiment of the present disclosure is shown.

[0031] Figure 7 A schematic diagram of a CA signal transmission module according to another embodiment of the present disclosure is shown.

[0032] Figure 8 A schematic diagram showing partial connections of a CA signal transmission module when the chip structure is flipped according to another embodiment of the present disclosure is shown.

[0033] Figure 9 A schematic diagram of a CA signal transmission module according to another embodiment of the present disclosure is shown.

[0034] Figure 10 A schematic diagram showing partial connections of a CA signal transmission module when the chip structure is flipped in accordance with another embodiment of the present disclosure is shown.

[0035] Figure 11 A schematic diagram of a CA signal transmission module according to another embodiment of the present disclosure is shown.

[0036] Figure 12 A schematic diagram showing partial connections of a CA signal transmission module when the chip structure is flipped in accordance with another embodiment of the present disclosure is shown.

[0037] Figure 13 A circuit diagram of a flip-chip connection of a chip structure in the related art is shown.

[0038] Figure 14 A circuit diagram of a flip-chip connection of a chip structure according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The described features, circuit structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other components, devices, components, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0041] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] It should be pointed out that the terms "first\second\third" etc. involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" etc. can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] A memory is an electronic device used to store data. The memory involved in the present disclosure includes but is not limited to DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), PCRAM (Phase Change Random Access Memory), NAND (NAND flash memory), NOR (NOR flash memory), etc. For example, the memory can be LPDDR4 memory or LPDDR5 memory.

[0044] refer to Figures 1 to 3 In order to achieve the goal of miniaturization while continuously improving performance, a stacked package method is usually used to manufacture memories. Stacked package refers to stacking multiple chip structures 1 in sequence, and connecting each chip structure 1 except the chip structure 1 on the top layer to the package substrate 2. For example, the memory may include four stacked chip structures 1, and the four chip structures 1 may include a first chip 11, a second chip 12, a third chip 13 and a fourth chip 14. The second chip 12, the third chip 13 and the fourth chip 14 may be connected to the package substrate 2 by wire bonding or the like. In addition, an adhesive layer 15 may be provided between the second chip 12 and the third chip 13, between the third chip 13 and the fourth chip 14, and between the fourth chip and the package substrate 2, so as to bond the second chip 12, the third chip 13, the fourth chip 14 and the package substrate 2 using the adhesive layer 15. The material of the adhesive layer 15 may be DAF glue, but is not limited thereto.

[0045] In stacked packaging, the chip structure 1 on the top layer can be the first chip 11, and the adjacent chip structure 1 can be the second chip 12. The first chip 11 and the second chip 12 can be flip-chip connected. A redistribution layer can be designed on the second chip 12. During flip-chip connection, one end of the redistribution layer on the second chip 12 is connected to the connection terminal 30 on the first chip 11, and the other end of the redistribution layer on the second chip 12 is connected to the pad 31 on the second chip 12, so that the first chip 11 and the second chip 12 are flip-chip connected. The connection terminal 30 can include connection structures such as a connection bump and a pad 31.

[0046] The first chip 11 may also be provided with a rewiring layer, one end of the rewiring layer on the first chip 11 may be connected to the pad 31 on the first chip 11, and the other end of the rewiring layer on the first chip 11 may be provided with a connection bump for connecting to the rewiring layer on the second chip 12.

[0047] For example, the CA signal transmission module 3 in the first chip 11 needs to be flip-chip connected to the CA signal transmission module 3 in the second chip 12. Specifically, the pads for transmitting CA signals in the CA signal transmission module 3 of the first chip 11 need to be connected to the pads for transmitting CA signals in the CA signal transmission module 3 of the second chip 12 through a redistribution layer on the second chip 12. Furthermore, the pads for transmitting power signals in the CA signal transmission module 3 of the first chip 11 need to be connected to the pads for transmitting power signals in the CA signal transmission module 3 of the second chip 12 through a redistribution layer on the second chip 12.

[0048] However, the location of the pads 31 of the first chip 11 after flipping is significantly different from the location of the corresponding pads 31 in the second chip 12 that has not flipped. This results in the corresponding pads 31 being unable to be directly connected to the rewiring layer on the second chip 12 when the flipped first chip 11 is connected to the second chip 12 that has not flipped. This causes the first chip 11 to have poor routing consistency and poor integrity of signal transmission on the rewiring layer on the second chip 12 after flipping. For example, when the first chip 11 and the second chip 12 are flipped, there is a significant distance between the pads for transmitting CA signals in the first chip 11 and the pads for transmitting CA signals in the second chip 12. This results in the pads for transmitting CA signals requiring longer routing when connected through the rewiring layer on the second chip 12, which results in poor routing consistency and poor integrity of CA signal transmission on the rewiring layer on the second chip 12.

[0049] To further solve the above problems, the present disclosure further provides a new chip structure 1. The chip structure 1 may include a CA signal transmission module 3 for transmitting CA signals. It should be noted that the chip structure 1 of the embodiment of the present disclosure can be applied to various memories.

[0050] refer to Figures 3 to 12The CA signal transmission module 3 of the embodiment of the present disclosure may include M pads 31, wherein the M pads 31 may include N first pads 311 and T second pads 312, where M, N, and T may all be positive integers. The first pad 311 may be used to transmit a CA signal, i.e., the first pad 311 may be a CA pad 31. The second pad 312 may be used to transmit other signals, for example, the second pad 312 may include multiple first power pads 313, which may include a first power supply pad 314 (VDD) and a first ground pad 315 (VSS). The second pad 312 may also include a clock signal pad, which may include a clock signal pad (CKC) in normal operation mode and a clock signal pad (CKT) in test mode. However, the present invention is not limited thereto, and the second pad 312 may also include pads for transmitting other signals, which may be selected and set according to actual conditions.

[0051] The CA signal transmission module 3 may have a center position, and the number of pads 31 on either side of the center position may be the same. It should be noted that the center position referred to herein may also be the geometric center of the CA signal transmission module 3, that is, the number of pads 31 on either side of the center position is the same, and the CA signal transmission modules 3 on either side of the center position have the same size.

[0052] The CA signal transmission module may have only one first pad 311 (i.e., N is 1), and one first pad 311 can be used to transmit one CA signal. Alternatively, the CA signal transmission module may have multiple first pads 311 (i.e., N is greater than 1), and multiple first pads 311 can implement multiplexing, respectively used to transmit different CA signals.

[0053] When the CA signal transmission module has only one first pad 311, that is, when N is 1, the first pad 311 is located at the center. For example, when the CA signal transmission module includes 19 pads 31, the first pad 311 may be the 10th pad 31; when the CA signal transmission module includes 20 pads 31, the first pad 311 may be the 10th pad 31 or the 11th pad 31.

[0054] Based on this, when N is 1, the first pad 311 of the chip structure 1 will remain in the center after flipping. For example, when the CA signal transmission module includes 19 pads 31 and the first pad 311 is the 10th pad 31, after flipping the chip structure 1, this first pad 311 will still be the 10th pad 31. When the CA signal transmission module includes 20 pads 31 and the first pad 311 is the 10th or 11th pad 31, after flipping the chip structure 1, this first pad 311 will still be the 10th or 11th pad 31. Thus, when the two chip structures 1 are flip-chip connected, the position of the first solder pad 311 of the flipped chip structure 1 (for example, the first chip 11) is the same as the position of the first solder pad 311 of the non-flipped chip structure 1 (for example, the second chip 12), so that they can be directly connected using the redistribution layer in the non-flipped chip structure 1 (for example, the second chip 12), effectively shortening the routing length of the redistribution layer connecting the first solder pad 311 of the non-flipped chip structure 1 (for example, the second chip 12), improving the consistency of the redistribution layer routing of the non-flipped chip structure 1 (for example, the second chip 12), and helping to improve the CA signal transmission rate and integrity.

[0055] The CA signal transmission module includes multiple first pads 311. Specifically, when N is greater than 1, the number of first pads 311 on either side of the center is the same, and the first pads 311 on either side of the center are symmetrically arranged about the center. For example, when the CA signal transmission module includes 19 pads 31 and there are 7 first pads 311, the number of first pads 311 on either side of the center can be 3, and another first pad 311 can be located at the center. The first pads 311 on either side of the center can be the 5th pad 31, the 7th pad 31, the 8th pad 31, the 12th pad 31, the 13th pad 31, and the 15th pad 31, respectively. The 5th pad 31 and the 15th pad 31 are symmetrical about the center, the 7th pad 31 and the 13th pad 31 are symmetrical about the center, and the 8th pad 31 and the 12th pad 31 are symmetrical about the center. It should be noted that each first pad 311 can be universal, that is, the type of CA signal that each first pad 311 can transmit is not limited, and each first pad 311 can be used to transmit different types of CA signals.

[0056] Based on this, when N is greater than 1, after the chip structure 1 is flipped, the first pads 311 located on both sides of the center position will still be symmetrically arranged about the center position. For example: the 5th pad 31 before flipping becomes the 15th pad 31 after flipping, the 15th pad 31 before flipping becomes the 5th pad 31 after flipping, the 7th pad 31 before flipping becomes the 13th pad 31 after flipping, the 13th pad 31 before flipping becomes the 7th pad 31 after flipping, the 8th pad 31 before flipping becomes the 12th pad 31 after flipping, and the 12th pad 31 before flipping becomes the 8th pad 31 after flipping. At this time, after the chip is flipped, the multiple first pads 311 are still located at the 5th pad 31, the 7th pad 31, the 8th pad 31, the 12th pad 31, the 13th pad 31 and the 15th pad 31, and the positions of the multiple first pads 311 in the CA signal module have not changed.

[0057] In this way, the positions of the first pads 311 of the flipped chip structure 1 (for example, the first chip 11) are still the same as the positions of the first pads 311 of the non-flipped chip structure 1 (for example, the second chip 12). Therefore, when the two chip structures 1 are flipped and connected, the first pads 311 can be directly connected using the redistribution layer in the non-flipped chip structure 1 (for example, the second chip 12), which effectively shortens the routing length of the redistribution layer of the non-flipped chip structure 1 (for example, the second chip 12) connecting the first pads 311, improves the consistency of the redistribution layer routing of the non-flipped chip structure 1 (for example, the second chip 12), and helps to improve the CA signal transmission rate and integrity.

[0058] In some embodiments of the present disclosure, when M and N are both odd numbers and N is greater than 1, the N first pads 311 may include a first center pad and N-1 first edge pads, the first center pad may be located at the center position, and the N-1 first edge pads are symmetrically arranged around the first center pad.

[0059] For example: Reference Figure 3 When M is 19 and N is 7, the seven first pads 311 may be CA0, CA1, CA2, CA3, CA4, CA5, and CA6. Before the chip structure 1 is flipped, for example, in the second chip 12, CA3 is the first center pad, and CA0, CA1, CA2, CA4, CA5, and CA6 are first edge pads. CA3 may be the tenth pad 31, CA6 the fifth pad 31, CA5 the seventh pad 31, CA4 the eighth pad 31, CA2 the twelfth pad 31, CA1 the thirteenth pad 31, and CA0 the fifteenth pad 31. CA6 and CA0 are symmetrically arranged with respect to CA3, CA5 and CA1 are symmetrically arranged with respect to CA3, and CA4 and CA2 are symmetrically arranged with respect to CA3.

[0060] Reference Figure 4 When the chip structure 1 is inverted, for example, CA3 is the 10th pad 31, CA6 is the 15th pad 31, CA5 is the 13th pad 31, CA4 is the 12th pad 31, CA2 is the 8th pad 31, CA1 is the 7th pad 31, and CA0 is the 5th pad 31 in the first chip 11. After the chip structure 1 is inverted, the positions of the 7 first pads 311 in the CA signal module remain unchanged. At the same time, since each first pad 311 can be universal, that is, when the first chip 11 and the second chip 12 are connected by inversion, CA6 in the first chip 11 can be directly connected to CA0 of the second chip 12, CA5 in the first chip 11 can be directly connected to CA1 of the second chip 12, CA4 in the first chip 11 can be directly connected to CA2 of the second chip 12, CA3 in the first chip 11 can be directly connected to CA3 of the second chip 12, CA2 in the first chip 11 can be directly connected to CA4 of the second chip 12, CA1 in the first chip 11 can be directly connected to CA5 of the second chip 12, and CA0 in the first chip 11 can be directly connected to CA6 of the second chip 12.

[0061] In this way, the wire length of CA6 in the first chip 11 directly connected to CA0 of the second chip 12, the wire length of CA5 in the first chip 11 directly connected to CA1 of the second chip 12, the wire length of CA4 in the first chip 11 directly connected to CA2 of the second chip 12, the wire length of CA3 in the first chip 11 directly connected to CA3 of the second chip 12, the wire length of CA2 in the first chip 11 directly connected to CA4 of the second chip 12, the wire length of CA1 in the first chip 11 directly connected to CA5 of the second chip 12, and the wire length of CA0 in the first chip 11 directly connected to CA6 of the second chip 12 are basically the same, thereby improving the consistency of the re-wiring layer wire on the second chip 12, ensuring that the CA signal rates transmitted by each first pad 311 are the same, and ensuring the integrity of the CA signal transmission.

[0062] In some embodiments of the present disclosure, when M is an odd number, N is an even number, and N is greater than 1, the N first pads 311 are symmetrically arranged at the center position.

[0063] For example, reference Figure 5When M is 19 and N is 6, the six first pads 311 can be CA0, CA1, CA2, CA3, CA4, and CA5, and the center position can be the 10th pad 31, wherein, before the chip structure 1 is flipped, for example: the second chip 12, CA5 is the 5th pad 31, CA4 is the 7th pad 31, CA3 is the 8th pad 31, CA2 is the 12th pad 31, CA1 is the 13th pad 31, and CA0 is the 15th pad 31, wherein CA5 and CA0 are symmetrically arranged with respect to the 10th pad 31, CA4 and CA1 are symmetrically arranged with respect to the 10th pad 31, and CA3 and CA2 are symmetrically arranged with respect to the 10th pad 31.

[0064] refer to Figure 6 When the chip structure 1 is flipped, for example, in the first chip 11, CA5 is the 15th pad 31, CA4 is the 13th pad 31, CA3 is the 12th pad 31, CA2 is the 8th pad 31, CA1 is the 7th pad 31, and CA0 is the 5th pad 31. After the chip structure 1 is flipped, the positions of the six first pads 311 in the CA signal module remain unchanged. At the same time, since each first solder pad 311 can be universal, that is: when the first chip 11 and the second chip 12 are flip-chip connected, CA5 in the first chip 11 can be directly connected to CA0 of the second chip 12, CA4 in the first chip 11 can be directly connected to CA1 of the second chip 12, CA3 in the first chip 11 can be directly connected to CA2 of the second chip 12, CA2 in the first chip 11 can be directly connected to CA3 of the second chip 12, CA1 in the first chip 11 can be directly connected to CA4 of the second chip 12, and CA0 in the first chip 11 can be directly connected to CA5 of the second chip 12.

[0065] In this way, the routing length of CA5 in the first chip 11 directly connecting CA0 of the second chip 12, the routing length of CA4 in the first chip 11 directly connecting CA1 of the second chip 12, the routing length of CA3 in the first chip 11 directly connecting CA2 of the second chip 12, the routing length of CA2 in the first chip 11 directly connecting CA3 of the second chip 12, the routing length of CA1 in the first chip 11 directly connecting CA4 of the second chip 12, and the routing length of CA0 in the first chip 11 directly connecting CA5 of the second chip 12 are basically the same, thereby improving the consistency of the redistribution layer routing on the second chip 12, ensuring that the CA signal rates transmitted by each first pad 311 are the same, and ensuring the integrity of the CA signal transmission.

[0066] The T second pads 312 may include a second center pad, which may be any one of a clock signal pad, a first power pad, and a chip select signal pad. The second center pad may be located at the center, and the N first pads 311 may be symmetrically arranged around the second center pad. For example: Figure 5 and Figure 6 , when M is 19 and N is 6, the second center pad may be the 10th center pad.

[0067] In some embodiments of the present disclosure, when both M and N are even numbers, and N is greater than 1, the N first pads 311 may include two third center pads and N-2 third edge pads. The two third center pads may be adjacently disposed and located on either side of the center position, respectively, and the N-2 third edge pads may be symmetrically disposed about the center position. It should be noted that when M is an even number, the center position may not be the location of the pad structure; the center position may be the gap between two adjacent pads 31 located in the middle, for example.

[0068] For example: Reference Figure 7 , when M is 20 and N is 6, the six first pads 311 can be CA0, CA1, CA2, CA3, CA4, and CA5. Before the chip structure 1 is flipped, for example, the second chip 12, CA2 and CA3 are the third center pads, and CA0, CA1, CA5, and CA6 are the third edge pads. CA3 can be the 10th pad 31, CA2 can be the 11th pad 31, and the middle position is the gap between CA2 and CA3. CA5 is the 7th pad 31, CA4 is the 8th pad 31, CA1 is the 13th pad 31, and CA0 is the 14th pad 31, wherein CA5 and CA0 are symmetrically arranged with respect to the gap between CA2 and CA3, and CA4 and CA1 are symmetrically arranged with respect to the gap between CA2 and CA3.

[0069] refer to Figure 8When the chip structure 1 is flipped, for example, in the first chip 11, CA2 is the 10th pad 31, CA3 is the 11th pad 31, CA5 is the 14th pad 31, CA4 is the 13th pad 31, CA1 is the 8th pad 31, and CA0 is the 7th pad 31. After the chip structure 1 is flipped, the positions of the six first pads 311 in the CA signal module remain unchanged. At the same time, since each first solder pad 311 can be universal, that is: when the first chip 11 and the second chip 12 are flip-chip connected, CA5 in the first chip 11 can be directly connected to CA0 of the second chip 12, CA4 in the first chip 11 can be directly connected to CA1 of the second chip 12, CA3 in the first chip 11 can be directly connected to CA2 of the second chip 12, CA2 in the first chip 11 can be directly connected to CA3 of the second chip 12, CA1 in the first chip 11 can be directly connected to CA4 of the second chip 12, and CA0 in the first chip 11 can be directly connected to CA5 of the second chip 12.

[0070] In this way, the routing length of CA5 in the first chip 11 directly connecting CA0 of the second chip 12, the routing length of CA4 in the first chip 11 directly connecting CA1 of the second chip 12, the routing length of CA3 in the first chip 11 directly connecting CA2 of the second chip 12, the routing length of CA2 in the first chip 11 directly connecting CA3 of the second chip 12, the routing length of CA1 in the first chip 11 directly connecting CA4 of the second chip 12, and the routing length of CA0 in the first chip 11 directly connecting CA5 of the second chip 12 are basically the same, thereby improving the consistency of the redistribution layer routing on the second chip 12, ensuring that the CA signal rates transmitted by each first pad 311 are the same, and ensuring the integrity of the CA signal transmission.

[0071] In some embodiments of the present disclosure, when M and N are even numbers and N is greater than 1, the T second pads 312 may include two fourth center pads, the two fourth center pads may be arranged adjacent to each other and respectively located on both sides of the center position, and the N first pads 311 may be arranged symmetrically at the center position.

[0072] For example: Reference Figure 9When M is 20 and N is 6, the six first pads 311 may be CA0, CA1, CA2, CA3, CA4, and CA5, and the two fourth center pads may be CKC and CKT. Before the chip structure 1 is flipped, for example, in the second chip 12, CA5 is the fifth pad 31, CA4 is the sixth pad 31, CA3 is the eighth pad 31, CA2 is the thirteenth pad 31, CA1 is the fifteenth pad 31, and CA0 is the sixteenth pad 31. CKC is the tenth pad 31, and CKT is the eleventh pad 31. The center position may be the gap between CKT and CKC. CA5 and CA0 are symmetrically arranged with respect to the gap between CKT and CKC, CA4 and CA1 are symmetrically arranged with respect to the gap between CKT and CKC, and CA3 and CA2 are symmetrically arranged with respect to the gap between CKT and CKC.

[0073] refer to Figure 10 When the chip structure 1 is flipped, for example, in the first chip 11, CA5 is the 16th pad 31, CA4 is the 15th pad 31, CA3 is the 13th pad 31, CA2 is the 8th pad 31, CA1 is the 6th pad 31, and CA0 is the 5th pad 31. After the chip structure 1 is flipped, the positions of the six first pads 311 in the CA signal module remain unchanged. At the same time, since each first solder pad 311 can be universal, that is: when the first chip 11 and the second chip 12 are flip-chip connected, CA5 in the first chip 11 can be directly connected to CA0 of the second chip 12, CA4 in the first chip 11 can be directly connected to CA1 of the second chip 12, CA3 in the first chip 11 can be directly connected to CA2 of the second chip 12, CA2 in the first chip 11 can be directly connected to CA3 of the second chip 12, CA1 in the first chip 11 can be directly connected to CA4 of the second chip 12, and CA0 in the first chip 11 can be directly connected to CA5 of the second chip 12.

[0074] In this way, the routing length of CA5 in the first chip 11 directly connecting CA0 of the second chip 12, the routing length of CA4 in the first chip 11 directly connecting CA1 of the second chip 12, the routing length of CA3 in the first chip 11 directly connecting CA2 of the second chip 12, the routing length of CA2 in the first chip 11 directly connecting CA3 of the second chip 12, the routing length of CA1 in the first chip 11 directly connecting CA4 of the second chip 12, and the routing length of CA0 in the first chip 11 directly connecting CA5 of the second chip 12 are basically the same, thereby improving the consistency of the redistribution layer routing on the second chip 12, ensuring that the CA signal rates transmitted by each first pad 311 are the same, and ensuring the integrity of the CA signal transmission.

[0075] In some embodiments of the present disclosure, reference Figure 3 and Figure 4 As shown, when N is greater than 1, the M pads 31 may include multiple pad groups 32, and the pad group 32 may include at most two adjacent first pads 311. That is, the pad group 32 may include one first pad 311, or may include two adjacent first pads 311. The T second pads 312 include a first power pad 313, and at least one first power pad 313 is provided between any two adjacent pad groups 32. The first power pad 313 is used to separate the two adjacent pad groups 32, thereby avoiding crosstalk between the two adjacent pad groups 32, and effectively improving the operating performance of the chip structure 1.

[0076] like Figures 9 to 12 As shown, the T second pads 312 may include a plurality of first power supply pads 313, and the plurality of first power supply pads 313 may include at least two first power supply pads 314 and at least two first grounding pads 315. The at least two first power supply pads 314 are symmetrically arranged about a central position, and the at least two first grounding pads 315 are symmetrically arranged about a central position. For example, the positions of the first power supply pads 314 of the first chip 11 and the positions of the first power supply pads 314 of the second chip 12 remain the same. Thus, when the first chip 11 and the second chip 12 are flip-chip connected, the first power supply pads 314 can be directly connected using the routing in the rewiring layer on the second chip 12, effectively shortening the routing length of the rewiring layer on the second chip 12 connecting the first power supply pads 314, further improving the consistency of the routing in the rewiring layer on the second chip 12.

[0077] Moreover, the positions of the first grounding pads 315 of the first chip 11 and the first grounding pads 315 of the second chip 12 are still the same, so that when the first chip 11 and the second chip 12 are flip-chip connected, the first grounding pads 315 can be directly connected using the routing in the rewiring layer on the second chip 12, effectively shortening the routing length of the rewiring layer on the second chip 12 connecting the first grounding pads 315, and further improving the consistency of the routing of the rewiring layer on the second chip 12.

[0078] For example: Reference Figure 11When M is 19 and the T second pads 312 include four first power supply pads 314 and four first ground pads 315 , the four first power supply pads 314 can be VDD1 , VDD2 , VDD3 , and VDD4 , and the four first ground pads 315 can be VSS1 , VSS2 , VSS3 , and VSS4 . Among them, before the chip structure 1 is flipped, for example: the second chip 12, the middle position can be the position of the 10th pad 31, VDD4 is the 1st pad 31, VDD3 is the 6th pad 31, VDD2 is the 14th pad 31, VDD1 is the 19th pad 31, VSS4 is the 4th pad 31, VSS3 is the 9th pad 31, VSS2 is the 11th pad 31, and VSS1 is the 16th pad 31, among which VDD4 and VDD1 are symmetrically arranged with respect to the 10th pad 31, VDD3 and VDD2 are symmetrically arranged with respect to the 10th pad 31, VSS4 and VSS1 are symmetrically arranged with respect to the 10th pad 31, and VSS4 and VSS1 are symmetrically arranged with respect to the 10th pad 31.

[0079] refer to Figure 12 After the chip structure 1 is flipped, for example, in the first chip 11, VDD4 is the 19th pad 31, VDD3 is the 14th pad 31, VDD2 is the 6th pad 31, VDD1 is the 1st pad 31, VSS4 is the 16th pad 31, VSS3 is the 11th pad 31, VSS2 is the 9th pad 31, and VSS1 is the 4th pad 31. After the chip structure 1 is flipped, the positions of the four first power supply pads 314 and the four first ground pads 315 in the CA signal module remain unchanged. For example: VDD4 in the first chip 11 can be directly connected to VDD1 of the second chip 12, VDD3 in the first chip 11 can be directly connected to VDD2 of the second chip 12, VDD2 in the first chip 11 can be directly connected to VDD3 of the second chip 12, VDD1 in the first chip 11 can be directly connected to VDD4 of the second chip 12, VSS4 in the first chip 11 can be directly connected to VSS1 of the second chip 12, VSS3 in the first chip 11 can be directly connected to VSS2 of the second chip 12, VSS2 in the first chip 11 can be directly connected to VSS3 of the second chip 12, and VSS1 in the first chip 11 can be directly connected to VSS4 of the second chip 12.

[0080] In this way, the length of the trace directly connecting VDD4 in the first chip 11 and VDD1 of the second chip 12, the length of the trace directly connecting VDD3 in the first chip 11 and VDD2 of the second chip 12, the length of the trace directly connecting VDD2 in the first chip 11 and VDD3 of the second chip 12, the length of the trace directly connecting VDD1 in the first chip 11 and VDD4 of the second chip 12, the length of the trace directly connecting VSS4 in the first chip 11 and VSS1 of the second chip 12, the length of the trace directly connecting VSS3 in the first chip 11 and VSS2 of the second chip 12, the length of the trace directly connecting VSS2 in the first chip 11 and VSS3 of the second chip 12, and the length of the trace directly connecting VSS1 in the first chip 11 and VSS4 of the second chip 12 are basically the same, thereby improving the consistency of the redistribution layer traces on the second chip 12.

[0081] In some embodiments, reference Figures 9 to 12 Any two first power supply pads 314 are separated to avoid signal interference between two adjacent first power supply pads 314, which can effectively improve the operating stability of the chip structure 1. Any two first ground pads 315 are separated to avoid signal interference between two adjacent first power supply pads 314, which can further improve the operating stability of the chip structure 1.

[0082] refer to Figures 9 to 12 The chip structure 1 may further include a peripheral transmission module 33 . The peripheral transmission module 33 may include an edge transmission pad 331 . The edge transmission pad 331 may be disposed adjacent to the CA signal transmission module 3 .

[0083] At least two first power supply pads 314 may include a first edge power supply pad 316. The first edge power supply pad 316 may be located at the edge of the CA signal transmission module 3 and adjacent to the edge transmission pad 331. The first edge power supply pad 316 and the edge transmission pad 331 transmit different types of signals. For example, the edge transmission pad 331 may be a second ground pad 333, etc., which can effectively avoid signal crosstalk between the first edge power supply pad 316 and the edge transmission pad 331.

[0084] At least two first ground pads 315 may include a first edge ground pad 317. The first edge ground pad 317 may be located at the edge of the CA signal transmission module 3 and adjacent to the edge transmission pad 331. The first edge ground pad 317 and the edge transmission pad 331 transmit different types of signals. For example, the edge transmission pad 331 may be a second power supply pad 332, etc., which can effectively avoid signal crosstalk between the first edge ground pad 317 and the edge transmission pad 331.

[0085] At the same time, if Figures 9 to 12 The CA signal transmission module can also use the second power supply pad 332 and the second ground pad 333 in the surrounding transmission module, so that the number of power supply pads and ground pads used for the CA signal transmission module is consistent. After the chip is flipped, the number of power supply pads and ground pads used for the CA signal transmission module remains unchanged.

[0086] In the art, with reference to Figure 13 When the first chip 11 and the second chip 12 are flip-chip connected, it is usually necessary to separately provide a connection pad 34 on the second chip 12 for leading out the CS1 signal in the flip-chip structure 1. However, with reference to Figure 1 and Figure 13 In order to ensure that signal crosstalk does not occur between the pad 31 of the first chip 11 and the connection pad 34, a distance H3 of more than 100 μm needs to be ensured between the pad 31 in the first chip 11 and the connection pad 34, thereby increasing the distance H1 between the pad of the first chip 11 and the pad of the second chip 12. When the first chip 11 and the second chip 12 are flip-chip connected, the distance H1 between the pad 31 of the first chip 11 and the pad 31 of the second chip 12 is large, which leads to an increase in the length of the wire connecting the pad 31 of the first chip 11 and the pad 31 of the second chip 12, resulting in a slow signal transmission speed between the first chip 11 and the second chip 12, which seriously affects the working performance of the flip-chip connected first chip 11 and second chip 12.

[0087] In order to further solve this technical problem, in some embodiments of the present disclosure, with reference to Figure 14 The T second pads 312 can include at least two chip select signal pads, one of which can be multiplexed as a redundant pad 35 (dummy). The redundant pad 35 can be used to lead out the CS1 signal of the first chip 11. Therefore, with reference to Figure 2 and Figure 14Compared to the related art, in this embodiment, the second chip 12 no longer needs to be provided with connecting pads 34. Consequently, there is no need to maintain a distance H2 of more than 100 μm between the pads 31 of the first chip 11 and the connecting pads 34. This shortens the distance H1 between the pads 31 of the first chip 11 and the pads 31 of the second chip 12. When the first chip 11 and the second chip 12 are flip-chip connected, the distance H1 between the pads 31 of the first chip 11 and the pads 31 of the second chip 12 can be shortened. When the distance H1 between the pads 31 of the first chip 11 and the pads 31 of the second chip 12 is shorter, the length of the trace connecting the pads 31 of the first chip 11 and the pads 31 of the second chip 12 can be effectively reduced, thereby increasing the signal transmission speed between the first chip 11 and the second chip 12. This effectively improves the operating performance of the flip-chip connection between the pads 31 of the first chip 11 and the second chip 12, thereby increasing the signal transmission rate of the memory.

[0088] For further reference, Figure 1 and Figure 2 The present disclosure also provides a semiconductor structure. The semiconductor structure includes a first chip structure and a second chip structure. The first chip structure and the second chip structure are identical and can both be the aforementioned chip structures. Either the first chip structure or the second chip structure is a flip chip, and the pads 31 in the first chip structure and the second chip structure are connected to each other.

[0089] It should be noted that when the first chip structure is located above the second chip structure, the first chip structure can be the aforementioned first chip 11, and the second chip structure can be the aforementioned second chip 12, that is, the first chip structure can be a flip chip, and the second chip structure can be a non-flip chip. When the second chip structure is located above the first chip structure, the second chip structure can be the aforementioned first chip 11, and the first chip structure can be the aforementioned second chip 12, that is, the second chip structure can be a flip chip, and the first chip structure can be a non-flip chip.

[0090] Since both the first chip structure and the second chip structure can be the above-mentioned chip structure 1, after the above-mentioned chip structure 1 is flipped, the first pads 311 located on both sides of the center position will still be symmetrically arranged about the center position, and the positions of the first pads 311 of the flipped chip are still the same as the positions of the first pads 311 of the non-flipped chip. Therefore, when the first chip structure and the second chip structure are flipped and connected, the first pads 311 can be directly connected using the redistribution layer in the non-flipped chip, which effectively shortens the routing length of the redistribution layer in the non-flipped chip connecting the first pads 311, improves the consistency of the redistribution layer routing in the non-flipped chip, and helps to improve the CA signal transmission rate and integrity.

[0091] Furthermore, an embodiment of the present disclosure also provides a memory comprising the above-mentioned semiconductor structure.

[0092] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0093] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip structure, characterized in that: include: A CA signal transmission module, comprising M pads, wherein the M pads include N first pads and T second pads, wherein the first pads are used to transmit CA signals; the CA signal transmission module has a central position, and the number of pads located on both sides of the central position is the same; When N is 1, the first pad is located at the center position; When N is greater than 1, the number of the first pads on both sides of the center position is the same, and the first pads on both sides of the center position are symmetrically arranged with respect to the center position.

2. The chip structure according to claim 1, characterized in that: When M and N are both odd numbers and N is greater than 1, the N first pads include a first center pad and N-1 first edge pads, the first center pad is located at the center position, and the N-1 first edge pads are symmetrically arranged around the first center pad.

3. The chip structure according to claim 1, wherein: When M is an odd number, N is an even number, and N is greater than 1, the N first pads are symmetrically arranged around the center position.

4. The chip structure according to claim 3, characterized in that: The T second pads include a second central pad, and the second central pad is located at the center position, and the N first pads are symmetrically arranged around the second central pad.

5. The chip structure according to claim 4, characterized in that: The second center pad is any one of a clock signal pad, a first power supply pad, and a chip select signal pad.

6. The chip structure according to claim 1, characterized in that: When M and N are both even numbers and N is greater than 1, the N first pads include two third center pads and N-2 third edge pads, the two third center pads are adjacent to each other and are respectively located on both sides of the center position, and the N-2 third edge pads are symmetrically arranged around the center position.

7. The chip structure according to claim 1, characterized in that: When M and N are even numbers and N is greater than 1, the T second pads include two fourth center pads, the two fourth center pads are adjacently arranged and respectively located on both sides of the center position, and the N first pads are symmetrically arranged about the center position.

8. The chip structure according to any one of claims 1 to 7, characterized in that: When N is greater than 1, the M pads include multiple pad groups, each pad group includes at most two adjacent first pads; the T second pads include a first power pad, and at least one first power pad is arranged between any two adjacent pad groups.

9. The chip structure according to claim 8, characterized in that: The T second pads include multiple first power pads, the multiple first power pads include at least two first power pads and at least two first ground pads, at least two of the first power pads are symmetrically arranged about the center position, and at least two of the first ground pads are symmetrically arranged about the center position.

10. The chip structure according to claim 9, characterized in that: Any two of the first power supply pads are separately arranged, and any two of the first ground pads are separately arranged.

11. The chip structure according to claim 10, characterized in that: The chip structure further includes: a peripheral transmission module including an edge transmission pad, wherein the edge transmission pad is disposed adjacent to the CA signal transmission module; The at least two first power supply pads include a first edge power supply pad, the first edge power supply pad is located at an edge of the CA signal transmission module and is adjacent to the edge transmission pad, and the first edge power supply pad and the edge transmission pad transmit different signals; And / or, at least two of the first ground pads include a first edge ground pad, the first edge ground pad is located at the edge of the CA signal transmission module and is adjacent to the edge transmission pad, and the first edge ground pad and the edge transmission pad transmit different types of signals.

12. The chip structure according to any one of claims 1 to 7, characterized in that: The T second pads include at least two chip select signal pads, and one of the chip select signal pads is multiplexed as a redundant pad.

13. A semiconductor structure, characterized in that include: a first chip structure; The second chip structure is the chip structure according to any one of claims 1 to 12, and the first chip structure and the second chip structure are the same; Wherein, any one of the first chip structure and the second chip structure is a flip chip, and the pads in the first chip structure and the second chip structure are correspondingly connected.

14. A memory, characterized in that: Comprising the semiconductor structure as claimed in claim 13.

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