Clock circuit generation method and device based on node negotiation, chip and medium

Abstract

The invention provides a clock circuit generation method and device based on node negotiation, a chip and a medium. The method comprises the following steps: acquiring input preset parameters; analyzing the obtained preset parameters, judging nodes included in the clock circuit to be generated and node types thereof, and determining parameters of each node according to the node types; the nodes are connected according to a node connection rule, negotiation among the nodes is carried out according to a node negotiation rule, and the SoC clock circuit based on node negotiation is generated; innovative concepts and technical means are introduced into clock network design, an effective solution is provided for solving technical challenges in clock management, and the design process is more efficient and simpler.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock circuit generation, and in particular to a clock circuit generation method, device, chip and medium based on node negotiation. BACKGROUND

[0002] In the modern system on chip (SoC) design process, due to the variability of IP modules and application scenarios, clock requirements and their architecture often face changes. This raises a challenge that chip design engineers need to update the clock tree architecture diagram and the corresponding code synchronously at each change. Frequent changes and synchronous updates not only increase the complexity of the design phase, but also increase the possibility of errors and correspondingly prolong the development cycle. Although there are currently methods for generating clock tree code based on tables or schematics, these methods usually require engineers to draw each component and their relationships in detail. Such operations are not only tedious, but also increase the probability of errors to some extent, especially when the architecture complexity increases.

[0003] To solve the above technical problems, in the prior art (publication number: CN112737571A), a clock circuit and a clock circuit generation method, device, equipment and medium are disclosed;

[0004] The main disadvantages of the method based on the preset text information in this calculation scheme may include the tediousness and error-prone nature of the input, the inefficient verification process, and the insufficient intuitiveness in complex designs. When making design modifications, it may be necessary to frequently update the table data, which may introduce errors and be difficult to track.

[0005] The prior art (publication number: CN115373685A) also discloses a code generation method, device and equipment based on a chip clock tree schematic diagram;

[0006] The method based on the clock tree schematic diagram in this calculation scheme, although visually intuitive, constructing a detailed schematic diagram can be very time-consuming and error-prone. For complex and large-scale clock networks, even small modifications can require a lot of manual adjustments and verification work. SUMMARY

[0007] The technical problem to be solved by the present application is to provide a clock circuit generation method, device, chip and medium based on node negotiation to overcome the shortcomings of the prior art.

[0008] To solve the above technical problems, the present application discloses a clock circuit generation method, device, chip and medium based on node negotiation.

[0009] The method comprises:

[0010] Get the input preset parameters;

[0011] Analyze the obtained preset parameters, determine the nodes and node types included in the clock circuit to be generated, and confirm the parameters of each node according to the node type;

[0012] The nodes are connected using the node connection rules, and the nodes are negotiated according to the node negotiation rules to generate the SoC clock circuit based on the node negotiation.

[0013] Furthermore, the specific method for determining the nodes and node types included in the clock circuit to be generated includes:

[0014] Determine the starting point of a clock signal in a clock circuit as a source node, wherein information of the source node includes at least: a clock frequency and a duty cycle;

[0015] Determine a node used for clock signal distribution and management as a routing node, where the types of the routing node include at least: a clock frequency division node, a clock selection node, and a clock gating node;

[0016] A termination point of a clock signal in a clock circuit is determined as a destination node, where the destination node receives the clock signal from a routing node or a source node.

[0017] Furthermore, the parameters of the node specifically include:

[0018] Incoming edge parameters are used to indicate the negotiation result between the current node and the upstream node, providing the current node with information from the upstream node.

[0019] Outbound parameters are used to indicate the negotiation result between the current node and the downstream node, providing the downstream node with information about the current node.

[0020] Furthermore, the confirmation of the parameters of each node specifically includes:

[0021] The source node only includes outbound edge parameters, which contain information about each clock in the source node.

[0022] A routing node includes both incoming and outgoing parameters. The incoming parameters are the result of negotiation between the node and the upstream node, while the outgoing parameters are the result of negotiation with the downstream node.

[0023] The destination node only includes the incoming edge parameters, which are the result of negotiation with the upstream node.

[0024] Furthermore, the nodes are connected using node connection rules, specifically including:

[0025] The source node is a master node relative to the routing node and the destination node, the routing node is a slave node relative to the source node and a master node relative to the destination node, and the destination node is a slave node relative to the source node and the routing node;

[0026] The connection between the nodes includes a connection from a master node to a slave node and a connection between routing nodes;

[0027] For each connection between the nodes, corresponding in-edge parameters and out-edge parameters are created in the nodes on both sides of the connector.

[0028] Further, the connector specifically includes:

[0029] The connector is represented by a preset special symbol, and when the nodes are connected using the connector, the slave node is located on the left side of the connector, and the master node upstream node is located on the right side of the connector, the slave node is a downstream node, and the master node is an upstream node.

[0030] Further, the inter-node negotiation according to the node negotiation rule specifically includes:

[0031] Determine whether all source nodes in the clock circuit participate in clock selection, clock frequency division and clock gating, and make corresponding circuit connections according to the determination result;

[0032] If the clock frequency division module is included in the clock circuit, set the minimum frequency division coefficient of the clock frequency division module;

[0033] Determine whether all destination nodes in the clock circuit need clock gating, if the clock gating module is used for connection if clock gating is needed, otherwise the destination node is not connected to the clock gating node;

[0034] Determine whether the clock selection, clock frequency division and clock gating of all destination nodes in the clock circuit are independent, and make corresponding circuit connections according to the determination result.

[0035] Further, determine whether all source nodes in the clock circuit participate in clock selection, clock frequency division and clock gating, and make corresponding circuit connections according to the determination result, specifically including:

[0036] If the source node participates in clock selection, the clock selection module is used for connection and participates in clock selection, otherwise the source node is only connected to the specified routing node;

[0037] If the source node participates in clock frequency division, the clock frequency division module is used for connection and participates in clock frequency division, otherwise the source node is only connected to the specified routing node;

[0038] If the source node participates in clock gating, a clock gating module is used to connect with the source node and participate in clock gating, otherwise the source node is only connected with the designated routing node.

[0039] Further, whether clock selection, clock frequency division and clock gating of all destination nodes in the clock circuit are independent is judged, and corresponding circuit connection is performed according to the judgment result, and specifically includes:

[0040] If the clock selection of the destination nodes is independent, an independent clock selection module is generated for the circuit module corresponding to the destination nodes; if the clock selection of the designated destination nodes is shared, a shared clock selection module is generated for the circuit module corresponding to the destination nodes;

[0041] If the clock frequency division of the destination nodes is independent, an independent clock frequency division module is generated for the circuit module corresponding to the destination nodes; if the clock frequency division of the designated destination nodes is shared, a shared clock frequency division module is generated for the circuit module corresponding to the destination nodes;

[0042] If the clock gating of the destination nodes is independent, an independent clock gating module is generated for the circuit module corresponding to the destination nodes; if the clock gating of the designated destination nodes is shared, a shared clock gating module is generated for the circuit module corresponding to the destination nodes.

[0043] Further, the minimum frequency division coefficient of the clock frequency division module specifically includes: according to the highest frequency of the destination node and the frequency size of the clock source, the minimum frequency division coefficient is calculated.

[0044] The application also proposes a clock circuit generation device based on node negotiation, which is used to generate a clock circuit according to the aforementioned method, and includes:

[0045] The input module is used to acquire the input preset parameters.

[0046] The configuration module is used to predefine the clock circuit generation rule.

[0047] The analysis generation module analyzes the preset parameters acquired by the input module, and generates the clock circuit based on node negotiation according to the clock circuit generation rule predefined by the configuration module.

[0048] The output module is used to output the clock circuit based on node negotiation.

[0049] Further, the clock circuit generation rule in the configuration module at least includes: node classification rule, node parameter confirmation rule, node connection rule and node negotiation rule.

[0050] Further, the analysis generation module at least includes:

[0051] The node type definition submodule is used to analyze and define node types according to node classification rules;

[0052] The node parameter confirmation submodule is used to confirm the node parameters according to the node parameter confirmation rules;

[0053] A node connection submodule, configured to connect the nodes using connectors according to node connection rules;

[0054] The node negotiation submodule is used to negotiate according to the node negotiation rules when connecting nodes and generate the final clock circuit.

[0055] The present invention also provides a chip for executing a program, wherein the program implements the above method.

[0056] The present invention also provides a computer-readable storage medium having computer instructions stored thereon, and when the computer instructions are executed, the above method is implemented.

[0057] The present invention also provides a clock circuit, which is generated using the above method.

[0058] Beneficial effects:

[0059] The present invention provides a more flexible and efficient clock network management solution by introducing three different types of node definitions (source node, routing node and destination node) and a parameter and circuit generation mechanism based on negotiation.

[0060] First, through clear node definitions, this invention makes clock network construction more structured and modular. The categorization of source, routing, and destination nodes provides a clear hierarchy for the entire system, allowing designers to better understand and manage complex clock networks. Compared to traditional clock management methods, this significantly simplifies the design process and improves efficiency. While maintaining a certain level of intuitiveness, it also significantly reduces the complexity of the design process.

[0061] Secondly, the negotiated parameter and circuit generation mechanism provides tremendous flexibility for implementing specific applications. By setting different negotiation rules, designers can automatically determine the actual configuration of clock sources, selection, frequency division, and gating based on specific requirements and constraints. This adaptive design approach not only reduces the workload of manual configuration and optimization, but also ensures optimal clock network performance. Compared to traditional methods, this rule-based automatic configuration is more intelligent and efficient, helping to solve clock management problems in complex systems.

[0062] In summary, the innovative concepts and technical means introduced in the clock network design of the present invention provide an effective solution to the technical challenges in clock management, making the design process more efficient and concise. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0064] Figure 1 This is a schematic diagram of original code information in one embodiment of the present invention;

[0065] Figure 2 This is a structural diagram corresponding to node connections in one embodiment of the present invention;

[0066] Figure 3 This is a schematic diagram of a clock circuit finally generated in one embodiment of the present invention;

[0067] Figure 4 It is a schematic diagram of the overall process of the present invention;

[0068] Figure 5 It is a schematic diagram of a flow chart for determining nodes and node types included in a clock circuit to be generated in the present invention;

[0069] Figure 6 It is a flowchart of negotiation between nodes according to the node negotiation rules in the present invention. DETAILED DESCRIPTION

[0070] This paper proposes a method for generating clock circuits based on node negotiation (the clock circuits proposed in this paper are SoC clock circuits). This method utilizes a negotiation mechanism between nodes to achieve dynamic and flexible construction and adjustment of the clock tree. Compared with methods based on schematics or tables, this method based on node negotiation can provide a more streamlined, intuitive, and robust solution for dealing with changing and complex design requirements, reducing the burden on engineers in detailed design and modification while maintaining the robustness and flexibility of the system. The main ideas of this invention are as follows:

[0071] Improve design efficiency: Reduce manual work during design, verification, and code generation, and reduce the possibility of errors.

[0072] Enhanced design flexibility: Easily respond to changes during the design phase and adapt to different design requirements through simple parameter adjustments or node negotiation instead of tedious manual adjustments.

[0073] Improve code quality: Automatically generated Verilog code reduces errors and inconsistencies introduced by manual coding.

[0074] Retain intuitiveness while reducing complexity: Although it does not rely on complex prototype diagrams, it can still provide sufficient intuitiveness and ease of understanding through the logical expression and relationship description of nodes to assist designers in decision-making and verification.

[0075] Based on the above principles and overall ideas, the present invention proposes a method for generating a SoC clock circuit based on node negotiation, which relies on the definition of three different types of nodes, two parameter types, and a connector, as follows:

[0076] 1. Two parameter types:

[0077] Inbound edge parameter: It represents the negotiation result with the upstream node and provides the current node with information from the upstream node.

[0078] Outbound parameters: They represent the negotiation results with downstream nodes and provide downstream nodes with information about the current node.

[0079] 2. Three types of nodes:

[0080] Source nodes: These are the starting points for clocks, such as crystal oscillators and PLLs. For source nodes, you need to enter information such as the clock frequency and duty cycle. Source nodes only have outbound parameters, which contain information about each clock in the source node. You can have any number of source nodes.

[0081] Routing nodes: They act as intermediaries in the clock tree, responsible for clock distribution and management. Routing nodes can be further divided into clock divider nodes, clock selection nodes, and clock gating nodes. Routing nodes contain both inbound and outbound parameters. Inbound parameters are the result of negotiation between the node and upstream nodes, while outbound parameters are the result of negotiation with downstream nodes. Based on the results of parameter negotiation, the node may generate multiple circuit instances. Routing node subdivision types are customizable and extensible.

[0082] Destination nodes: These are the endpoints of the clock, such as IPs, CPUs, and DSPs. They receive clock signals from routing nodes or directly from source nodes. Destination nodes only have input edge parameters, which are negotiated with upstream nodes. The number of destination nodes is arbitrary.

[0083] 3. Connectors:

[0084] The connector is represented by a preset special symbol, and here "<-" is used as an example (in other embodiments, any custom symbol can also be used). When the connector is used to connect nodes, such as Figure 1 As shown, slave nodes should be located to the left of the connection symbol, and master nodes should be located to the right of the connection symbol. Routing nodes can also be directly connected to each other. Each time a node is connected, incoming or outgoing edge parameters are created for the nodes on both sides.

[0085] Of the three types of nodes, the source node is the master node relative to both the routing node and the destination node. The routing node is a slave node relative to the source node. The destination node is a master node relative to both the source node and the routing node. When describing node connections, the slave node should be located to the left of the connection symbol, and the master node to the right. Routing nodes can be directly connected to each other; the routing node to the left of the connection symbol is a slave node relative to the routing node to the right.

[0086] Based on the above setting principle, the present invention proposes a SoC clock circuit generation method based on node negotiation, such as Figure 4 As shown, the specific steps include:

[0087] Step 1: Obtain input preset parameters; the preset parameters may include various information of the clock circuit to be generated;

[0088] Step 2: Analyze the acquired preset parameters and determine the nodes and node types included in the clock circuit to be generated, such as Figure 5 As shown, the specific methods include:

[0089] Step 2-1: determining the starting point of a clock signal in a clock circuit as a source node, wherein information of the source node includes at least: a clock frequency and a duty cycle;

[0090] Step 2-2: determining a node used for clock signal distribution and management as a routing node, where the types of routing nodes include at least: a clock frequency division node, a clock selection node, and a clock gating node;

[0091] Step 2-3: Determine the end point of the clock signal in the clock circuit as a destination node, where the destination node receives the clock signal from the routing node or the source node.

[0092] For example, based on preset parameters, circuit nodes such as crystal oscillators and PLLs are identified and set as source nodes; circuit nodes such as IP, CPU, and DSP are identified and set as destination nodes; other nodes responsible for clock distribution and management are set as routing nodes, and routing nodes can be further subdivided into clock division nodes, clock selection nodes, and clock gating nodes according to their functions;

[0093] Step 3: Confirm the parameters of each node according to the node type; wherein the parameters of the node specifically include:

[0094] Incoming edge parameters are used to indicate the negotiation result between the current node and the upstream node, providing the current node with information from the upstream node.

[0095] Outbound parameters are used to indicate the negotiation result between the current node and the downstream node, providing the downstream node with information about the current node.

[0096] The parameters of each node are confirmed, including:

[0097] The source node only includes outbound edge parameters, which contain information about each clock in the source node.

[0098] A routing node includes both incoming and outgoing parameters. The incoming parameters are the result of negotiation between the node and the upstream node, while the outgoing parameters are the result of negotiation with the downstream node.

[0099] The destination node only includes the incoming edge parameters, which are the result of negotiation with the upstream node.

[0100] Step 4: Based on the nodes and related information analyzed and confirmed in steps 2 and 3, the nodes are connected using node connection rules. The specific method includes:

[0101] The source node is the master node relative to the routing node and the destination node, the routing node is the slave node relative to the source node, the source node is the master node relative to the destination node, and the destination node is the slave node relative to the source node and the routing node;

[0102] Connections between nodes, including connections from master nodes to slave nodes, and connections between routing nodes;

[0103] Each time nodes are connected, corresponding inbound and outbound parameters are created in the nodes on both sides of the connector.

[0104] The connectors are as follows:

[0105] The connector is represented by a preset special symbol. When the connector is used to connect the nodes, the slave node is located on the left side of the connector, and the upstream node of the master node is located on the right side of the connector. The slave node is the downstream node, and the master node is the upstream node.

[0106] Step 5: Perform inter-node negotiation according to the node negotiation rules to generate the SoC clock circuit based on the node negotiation, such as Figure 6 As shown, the specific methods include:

[0107] Step 5-1: Determine whether all source nodes in the clock circuit participate in clock selection, clock division, and clock gating, and make corresponding circuit connections based on the determination result. The specific method is as follows:

[0108] If the source node participates in clock selection, the clock selection module is used to connect to it and participate in clock selection. Otherwise, the source node is only connected to the specified routing node.

[0109] If the source node participates in clock division, the clock division module is used to connect to it and participate in clock division. Otherwise, the source node is only connected to the specified routing node.

[0110] If the source node participates in clock gating, the clock gating module is used to connect to it and participate in clock gating. Otherwise, the source node is only connected to the specified routing node.

[0111] Step 5-2: If the clock circuit includes a clock frequency division module, set the minimum frequency division coefficient of the clock frequency division module. The specific method is as follows: calculate the minimum frequency division coefficient based on the maximum frequency of the destination node and the frequency of the clock source;

[0112] Step 5-3, determining whether all destination nodes in the clock circuit require clock gating, if so, connecting them to the clock gating node using a clock gating module, otherwise the destination node is not connected to the clock gating node;

[0113] Step 5-4: Determine whether the clock selection, clock division, and clock gating of all destination nodes in the clock circuit are independent, and make corresponding circuit connections based on the determination result. The specific method is as follows:

[0114] If the clock selection of the destination node is independent, an independent clock selection module is generated for the circuit module corresponding to the destination node; if the common clock selection of the specified destination node is selected, a common clock selection module is generated for the circuit modules corresponding to these destination nodes;

[0115] If the clock frequency division of the destination node is independent, an independent clock frequency division module is generated for the circuit module corresponding to the destination node; if the clock frequency division of the specified destination node is shared, a shared clock frequency division module is generated for the circuit modules corresponding to these destination nodes;

[0116] If the clock gating of the destination node is independent, an independent clock gating module is generated for the circuit module corresponding to the destination node; if the shared clock gating of the specified destination node is specified, a shared clock gating module is generated for the circuit modules corresponding to these destination nodes.

[0117] The present invention also proposes a SoC clock circuit generation device based on node negotiation, which is used to generate a clock circuit according to the above method, including:

[0118] Input module, used to obtain input preset parameters;

[0119] Configuration module, used to predefine clock circuit generation rules;

[0120] The analysis and generation module analyzes the preset parameters obtained by the input module and generates the SoC clock circuit based on node negotiation according to the clock circuit generation rules predefined by the configuration module;

[0121] The output module is used to output the SoC clock circuit based on node negotiation.

[0122] The clock circuit generation rules in the configuration module at least include: node classification rules, node parameter confirmation rules, node connection rules and node negotiation rules.

[0123] The analysis and generation module at least includes:

[0124] The node type definition submodule is used to analyze and define node types according to node classification rules;

[0125] The node parameter confirmation submodule is used to confirm the node parameters according to the node parameter confirmation rules;

[0126] A node connection submodule, configured to connect the nodes using connectors according to node connection rules;

[0127] The node negotiation submodule is used to negotiate according to the node negotiation rules when connecting nodes and generate the final clock circuit.

[0128] The present invention also provides a chip for executing a program, wherein the program implements the above method.

[0129] The present invention also provides a computer-readable storage medium having computer instructions stored thereon, and when the computer instructions are executed, the above method is implemented.

[0130] The present invention also proposes a clock circuit generated using the above method.

[0131] Example:

[0132] like Figure 1The figure below shows a schematic diagram of the original code information connecting various nodes using the aforementioned definitions. Analysis of the original code reveals that a total of three source nodes are used: the PLL node (1200MHz), the crystal oscillator node (25MHz), and the ring oscillator node (120MHz); three routing nodes are used: the clock selection node, the clock frequency division node, and the clock gating node; and three destination nodes are used: the CPU node, the DSP node, and the SPI node. The PLL, crystal oscillator, and ring oscillator source nodes are all connected as slave nodes to the clock selection node. The clock selection node, as the master node, is connected to the clock frequency division node, which is connected to the clock gating node. Finally, the clock gating node is connected to the CPU node, the DSP node, and the SPI node.

[0133] After defining the node connection information, the node negotiation rules will be used to negotiate the parameters between the nodes. The negotiation rules designed in this embodiment include the following points:

[0134] Key point 1: Whether each clock source can participate in clock selection, clock division and clock gating;

[0135] Point 2: The maximum frequency of each destination node cannot exceed a certain MHz;

[0136] Point 3: Does each destination node require clock gating?

[0137] Point 4: Do the clock selection, clock division, and clock gating of each destination node need to be independent?

[0138] Specifically, in this embodiment, a practical negotiation rule that may be adopted is as follows:

[0139] Rule 1: Each clock source can participate in clock selection, clock division, and clock gating;

[0140] Rule 2: The maximum frequency of DSP shall not exceed 400MHz;

[0141] Rule 3: The maximum frequency of SPI does not exceed 100MHz;

[0142] Rule 4: The CPU does not need clock gating;

[0143] Rule 5: The clock selection, clock division, and clock gating of each destination node must be independent.

[0144] Through the above negotiation rules, each node negotiates and finally obtains the following specific parameters and circuits:

[0145] PLL, crystal oscillator, and ring oscillator nodes: Since each clock source can participate in clock selection, each clock source is connected to the downstream clock selection module.

[0146] Clock selection node: Since the clock selection of the three destination nodes needs to be independent, the clock selection node establishes three independent clock selection modules. Since each clock source can participate in clock selection, the selection source of each clock selection module is a collection of clocks.

[0147] Clock frequency division node: Since the clock frequency division of the three destination nodes needs to be independent, the clock frequency division node will establish three independent clock frequency division modules. Since the maximum frequency of the DSP node does not exceed 400MHz, the minimum frequency division coefficient of the clock divider corresponding to the DSP is 3 when the input clock source is PLL (the PLL node frequency is 1200MHz, 1200 / 400=3); since the maximum frequency of the SPI node does not exceed 100MHz, the minimum frequency division coefficient of the clock divider corresponding to the SPI is 12 when the input clock source is PLL, and the minimum frequency division coefficient of the clock divider corresponding to the SPI is 2 when the input clock source is ring oscillator;

[0148] Clock gating node: Because the clock gating of the three destination nodes requires independence, the clock gating node establishes three independent clock gating modules. Since the CPU does not participate in clock gating, the clock gating module corresponding to the CPU remains normally open.

[0149] CPU, DSP and SPI nodes: These three nodes are destination nodes. Figure 2 connection relationship, directly receiving the clock from the clock gating node.

[0150] Finally, the circuit constructed according to the negotiation rules is as follows: Figure 3 As shown, the details are as follows:

[0151] The three source nodes correspond to three clock source circuits, namely, a PLL clock source, a crystal oscillator clock source, and a ring oscillator clock source.

[0152] The clock selection node corresponds to three clock selection modules: clock selection module 1, clock selection module 2, and clock selection module 3. The inputs of the three clock selection modules are all sets of three clock sources, and the outputs are all selected clocks.

[0153] The clock division node corresponds to three clock division modules: clock division module 1, clock division module 2, and clock division module 3. The minimum division factor of clock division module 2 is 2, and the minimum division factor of clock division module 3 is 12. The input of all three clock division modules is the output of the clock selection module at the previous level, and the output is the divided clock.

[0154] The clock gating node corresponds to three clock gating modules: clock gating module 1, clock gating module 2, and clock gating module 3. Clock gating module 1 remains normally open. The inputs of the three clock divider modules are all the outputs of the previous-level clock divider module, and the outputs are all gated clocks.

[0155] The three destination nodes correspond to three clock receiving circuits, namely the CPU module, DSP module, and SPI module. All three modules receive the output clock from the upper-level clock gating module.

[0156] In one embodiment, the present invention further provides a SoC clock circuit generation device based on node negotiation, for generating a clock circuit according to the aforementioned method of the claims, the device comprising:

[0157] Input module, used to obtain input preset parameters;

[0158] Configuration module, used to predefine clock circuit generation rules;

[0159] The analysis and generation module analyzes the preset parameters obtained by the input module and generates the SoC clock circuit based on node negotiation according to the clock circuit generation rules predefined by the configuration module;

[0160] The output module is used to output the SoC clock circuit based on node negotiation.

[0161] In another embodiment, the clock circuit generation rules in the configuration module include at least: node classification rules, node parameter confirmation rules, node connection rules and node negotiation rules.

[0162] In another embodiment, the analysis generation module at least includes:

[0163] The node type definition submodule is used to analyze and define node types according to node classification rules;

[0164] The node parameter confirmation submodule is used to confirm the node parameters according to the node parameter confirmation rules;

[0165] A node connection submodule, configured to connect the nodes using connectors according to node connection rules;

[0166] The node negotiation submodule is used to negotiate according to the node negotiation rules when connecting nodes and generate the final clock circuit.

[0167] In one embodiment, the present invention further provides a chip for executing a program, wherein the program implements the aforementioned method.

[0168] In one embodiment, the present invention further provides a computer-readable storage medium having computer instructions stored thereon. When the computer instructions are executed, the aforementioned method is implemented.

[0169] In one embodiment, the present invention further provides a clock circuit, which is generated using the aforementioned method.

[0170] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium is capable of storing a computer program that, when executed by the data processing unit, can execute the invention content of a clock circuit generation method, device, chip, and medium based on node negotiation provided by the present invention, as well as some or all of the steps in each embodiment. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0171] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, in essence or in other words, the part that contributes to the prior art, can be embodied in the form of a computer program, i.e., a software product. The computer program software product can be stored in a storage medium and includes a number of instructions for enabling a device including a data processing unit (which can be a personal computer, server, single-chip microcomputer, MCU, or network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0172] The present invention provides a method, device, chip, and medium for generating a clock circuit based on node negotiation. While there are numerous methods and approaches for implementing this technical solution, the foregoing merely represents a preferred embodiment of the present invention. It should be noted that those skilled in the art may make improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are considered within the scope of protection of the present invention. Any components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A clock circuit generation method based on node negotiation, characterized in that: The method comprises: Get the input preset parameters; Analyze the obtained preset parameters, determine the nodes and node types included in the clock circuit to be generated, and confirm the parameters of each node according to the node type; Use node connection rules to connect nodes; According to the node negotiation rules, different types of nodes are negotiated among each other, the parameters of the nodes are generated according to the negotiation results, and the clock circuit based on the node negotiation is generated.

2. A clock circuit generation method based on node negotiation according to claim 1, characterized in that: The specific method for determining the nodes and node types included in the clock circuit to be generated includes: Determine the starting point of a clock signal in a clock circuit as a source node, wherein information of the source node includes at least: a clock frequency and a duty cycle; Determine nodes used for clock signal distribution and management as routing nodes, where the types of routing nodes include at least: clock frequency division nodes, clock selection nodes, and clock gating nodes; A termination point of a clock signal in a clock circuit is determined as a destination node, where the destination node receives the clock signal from a routing node or a source node.

3. The method for generating a clock circuit based on node negotiation according to claim 2, wherein: The parameters of the node specifically include: Incoming edge parameters are used to indicate the negotiation result between the current node and the upstream node, providing the current node with information from the upstream node. Outbound parameters are used to indicate the negotiation result between the current node and the downstream node, providing the downstream node with information about the current node.

4. The method for generating a clock circuit based on node negotiation according to claim 3, wherein: The parameters of each node are confirmed, including: The source node only includes outbound edge parameters, which contain information about each clock in the source node. A routing node includes both incoming and outgoing parameters. The incoming parameters are the result of negotiation between the node and the upstream node, while the outgoing parameters are the result of negotiation with the downstream node. The destination node only includes the incoming edge parameters, which are the result of negotiation with the upstream node.

5. The method for generating a clock circuit based on node negotiation according to claim 4, wherein: Nodes are connected using node connection rules, including: The source node is the master node relative to the routing node and the destination node, the routing node is the slave node relative to the source node, the source node is the master node relative to the destination node, and the destination node is the slave node relative to the source node and the routing node; Connections between nodes, including connections from master nodes to slave nodes, and connections between routing nodes; Each time nodes are connected, corresponding inbound and outbound parameters are created in the nodes on both sides of the connector.

6. The method for generating a clock circuit based on node negotiation according to claim 5, wherein: The connector specifically includes: The connector is represented by a preset special symbol. When the connector is used to connect the nodes, the slave node is located on the left side of the connector, and the upstream node of the master node is located on the right side of the connector. The slave node is the downstream node, and the master node is the upstream node.

7. The method for generating a clock circuit based on node negotiation according to claim 6, wherein: The negotiation between nodes according to the node negotiation rules specifically includes: Determine whether all source nodes in the clock circuit participate in clock selection, clock division, and clock gating, and make corresponding circuit connections based on the determination result; If the clock circuit includes a clock frequency division module, setting a minimum frequency division coefficient of the clock frequency division module; Determine whether all destination nodes in the clock circuit require clock gating, and if so, connect them to the clock gating node using a clock gating module; otherwise, the destination node is not connected to the clock gating node; Determine whether the clock selection, clock frequency division, and clock gating of all destination nodes in the clock circuit are independent, and make corresponding circuit connections based on the determination result.

8. The method for generating a clock circuit based on node negotiation according to claim 7, wherein: Determining whether all source nodes in the clock circuit participate in clock selection, clock division, and clock gating, and making corresponding circuit connections based on the determination result, specifically includes: If the source node participates in clock selection, the clock selection module is used to connect to it and participate in clock selection. Otherwise, the source node is only connected to the specified routing node. If the source node participates in clock division, the clock division module is used to connect to it and participate in clock division. Otherwise, the source node is only connected to the specified routing node. If the source node participates in clock gating, the clock gating module is used to connect to it and participate in clock gating. Otherwise, the source node is only connected to the specified routing node.

9. The method for generating a clock circuit based on node negotiation according to claim 8, wherein: Determining whether the clock selection, clock division, and clock gating of all destination nodes in the clock circuit are independent, and making corresponding circuit connections based on the determination result, specifically including: If the clock selection of the destination node is independent, an independent clock selection module is generated for the circuit module corresponding to the destination node; if the common clock selection of the specified destination node is selected, a common clock selection module is generated for the circuit modules corresponding to these destination nodes; If the clock frequency division of the destination node is independent, an independent clock frequency division module is generated for the circuit module corresponding to the destination node; if the clock frequency division of the specified destination node is shared, a shared clock frequency division module is generated for the circuit modules corresponding to these destination nodes; If the clock gating of the destination node is independent, an independent clock gating module is generated for the circuit module corresponding to the destination node; if the shared clock gating of the specified destination node is specified, a shared clock gating module is generated for the circuit modules corresponding to these destination nodes.

10. The method for generating a clock circuit based on node negotiation according to claim 9, characterized in that: The setting of the minimum frequency division coefficient of the clock frequency division module specifically includes: calculating the minimum frequency division coefficient according to the maximum frequency of the destination node and the frequency of the clock source.

11. A clock circuit generation device based on node negotiation, characterized in that: A circuit for generating a clock according to any one of claims 1 to 10, comprising: Input module, used to obtain input preset parameters; Configuration module, used to predefine clock circuit generation rules; The analysis and generation module analyzes the preset parameters obtained by the input module and generates the SoC clock circuit based on node negotiation according to the clock circuit generation rules predefined by the configuration module; The output module is used to output the SoC clock circuit based on node negotiation.

12. The clock circuit generation device based on node negotiation according to claim 11, characterized in that: The clock circuit generation rules in the configuration module at least include: node classification rules, node parameter confirmation rules, node connection rules and node negotiation rules.

13. The clock circuit generation device based on node negotiation according to claim 12, characterized in that: The analysis and generation module at least includes: The node type definition submodule is used to analyze and define node types according to node classification rules; The node parameter confirmation submodule is used to confirm the node parameters according to the node parameter confirmation rules; A node connection submodule, configured to connect the nodes using connectors according to node connection rules; The node negotiation submodule is used to negotiate according to the node negotiation rules when connecting nodes and generate the final clock circuit.

14. A chip, characterized in that: Used to execute a program, wherein the program implements the method according to any one of claims 1 to 10.

15. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed, the method according to any one of claims 1 to 10 is implemented.

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