Magnetic memory and method of data reading for magnetic memory

Abstract

The application provides a magnetic memory and a data reading method of the magnetic memory, and relates to the technical field of semiconductors. The magnetic memory comprises a reading signal generating circuit, a hysteresis comparison circuit and a switch timing circuit which are electrically connected with each other. The reading signal generating circuit comprises a data magnetic storage unit for generating a data signal and a reference magnetic storage unit for generating a reference signal. The reading signal generating circuit inputs the data signal into the switch timing circuit and inputs the reference signal into a first input end of the hysteresis comparison circuit, and determines a hysteresis interval of the hysteresis comparison circuit through the reference signal. The switch timing circuit is used for resetting an output end of the hysteresis comparison circuit to a first logic signal before each data reading, and then inputting the data signal into a second input end of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, and the output end of the hysteresis comparison circuit outputs a data reading result. The introduction of the hysteresis comparison circuit reduces the layout area and power consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a magnetic memory and a method for reading data from the magnetic memory. Background Technology

[0002] Magnetic random access memory (MRAM) is a novel non-volatile memory technology that combines the advantages of traditional magnetic storage and semiconductor technology. Magnetic storage technology utilizes the magnetization state of magnetic materials to store information. Each storage cell typically consists of a small magnetic region, whose magnetization direction can represent "0" or "1" in binary data. Data is retrieved by detecting the magnetization state of these magnetic regions.

[0003] For example, a data branch and two parallel reference branches are set up. The data branch includes a data magnetic storage unit for generating data signals, and each reference branch includes a reference magnetic storage unit. The two reference magnetic storage units jointly generate a reference signal, and the data signal and the reference signal are differentially compared to determine the actual stored data, and then the data is read.

[0004] However, since each data magnetic storage unit requires two reference magnetic storage units, this increases the area of ​​the storage array. Therefore, how to save reference branches to save area during data reading is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a magnetic memory and a method for reading data from the magnetic memory. By introducing a hysteresis comparator circuit and a switching timing circuit, the layout area of ​​the reference branch is saved, the power consumption of the reference branch during data reading is reduced, and the accuracy and stability of data reading are improved.

[0006] In a first aspect, this application provides a magnetic storage device, including a read signal generation circuit, a hysteresis comparison circuit, and a switching timing circuit that are electrically connected to each other;

[0007] The read signal generation circuit includes a data magnetic storage unit for generating data signals and a reference magnetic storage unit for generating reference signals. The read signal generation circuit inputs the data signal into the switching timing circuit and inputs the reference signal into the first input terminal of the hysteresis comparator circuit to determine the hysteresis range of the hysteresis comparator circuit through the reference signal.

[0008] The switching timing circuit is used to reset the output of the hysteresis comparator circuit to the first logic signal before each data read, and then input the data signal to the second input of the hysteresis comparator circuit, so that the hysteresis comparator circuit performs a hysteresis comparison on the data signal and the hysteresis interval, thereby causing the output of the hysteresis comparator circuit to output the data read result.

[0009] Optionally, when the reference magnetic storage cell is in a low-resistance state, the reference signal it generates is a low-resistance state reference signal; when the reference magnetic storage cell is in a high-resistance state, the reference signal it generates is a high-resistance state reference signal.

[0010] The hysteresis range of the hysteresis comparator circuit is determined by a reference signal, including:

[0011] The threshold value of the hysteresis interval is determined by using the low-resistivity reference signal and the high-resistivity reference signal.

[0012] Optionally, the hysteresis comparator circuit performs a hysteresis comparison between the data signal and the hysteresis interval, thereby outputting the data reading result at the output terminal of the hysteresis comparator circuit, including:

[0013] If the data signal is greater than the threshold, the data reading result is flipped from the first logic signal to the second logic signal; or, if the data signal is less than the threshold, the data reading result remains the first logic signal.

[0014] The first logic signal represents the opposite logic to the second logic signal.

[0015] Optionally, the hysteresis comparator circuit performs a hysteresis comparison between the data signal and the hysteresis interval, thereby outputting the data reading result at the output terminal of the hysteresis comparator circuit, including:

[0016] If the data signal is less than the threshold, the data reading result is flipped from the first logic signal to the second logic signal; or, if the data signal is greater than the threshold, the data reading result remains the first logic signal.

[0017] The first logic signal represents the opposite logic to the second logic signal.

[0018] Optionally, the switching timing circuit includes a first switching unit and a second switching unit;

[0019] The first switching unit is electrically connected to the second input terminal of the read signal generation circuit and the hysteresis comparator circuit; the second switching unit is electrically connected to the second input terminal of the hysteresis comparator circuit; the output terminal of the hysteresis comparator circuit is reset to the first logic signal by controlling the on / off state of the first and second switching units, or the data signal is input to the second input terminal of the hysteresis comparator circuit by controlling the on / off state of the first and second switching units.

[0020] Optionally, the read signal generation circuit includes: a reference signal generation module and a data signal generation module;

[0021] The reference signal generation module is electrically connected to the first input terminal of the hysteresis comparator circuit. The reference signal generation module includes at least one reference magnetic storage unit for generating and outputting a reference signal.

[0022] The data signal generation module is electrically connected to the second input terminal of the hysteresis comparator circuit through a switching timing circuit. The data signal generation module includes at least one data magnetic storage unit for generating and outputting data signals.

[0023] Optionally, the data signal generation module includes multiple data magnetic storage units;

[0024] Each data magnetic storage unit generates a corresponding data signal that is electrically connected to the second input terminal of the hysteresis comparator circuit, so that multiple data signals share the same reference signal.

[0025] It should be noted that each data magnetic storage unit generates a corresponding data signal that is electrically connected to the hysteresis comparator circuit. This means that each data magnetic storage unit can be electrically connected to the hysteresis comparator circuit through row selection or column selection, so that multiple data magnetic storage units can share the same hysteresis comparator circuit.

[0026] Optionally, the reference magnetic storage cell includes a magnetic tunnel junction, which includes a free layer, a barrier layer, and a reference layer stacked sequentially.

[0027] In this case, the magnetization directions of the free layer and the reference layer in the reference magnetic storage cell are parallel, or the magnetization directions of the free layer and the reference layer in the reference magnetic storage cell are antiparallel.

[0028] Optionally, when there are multiple data magnetic storage units, reference magnetic storage units, and hysteresis comparator circuits, the data magnetic storage units are configured to be arranged in multiple columns in an array, and the reference magnetic storage units are configured to be arranged in at least one column in an array.

[0029] In this system, the data signal generated by each row of data magnetic storage unit is input to the second input terminal of the hysteresis comparator circuit corresponding to each row, and the reference signal generated by each row of reference magnetic storage unit is input to the first input terminal of the same hysteresis comparator circuit corresponding to each row, so that each row of data magnetic storage unit shares the same reference magnetic storage unit.

[0030] Secondly, this application provides a data reading method for a magnetic storage device, applied to the magnetic storage device as described in any one of the first aspects; the method includes:

[0031] Before each data read, reset the output of the hysteresis comparator to the first logic signal;

[0032] A data signal is input to the second input terminal of the hysteresis comparator circuit, so that the hysteresis comparator circuit performs a hysteresis comparison between the data signal and the hysteresis interval, thereby causing the output terminal of the hysteresis comparator circuit to output the data reading result.

[0033] In summary, this application provides a magnetic memory and a method for reading data from the magnetic memory. The magnetic memory includes a read signal generation circuit, a hysteresis comparator circuit, and a switching timing circuit. The read signal generation circuit includes a data magnetic memory unit and a reference magnetic memory unit. The data magnetic memory unit generates a data signal, and the reference magnetic memory unit generates a reference signal. The hysteresis comparator circuit uses the reference signal to determine the hysteresis interval. To prevent the flip state of the previous data read from affecting the next read, before each data read, the switching timing circuit resets the output of the hysteresis comparator circuit to a first logic signal. Then, based on the hysteresis characteristics of the hysteresis comparator circuit, the input data signal is compared with the hysteresis interval determined by the reference signal. Based on the result of the hysteresis comparison, the output of the hysteresis comparator circuit generates the data read result. Since the hysteresis interval is determined by the reference signal, and the hysteresis characteristics of the hysteresis comparator circuit, such as eliminating output oscillations and resisting noise interference, allow the hysteresis interval to effectively represent the reference signal jointly generated by the two conventional reference branches. Firstly, when designing the reference signal, data reading only requires one reference magnetic storage unit in one reference branch. Compared to the traditional configuration of two reference magnetic storage units in two reference branches, this reduces the number of reference branches and reference magnetic storage units, significantly reducing the layout area of ​​the magnetic memory. Secondly, the use of a hysteresis comparator circuit reduces the number of reference branches, decreasing the need to generate and maintain multiple reference signals, thereby reducing power consumption during data reading. Thirdly, during data reading, the hysteresis comparator circuit eliminates output oscillations and noise interference, improving the accuracy and stability of data reading. Furthermore, the reset operation before each data reading ensures the consistency of the initial state of the hysteresis comparator circuit, further enhancing the accuracy and stability of data reading. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0035] Figure 1 This is a schematic diagram illustrating an application scenario of a magnetic storage device provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the structure of a magnetic storage device provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the circuit structure of the hysteresis comparator provided in the embodiments of this application;

[0038] Figure 4 A schematic diagram showing the relationship between the reference voltage, data voltage and hysteresis interval when the reference magnetic storage cell is in a low-resistance state and the hysteresis comparator circuit has a clockwise transmission characteristic curve, as provided in an embodiment of this application.

[0039] Figure 5 A schematic diagram showing the relationship between the reference voltage, data voltage and hysteresis interval when the reference magnetic storage cell is in a low-resistance state and the hysteresis comparator circuit has a counterclockwise transmission characteristic curve, as provided in an embodiment of this application.

[0040] Figure 6 A schematic diagram showing the relationship between the reference voltage, data voltage and hysteresis interval when the reference magnetic storage cell is in a high-resistivity state and the hysteresis comparator circuit has a clockwise transmission characteristic curve, as provided in an embodiment of this application.

[0041] Figure 7 A schematic diagram showing the relationship between the reference voltage, data voltage and hysteresis interval when the reference magnetic storage cell is in a high-resistivity state and the hysteresis comparator circuit has a counterclockwise transmission characteristic curve, as provided in an embodiment of this application.

[0042] Figure 8 A schematic diagram illustrating the mapping relationship between the switching states of the first and second switching units of a magnetic storage device and the data reading method flow, provided for an embodiment of this application;

[0043] Figure 9 A schematic diagram of the circuit structure and signal flow of a magnetic storage device provided in an embodiment of this application;

[0044] Figure 10 A schematic diagram of the read signal generation circuit structure and signal flow of a magnetic storage device provided in an embodiment of this application;

[0045] Figure 11 A schematic diagram of the read signal generation circuit structure and signal flow of another magnetic storage device provided in this application embodiment;

[0046] Figure 12 A general architecture diagram of a magnetic storage device provided for an embodiment of this application;

[0047] Figure 13 This is a flowchart illustrating a data reading method for a magnetic storage device provided in an embodiment of this application.

[0048] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0049] To facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and purpose. For example, the first input terminal and the second input terminal are merely used to distinguish different input terminals and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0050] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0052] Magnetic memory has a non-volatile magnetic storage array. When reading data, the magnetic storage array usually relies on a sensitive amplifier to compare the voltage or current of the data bit and the reference bit. The generation of the reference voltage requires area and power consumption, and different methods have different costs.

[0053] In one possible implementation, data reading is based on a self-reference method. Specifically, one data branch and two parallel reference branches are set up. The data branch includes a data magnetic storage unit for generating data signals, and each reference branch includes a reference magnetic storage unit. The two reference magnetic storage units jointly generate a reference signal. During the data writing stage, two adjacent magnetic storage units can be written with opposite data states, one as a data bit and the other as a reference bit. During data reading, the actual stored data is determined by differential comparison between the data signals of these two adjacent bits and the reference signal, thereby realizing data reading.

[0054] However, since storing each data magnetic storage unit requires two reference magnetic storage units, this doubles the area of ​​the storage array, thus significantly increasing the area cost.

[0055] In another possible implementation, data reading is based on a mutual reference method. Specifically, an average voltage or average current representing data "1" and "0" is designed in the magnetic storage array. Multiple data bits share the average voltage or average current. During data reading, the stored information is determined by comparing the data of each magnetic storage cell with the magnitude of the average voltage or average current. Since multiple data bits share the same reference, the area cost is reduced.

[0056] However, the process of generating an average voltage or average current each time data is read increases the power consumption of the magnetic storage array, which is twice that of the self-reference method. Therefore, the power consumption of data reading using the mutual reference method is high.

[0057] The above methods reveal that magnetic storage arrays typically rely on a sensitive amplifier to compare the voltage or current between the data bits and the reference bits during data reading. However, generating the reference voltage involves certain area and power consumption overhead, and current technologies struggle to optimize both aspects simultaneously.

[0058] To address the aforementioned issues, this application provides a magnetic memory that, by introducing a hysteresis comparator circuit and a switching timing circuit, saves the layout area of ​​the reference branch, reduces the power consumption of the reference branch during data reading, and improves the accuracy and stability of data reading.

[0059] It should be noted that the magnetic storage provided in this application can be applied to various application scenarios, including embedded systems, industrial control, automotive electronics, and IoT devices. For example, its application in IoT devices is used as an example. Figure 1 This is a schematic diagram illustrating an application scenario of a magnetic storage device provided in an embodiment of this application, such as... Figure 1As shown, the terminal device 200 reads data through its internal magnetic memory 100, which includes a read signal generation circuit, a hysteresis comparison circuit, and a switching timing circuit.

[0060] When reading data from a specific data magnetic storage cell in a row, that data magnetic storage cell generates a data signal, which is then input to the switching timing circuit. Correspondingly, the reference magnetic storage cell for that row generates a reference signal, which is input to the first input terminal of the hysteresis comparator circuit. The hysteresis range of the hysteresis comparator circuit is determined by the reference signal.

[0061] It should be noted that the hysteresis interval can be determined by identifying its midpoint and width. The midpoint of the hysteresis interval can be determined using a reference signal, while the width of the interval in the hysteresis comparator circuit is determined by the threshold adjustment module within the hysteresis comparator circuit (specifically, by the ratio of the two resistors in the threshold adjustment module). The ratio of the two resistors in the threshold adjustment module is also determined by the reference signal; therefore, it can be understood that the hysteresis interval is determined by the reference signal.

[0062] Furthermore, the switching timing circuit inputs the data signal to the second input terminal of the hysteresis comparator circuit, so that the hysteresis comparator circuit can use its hysteresis characteristics to compare the input data signal with the hysteresis interval determined by the reference signal. Then, the hysteresis comparator circuit generates a data reading result and outputs it based on the result of the hysteresis comparison. This data reading result reflects the state of the data signal relative to the reference signal, thereby realizing data reading.

[0063] It is understandable that the terminal device 200 uses the above method to read data from the data magnetic storage units on different rows or columns, and displays the data reading results on the terminal device 200 for the user to view.

[0064] Before the data in the magnetic storage unit is read, the switching timing circuit resets the output of the hysteresis comparator circuit to the first logic signal. This step ensures that the hysteresis comparator circuit starts the comparison operation in a known initial state, avoiding interference from the previous data reading.

[0065] It should be noted that the specific application scenarios of the magnetic storage 100 are not limited in the embodiments of this application; the above are merely illustrative examples.

[0066] For example, Figure 2 This is a schematic diagram of the structure of the magnetic storage device provided in the embodiments of this application, as shown below. Figure 2 As shown, the magnetic storage 100 includes a read signal generation circuit 101, a hysteresis comparison circuit 102, and a switching timing circuit 103 that are electrically connected to each other;

[0067] The read signal generation circuit 101 includes a data magnetic storage unit 11 for generating data signals and a reference magnetic storage unit 12 for generating reference signals. The read signal generation circuit 101 inputs the data signal into the switching timing circuit 103 and inputs the reference signal into the first input terminal of the hysteresis comparison circuit 102 to determine the hysteresis range of the hysteresis comparison circuit 102 through the reference signal.

[0068] The switching timing circuit 103 is used to reset the output of the hysteresis comparator circuit 102 to the first logic signal before each data read, and then input the data signal to the second input of the hysteresis comparator circuit 102, so that the hysteresis comparator circuit 102 performs a hysteresis comparison on the data signal and the hysteresis interval, thereby outputting the data read result at the output of the hysteresis comparator circuit 102.

[0069] This application provides a magnetic memory 100, which includes a read signal generation circuit 101, a hysteresis comparison circuit 102, and a switching timing circuit 103. The read signal generation circuit 101 includes a data magnetic storage unit 11 and a reference magnetic storage unit 12. The data magnetic storage unit 11 generates a data signal, and the reference magnetic storage unit 12 generates a reference signal. The hysteresis comparison circuit 102 uses the reference signal to determine the hysteresis interval. To prevent the flip state of the previous data read from affecting the next read, before each data read, the switching timing circuit 103 resets the output of the hysteresis comparison circuit 102 to a first logic signal. Then, based on the hysteresis characteristics of the hysteresis comparison circuit 102, it compares the input data signal with the hysteresis interval determined by the reference signal. Based on the result of the hysteresis comparison, the output of the hysteresis comparison circuit 102 generates a data read result. Since the hysteresis interval is determined by the reference signal, and the hysteresis characteristics of the hysteresis comparison circuit 102, such as eliminating output oscillation and resisting noise interference, allow the hysteresis interval to effectively represent the reference signal jointly generated by the two conventional reference branches. In this way, firstly, when designing the reference signal, data reading can be achieved using only one reference magnetic storage unit 12 in one reference branch. Compared with the traditional configuration of two reference magnetic storage units in two reference branches, this reduces the number of reference branches and the number of reference magnetic storage units 12, significantly reducing the layout area of ​​the magnetic memory 100. Secondly, the use of the hysteresis comparator circuit 102 reduces the number of reference branches, reducing the need to generate and maintain multiple reference signals, thereby reducing power consumption during data reading. Thirdly, during data reading, the hysteresis comparator circuit 102 can eliminate output oscillations and noise interference, thereby improving the accuracy and stability of data reading. Furthermore, the reset operation before each data reading ensures the consistency of the initial state of the hysteresis comparator circuit 102, further improving the accuracy and stability of data reading.

[0070] In this embodiment, the data signal is used to indicate the data stored in the data magnetic storage unit 11. When data needs to be read, the data magnetic storage unit 11 will convert the stored data into an electrical signal and output it as a data signal. The electrical signal can be characterized by data voltage or data current. This embodiment does not specifically limit the form of the data signal. It should be noted that in the following embodiments, data voltage is used as an example for explanation.

[0071] Accordingly, the reference signal is used to determine the hysteresis interval of the hysteresis comparator circuit 102. The hysteresis interval can refer to the threshold range of the hysteresis comparator circuit 102 when performing signal comparison, which determines the sensitivity and threshold range of the comparison. The embodiments of this application do not specifically limit the method of determining the hysteresis interval based on the reference signal. Optionally, the hysteresis interval can be understood as a window value that lasts for a period of time.

[0072] It is understood that the reference signal can be characterized in the form of a reference voltage or a reference current, and the embodiments of this application do not specifically limit it in this way.

[0073] It should be noted that before each data read, the switching timing circuit 103 resets the output of the hysteresis comparator circuit 102 to the first logic signal. This reset operation ensures that the hysteresis comparator circuit 102 starts working from a known initial state, avoiding the influence of the previous read operation on the current operation. Furthermore, after the reset is completed, the switching timing circuit 103 inputs the data signal to the second input of the hysteresis comparator circuit 102 to provide the data signal to be compared. Then, the hysteresis comparator circuit 102 uses its hysteresis characteristics to compare the data signal with the hysteresis interval determined by the reference signal. Based on the comparison result, the output of the hysteresis comparator circuit 102 generates a data read result, which reflects the state of the data signal relative to the reference signal, thereby realizing data reading.

[0074] The hysteresis characteristic allows the hysteresis comparator circuit 102 to remain stable for a period of time when the data signal is close to the threshold, reducing false judgments. Optionally, the hysteresis comparator circuit 102 can be characterized in the form of a hysteresis comparator. The embodiments of this application do not specifically limit the form of the hysteresis comparator circuit 102. A hysteresis comparator is a special type of comparator circuit that has hysteresis characteristics, which can prevent the output from switching back and forth frequently due to noise or other interference when the input signal is close to the threshold.

[0075] It should be noted that in this application, the switching timing is set by the switching timing circuit 103, which can be used to avoid interference from the previous data reading. For example, if the circuit caches the voltage information read previously, it may directly interfere with subsequent readings. In this application, the data path is disconnected by setting the switching timing between two readings, thereby avoiding interference between the two readings.

[0076] Optionally, the first input terminal can be either a non-inverting input terminal or an inverting input terminal. When the first input terminal is a non-inverting input terminal, the second input terminal is an inverting input terminal. When the first input terminal is an inverting input terminal, the second input terminal is a non-inverting input terminal. Therefore, it can be concluded that the hysteresis comparator circuit 102 can be connected in the correct direction to the read signal generation circuit 101 or in the reverse direction to the read signal generation circuit 101. Correspondingly, when the hysteresis comparator circuit 102 is connected in the correct direction to the read signal generation circuit 101, the hysteresis comparator circuit 102 is connected in the reverse direction to the switching timing circuit 103. When the hysteresis comparator circuit 102 is connected in the reverse direction to the read signal generation circuit 101, the hysteresis comparator circuit 102 is connected in the correct direction to the switching timing circuit 103.

[0077] Taking the hysteresis comparator circuit 102 as an example of a hysteresis comparator, Figure 3 This is a schematic diagram of the circuit structure of the hysteresis comparator provided in the embodiments of this application, as shown below. Figure 3 As shown in Figure A, this is a model diagram of the hysteresis comparator 104. The reference voltage Vref and the data voltage Vdata are connected at different positions, as shown below. Figure 3 As shown in Figure B, this is the positive connection mode of the hysteresis comparator 104. Figure 3 As shown in Figure C, this is the reverse connection mode of the hysteresis comparator 104. The normal connection mode means that the reference voltage Vref is input to the non-inverting input terminal (usually marked "+") of the hysteresis comparator 104, and the data voltage Vdata is input to the inverting input terminal (usually marked "-") of the hysteresis comparator 104. The reverse connection mode means that the reference voltage Vref is input to the inverting input terminal (usually marked "-") of the hysteresis comparator 104, and the data voltage Vdata is input to the non-inverting input terminal (usually marked "+").

[0078] The hysteresis comparator 104 includes a comparator 21 and a threshold adjustment module 22. The threshold adjustment module 22 is used to adjust the threshold of the hysteresis range of the hysteresis comparator 104. The input terminal of the threshold adjustment module 22 serves as the non-inverting input terminal of the hysteresis comparator 104, and the output terminal of the threshold adjustment module 22 is electrically connected to the non-inverting input terminal of the comparator 21. The inverting input terminal of the comparator 21 serves as the inverting input terminal of the hysteresis comparator 104. The threshold adjustment module 22 includes a first resistor R1 and a second resistor R2. The first terminals of both the first resistor R1 and the second resistor R2 are electrically connected to the non-inverting input terminal of the comparator 21. The second terminal of the first resistor R1 serves as the input terminal of the threshold adjustment module 22 and also as the non-inverting input terminal of the hysteresis comparator 104. The second terminal of the second resistor R2 is electrically connected to the output terminal of the comparator 21 and also serves as the output terminal of the hysteresis comparator 104.

[0079] In this way, the threshold adjustment module 22 is set in the hysteresis comparator 104, which is conducive to more precise adjustment of the hysteresis interval of the hysteresis comparator 104. Thus, the hysteresis interval threshold can be adjusted according to the requirements of the reference signal, so that the hysteresis interval can more effectively represent the reference signal, thereby improving the reading stability and accuracy.

[0080] In this application, the data magnetic storage unit 11 and the reference magnetic storage unit 12 generate data signals and reference signals respectively, ensuring the accuracy and stability of the signals. Furthermore, by using the reference signal to set the hysteresis interval, the hysteresis comparison circuit 102 can more accurately determine the state of the data signal, improving the accuracy of data reading. Before each reading, the output of the hysteresis comparison circuit 102 is reset by the control of the switching timing circuit 103, ensuring the consistency of the initial state of the hysteresis comparison circuit 102. This reduces the possibility of misjudgment, avoids interference from the previous data reading operation, and reduces the need for complex control logic. Furthermore, after the hysteresis comparison circuit 102 is reset, the data signal is compared with the hysteresis interval based on the characteristics of the hysteresis comparison circuit 102, thereby outputting a stable data reading result.

[0081] Therefore, based on the characteristics of the hysteresis comparator circuit 102, the hysteresis interval can flexibly represent the traditional reference signal. Thus, during data reading, by resetting before reading, only one reference magnetic storage unit 12 in one reference branch is needed to complete the data reading. Compared to the traditional arrangement of two reference magnetic storage units 12 in two reference branches, this reduces the number of reference branches and reference magnetic storage units, significantly reducing the layout area of ​​the magnetic memory 100. The reduced number of reference branches also reduces the need to generate and maintain multiple reference signals, thereby reducing power consumption during data reading.

[0082] Optionally, when the reference magnetic storage cell 12 is in a low-resistance state, the reference signal it generates is a low-resistance state reference signal; when the reference magnetic storage cell 12 is in a high-resistance state, the reference signal it generates is a high-resistance state reference signal.

[0083] The hysteresis range of the hysteresis comparator circuit 102 is determined by a reference signal, including:

[0084] The threshold value of the hysteresis interval is determined by using the low-resistivity reference signal and the high-resistivity reference signal.

[0085] It should be noted that the hysteresis interval can be determined by determining the midpoint and width of the hysteresis interval. Therefore, the threshold is determined by the midpoint and width of the hysteresis interval. The midpoint is determined by a reference signal (e.g., the average value of the reference signal is set as the midpoint). The width is determined by the threshold adjustment module 22 in the hysteresis comparator circuit 102 (specifically, by the ratio of the two resistors in the threshold adjustment module 22). The ratio of the two resistors in the threshold adjustment module 22 is also determined by the reference signal. Specifically, the ratio of the two resistors in the threshold adjustment module 22 is determined by the low-resistance reference signal and the high-resistance reference signal. Based on this, it can be understood that the threshold is determined by the low-resistance reference signal and the high-resistance reference signal.

[0086] In this embodiment, the reference magnetic storage cell 12 includes a magnetic tunnel junction, which comprises a free layer, a barrier layer, and a reference layer stacked sequentially. The reference magnetic storage cell 12 also includes a spin-orbit moment layer adjacent to the free layer. The data magnetic storage cell 11 similarly includes a magnetic tunnel junction, which comprises a free layer, a barrier layer, and a reference layer stacked sequentially. Both the reference magnetic storage cell 12 and the data magnetic storage cell 11 include spin-orbit moment layers adjacent to the free layer. When a write current is applied to the spin-orbit moment layer, a spin-orbit moment effect occurs, causing the magnetization direction of the free layer to flip or remain unchanged.

[0087] A low-resistance state refers to a magnetic tunnel junction where the magnetization directions of the free layer and the reference layer are parallel, resulting in a low-resistance state for the reference magnetic tunnel junction. For example, when the write current supplied to the spin-orbit layer is less than the critical current threshold, the resistance of the magnetic tunnel junction is less than the critical threshold, and the low-resistance state can be used to represent a logic "0" or "low" signal. A high-resistance state refers to a magnetic tunnel junction where the magnetization directions of the free layer and the reference layer are antiparallel, resulting in a high-resistance state for the reference magnetic tunnel junction. For example, when the write current supplied to the spin-orbit layer is greater than the critical current threshold, the resistance of the magnetic tunnel junction is greater than the critical threshold, and the high-resistance state can be used to represent a logic "1" or "high" signal.

[0088] It should be noted that the embodiments of this application do not specifically limit the size of the critical threshold. The critical threshold can be set based on the characteristics of the reference magnetic storage unit 12 or the characteristics of the circuit.

[0089] Optionally, the low-resistance state can be understood as a parallel state, and the high-resistance state as an anti-parallel state. In magnetic storage, a parallel state typically represents a logic "0" in the memory cell, while an anti-parallel state typically represents the opposite state of the memory cell, mapped to logic "1". Alternatively, a parallel state typically represents a logic "1" in the memory cell, while an anti-parallel state typically represents the opposite state of the memory cell, mapped to logic "0".

[0090] Optionally, the low-impedance reference signal can be represented by a first voltage Vp, the high-impedance reference signal can be represented by a second voltage Vap, and the threshold can be represented by Vh, where Vh = (Vp + Vap) / 2. The threshold Vh can represent either the upper or lower threshold.

[0091] For example, Figure 4 This application provides a schematic diagram illustrating the relationship between the reference voltage, data voltage, and hysteresis interval when the reference magnetic storage cell is in a low-resistance state and the hysteresis comparator circuit has a clockwise transmission characteristic curve. Taking a hysteresis comparator 104 with a clockwise transmission characteristic curve as an example, and the reference voltage Vref as the first reference voltage Vp, as shown... Figure 4 As shown in Figure A, the normal distributions of the reference voltage (or data voltage) generated when the reference magnetic storage unit 12 (or data magnetic storage unit 11) is in a parallel state and an antiparallel state are respectively represented. The average reference voltage (or average data voltage) in the parallel state is the first voltage Vp, and the average reference voltage (or average data voltage) in the antiparallel state is the second voltage Vap. Figure 4 As shown in Figure B, the lower threshold of the hysteresis comparator 104 is Vh1, and the upper threshold is Vh2. A first voltage Vp is set within the hysteresis interval such that Vh1 < Vp < Vh2, and the lower threshold Vh1 and upper threshold Vh2 are symmetrical about the first voltage Vp. The output of the hysteresis comparator 104 is either a high level VDD or a low level VSS. Figure 4As shown in Figure C, the hysteresis interval is set between the first voltage Vp and the second voltage Vap. Furthermore, the threshold value Vh of the hysteresis interval is the upper threshold value Vh2. The threshold value adjustment module is used to make Vh = Vh2 = (Vp + Vap) / 2. The normal distribution curves of the reference magnetic storage unit 12 or the data magnetic storage unit 11 in a parallel state are all less than the upper threshold value Vh2, and the normal distribution curves of the reference magnetic storage unit 12 or the data magnetic storage unit 11 in an anti-parallel state are all greater than the upper threshold value Vh2. The upper threshold value Vh2 designed above can completely distinguish between the first voltage Vp and the second voltage Vap of the data magnetic storage unit 11. That is, by simply comparing the data voltage with the upper threshold value Vh2, it can be determined whether the data voltage is the first voltage Vp or the second voltage Vap, thereby allowing the data in the data magnetic storage unit 11 to be read.

[0092] Optionally, taking hysteresis comparator 104 as an example, hysteresis comparator circuit 102 is used. Figure 3 As shown, by adjusting the ratio of the first resistor R1 and the second resistor R2, the threshold value Vh of the hysteresis comparator 104 can be determined so that Vh = (Vp + Vap) / 2.

[0093] Optionally, the first resistor R1 and the second resistor R2 satisfy the following formula:

[0094]

[0095] Wherein, the reference voltage Vref is set as the first voltage Vp, Vcc is the power supply voltage applied to the hysteresis comparator 104, and Vref is the voltage at the input terminal of the hysteresis comparator 104. As long as the first resistor R1 and the second resistor R2 satisfy the above formula, then Vh = (Vp + Vap) / 2 can be satisfied.

[0096] It should be noted that the ratio of the first resistor R1 and the second resistor R2 may not be an integer. The first resistor R1 and the second resistor R2 are each composed of multiple small resistors with the same resistance value connected in series. Therefore, one or both of the first resistor R1 and the second resistor R2 can be set as fine-tuning resistors to deal with the effects of parasitics and processes.

[0097] It should also be noted that when the reference signal is Vp, the threshold Vh is the upper threshold Vh2, and when the reference signal is Vap, the threshold Vh is the lower threshold Vh1. In this way, the hysteresis interval determined by the upper or lower threshold can represent the traditional reference signal.

[0098] It should be noted that the hysteresis interval can be determined by determining the midpoint and width of the hysteresis interval. Therefore, the threshold is determined by the midpoint and width of the hysteresis interval. The midpoint is determined by a reference signal (e.g., the average value of the reference signal is set as the midpoint), and the width is determined by the ratio of the first resistor R1 and the second resistor R2. The ratio of the first resistor R1 and the second resistor R2 is also determined by the reference signal (i.e., the low-resistance reference signal and the high-resistance reference signal). Based on this, it can be understood that the threshold is determined by the low-resistance reference signal and the high-resistance reference signal.

[0099] Furthermore, in the actual process, if the low-resistance reference signal and the high-resistance reference signal are inconsistent with the design due to process errors, and the threshold determined based on the ratio of the first resistor R1 and the second resistor R2 cannot meet the reading requirements, the resistance values ​​of the first resistor R1 and the second resistor R2 can be further adjusted according to the actual needs so that the ratio of the first resistor R1 and the second resistor R2 meets the threshold required for actual reading.

[0100] In this way, by using clearly defined low-resistance and high-resistance reference signals, the threshold of the hysteresis interval can be precisely set, improving the accuracy of signal comparison. Furthermore, by generating reference signals using different resistance states of the reference magnetic storage cell 12, effective signal comparison can be achieved with only one reference branch, simplifying circuit design. Since only one reference branch is needed, unnecessary circuit complexity and power consumption are reduced. During data reading, the hysteresis comparator circuit 102 can eliminate output oscillations and resist noise interference, thereby improving the accuracy and stability of data reading. In addition, by adjusting the resistance state of the reference magnetic storage cell 12, the threshold of the hysteresis interval can be flexibly changed, allowing the magnetic memory 100 to adapt to different application requirements.

[0101] Optionally, the hysteresis comparator circuit 102 performs a hysteresis comparison between the data signal and the hysteresis interval, thereby causing the output terminal of the hysteresis comparator circuit 102 to output the data reading result, including:

[0102] If the data signal is greater than the threshold, the data reading result is flipped from the first logic signal to the second logic signal; or, if the data signal is less than the threshold, the data reading result remains the first logic signal.

[0103] The first logic signal represents the opposite logic to the second logic signal.

[0104] It should be noted that the hysteresis characteristic means that the hysteresis comparator circuit 102 has different threshold values ​​when the signal rises and falls. Therefore, the threshold values ​​have an upper threshold value and a lower threshold value.

[0105] It is understood that the first logic signal and the second logic signal are opposite. For example, the first logic signal can be a high level or logic "1", while the second logic signal is a low level or logic "0". The first logic signal can also be a low level or logic "0", while the second logic signal can be a high level or logic "1". The embodiments of this application do not limit the specific form of the logic signal.

[0106] Optionally, different resistive states of the reference magnetic storage cell and / or different states of the reference signal will result in different data reading results.

[0107] For example, such as Figure 4 As shown in Figure C, taking a hysteresis comparator 104 with a clockwise transmission characteristic curve and a reference voltage Vref equal to the first voltage Vp as an example, the first logic signal is represented by a high level VDD or logic "1", the second logic signal is represented by a low level VSS or logic "0", and the threshold Vh of the hysteresis interval is the upper threshold Vh2. Before data reading, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a high level VDD, that is, sets the output of the hysteresis comparator 104 to logic "1", thus resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again, compares the data voltage Vdata with the upper threshold Vh2. If the data voltage Vdata is greater than the upper threshold Vh2, the output terminal is flipped from the first logic signal (i.e., high level VDD or logic "1") to the second logic signal (i.e., low level VSS or logic "0"). If the data voltage Vdata is less than the upper threshold Vh2, the output terminal maintains the first logic signal (i.e., high level VDD or logic "1").

[0108] For example, Figure 5 A schematic diagram illustrating the relationship between the reference voltage, data voltage, and hysteresis interval when the reference magnetic storage cell is in a low-resistance state and the hysteresis comparator circuit has a counterclockwise transfer characteristic curve, as provided in the embodiments of this application, is shown below. Figure 5As shown, taking a hysteresis comparator 104 with a counterclockwise propagation characteristic curve and a reference voltage Vref equal to the first voltage Vp as an example, the first logic signal is represented by a low level VSS or logic "0", the second logic signal is represented by a high level VDD or logic "1", and the threshold Vh of the hysteresis interval is the upper threshold Vh2. Before data reading, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a low level VSS, that is, sets the output of the hysteresis comparator 104 to logic "0", thus resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata, compares the data voltage Vdata with the upper threshold Vh2. If the data voltage Vdata is greater than the upper threshold Vh2, the output terminal is flipped from the first logic signal (i.e., low level VSS or logic "0") to the second logic signal (i.e., high level VDD or logic "1"). If the data voltage Vdata is less than the upper threshold Vh2, the output terminal maintains the first logic signal (i.e., low level VSS or logic "0").

[0109] For example, Figure 6 A schematic diagram illustrating the relationship between the reference voltage, data voltage, and hysteresis interval when the reference magnetic storage cell is in a high-impedance state and the hysteresis comparator circuit has a clockwise transfer characteristic curve, as provided in this application embodiment, is shown below. Figure 6 As shown, taking a hysteresis comparator 104 with a clockwise transmission characteristic curve and a reference voltage Vref equal to the second voltage Vap as an example, the first logic signal is represented by a high level VDD or logic "1", the second logic signal is represented by a low level VSS or logic "0", and the threshold Vh of the hysteresis interval is the lower threshold Vh1. Before data reading, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a high level VDD, that is, sets the output of the hysteresis comparator 104 to logic "1", thus resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again, compares the data voltage Vdata with the lower threshold Vh1. If the data voltage Vdata is less than the lower threshold Vh1, the output terminal maintains the first logic signal (high level VDD or logic "1"). If the data voltage Vdata is greater than the lower threshold Vh1, the output terminal is flipped from the first logic signal (i.e., high level VDD or logic "1") to the second logic signal (i.e., low level VSS or logic "0").

[0110] Compared to existing single-threshold comparators, where the output signal may frequently flip due to noise, such as small fluctuations, in the input signal near the threshold, leading to incorrect logic judgments, this application improves the noise immunity of the hysteresis comparator circuit 102 by setting a threshold value. Even if the input data signal fluctuates with noise near the threshold, as long as the noise fluctuation does not exceed the hysteresis range, the output will not erroneously flip, thus improving noise immunity and avoiding output signal jitter. This makes the output of the hysteresis comparator circuit 102 more stable. Furthermore, the impedance state of the corresponding reference magnetic storage unit 12 and the transfer characteristic curve of the hysteresis comparator circuit 102 can be adjusted according to the required data voltage magnitude and the correspondence between the first and second logic signals generated at the output terminal, thereby improving the flexibility of circuit design.

[0111] Optionally, the hysteresis comparator circuit 102 performs a hysteresis comparison between the data signal and the hysteresis interval, thereby causing the output terminal of the hysteresis comparator circuit 102 to output the data reading result, including:

[0112] If the data signal is less than the threshold, the data reading result is flipped from the first logic signal to the second logic signal; or, if the data signal is greater than the threshold, the data reading result remains the first logic signal.

[0113] The first logic signal represents the opposite logic to the second logic signal.

[0114] For example, Figure 7 A schematic diagram illustrating the relationship between the reference voltage, data voltage, and hysteresis interval when the reference magnetic storage cell is in a high-impedance state and the hysteresis comparator circuit has a counterclockwise transfer characteristic curve, as provided in the embodiments of this application, is shown below. Figure 7As shown, taking a hysteresis comparator 104 with a counter-clockwise propagation characteristic curve and a reference voltage Vref equal to the second voltage Vap as an example, the first logic signal is represented by a high level VDD or logic "1", the second logic signal is represented by a low level VSS or logic "0", and the threshold Vh of the hysteresis interval is the lower threshold Vh1. Before data reading, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a high level VDD, that is, sets the output of the hysteresis comparator 104 to logic "0", thus resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again, compares the data voltage Vdata with the lower threshold Vh1. If the data voltage Vdata is less than the lower threshold Vh1, the output terminal is flipped from the first logic signal (i.e., high level VDD or logic "1") to the second logic signal (i.e., low level VSS or logic "0"). If the data voltage Vdata is greater than the lower threshold Vh1, the output terminal maintains the first logic signal (high level VDD or logic "1").

[0115] Understandably, if the input signal fluctuates around a single threshold, such as due to noise interference, existing comparators may frequently toggle their output, leading to logic errors. This application employs a hysteresis interval; by setting the threshold, the output only toggles when the data signal falls below the threshold. Thus, even if the input signal fluctuates slightly around the threshold, as long as it doesn't exceed the hysteresis interval, the output won't erroneously toggle, thereby improving noise immunity and avoiding false triggering caused by noise or small fluctuations. Furthermore, since the hysteresis characteristic ensures that the output only changes its toggle state when the data signal clearly crosses the hysteresis interval, unnecessary toggles can be reduced, thereby lowering the overall power consumption of the magnetic memory 100. In addition, the impedance state of the corresponding reference magnetic memory cell 12 and the transfer characteristic curve of the hysteresis comparator circuit 102 can be adjusted according to the correspondence between the required data voltage and the first and second logic signals generated at the output, thereby improving the flexibility of circuit design.

[0116] Optionally, the switching timing circuit 103 includes a first switching unit and a second switching unit;

[0117] The first switching unit is electrically connected to the second input terminal of the read signal generation circuit 101 and the hysteresis comparison circuit 102; the second switching unit is electrically connected to the second input terminal of the hysteresis comparison circuit 102; the output terminal of the hysteresis comparison circuit 102 is reset to the first logic signal by controlling the on / off state of the first and second switching units, or the data signal is input to the second input terminal of the hysteresis comparison circuit 102 by controlling the on / off state of the first and second switching units.

[0118] In this embodiment, one end of the second switching unit is electrically connected to the second input terminal of the hysteresis comparator circuit 102, and the other end is grounded (GND). Taking the hysteresis comparator circuit 102 as a hysteresis comparator 104 as an example, when the first switching unit is in the open state and the second switching unit is in the closed state, the second input terminal of the hysteresis comparator 104 is grounded to GND so that the output terminal of the hysteresis comparator 104 is reset to the first logic signal. When the first switching unit is in the closed state and the second switching unit is in the open state, the second input terminal of the hysteresis comparator 104 is electrically connected to the read signal generation circuit 101 so that the data signal is input to the second input terminal of the hysteresis comparator 104.

[0119] It should be noted that, in order to prevent the flip state of the previous read from affecting the next data read, the on / off state of the first and second switching units needs to be controlled before each data read to set the input voltage to the initial unflipped level, so that the output of the hysteresis comparator circuit 102 is reset to the first logic signal.

[0120] It should also be noted that the specific switching types of the first switching unit and the second switching unit are not limited in the embodiments of this application. Optionally, the first switching unit and the second switching unit can be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), complementary metal-oxide-semiconductor switches (CMOS), solid-state relays (SSRs), transmission gates, etc.

[0121] For example, Figure 8 A schematic diagram illustrating the mapping relationship between the switching states of the first and second switching units of a magnetic storage device and the data reading method flow, provided in an embodiment of this application, is shown below. Figure 8As shown, data reading is implemented using a parallel magnetic tunnel junction (MTJ) unit. Taking the first switch unit (S1) and the second switch unit (S2) as an example, in step S801, before each data reading, by controlling the first switch S1 to be closed and the second switch S2 to be open, the input signal at the second input terminal of the hysteresis comparator circuit 102 is grounded, thereby resetting the output terminal of the hysteresis comparator circuit 102 to the first logic signal. Further, in step S802, the first switch S1 is controlled to be open and the second switch S2 to be closed, thereby controlling the data signal input to the second input terminal of the hysteresis comparator circuit 102. In step S803, the first switch S1 remains open and the second switch S2 remains closed, and the data signal is compared with the hysteresis interval to obtain the data reading result.

[0122] In this way, by independently controlling the on / off state of the two switching units, the circuit's operating mode can be flexibly switched, placing it in reset mode or data reading mode. This dual-switch design isolates the data signal and data reading result from the previous data reading from the current data reading, preventing interference from the previous data reading. In addition, by controlling the on / off state of the input signal through the two switching units, it can also ensure that the hysteresis comparator circuit is not affected by external noise during reset, avoiding false triggering.

[0123] Optional, such as Figure 9 As shown, the read signal generation circuit 101 includes: a reference signal generation module 13 and a data signal generation module 14;

[0124] The reference signal generation module 13 is electrically connected to the first input terminal of the hysteresis comparator circuit 102. The reference signal generation module 13 includes at least one reference magnetic storage unit 12, which is used to generate and output a reference signal.

[0125] The data signal generation module 14 is electrically connected to the second input terminal of the hysteresis comparator circuit 102 via the switching timing circuit 103. The data signal generation module 14 includes at least one data magnetic storage unit 11 for generating and outputting data signals.

[0126] For example, Figure 9 A schematic diagram of the circuit structure and signal flow of a magnetic storage device provided in an embodiment of this application is shown below. Figure 9As shown, taking the hysteresis comparator 104 as an example, the read signal generation circuit 101 includes a reference signal generation module 13 and a data signal generation module 14. The reference signal generation module 13 is electrically connected to the first input terminal of the hysteresis comparator 104 and is used to generate and output a reference signal to the hysteresis comparator 104. The data signal generation module 14 is electrically connected to the second input terminal of the hysteresis comparator 104 through a first switching unit and is used to generate and output a data signal to the hysteresis comparator 104. Furthermore, based on the switching timing settings of the hysteresis comparator 104, the data is read out.

[0127] Optionally, the reference signal generation module 13 has a reference magnetic storage unit 12 for generating a reference signal, and the data signal generation module 14 has a data magnetic storage unit 11 for generating a data signal.

[0128] It is understandable that the comparator in the magnetic memory 100 is designed as a hysteresis comparator 104 so that the reference signal generation module 13 only needs a reference magnetic memory unit 12 in one state to generate the reference signal required for reading. However, the reading process requires the cooperation of the first switching unit and the second switching unit.

[0129] For example, Figure 10 This application provides a schematic diagram of the read signal generation circuit structure and signal flow of a magnetic storage device, as shown in the embodiment of the present application. Figure 10 As shown, taking the hysteresis comparator 104 as an example, the reference signal generation module 13 includes at least one reference magnetic storage unit 12. One end of the reference magnetic storage unit 12 is connected to the first transistor 15, the second transistor 16 and the third transistor 17 in sequence. The other end of the reference magnetic storage unit 12 is grounded through the fourth transistor 18. The third transistor 17 is used to determine the path of current flow in the circuit, the second transistor 16 is used for column selection, the first transistor 15 is used to isolate or transmit signals to the hysteresis comparator 104, and the fourth transistor 18 is used to control the data writing direction.

[0130] The data signal generation module 14 includes at least one data magnetic storage unit 11. One end of the data magnetic storage unit 11 is connected to the fifth transistor 19, the sixth transistor 20 and the seventh transistor 23 in sequence. The other end of the data magnetic storage unit 11 is grounded through the eighth transistor 24. The seventh transistor 23 has a similar function to the third transistor 17, the sixth transistor 20 has a similar function to the second transistor 16, the fifth transistor 19 has a similar function to the first transistor 15, and the eighth transistor 24 has a similar function to the fourth transistor 18. These functions will not be described in detail here.

[0131] Optionally, the first transistor 15, the second transistor 16, the fourth transistor 18, the fifth transistor 19, the sixth transistor 20 and the eighth transistor 24 are N-type metal-oxide-semiconductor field-effect transistors, and the third transistor 17 and the seventh transistor 23 are P-type metal-oxide-semiconductor field-effect transistors.

[0132] The first input terminal of the hysteresis comparator 104 is electrically connected to the connection terminal of the third transistor 17 and the seventh transistor 23. In fact, it is connected to the gate of the third transistor 17, but there is no direct electrical connection. The second input terminal of the hysteresis comparator 104 is electrically connected to the gate of the seventh transistor 23 based on the first switching unit (taking the second switch S2 as an example in the figure).

[0133] It is understandable that the first input of the hysteresis comparator 104 can also have other connection methods, for example, Figure 11 A schematic diagram of the read signal generation circuit structure and signal flow of another magnetic storage device provided in this application embodiment is shown below. Figure 11 As shown, with Figure 10 The difference is that the first input of the hysteresis comparator 104 is directly connected to the gate of the third transistor 17, and the read link also needs to be connected to an external bias voltage.

[0134] In this way, the design of separating the reference signal generation module 13 and the data signal generation module 14 and connecting them to the hysteresis comparator circuit 102 respectively can share some current paths, such as the bias circuit, thereby reducing the total power consumption. Furthermore, since the reference signal generation module 13 and the data signal generation module 14 can be set independently, they can be adapted to different storage states, such as the parallel state and antiparallel state of the magnetic tunnel junction.

[0135] Optionally, the data signal generation module 14 includes multiple data magnetic storage units 11;

[0136] Each data magnetic storage unit 11 generates a corresponding data signal that is electrically connected to the second input terminal of the hysteresis comparator circuit 102, so that multiple data signals share the same reference signal.

[0137] It should be noted that each data magnetic storage unit 11 generates a corresponding data signal that is electrically connected to the hysteresis comparator circuit 102. This means that each data magnetic storage unit 11 can be electrically connected to the hysteresis comparator circuit 102 through row selection or column selection, so that multiple data magnetic storage units 11 can share the same hysteresis comparator circuit 102.

[0138] For example, taking the reference magnetic storage cell 12 as a magnetic tunnel junction, the magnetic tunnel junction can generate a stable reference signal (e.g., reference voltage Vref) and input the reference signal to the first input terminal of the hysteresis comparator 104. Multiple data magnetic storage cells 11, such as the data magnetic storage cells 11 in parallel state in the magnetic memory 100, generate their own data signals (e.g., data voltage Vdata). Further, through the data signal generation module 14 and the switching timing circuit 103, they are sequentially connected to the second input terminal of the hysteresis comparator 104. The hysteresis comparator 104 performs a hysteresis comparison between each data signal (e.g., data voltage Vdata) and the hysteresis interval determined by the reference signal (e.g., reference voltage Vref), and outputs the corresponding logic signal "0" or "1".

[0139] It is understandable that existing magnetic storage devices 100 typically require at least two reference branches for data reading, each including a reference magnetic storage cell 12. One reference magnetic storage cell 12 is in a parallel state, and the other is in an antiparallel state. However, this application, based on a hysteresis comparator circuit design, only requires one reference magnetic storage cell 12. That is, data reading can be achieved by multiple data magnetic storage cells 11 sharing the same reference signal. The reference magnetic storage cell 12 required in this application can be in either a parallel or antiparallel state, such as... Figure 12 The array shown in this application embodiment does not specifically limit the state of the reference magnetic storage unit 12.

[0140] Therefore, multiple data magnetic storage units 11 share the same reference signal, meaning that when reading data, the reference magnetic storage unit has only one reference branch, reducing redundant reference magnetic storage units 12 and thus saving layout area. Furthermore, the reference signal path only needs to generate a reference signal once, which can compare multiple data signals in a time-division manner, reducing the current generated by the reference voltage and thus reducing reading power consumption. In addition, multiple data magnetic storage units 11 using the same reference signal as a reference can also avoid logical misjudgments caused by fluctuations in the reference signal.

[0141] Optionally, the reference magnetic storage cell 12 includes a magnetic tunnel junction, which includes a free layer, a barrier layer, and a reference layer stacked sequentially.

[0142] In the reference magnetic storage cell 12, the magnetization directions of the free layer and the reference layer are parallel, or the magnetization directions of the free layer and the reference layer are antiparallel.

[0143] It should be noted that the magnetic memory 100 uses the tunneling magnetoresistance (TMR) effect to realize data storage. Its basic unit is the magnetic tunnel junction. The magnetic memory 100 determines the stored data value by measuring the resistance of the magnetic tunnel junction in order to read the data.

[0144] In this application, the magnetic tunnel junction is composed of three stacked layers: a free layer, a barrier layer, and a reference layer. The magnetization direction of the free layer can be changed by an external magnetic field or current. The barrier layer is an insulating layer, and its thickness affects the tunneling magnetoresistance effect. The magnetization direction of the reference layer is fixed.

[0145] Therefore, when the magnetization directions of the free layer and the reference layer are parallel (i.e., the directions are the same), it indicates that the reference magnetic storage cell is in a low-resistivity state. When the magnetization directions of the free layer and the reference layer are antiparallel (i.e., the directions are opposite), it indicates that the reference magnetic storage cell 12 is in a high-resistivity state. Thus, when the magnetization directions of the free layer and the reference layer are parallel, a low-resistivity reference signal can be generated, and when the magnetization directions of the free layer and the reference layer are antiparallel, a high-resistivity reference signal can be generated.

[0146] It is understood that by designing the reference magnetic storage cell 12 as described above, the magnetization state of the reference magnetic storage cell 12 is not affected by read and write operations, thereby providing a long-term stable reference signal. Moreover, the method of this application can be applied regardless of whether the reference magnetic storage cell 12 is in a parallel or antiparallel state, which greatly improves the flexibility of the application. In addition, the reference magnetic storage cell 12 is designed with a fixed magnetization direction, which eliminates the need for a circuit to dynamically adjust the reference signal, simplifying the circuit design and control logic of the magnetic memory.

[0147] Optionally, when there are multiple data magnetic storage units 11, reference magnetic storage units 12, and hysteresis comparator circuits 102, the data magnetic storage units 11 are configured to be arranged in multiple columns in an array, and the reference magnetic storage units 12 are configured to be arranged in at least one column in an array.

[0148] In this configuration, the data signal generated by each row of data magnetic storage unit 11 is input to the second input terminal of the hysteresis comparison circuit 102 corresponding to each row, and the reference signal generated by each row of reference magnetic storage unit 12 is input to the first input terminal of the same hysteresis comparison circuit 102 corresponding to each row, so that each row of data magnetic storage unit 11 shares the same reference magnetic storage unit 12.

[0149] For example, Figure 12 A general architecture diagram of a magnetic storage device provided in this application embodiment is shown below. Figure 12As shown, the data magnetic storage unit 11 has N columns, the reference magnetic storage unit 12 has 1 column, and both the data magnetic storage unit 11 and the reference magnetic storage unit 12 have M rows. Each row of data magnetic storage unit 11 shares the reference signal generated by the corresponding reference magnetic storage unit 12. M is a natural number greater than 1, and N is a natural number greater than 1.

[0150] Optionally, in addition to the read signal generation circuit 101, the hysteresis comparison circuit 102, and the switching timing circuit 103, the magnetic memory 100 also includes a word line selection module 105, a drive module 106, and a bit line selection module 107.

[0151] It should be noted that the reference magnetic storage unit 12 does not necessarily have to be the same as... Figure 12 As shown, it is located on the far right of the array, and it can be in any column. In this embodiment of the application, the deployment position of the reference magnetic storage unit 12 is not specifically limited.

[0152] Therefore, each row of data magnetic storage unit 11 shares one reference magnetic storage unit 12, which can greatly save area compared to each column requiring an independent column of reference magnetic storage units 12. Moreover, each row only requires one hysteresis comparator circuit 102, instead of one hysteresis comparator circuit 102 per column, which can significantly reduce the area of ​​analog circuits. In addition, the same hysteresis comparator circuit 102 can process multiple columns of data in a time-sharing manner, reducing repetitive current paths and lowering power consumption.

[0153] It is understood that the data reading method of the magnetic memory provided in this application can be applied to the magnetic memory 100 that only requires adjusting the resistance state of the reference magnetic memory cell 12.

[0154] For example, this application also provides a data reading method for a magnetic storage device, applied to a magnetic storage device 100 as described in any of the above embodiments; Figure 13 This is a flowchart illustrating a data reading method for a magnetic storage device provided in an embodiment of this application, as shown below. Figure 13 As shown, the data reading method of this magnetic storage device includes the following steps:

[0155] S1301. Before each data read, reset the output of the hysteresis comparator to the first logic signal;

[0156] S1302. Input a data signal to the second input terminal of the hysteresis comparator circuit so that the hysteresis comparator circuit performs a hysteresis comparison on the data signal and the hysteresis interval, thereby causing the output terminal of the hysteresis comparator circuit to output the data reading result.

[0157] It should be noted that the specific implementation principle and effect of the above-mentioned magnetic storage data reading method can be found in the relevant description and effect of the above embodiments, and will not be elaborated further here.

[0158] In the embodiments provided in this application, it should be understood that the disclosed modules and methods can be implemented in other ways. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between modules may be electrical, mechanical, or other forms.

[0159] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0160] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit composed of the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0161] It should be understood that the aforementioned magnetic storage device can be a magnetic random access memory or a non-volatile memory (NVM), such as at least one disk storage device, or a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0162] The array of magnetic storage cells described above can be located in any type of non-volatile storage device or combination thereof, such as electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), flash memory, magnetic disk, or optical disk.

[0163] The aforementioned magnetic storage can also be applied to application-specific integrated circuits (ASICs), but this application does not specifically limit this application.

[0164] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0165] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0166] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0167] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0168] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A magnetic memory, comprising: The read signal generating circuit, the hysteresis comparison circuit and the switch timing circuit are electrically connected to each other; The read signal generating circuit includes a data magnetic storage unit for generating a data signal and a reference magnetic storage unit for generating a reference signal; the read signal generating circuit inputs the data signal into the switch timing circuit and inputs the reference signal into a first input end of the hysteresis comparison circuit to determine a hysteresis interval of the hysteresis comparison circuit through the reference signal; The switch timing circuit is configured to reset an output end of the hysteresis comparison circuit to a first logic signal before each data read, and then input the data signal into a second input end of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, and the output end of the hysteresis comparison circuit outputs a data read result; When the reference magnetic storage unit is in a low resistance state, the reference signal generated thereby is a low resistance state reference signal; when the reference magnetic storage unit is in a high resistance state, the reference signal generated thereby is a high resistance state reference signal; The determination of the hysteresis interval of the hysteresis comparison circuit through the reference signal includes: The determination of a threshold of the hysteresis interval through the low resistance state reference signal and the high resistance state reference signal.

2. The magnetic memory of claim 1 wherein, The hysteresis comparison of the hysteresis comparison circuit on the data signal and the hysteresis interval, so that the output end of the hysteresis comparison circuit outputs a data read result, includes: In a case where the data signal is greater than the threshold, the data read result is flipped from the first logic signal to a second logic signal; or, in a case where the data signal is less than the threshold, the data read result remains the first logic signal; The first logic signal and the second logic signal represent opposite logic.

3. The magnetic memory of claim 1 wherein, The hysteresis comparison of the hysteresis comparison circuit on the data signal and the hysteresis interval, so that the output end of the hysteresis comparison circuit outputs a data read result, includes: In a case where the data signal is less than the threshold, the data read result is flipped from the first logic signal to a second logic signal; or, in a case where the data signal is greater than the threshold, the data read result remains the first logic signal; The first logic signal and the second logic signal represent opposite logic.

4. The magnetic memory of claim 1 wherein, The switch timing circuit includes a first switch unit and a second switch unit; The first switch unit is electrically connected to the read signal generating circuit and the second input end of the hysteresis comparison circuit; the second switch unit is electrically connected to the second input end of the hysteresis comparison circuit; the output end of the hysteresis comparison circuit is reset to the first logic signal by controlling the on-off of the first switch unit and the second switch unit, or the data signal is input into the second input end of the hysteresis comparison circuit by controlling the on-off of the first switch unit and the second switch unit.

5. The magnetic memory of claim 1 wherein, The read signal generating circuit includes a reference signal generating module and a data signal generating module; The reference signal generation module is electrically connected with a first input end of the hysteresis comparison circuit, and the reference signal generation module includes at least one reference magnetic storage unit for generating and outputting the reference signal. The data signal generation module is electrically connected with a second input end of the hysteresis comparison circuit through the switch timing circuit, and the data signal generation module includes at least one data magnetic storage unit for generating and outputting the data signal.

6. The magnetic memory of claim 5 wherein, The data signal generation module includes a plurality of data magnetic storage units. Each of the data magnetic storage units generates the corresponding data signal, which is electrically connected with the second input end of the hysteresis comparison circuit, so that the plurality of data signals share the same reference signal.

7. The magnetic memory of claim 1 wherein, The reference magnetic storage unit includes a magnetic tunnel junction, and the magnetic tunnel junction includes a free layer, a barrier layer and a reference layer which are sequentially stacked. The magnetization directions of the free layer and the reference layer in the reference magnetic storage unit are in a parallel state, or the magnetization directions of the free layer and the reference layer in the reference magnetic storage unit are in an anti-parallel state.

8. The magnetic memory of claim 1 wherein, When the number of the data magnetic storage units, the reference magnetic storage units and the hysteresis comparison circuits is plural, the data magnetic storage units are arranged in multiple columns in an array, and the reference magnetic storage units are arranged in at least one column in an array. The data signal generated by each row of the data magnetic storage units is input to the second input end of the corresponding hysteresis comparison circuit of each row, and the reference signal generated by each row of the reference magnetic storage units is input to the first input end of the same hysteresis comparison circuit of each row, so that each row of the data magnetic storage units shares the same reference magnetic storage unit.

9. A method of reading data from a magnetic memory, characterized by, The method is applied to the magnetic memory as claimed in any one of claims 1 to 8, and the method includes: resetting an output end of the hysteresis comparison circuit to a first logic signal before each data reading; inputting the data signal to the second input end of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, thereby outputting a data reading result from the output end of the hysteresis comparison circuit.

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