Quantum circuit simulation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a quantum circuit simulation method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the multi-time partial amplitude calculation of each quantum circuit in one or more quantum circuits through a plurality of calculation nodes, obtaining a full amplitude result of each quantum circuit in the one or more quantum circuits; and obtaining an expected value of each of the one or more quantum lines based on the total amplitude result of each of the one or more quantum lines.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and specifically to a quantum circuit simulation method, device, electronic device, and storage medium. Background Art

[0002] Quantum computing is a computing method based on quantum mechanics. Unlike classical computing, it can perform more complex calculations through properties such as quantum superposition and quantum entanglement. Quantum circuits are the manifestation of quantum computing algorithms and are composed of quantum bits and quantum logic gates. Existing quantum computers are expensive to use and have low fidelity. Therefore, quantum circuits are usually verified using quantum simulators for simulation verification. The dimension of the Hilbert space of quantum circuits grows exponentially. For large-scale quantum circuits, either a lot of time or a lot of resources are required, and computing efficiency cannot be guaranteed with limited resources. Summary of the Invention

[0003] The embodiments of the present application provide a quantum circuit simulation method, device, electronic device, and storage medium.

[0004] The quantum circuit simulation method provided in the embodiments of the present application includes: Performing multiple partial amplitude calculations on each quantum circuit in the one or more quantum circuits through multiple computing nodes to obtain full amplitude results for each quantum circuit in the one or more quantum circuits; Based on the full amplitude result of each quantum circuit in the one or more quantum circuits, an expected value of each quantum circuit in the one or more quantum circuits is obtained.

[0005] The quantum circuit simulation device provided in the embodiments of the present application includes: A simulation unit is configured to perform multiple partial amplitude calculations on each quantum circuit in one or more quantum circuits through multiple computing nodes to obtain a full amplitude result for each quantum circuit in the one or more quantum circuits; The simulation unit is configured to obtain an expected value of each quantum circuit in the one or more quantum circuits based on a full amplitude result of each quantum circuit in the one or more quantum circuits.

[0006] The electronic device provided in an embodiment of the present application includes: a processor and a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the quantum circuit simulation method corresponding to the embodiment of the present application.

[0007] The chip provided in the embodiment of the present application includes: a processor for calling and running a computer program from a memory, so that a device equipped with the chip executes any quantum circuit simulation method provided in the embodiment of the present application.

[0008] The storage medium provided in the embodiments of the present application is used to store a computer program, which enables a computer to execute any quantum circuit simulation method provided in the embodiments of the present application.

[0009] The computer program product provided in the embodiments of the present application includes a computer program, which, when executed by a processor, implements any quantum circuit simulation method provided in the embodiments of the present application.

[0010] Through the quantum circuit simulation method, device, electronic device, and storage medium provided in the embodiments of the present application, multiple partial amplitude calculations are performed on the quantum circuit through multiple computing nodes to obtain a full amplitude result. The expected value of the quantum circuit is obtained based on the full amplitude result. The multiple partial amplitude calculations are distributed on different nodes in a distributed manner for simulation calculation, which can ensure quantum simulation efficiency under limited resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 Schematic diagram of the implementation process of the quantum circuit simulation method provided in the embodiment of this application Figure 1 ; Figure 2 A schematic diagram of a tensor network construction method provided in an embodiment of the present application; Figure 3 Schematic diagram of tensor network contraction processing provided in the embodiment of the present application Figure 1 ; Figure 4 Schematic diagram of tensor network contraction processing provided in the embodiment of the present application Figure 2 ; Figure 5 A schematic diagram of the wire cutting method provided in an embodiment of the present application; Figure 6 Schematic diagram of the door cutting method provided in the embodiment of the present application; Figure 7 A schematic diagram comparing cutting methods provided in the embodiments of the present application; Figure 8 Schematic diagram of the implementation process of the quantum circuit simulation method provided in the embodiment of this application Figure 2 ; Figure 9 A schematic diagram of the structure of a quantum circuit simulation device 900 provided in an embodiment of the present application; Figure 10 A schematic structural diagram of an electronic device provided in an embodiment of the present application; Figure 11 A schematic structural diagram of the chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The following will describe the technical solutions in the embodiments of this application in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0013] It should be noted that in the embodiments of the present application, the term "and / or" is merely a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the embodiments of the present application, the character " / " generally indicates that the associated objects are in an "or" relationship.

[0014] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0015] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following relevant technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all fall within the protection scope of the embodiments of the present application.

[0016] Quantum computing is a method based on quantum mechanics. Unlike classical computing, it can perform more complex calculations through properties such as quantum superposition and quantum entanglement. Quantum circuits, the manifestation of quantum computing algorithms, are composed of quantum bits and quantum logic gates. Existing quantum computers are expensive and have low fidelity. Therefore, quantum circuits are typically verified using quantum simulators. The most important metric for quantum simulators is the number of bits that can execute the quantum circuit; the larger the number of bits, the better the simulator's performance.

[0017] The traditional Schrödinger simulation method calculates all amplitudes at once, but each calculation requires a large amount of memory; the Feynman integration method can greatly reduce memory usage, but can only perform single amplitude calculations at a time; combining the Schrödinger and Feynman methods can obtain simulation calculation results, but cannot calculate more complex quantum circuits.

[0018] Quantum circuit simulation technology can use tensor networks to optimize and shrink quantum circuits, reduce the complexity of large-scale quantum circuits, and complete larger-scale quantum circuit simulations with limited resources. However, a single tensor network method does not have an advantage in large-scale quantum circuit simulations. The dimension of the Hilbert space of quantum circuits with hundreds of bits grows exponentially, especially when calculating a large number of amplitudes, which may require repeated tensor network contractions.

[0019] refer to Figure 1 , Figure 1 Schematic diagram of the implementation process of the quantum circuit simulation method provided in the embodiment of this application Figure 1 ,like Figure 1 As shown, the quantum circuit simulation method provided in this embodiment includes the following steps: Step 101: performing multiple partial amplitude calculations on each quantum circuit in one or more quantum circuits through multiple computing nodes to obtain a full amplitude result for each quantum circuit in the one or more quantum circuits.

[0020] In an embodiment of the present application, for each quantum circuit in one or more quantum circuits, multiple partial amplitude calculations are performed on the quantum circuit through multiple computing nodes to obtain a full amplitude result of the quantum circuit.

[0021] In the embodiment of the present application, the computing node may be a graphics processing unit (GPU) or other types of computing nodes, which is not limited in the embodiment of the present application.

[0022] In the embodiment of the present application, if the quantum circuit is directly calculated by the traditional Schrödinger simulation method, the calculation memory limit will be exceeded. The number of amplitudes calculated theoretically for an N-bit quantum circuit is 2 N Each amplitude is represented by a complex number (2 float64 precision storage, 16 bytes), and the memory required for calculation is 2 N ×16 bytes, N=30 requires 16G memory, so when the circuit is large, tensor network computing can be used. Tensor network computing converts quantum circuits into tensor network form, reducing computing memory and improving simulation efficiency.

[0023] In an embodiment of the present application, according to tensor network theory, after converting a quantum circuit into a tensor network, multiple partial amplitude calculations are performed on the tensor network of the quantum circuit through multiple computing nodes to obtain the full amplitude result of the tensor network of the quantum circuit.

[0024] refer to Figure 2 , Figure 2 A schematic diagram of a tensor network construction method provided in an embodiment of the present application is shown in FIG. Figure 2As shown, each point is a tensor, and also has a corresponding edge that can connect different points or even the same point, and the number of connected edges is the rank of the tensor, for example, a point without connected edges is a scalar, and a point with only one connected edge is a vector. The edge represents the output dimension of the tensor, and each edge points to the tensor to be contracted.

[0025] Based on this, in an optional embodiment of the present application, before performing multiple partial amplitude calculations on each quantum circuit in one or more quantum circuits through multiple computing nodes, the tensor network of each quantum circuit in the one or more quantum circuits is obtained based on the one or more quantum circuits. The multiple partial amplitude calculations on each quantum circuit in one or more quantum circuits through multiple computing nodes to obtain the full amplitude result of each quantum circuit in the one or more quantum circuits includes: For each quantum circuit in one or more quantum circuits, multiple partial amplitude calculations are performed on the tensor network of the quantum circuit through multiple computing nodes to obtain the full amplitude result of the tensor network of the quantum circuit.

[0026] In the embodiment of the present application, the full amplitude result of the tensor network of the quantum circuit is the full amplitude result of the quantum circuit.

[0027] In the embodiment of the present application, the tensor network can also be subjected to contraction processing and / or graph optimization processing to further reduce the amount of calculation. The contraction of the tensor network refers to the process of combining tensors in the network by summation or integration according to certain rules, thereby simplifying the network structure or extracting useful information. In the contraction process, specific operation rules will be followed, such as tensor contraction, i.e., summing two or more tensors in one or more dimensions to obtain a new tensor. The graph optimization algorithm of the tensor network aims to reduce the computational complexity, reduce the storage requirement, and improve the numerical stability by adjusting the structure of the tensor network, such as merging, decomposing, or rearranging tensors.

[0028] Reference Figure 3 and Figure 4 , Figure 3 The schematic diagram of the contraction processing of the tensor network provided by the embodiment of the present application Figure 1 , Figure 4 The schematic diagram of the contraction processing of the tensor network provided by the embodiment of the present application Figure 2 As shown in Figure 3 , the contraction processing can optimize two non-connected points into two connected points, as shown in Figure 4 , Figure 4 The left side shows a simple tensor network composed of two tensors connected by a line segment; as the contraction proceeds, the network structure changes; Figure 4The middle shows an intermediate state in the contraction process, where the line segments represent the connection between tensors and the direction of contraction; Figure 4 The right side shows the result after the tensor network is fully collapsed, that is, only one tensor remains.

[0029] Based on this, in an optional embodiment of the present application, based on the one or more quantum circuits, a tensor network of each quantum circuit in the one or more quantum circuits is obtained; wherein, the tensor network represents the tensor network after a first processing; the first processing includes: contraction processing and graph optimization processing.

[0030] In the embodiment of the present application, the output edge can be set for the tensor network to perform calculations of different amplitudes. Setting all bits as output edges can calculate the full amplitude result at one time, setting some bits as output edges can calculate partial amplitude results, and not setting output edges can calculate a single amplitude result. However, the more output edges are set, the higher the space and time complexity of the relative calculation. In the embodiment of the present application, the output edge is limited according to the memory of the computing node, and the partial amplitude is calculated at one time and the full amplitude is calculated multiple times. For example: For example, the quantum circuit has 40 bits, a total of 2 40 Theoretically, 16T memory is required to calculate the full amplitude. If each GPU computing node has only 16G memory, when 35 bits are set as the output edge, the computing memory is about 16G after the tensor network is contracted. Therefore, each GPU can calculate about 2 at a time. 35 amplitude, then 2 40 The amplitude is assigned to 2 5 In the GPU computing nodes, each calculation is 2 35 The full amplitude of 40 bits can be calculated.

[0031] In an embodiment of the present application, the output edge can be set according to the memory of the computing node. The number of amplitudes calculated each time can be the same or different. Each computing node can perform one calculation to save computing time. There can also be a situation where the computing node performs multiple calculations to save resources.

[0032] Based on this, in an optional embodiment of the present application, performing multiple partial amplitude calculations on the tensor network of the quantum circuit by multiple computing nodes to obtain the full amplitude result of the tensor network of the quantum circuit includes: A preset number of output edges is set for the tensor network of the quantum circuit, and multiple partial amplitude calculations are performed on the tensor network of the quantum circuit according to the preset number of output edges through multiple computing nodes to obtain a full amplitude result of the tensor network of the quantum circuit; the value of the preset number of bits is related to the memory of the computing node.

[0033] Step 102: obtaining an expected value of each quantum circuit in the one or more quantum circuits based on the full amplitude result of each quantum circuit in the one or more quantum circuits.

[0034] In the embodiment of the present application, for a tensor network of a quantum circuit, each time a partial amplitude is calculated, a partial amplitude result is obtained, which can also be called a sub-amplitude result. Based on multiple sub-amplitude results, the full amplitude calculation result of the quantum circuit is obtained.

[0035] In the embodiment of the present application, when 35 bits are set as the output edge, the computing memory is about 16G after the tensor network is contracted, but the storage 2 35 The total memory required for each amplitude is 512G, so calculating all the results at one time exceeds the GPU memory size. In the embodiment of the present application, the calculation results of each partial amplitude can be saved in sequence as a file format. At this time, only 512G hard disk size is required to realize the storage of sub-amplitudes.

[0036] Based on this, in an optional implementation manner of the present application, the full amplitude result includes multiple sub-amplitude results; the multiple sub-amplitude results correspond one-to-one to the multiple partial amplitude calculations; and the multiple sub-amplitude results are stored in a memory.

[0037] In an embodiment of the present application, for a quantum circuit, the expected value of the quantum circuit can be obtained based on the full amplitude result of the quantum circuit. In this embodiment of the present application, the data of the sub-amplitude results is relatively large. If the expected value of the quantum circuit is calculated directly based on the full amplitude result, too many resources will be consumed. Therefore, for a quantum circuit, the sub-expected value of each sub-amplitude result can be calculated, and the expected value of the quantum circuit can be obtained based on the sub-expected values ​​of each sub-amplitude result.

[0038] Based on this, in an optional embodiment of the present application, obtaining the expected value of each quantum circuit in the one or more quantum circuits based on the full amplitude result of each quantum circuit in the one or more quantum circuits includes: For each quantum circuit in the one or more quantum circuits, multiple sub-expectation values ​​of the quantum circuit are obtained based on multiple sub-amplitude results of the quantum circuit; the multiple sub-amplitude results of the quantum circuit correspond one-to-one to the multiple sub-expectation values ​​of the quantum circuit; Based on the multiple sub-expectation values ​​of the quantum circuit, an expectation value of the quantum circuit is obtained.

[0039] In an embodiment of the present application, for a large-scale first quantum circuit, the first quantum circuit can be cut into multiple quantum circuits, and the expected values ​​of the multiple quantum circuits are calculated respectively, and then the expected value of the first quantum circuit is obtained based on the expected values ​​of the multiple quantum circuits.

[0040] In the embodiment of the present application, the first quantum circuit can be cut by combining the wire cutting method and the gate cutting method, which is more efficient than using only the wire cutting method or the gate cutting method.

[0041] Based on this, in an optional embodiment of the present application, the plurality of quantum circuits are obtained by cutting the first quantum circuit in a first manner, wherein the first manner includes: a wire cutting manner and a gate cutting manner; the method further includes: According to the decomposition formulas of the line cutting method and the gate cutting method, based on the expected value of each quantum circuit in the multiple quantum circuits, the expected value of the first quantum circuit is reconstructed.

[0042] In the embodiment of the present application, the basic principle of wire cutting is that any quantum unitary matrix calculation in the quantum circuit can be decomposed into a set of orthogonal matrix bases, that is, 、 、 、 As the decomposition basis. The following formula: ,in represents a 2*2 matrix, represents the trace of the matrix. 、 、 、 The characteristic basis combination of the substrate can be prepared from 6 quantum states, including: , so the matrix It can be expressed by the following formula: ,in, .

[0043] refer to Figure 5 , Figure 5 This is a schematic diagram of the wire cutting method provided in the embodiment of the present application, as shown in FIG. Figure 5 As shown, a 7-bit circuit can be split into two 4-bit circuits, where quantum circuit 1 performs 、 、 Projection measurement, performed by quantum circuit 2 Initial preparation.

[0044] In the embodiment of the present application, gate cutting will generate 6 different lines at a time. Each line has no connection before, and the expected value of the original line can be calculated and reconstructed separately. According to the gate cutting theory, any line that can be used The expected value of the output of a two-bit quantum gate represented by , such as the controlled-NOT gate (CNOT) and the controlled-Z gate (CZ), can be decomposed into 6 circuits for calculation, such asFigure 6 As shown, Figure 6 This is a schematic diagram of the door cutting method provided in the embodiment of the present application. The formula is as follows: ,in, and is the measurement result, is the identity matrix, the quantum circuit density matrix After the unitary matrix After evolution, it can be expressed as , .

[0045] refer to Figure 7 , Figure 7 A schematic diagram comparing cutting methods provided in the embodiments of the present application is shown in FIG. Figure 7 As shown, Figure 7 (a) is the original circuit. If each quantum circuit after cutting is set to no more than 4 bits, the following cutting can be performed: Figure 7 Middle (b) is for door cutting only, which requires 6 cuts; Figure 7 Middle (c) is for wire cutting only, which requires 4 cuts; Figure 7 Middle (d) is a combination of wire cutting and gate cutting, which only requires 3 cuts, greatly reducing the quantum circuits generated by cutting.

[0046] refer to Figure 8 , Figure 8 Schematic diagram of the implementation process of the quantum circuit simulation method provided in the embodiment of this application Figure 2 ,like Figure 8 As shown, the quantum circuit cutting method provided in this embodiment includes the following steps: Step 201: Cutting the first quantum circuit.

[0047] The first quantum circuit is cut through the master node to obtain multiple quantum circuits; the cutting method is a combination of line cutting and gate cutting; the number of bits of the quantum circuit obtained after cutting is less than a preset value.

[0048] Step 202: Construct a tensor network.

[0049] For each cut quantum circuit, the quantum circuit is converted into a tensor network by using slave nodes.

[0050] Step 203: Optimize the tensor network.

[0051] For each tensor network, a first processing is performed to obtain a tensor network after the first processing; the first processing includes: contraction processing and / or graph optimization processing.

[0052] Step 204: Batch amplitude calculation.

[0053] For each tensor network, according to the memory of the computing node, the preset number of output edges is set, the tensor network of the quantum circuit is distributed and calculated multiple times in parts according to the preset number of output edges through multiple computing nodes, multiple sub-amplitude results are obtained, according to the multiple sub-amplitude results, the sub-expected value corresponding to each sub-amplitude result in the multiple sub-amplitude results is obtained, and then according to the sub-expected value corresponding to each sub-amplitude result in the multiple sub-amplitude results, the expected value of the tensor network, that is, the expected value of the quantum circuit corresponding to the tensor network, is obtained.

[0054] Step 205: aggregate the calculation results.

[0055] The expected values of each quantum circuit in the multiple quantum circuits are aggregated, the quantum circuit calculation results are aggregated to the main node, the circuit is reconstructed through the circuit cutting formula, and finally the expected value of the large-scale quantum circuit is calculated.

[0056] The quantum circuit simulation method provided by the embodiment of the application first converts the quantum circuit into multiple circuits with relatively small number of bits through circuit cutting and gate cutting, in order to solve the problem of complex quantum Hilbert space caused by large-scale quantum circuit and large number of bits, reduce the overall complexity of the circuit, and make it meet the requirements of tensor network calculation; secondly, the sub-circuit is calculated and optimized through the tensor network contraction method, so that it is contracted to a small quantum calculation complexity and can be executed in the computing node within the effective time; then, according to the upper limit of the memory of each computing node, the circuit is calculated in full amplitude, and the batch amplitude of each computing node is calculated to reduce the calculation complexity; finally, the calculation results of each computing node are aggregated from the node, and then returned to the main node for circuit result reconstruction.

[0057] The embodiment of the present application provides a distributed circuit simulation method combining quantum circuit splitting and tensor network contraction. The Hilbert space of a quantum circuit exponentially increases with the number of bits, and therefore the calculation complexity of a large-scale quantum circuit is very high, and it is difficult to simulate the calculation by using a single method. The embodiment of the present application combines the advantage that quantum circuit splitting can reduce the number of bits of a quantum circuit, and simultaneously makes the circuit size meet the size that can be effectively calculated by using a tensor network, and then uses the tensor network to realize large-scale quantum circuit simulation calculation in an effective resource and time, and performs task allocation according to the calculation resource, and realizes the calculation on different calculation nodes by using a distributed method. The embodiment of the present application provides a quantum circuit cutting method combining wire cutting and gate cutting. Quantum circuit splitting is an effective method for reducing the complexity of a quantum circuit, but a large-scale quantum circuit often has a large number of quantum gates and high complexity, and single use of wire cutting and gate cutting cannot effectively split the quantum circuit according to different quantum circuits, so that the splitting result is poor, and the subsequent simulation calculation complexity is high, and therefore the number of two-bit quantum gates of the quantum circuit and the position are analyzed, and the circuit is split by combining the two splitting methods, which is beneficial to subsequent distributed tensor network simulation calculation.

[0058] The embodiment of the present application also provides a quantum circuit simulation device 900, and the quantum circuit simulation device 900 is used for simulating one or more quantum circuits. Figure 9 , Figure 9 The quantum circuit simulation device 900 provided in the embodiment of the present application has the structure as shown in the accompanying drawings, and the quantum circuit simulation device 900 in the embodiment includes: The simulation unit is configured to perform multiple partial amplitude calculations on each quantum circuit in the one or more quantum circuits by using multiple calculation nodes, and obtain full amplitude results of the quantum circuits; and the simulation unit is configured to obtain expected values of the quantum circuits based on the full amplitude results of the quantum circuits.

[0059] In the embodiment of the present application, before performing multiple partial amplitude calculations on each quantum circuit in the one or more quantum circuits by using multiple calculation nodes, the simulation unit is configured to obtain a tensor network of each quantum circuit in the one or more quantum circuits based on the quantum circuits; and for each quantum circuit in the one or more quantum circuits, the simulation unit is configured to perform multiple partial amplitude calculations on the tensor network of the quantum circuit by using multiple calculation nodes, and obtain full amplitude results of the tensor network of the quantum circuit.

[0060] In an embodiment of the present application, the simulation unit is configured to set a preset number of output edges for the tensor network of the quantum circuit, and perform multiple partial amplitude calculations on the tensor network of the quantum circuit according to the preset number of output edges through multiple computing nodes to obtain a full amplitude result of the tensor network of the quantum circuit; the value of the preset number of bits is related to the memory of the computing node.

[0061] In an embodiment of the present application, a tensor network of each quantum circuit in the one or more quantum circuits is obtained based on the one or more quantum circuits; wherein the tensor network represents a tensor network after a first processing; the first processing includes: contraction processing and / or graph optimization processing.

[0062] In an embodiment of the present application, the full amplitude result includes multiple sub-amplitude results; the multiple sub-amplitude results correspond one-to-one to the multiple partial amplitude calculations; and the multiple sub-amplitude results are stored in a memory.

[0063] In an embodiment of the present application, the simulation unit is configured to obtain, for each quantum circuit in one or more quantum circuits, a plurality of sub-expectation values ​​of the quantum circuit based on a plurality of sub-amplitude results of the quantum circuit; the plurality of sub-amplitude results of the quantum circuit correspond one-to-one to the plurality of sub-expectation values ​​of the quantum circuit; Based on the multiple sub-expectation values ​​of the quantum circuit, an expectation value of the quantum circuit is obtained.

[0064] In an embodiment of the present application, the plurality of quantum circuits are obtained by cutting a first quantum circuit in a first manner, the first manner including a line cutting manner and a gate cutting manner; the simulation unit is configured to reconstruct an expected value of the first quantum circuit based on the expected value of each quantum circuit in the plurality of quantum circuits according to a decomposition formula of the line cutting manner and the gate cutting manner.

[0065] It should be understood by those skilled in the art that Figure 9 The implementation functions of each unit in the quantum circuit simulation device 900 shown can be understood by referring to the relevant description of the aforementioned method. Figure 9 The functions of the various units in the quantum circuit simulation device 900 shown can be implemented by a program running on a processor, or by a specific logic circuit.

[0066] Figure 10 It is a schematic structural diagram of an electronic device 1000 provided in an embodiment of the present application. Figure 10 The electronic device 1000 shown includes a processor 1010, which can call and run a computer program from a memory to implement the quantum circuit simulation method provided in the embodiment of the present application.

[0067] Alternatively, asFigure 10 As shown, the electronic device 1000 may further include a memory 1020. The processor 1010 may call and run a computer program from the memory 1020 to implement the quantum circuit simulation method provided in the embodiment of the present application.

[0068] The memory 1020 may be a separate device independent of the processor 1010 , or may be integrated into the processor 1010 .

[0069] Alternatively, as Figure 10 As shown, the electronic device 1000 may further include a transceiver 1030, and the processor 1010 may control the transceiver 1030 to perform quantum circuit simulation with other devices. Specifically, it may send information or data to other devices, or receive information or data sent by other devices.

[0070] The transceiver 1030 may include a transmitter and a receiver. The transceiver 1030 may further include an antenna, and the number of antennas may be one or more.

[0071] The electronic device 1000 may specifically be the quantum circuit simulation device 900 of the embodiment of the present application, and the electronic device 1000 may implement the corresponding processes implemented by the quantum circuit simulation device 900 in the various methods of the embodiment of the present application. For the sake of brevity, they will not be described in detail here.

[0072] Illustratively, an embodiment of the present application further provides a computer program product, including a computer program, which can be executed by the processor 1010 of the electronic device 1000 to complete the steps of any of the aforementioned methods.

[0073] Figure 11 It is a schematic structural diagram of the chip of an embodiment of the present application. Figure 11 The chip 1100 shown includes a processor 1110, which can call and run a computer program from a memory to implement the method in the embodiment of the present application.

[0074] Alternatively, as Figure 11 As shown, the chip 1100 may further include a memory 1120. The processor 1110 may call and execute a computer program from the memory 1120 to implement the method in the embodiment of the present application.

[0075] The memory 1120 may be a separate device independent of the processor 1110 , or may be integrated into the processor 1110 .

[0076] Optionally, the chip 1100 may further include an input interface 1130. The processor 1110 may control the input interface 1130 to perform quantum circuit simulation with other devices or chips, and specifically, may obtain information or data sent by other devices or chips.

[0077] Optionally, the chip 1100 may further include an output interface 1140. The processor 1110 may control the output interface 1140 to perform quantum circuit simulation with other devices or chips, and specifically, may output information or data to other devices or chips.

[0078] The chip can be applied to the electronic device 1000 in the embodiment of the present application, and the chip can implement the corresponding processes implemented by the electronic device 1000 in the various methods of the embodiment of the present application. For the sake of brevity, they will not be repeated here.

[0079] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0080] It should be understood that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above-described method embodiments may be completed by hardware integrated logic circuits in the processor or by software instructions. The above-described processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application may be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software units in the decoding processor. The software units may be located in a storage medium known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in a memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above-described method.

[0081] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0082] It should be understood that the above-mentioned memories are exemplary and not restrictive. For example, the memories in the embodiments of the present application may also be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM RAM (DR RAM), etc. In other words, the memories in the embodiments of the present application are intended to include, but are not limited to, these and any other suitable types of memories.

[0083] The present application also provides a storage medium for storing a computer program. The storage medium can be applied to the electronic device 1000 in the present application, and the computer program enables a computer to execute the corresponding processes implemented by the electronic device 1000 in the various methods of the present application. For the sake of brevity, these are not further described here.

[0084] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0085] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0087] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0089] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or an electronic device 1000, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0090] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A quantum circuit simulation method, characterized in that: The method comprises: Performing multiple partial amplitude calculations on each quantum circuit in the one or more quantum circuits through multiple computing nodes to obtain full amplitude results for each quantum circuit in the one or more quantum circuits; Based on the full amplitude result of each quantum circuit in the one or more quantum circuits, an expected value of each quantum circuit in the one or more quantum circuits is obtained.

2. The method according to claim 1, characterized in that Before performing multiple partial amplitude calculations on each quantum circuit in the one or more quantum circuits through multiple computing nodes, the method further includes: obtaining a tensor network of each quantum circuit in the one or more quantum circuits based on the one or more quantum circuits; The method of performing multiple partial amplitude calculations on each quantum circuit in the one or more quantum circuits by using multiple computing nodes to obtain a full amplitude result for each quantum circuit in the one or more quantum circuits includes: For each quantum circuit in the one or more quantum circuits, multiple partial amplitude calculations are performed on the tensor network of the quantum circuit through multiple computing nodes to obtain a full amplitude result of the tensor network of the quantum circuit.

3. The method according to claim 2, characterized in that The method further comprises performing multiple partial amplitude calculations on the tensor network of the quantum circuit through multiple computing nodes to obtain a full amplitude result of the tensor network of the quantum circuit, including: A preset number of output edges is set for the tensor network of the quantum circuit, and multiple partial amplitude calculations are performed on the tensor network of the quantum circuit according to the preset number of output edges through multiple computing nodes to obtain a full amplitude result of the tensor network of the quantum circuit; the value of the preset number of bits is related to the memory of the computing node.

4. The method according to claim 3, characterized in that Based on the one or more quantum circuits, a tensor network of each quantum circuit in the one or more quantum circuits is obtained; wherein the tensor network represents a tensor network after a first processing; the first processing includes: contraction processing and / or graph optimization processing.

5. The method according to claim 4, characterized in that The full amplitude result includes a plurality of sub-amplitude results; the plurality of sub-amplitude results correspond one-to-one to the plurality of partial amplitude calculations; and the plurality of sub-amplitude results are stored in a memory.

6. The method according to claim 5, characterized in that Obtaining an expected value of each quantum circuit in the one or more quantum circuits based on the full amplitude result of each quantum circuit in the one or more quantum circuits includes: For each quantum circuit in the one or more quantum circuits, multiple sub-expectation values ​​of the quantum circuit are obtained based on multiple sub-amplitude results of the quantum circuit; the multiple sub-amplitude results of the quantum circuit correspond one-to-one to the multiple sub-expectation values ​​of the quantum circuit; Based on the multiple sub-expectation values ​​of the quantum circuit, an expectation value of the quantum circuit is obtained.

7. The method according to any one of claims 1 to 6, characterized in that The plurality of quantum circuits are obtained by cutting the first quantum circuit in a first manner, wherein the first manner includes: a line cutting manner and a gate cutting manner; the method further includes: According to the decomposition formulas of the line cutting method and the gate cutting method, based on the expected value of each quantum circuit in the multiple quantum circuits, the expected value of the first quantum circuit is reconstructed.

8. A quantum circuit simulation device, characterized in that: The device comprises: A simulation unit is configured to perform multiple partial amplitude calculations on each quantum circuit in one or more quantum circuits through multiple computing nodes to obtain a full amplitude result for each quantum circuit in the one or more quantum circuits; The simulation unit is configured to obtain an expected value of each quantum circuit in the one or more quantum circuits based on a full amplitude result of each quantum circuit in the one or more quantum circuits.

9. An electronic device, characterized in that: include: A processor and a memory, the memory being used to store a computer program, the processor being used to call and run the computer program stored in the memory to execute the quantum circuit simulation method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: Used to store a computer program, wherein the computer program causes a computer to execute the quantum circuit simulation method according to any one of claims 1 to 7.

11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the quantum circuit simulation method according to any one of claims 1 to 7.

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