Power conversion circuit and control method thereof

Abstract

The invention provides a power conversion circuit and a control method thereof. The power conversion circuit comprises a resonant capacitor, a transformer, an upper bridge transistor, a lower bridge transistor and a control circuit. The resonant capacitor is coupled to the switching node. The transformer includes a primary coil coupled to the resonant capacitor and a secondary coil. The upper bridge transistor and the lower bridge transistor respectively couple an input voltage and a ground terminal to the switching node. The control circuit generates a first signal by using a switching signal related to the voltage of the switching node in response to the conduction of the upper bridge transistor, generates a second signal by using the switching signal in response to the non-conduction of both the lower bridge transistor and the upper bridge transistor, and generates a third signal by comparing the second signal with a voltage threshold value corresponding to the first signal. The control circuit adjusts the turn-on time of the lower bridge transistor based on the third signal, so that the upper bridge transistor achieves zero voltage switching.

Description

TECHNICAL FIELD

[0001] The present application relates to a power conversion circuit and a control method thereof, and more particularly to a resonant power conversion circuit and a control method thereof achieving zero-voltage switching of an upper bridge transistor. BACKGROUND

[0002] With the development of portable electronic devices, the development trend of power conversion circuits is similar to most power products, which is towards high efficiency, high power density, high reliability and low cost. Since resonant power conversion circuits (including LLC resonant power conversion circuits, flyback power conversion circuits, etc.) are a kind of high-efficiency and high-power-density power conversion circuits, the power conversion circuits of portable electronic devices gradually tend to be resonant power conversion circuits.

[0003] The high efficiency of the resonant power conversion circuit is mainly due to resonance and zero-voltage switching (ZVS). However, the general resonant power conversion circuit often generates high power loss in order to achieve zero-voltage switching. Therefore, it is necessary to optimize the resonant power conversion circuit so that it can achieve high-efficiency zero-voltage switching at high load and light load. SUMMARY

[0004] The present application proposes a resonant power conversion circuit and a control method thereof, which adjusts the circulating current of the transformer by adjusting the conduction time of the lower bridge transistor, thereby achieving zero-voltage switching of the upper bridge transistor and increasing the conversion efficiency of the resonant power conversion circuit.

[0005] Therefore, the present application provides a power conversion circuit, which includes a resonant capacitor, a transformer, an upper bridge transistor, a lower bridge transistor, a first voltage dividing circuit, and a control circuit. The resonant capacitor is coupled between a switching node and a resonant node. The transformer includes a primary coil and a secondary coil, wherein one end of the primary coil is coupled to the resonant node. The upper bridge transistor provides an input voltage to the switching node based on an upper bridge driving signal. The lower bridge transistor couples the switching node to a ground terminal based on a lower bridge driving signal. The first voltage dividing circuit divides the voltage of the switching node to generate a switching signal. The control circuit generates a first signal using the switching signal in response to the upper bridge driving signal being enabled, generates a second signal using the switching signal in response to the lower bridge driving signal being disabled and the upper bridge transistor being non-conductive, and generates a third signal by comparing the second signal with a voltage threshold. The voltage threshold corresponds to the first signal. The control circuit charges and discharges the resonant capacitor and the transformer using the upper bridge driving signal and the lower bridge driving signal, so that the secondary coil generates an output voltage of the power conversion circuit. The control circuit adjusts the pulse width of the lower bridge driving signal based on the third signal, so that the upper bridge transistor achieves zero voltage switching.

[0006] According to an embodiment of the present application, the power conversion circuit further includes a level conversion circuit. When the second signal exceeds the voltage threshold, the level conversion circuit converts the voltage level of the upper bridge driving signal to turn on the upper bridge transistor.

[0007] According to an embodiment of the present application, the control circuit further includes a sample-and-hold circuit. The sample-and-hold circuit samples the switching signal to generate the first signal. The voltage level of the first signal is related to an input voltage of the voltage conversion circuit.

[0008] According to an embodiment of the present application, the control circuit further includes an up-down counter. The up-down counter adjusts the pulse width of the lower bridge driving signal based on the first signal and the second signal.

[0009] According to an embodiment of the present application, the control circuit generates a turn-off time voltage based on the time from when the lower bridge driving signal is disabled to when the upper bridge driving signal is enabled. The control circuit generates a threshold voltage based on a predetermined time threshold. The control circuit adjusts the pulse width of the lower bridge driving signal so that the turn-off time voltage is equal to the threshold voltage.

[0010] According to an embodiment of the present application, the control circuit determines a longest time from when the lower bridge drive signal is disabled to when the upper bridge drive signal is enabled based on a longest off time signal.

[0011] According to an embodiment of the present application, the control circuit includes a volt-second circuit. The volt-second circuit generates the lower bridge drive signal based on an enable time of the upper bridge transistor, a voltage difference of the primary coil, and the output voltage.

[0012] According to an embodiment of the present application, the control circuit enables the lower bridge transistor using the lower bridge drive signal to generate a circulating current. The circulating current is used to achieve zero voltage switching of the upper bridge transistor.

[0013] According to an embodiment of the present application, the predetermined time threshold is related to an optimal circulating current generated by the lower bridge transistor. The optimal circulating current is used to achieve zero voltage switching of the upper bridge transistor and to improve efficiency of the power conversion circuit.

[0014] According to an embodiment of the present application, when the time corresponding to the off time voltage is greater than the predetermined time threshold, the control circuit increases a pulse width of the lower bridge drive signal in a next cycle. When the time corresponding to the off time voltage is not greater than the predetermined time threshold, the control circuit decreases the pulse width of the lower bridge drive signal in the next cycle.

[0015] According to an embodiment of the present application, when the second signal is less than the voltage threshold, the control circuit increases a pulse width of the lower bridge drive signal. When the second signal is not less than the voltage threshold, the control circuit decreases the pulse width of the lower bridge drive signal.

[0016] The present application further provides a control method for controlling a power conversion circuit. The power conversion circuit includes a resonant capacitor coupled between a switching node and a resonant node, a transformer including a primary coil and a secondary coil, an upper bridge transistor for providing an input voltage to the switching node, and a lower bridge transistor for coupling the switching node to a ground. One end of the primary coil is coupled to the resonant node. The upper bridge transistor and the lower bridge transistor are driven respectively to generate a switching signal corresponding to the switching node, and to generate an output voltage of the power conversion circuit at the secondary coil. The control method includes: generating a voltage threshold using the switching signal in response to the upper bridge transistor being turned on; turning on the upper bridge transistor in response to the switching signal exceeding the voltage threshold and both the upper bridge transistor and the lower bridge transistor being turned off; and comparing the switching signal with the voltage threshold to adjust the turn-on time of the lower bridge transistor such that the upper bridge transistor achieves zero voltage switching.

[0017] According to an embodiment of the present application, the step of generating the voltage threshold using the switching signal in response to the upper bridge transistor being turned on includes: generating a first signal by sampling the switching signal using a sample-and-hold circuit; and generating the voltage threshold by dividing the first signal. The voltage level of the first signal is related to an input voltage of the power conversion circuit.

[0018] According to an embodiment of the present application, the control method further includes: generating an off-time voltage based on a time from when the lower bridge drive signal is disabled to when the upper bridge drive signal is enabled; generating a threshold voltage based on a predetermined time threshold; and adjusting the turn-on time of the lower bridge transistor such that the off-time voltage is equal to the threshold voltage.

[0019] According to an embodiment of the present application, the control method further includes determining a maximum time from when the lower bridge transistor is turned off to when the upper bridge transistor is turned on based on a maximum off-time voltage.

[0020] According to an embodiment of the present application, the control method further includes driving the lower bridge transistor based on the enable time of the upper bridge transistor, a voltage difference of the primary coil, and the output voltage. A circulating current is generated when the lower bridge transistor is turned on. The circulating current is used to achieve zero voltage switching of the upper bridge transistor.

[0021] According to an embodiment of the present application, the predetermined time threshold is related to an optimal circulating current generated by the lower bridge transistor. The optimal circulating current is used to achieve zero voltage switching of the upper bridge transistor and to improve the efficiency of the power conversion circuit.

[0022] According to an embodiment of the present application, the control method further comprises: when the time corresponding to the turn-off time voltage is greater than the predetermined time threshold, increasing the pulse width of the lower bridge drive signal in the next cycle; and when the time corresponding to the turn-off time voltage is not greater than the predetermined time threshold, decreasing the pulse width of the lower bridge drive signal in the next cycle.

[0023] According to an embodiment of the present application, the step of adjusting the turn-on time of the lower bridge transistor by comparing the switching signal with the voltage threshold further comprises: when the switching signal is greater than the voltage threshold, increasing the turn-on time of the lower bridge transistor in the next cycle; and when the switching signal is not greater than the voltage threshold, decreasing the turn-on time of the lower bridge transistor in the next cycle.

[0024] According to an embodiment of the present application, the power conversion circuit is an asynchronous half-bridge flyback power converter.

[0025] According to another embodiment of the present application, the power conversion circuit is a resonant power converter. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram showing a power conversion circuit according to an embodiment of the present application;

[0027] Figure 2 A schematic diagram showing a first circuit according to an embodiment of the present application;

[0028] Figure 3 A schematic diagram showing a second circuit according to an embodiment of the present application;

[0029] Figure 4 A schematic diagram showing a voltage-second circuit according to an embodiment of the present application;

[0030] Figure 5 A schematic diagram showing a third circuit according to an embodiment of the present application;

[0031] Figure 6 A waveform diagram showing a voltage-second circuit and a third circuit according to an embodiment of the present application;

[0032] Figure 7 A schematic diagram showing an adjustment circuit according to an embodiment of the present application; and

[0033] Figure 8 A flowchart showing a control method according to an embodiment of the present application.

[0034] LIST OF ABBREVIATIONS

[0035] 100: power conversion circuit

[0036] 111: upper bridge transistor

[0037] 112: lower bridge transistor

[0038] 120: first voltage dividing circuit

[0039] 130: second voltage dividing circuit

[0040] 111D: upper bridge parasitic diode

[0041] 112D: lower bridge parasitic diode

[0042] 140: feedback circuit

[0043] 150: control circuit

[0044] 160: level shifting circuit

[0045] CR: resonance capacitor

[0046] TM: transformer

[0047] DR: rectifying element

[0048] COUT: output capacitor

[0049] RC1: first current sensing resistor

[0050] RC2: second current sensing resistor

[0051] HSG: upper bridge gate drive signal

[0052] VIN: input voltage

[0053] SW: switching node

[0054] LSG: lower bridge gate drive signal

[0055] CD1: first voltage dividing capacitor

[0056] CD2: second voltage dividing capacitor

[0057] SX: switching signal

[0058] NR: resonance node

[0059] VCR: resonance voltage

[0060] PS: primary winding

[0061] SS: secondary winding

[0062] AS: auxiliary winding

[0063] IOUT: output current

[0064] NA: auxiliary node

[0065] VNA: auxiliary coil voltage

[0066] RD1: first voltage dividing resistor

[0067] RD2: second voltage dividing resistor

[0068] VAX: auxiliary voltage

[0069] VOUT: output voltage

[0070] IP: primary current

[0071] PD: optocoupler

[0072] HSD: upper bridge drive circuit

[0073] LSD: lower bridge drive circuit

[0074] IFB: feedback current

[0075] VFB: feedback voltage

[0076] 200: first circuit

[0077] 210: first sample-and-hold circuit

[0078] 220: second sample-and-hold circuit

[0079] 230: third voltage dividing circuit

[0080] BF1: first buffer

[0081] PG1: first pulse generator

[0082] INV1: first inverter

[0083] PG2: second pulse generator

[0084] BF2: second buffer

[0085] CMP1: first comparator

[0086] NOR1: first NOR gate

[0087] AND1: first AND gate

[0088] SW1: first switch

[0089] CSH1: first hold capacitor

[0090] SW2: second switch

[0091] CSH2: second hold capacitor

[0092] RD3: third voltage dividing resistor

[0093] RD4: fourth voltage dividing resistor

[0094] RD5: fifth voltage dividing resistor

[0095] S1: first signal

[0096] S2: second signal

[0097] S3: third signal

[0098] V1H: first high voltage

[0099] V1L: first low voltage

[0100] PG3: third pulse generator

[0101] INV2: second inverter

[0102] PG4: fourth pulse generator

[0103] SW3: third switch

[0104] CSH3: third hold capacitor

[0105] SW4: fourth switch

[0106] CSH4: fourth hold capacitor

[0107] VRE: reflected voltage

[0108] 300: second circuit

[0109] T1: first transistor

[0110] RB1: first bias resistor

[0111] RB2: second bias resistor

[0112] RB3: third bias resistor

[0113] CMP2: second comparator

[0114] INV3: third inverter

[0115] PG5: fifth pulse generator

[0116] SMP: maximum off time signal

[0117] OR1: first OR gate

[0118] DF1: first D flip-flop

[0119] VCC: supply voltage

[0120] VFBD: voltage feedback voltage

[0121] RST: reset signal

[0122] 400: volt-second circuit

[0123] AMP1: first amplifier

[0124] AMP2: second amplifier

[0125] T2: second transistor

[0126] T3: third transistor

[0127] RI1: first current resistance

[0128] RI2: second current resistance

[0129] CM1: first current mirror

[0130] CM2: second current mirror

[0131] CM3: third current mirror

[0132] VY: magnetization voltage

[0133] ICHG: charging current

[0134] IDCHG: discharging current

[0135] SW5: fifth switch

[0136] SW6: sixth switch

[0137] INV4: fourth inverter

[0138] CT1: first time capacitor

[0139] CMP3: third comparator

[0140] CMP4: fourth comparator

[0141] AND2: second AND gate

[0142] AND3: third AND gate

[0143] VTS: time voltage

[0144] VL1: first threshold value

[0145] VL2: second threshold value

[0146] ZPLS: trigger signal

[0147] pSL: pre-lower bridge drive signal

[0148] SHB: inverting upper bridge drive signal

[0149] 500 third circuit

[0150] DF2 second D-type flip-flop

[0151] INV5 fifth inverter

[0152] T4 fourth transistor

[0153] IF1 first current source

[0154] CT2 second time capacitor

[0155] CMP5 fifth comparator

[0156] INV6 sixth inverter

[0157] PG6 sixth pulse generator

[0158] DF3 third D-type flip-flop

[0159] OR2 second OR gate

[0160] SZVS zero voltage switching signal

[0161] IADJ adjustment current

[0162] VZVS zero voltage switching voltage

[0163] VTM threshold time voltage

[0164] xSL expected lower bridge drive signal

[0165] AND4 fourth AND gate

[0166] INV7 seventh inverter

[0167] PG7 seventh pulse generator

[0168] AND5 fifth AND gate

[0169] OR3 third OR gate

[0170] MODE mode signal

[0171] MODEB inverted mode signal

[0172] BURST: burst signal

[0173] 600: waveform diagram

[0174] TM1: first time point

[0175] TM2: second time point

[0176] TM3: third time point

[0177] TM4: fourth time point

[0178] TM5: fifth time point

[0179] TM6: sixth time point

[0180] TM7: seventh time point

[0181] 700: adjustment circuit

[0182] INV8: eighth inverter

[0183] DF4: fourth D-type flip-flop

[0184] SW7: seventh switch

[0185] T5: fifth transistor

[0186] IF2: second fixed current

[0187] CT3: third time capacitor

[0188] PG8: eighth pulse generator

[0189] SLB: inverting lower bridge drive signal

[0190] S3P: negative pulse signal

[0191] VPD: turn-off time voltage

[0192] CMP6: sixth comparator

[0193] CMP7: seventh comparator

[0194] CMP8: eighth comparator

[0195] DF5: fifth D-type flip-flop

[0196] DF6: sixth D-type flip-flop

[0197] DF7: seventh D-type flip-flop

[0198] AND6: sixth AND gate

[0199] AND7: seventh AND gate

[0200] AND8: eighth AND gate

[0201] AND9: ninth AND gate

[0202] AND10: tenth AND gate

[0203] OR4: fourth OR gate

[0204] OR5: fifth OR gate

[0205] 710: up-down counter

[0206] 720: analog-to-digital converter

[0207] SU: up signal

[0208] SD: down signal

[0209] ISU: inverted up signal

[0210] ISD: inverted down signal

[0211] NUD: no count signal

[0212] XU: extra up signal

[0213] XD: extra down signal

[0214] SFU: final up signal

[0215] SFD: final down signal

[0216] B1, B2, BN: digital code

[0217] 800: control method

[0218] S810-S830: step flow DETAILED DESCRIPTION

[0219] The following description is presented to enable any person skilled in the art to make and use the disclosure. Descriptions of specific devices, examples, and arrangements are presented only as examples of the general principles novel to the disclosure and are not intended to be limiting of the general principles presented. Further, identical reference numerals have been used in different drawings to indicate similar or identical features.

[0220] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. It is intended that each of the embodiments and / or examples can be implemented independently of each other embodiment and / or example. Many modifications can be made to the embodiments and / or examples described herein, and the general principles of the disclosure can be applied to other embodiments and / or examples as pertains to the general principles of the disclosure. Further, any feature described herein can be claimed in combination with any one, more than one, or all of the other features described herein.

[0221] Furthermore, descriptions using terms such as "attached", "connected", "engaged", "coupled", "interfaced", or similar terms are not intended to limit the components or items in question to direct and physical contact with one another. Rather, such descriptions are intended to cover any components or items that can be in direct and physical contact with one another and any components or items that can not be in direct and physical contact with one another, but can still cooperate and / or communicate with one another.

[0222] Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top", can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the Figures. These relative terms are intended to encompass different orientations of the device in its operation or use in addition to the orientation depicted in the Figures.

[0223] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of some embodiments of the disclosure.

[0224] The description of some embodiments of the disclosure can be presented using terms such as "coupled", "connected", "interconnected", etc. that are intended to include any arrangement of structures that are connected, either directly or indirectly, such as by way of other structures, and that can be either fixed or moveable arrangements. Thus, these terms are not limited to direct connections, but can also include indirect connections, unless otherwise defined in the specification.

[0225] As used herein, the terms "about", "approximately", "substantially" generally mean within 20% of a given value or range, preferably within 10% of a given value or range, more preferably within 5% of a given value or range, or within 3% of a given value or range, or within 2% of a given value or range, or within 1% of a given value or range, or within 0.5% of a given value or range. A given number that is about, approximately, substantially, etc. is also implicitly meant to be within the meaning of about, approximately, substantially, etc. unless otherwise specifically defined.

[0226] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure, and will not be interpreted in an overly idealized or overly formal sense unless expressly so defined herein.

[0227] In some embodiments of the disclosure, the term "connected" or "coupled" or the like, unless otherwise defined, can refer to two structures that are in direct contact, or it can also refer to two structures that are not in direct contact, where other structures are interposed therebetween. Also, the term "connected" or "coupled" or the like can include both movable and fixed structures.

[0228] In the drawings, like reference numerals can be used to denote similar elements throughout the several views. Different types of elements can be distinguished by the use of numerals followed by letters, e.g., 102a, 102b.

[0229] Figure 1 A schematic diagram of a power conversion circuit according to an embodiment of the present application is shown. As shown, the power conversion circuit 100 includes an upper bridge transistor 111, a lower bridge transistor 112, a first voltage dividing circuit 120, a resonance capacitor CR, a transformer TM, a rectifying element DR, an output capacitor COUT, a second voltage dividing circuit 130, a first current sensing resistor RC1, and a second current sensing resistor RC2. Figure 1

[0230] The upper bridge transistor 111 provides an input voltage VIN to a switching node SW based on an upper bridge gate drive signal HSG. According to an embodiment of the present application, the upper bridge transistor 111 includes an upper bridge parasitic diode 111D, which is coupled between the switching node SW and the input voltage VIN. The lower bridge transistor 112 couples the switching node SW to a ground based on a lower bridge gate drive signal LSG. According to an embodiment of the present application, the lower bridge transistor 112 includes a lower bridge parasitic diode 112D, which is coupled between the switching node SW and the ground.

[0231] The first voltage dividing circuit 120 includes a first voltage dividing capacitor CD1 and a second voltage dividing capacitor CD2 to divide a voltage of the switching node SW to generate a switching signal SX. The resonance capacitor CR is coupled between the switching node SW and a resonance node NR, and a resonance voltage VCR is generated across the resonance capacitor CR. The transformer TM includes a primary winding PS, a secondary winding SS, and an auxiliary winding AS. The primary winding PS is coupled to the resonance node NR.

[0232] The output current IOUT generated by the secondary winding SS is rectified by the rectifying element DR to charge the output capacitor COUT, which in turn generates an output voltage VOUT. The auxiliary winding AS is coupled between an auxiliary node NA and the ground, and an auxiliary winding voltage VNA is generated at the auxiliary node NA. The second voltage dividing circuit 130 includes a first voltage dividing resistor RD1 and a second voltage dividing resistor RD2 to divide the auxiliary winding voltage VNA to generate an auxiliary voltage VAX.

[0233] ​According to some embodiments of the present invention, the auxiliary voltage VAX is the output voltage VOUT multiplied by a ratio. According to one embodiment of the present invention, the turns ratio of the auxiliary winding AS and the secondary winding SS is adjusted so that the auxiliary winding voltage VNA is equal to the output voltage VOUT. Furthermore, the second voltage divider circuit 130 is configured to multiply the auxiliary winding voltage VNA by n times. Therefore, the auxiliary voltage VAX is equal to the output voltage VOUT multiplied by n times, where n is less than 1 and greater than 0.

[0234] The first current detection resistor RC1 is coupled between the primary coil PS and the ground terminal to detect the primary current IP flowing through the resonant capacitor CR and the primary coil PS. The second current detection resistor RC2 converts the voltage difference of the first current detection resistor RC1 into a current detection signal SCS.

[0235] like Figure 1 As shown, the power conversion circuit 100 further includes a feedback circuit 140, an optical coupling device PD, a control circuit 150, a level shifter circuit 160, a high-bridge driver circuit HSD, and a low-bridge driver circuit LSD. The feedback circuit 140 is configured to convert the output voltage VOUT into a feedback current IFB, and the optical coupling device PD is configured to convert the feedback current IFB into a feedback voltage VFB. The control circuit 150 generates a high-bridge driver signal SH and a low-bridge driver signal SL based on the feedback voltage VFB, a current detection signal SCS, an auxiliary voltage VAX, and a switching signal SX.

[0236] The level shifter circuit 160 is configured to shift the voltage level of the high-bridge driving signal SH to the input voltage VIN. The high-bridge driving circuit HSD generates an high-bridge gate driving signal HSG based on the shifted signal to drive the high-bridge transistor 111. The low-bridge driving circuit LSD generates a low-bridge gate driving signal LSG based on the low-bridge driving signal SL to drive the low-bridge transistor 112.

[0237] According to one embodiment of the present invention, the power conversion circuit 100 may be an asynchronous half-bridge flyback power converter. According to another embodiment of the present invention, the power conversion circuit 100 may be a resonant power converter.

[0238] Figure 2 A schematic diagram showing a first circuit according to an embodiment of the present invention is shown. According to an embodiment of the present invention, Figure 1 The control circuit 150 includes a first circuit 200. Figure 2 As shown, the first circuit 200 includes a first buffer BF1, a first sample and hold circuit 210, a first pulse generator PG1, a first inverter INV1, a second pulse generator PG2, a second buffer BF2, a third voltage divider circuit 230, a first comparator CMP1, a first NOR gate NOR1 and a first AND gate AND1.

[0239] First buffer BF1 receives switching signal SX and generates second signal S2. According to one embodiment of the present invention, first buffer BF1 generates second signal S2 to increase the current driving capability of switching signal SX. In other words, second signal S2 is equivalent to switching signal SX. First sample-and-hold circuit 210 includes a first switch SW1, a first hold capacitor CSH1, a second switch SW2, and a second hold capacitor CSH2.

[0240] When the high-bridge drive signal SH is enabled, the first pulse generator PG1 generates a positive pulse that turns on the first switch SW1, allowing the first buffer BF1 to charge the first holding capacitor CSH1. When the positive pulse generated by the first pulse generator PG1 ends, the first inverter INV1 and the second pulse generator PG2 turn on the second switch SW2, allowing the charge stored in the first holding capacitor CSH1 to charge the second holding capacitor CSH2.

[0241] The second buffer BF2 generates a first signal S1 based on the voltage difference across the second holding capacitor CSH2. According to one embodiment of the present invention, the first signal S1 corresponds to the maximum value of the switching signal SX when the upper bridge transistor 111 is on. According to one embodiment of the present invention, the first signal S1 is related to the input voltage VIN. The third voltage divider circuit 230 includes a third voltage divider resistor RD3, a fourth voltage divider resistor RD4, and a fifth voltage divider resistor RD5, and is configured to divide the first signal S1 to generate a first high voltage V1H and a first low voltage V1L, where the first high voltage V1H is higher than the first low voltage V1L.

[0242] The first comparator CMP1 compares the second signal S2 with the first low voltage V1L. The first NOR gate NOR1 performs a logical NOR operation on the high-bridge drive signal SH and the low-bridge drive signal SL. The first AND gate AND1 performs a logical AND operation on the output signal of the first comparator CMP1 and the output signal of the first NOR gate NOR1 to generate a third signal S3.

[0243] In other words, when Figure 1 When the upper bridge transistor 111 and the lower bridge transistor 112 are both turned off and the second signal S2 exceeds the first low voltage V1L, the third signal S3 is in the enabled state. According to some embodiments of the present invention, Figure 1 The control circuit 150 adjusts the pulse width of the lower bridge driving signal SL (ie, the on-time of the lower bridge transistor 112 ) based on the third signal S3 , so as to achieve zero voltage switching of the upper bridge transistor 111 .

[0244] like Figure 2As shown, the first circuit 200 further comprises a second sample-and-hold circuit 220, a third pulse generator PG3, a second inverter INV2 and a fourth pulse generator PG4. The second sample-and-hold circuit 220 comprises a third switch SW3, a third hold capacitor CSH3, a fourth switch SW4 and a fourth hold capacitor CSH4.

[0245] When the lower bridge drive signal SL is in the enable state, the positive pulse generated by the third pulse generator PG3 turns on the third switch SW3, so that the auxiliary voltage VAX charges the third hold capacitor CSH3. When the positive pulse generated by the third pulse generator PG3 ends, the second inverter INV2 and the fourth pulse generator PG4 then generate a positive pulse to turn on the fourth switch SW4, so that the charge of the third hold capacitor CSH3 charges the fourth hold capacitor CSH4 to generate a reflected voltage VRE.

[0246] According to an embodiment of the present application, the auxiliary voltage VAX is a proportion of the output voltage VOUT, and the reflected voltage VRE is equal to the auxiliary voltage VAX, so the reflected voltage VRE is equal to a proportion of the output voltage VOUT. In other words, the reflected voltage VRE is proportional to the output voltage VOUT.

[0247] Figure 3 A schematic diagram showing the second circuit according to an embodiment of the present application is shown. According to an embodiment of the present application, Figure 1 The control circuit 150 of FIG. 1 comprises a second circuit 300. As shown in FIG. 3, Figure 3 The second circuit 300 comprises a first transistor T1, a first bias resistor RB1, a second bias resistor RB2, a third bias resistor RB3, a second comparator CMP2, a third inverter INV3, a fifth pulse generator PG5, a first OR gate OR1 and a first D-type flip-flop DF1.

[0248] The drain terminal of the first transistor T1 receives the supply voltage VCC, the gate terminal of the first transistor T1 receives the feedback voltage VFB, and the first bias resistor RB1 is coupled between the drain terminal and the gate terminal of the first transistor T1. The second bias resistor RB2 and the third bias resistor RB3 are connected in series between the source terminal of the first transistor T1 and the ground terminal, and generate a divided feedback voltage VFBD.

[0249] The second comparator CMP2 compares the divided feedback voltage VFBD and the current sensing signal SCS, and generates a reset signal RST. The third inverter INV3 inverts the lower bridge drive signal SL, and triggers the fifth pulse generator PG5 to generate a longest off-time signal SMP having a negative pulse. According to an embodiment of the present application, the width of the negative pulse of the longest off-time signal SMP is used to determine the maximum allowable time from when the lower bridge transistor 112 is not turned on to when the upper bridge transistor 111 is turned on.

[0250] The first OR gate OR1 is configured to perform a logical OR operation on the third signal S3 and the maximum off-time signal SMP to trigger the first D-type flip-flop DF1. Upon a rising edge in the output of the first OR gate OR1, the first D-type flip-flop DF1 outputs the supply voltage VCC as the high-bridge drive signal SH, thereby turning on the high-bridge transistor 111. When the reset signal RST is at a low logic level, the first D-type flip-flop DF1 resets the high-bridge drive signal SH to a low logic level, thereby turning off the high-bridge transistor 111.

[0251] like Figure 3 As shown, the upper bridge driving signal SH is generated based on the third signal S3, and as Figure 2 The third signal S3 is enabled based on the second signal S2 exceeding the first low voltage V1L (and both the high-bridge driving signal SH and the low-bridge driving signal SL are in a disabled state). In other words, when both the high-bridge transistor 111 and the low-bridge transistor 112 are off, the high-bridge transistor 111 is turned on when the voltage of the switching node SW exceeds a threshold.

[0252] Figure 4 A schematic diagram showing a volt-second circuit according to an embodiment of the present invention is shown. According to an embodiment of the present invention, Figure 1 The control circuit 150 includes a volt-second circuit 400. Figure 4 As shown, the volt-second circuit 400 includes a first amplifier AMP1, a second transistor T2, a first current resistor RI1, a first current mirror CM1, a second amplifier AMP2, a third transistor T3, a second current resistor RI2, a second current mirror CM2, and a third current mirror CM3.

[0253] The first amplifier AMP1, the first current resistor RI1 and the first current mirror CM1 are used to generate a charging current ICHG based on the magnetizing voltage VY. Figure 1 When the high-bridge transistor 111 is turned on (i.e., the high-bridge drive signal SH is enabled and the transformer TM is magnetized), the magnetizing voltage VY is related to the voltage difference across the primary winding PS, where the magnetizing voltage VY is equal to the first signal S1 minus the reflected voltage VRE. According to some embodiments of the present invention, the first signal S1 is related to the input voltage VIN. According to some embodiments of the present invention, the first signal S1 can be considered equal to the input voltage VIN.

[0254] According to some embodiments of the present invention, when Figure 1The resonant voltage VCR is equal to the voltage difference of the primary coil PS when the transformer TM is demagnetized (i.e., the lower bridge transistor 112 is turned on), and the resonant voltage VCR when the transformer TM is demagnetized is substantially equal to the resonant voltage VCR when the transformer TM is magnetized (i.e., the upper bridge transistor 111 is turned on). In other words, the reflected voltage VRE is equal to the resonant voltage VCR, and the resonant voltages VCR when the transformer TM is demagnetized and magnetized are substantially equal, so the first signal S1 minus the reflected voltage VRE can represent the voltage difference of the primary coil PS when the transformer TM is magnetized. Therefore, the charging current ICHG is generated based on the voltage difference of the primary coil PS when the transformer TM is magnetized (i.e., the upper bridge transistor 111 is turned on).

[0255] The second amplifier AMP2, the third transistor T3, the second current resistor RI2, the second current mirror CM2, and the third current mirror CM3 are used to generate the discharging current IDCHG based on the reflected voltage VRE. As shown in FIG. 4, the volt-second circuit 400 further includes a fifth switch SW5, a fourth inverter INV4, a sixth switch SW6, a first time capacitor CT1, a third comparator CMP3, a fourth comparator CMP4, a second AND gate AND2, and a third AND gate AND3. Figure 4

[0256] The fourth inverter INV4 inverts the upper bridge drive signal SH to generate an inverted upper bridge drive signal SHB. When the upper bridge drive signal SH is enabled (i.e., the upper bridge transistor 111 is turned on), the fifth switch SW5 is turned on so that the charging current ICHG charges the first time capacitor CT1 to generate a time voltage VTS. When the upper bridge drive signal SH is disabled (i.e., the upper bridge transistor 111 is not turned on), the inverted upper bridge drive signal SHB is enabled to turn on the sixth switch SW6 so that the discharging current IDCHG discharges the first time capacitor CT1 to decrease the time voltage VTS.

[0257] The third comparator CMP3 compares the first threshold value VL1 with the time voltage VTS, and the fourth comparator CMP4 compares the time voltage VTS with the second threshold value VL2. The second AND gate AND2 logically ANDs the output of the third comparator CMP3 and the inverted upper bridge drive signal SHB to generate a trigger signal ZPLS. The third AND gate AND3 logically ANDs the output of the fourth comparator CMP4 and the inverted upper bridge drive signal SHB to generate a pre-lower bridge drive signal pSL. According to an embodiment of the present disclosure, the first threshold value VL1 is greater than the second threshold value VL2.

[0258] ​According to some embodiments of the present application, the trigger signal ZPLS is enabled when the upper bridge drive signal SH is disabled (i.e., the inverted upper bridge drive signal SHB is enabled and the upper bridge transistor 111 is non-conductive) and the time voltage VT falls below the first threshold value VL1. According to some embodiments of the present application, the pre- lower bridge drive signal pSL is enabled when the upper bridge drive signal SH is disabled; the pre-lower bridge drive signal pSL is disabled when the time voltage VT further falls below the second threshold value VL2. According to some embodiments of the present application, the pre-lower bridge drive signal pSL is used to generate the lower bridge drive signal SL and is related to the demagnetization time of the transformer TM.

[0259] Figure 5 A schematic diagram showing a third circuit according to an embodiment of the present application is shown. According to an embodiment of the present application, Figure 1 The control circuit 150 includes a third circuit 500. As shown in Figure 5 The third circuit 500 includes a second D-type flip-flop DF2, a fifth inverter INV5, a fourth transistor T4, a first current source IF1, a second time capacitor CT2, a fifth comparator CMP5, a sixth inverter INV6, a sixth pulse generator PG6, a third D-type flip-flop DF3, and a second OR gate OR2.

[0260] The second D-type flip-flop DF2 outputs the supply voltage VCC as a zero voltage switching signal SZVS based on the rising edge of the trigger signal ZPLS, and turns off the fourth transistor T4 through the fifth inverter INV5, so that the adjustment current IADJ and the current of the first current source IF1 charge the second time capacitor CT2 to generate a zero voltage switching voltage VZVS. The fifth comparator CMP5 compares the zero voltage switching voltage VZVS with the threshold time voltage VTM, and disables the second D-type flip-flop DF2.

[0261] When the zero voltage switching voltage VZVS exceeds the threshold time voltage VTM, the fifth comparator CMP5 resets the second D-type flip-flop DF2, thereby disabling the zero voltage switching signal SZVS. The fourth transistor T4 is also turned on when the zero voltage switching signal SZVS is disabled, and discharges the second time capacitor CT2. In other words, the first current source IF1, the adjustment current IADJ, and the second time capacitor CT2 are used to determine the positive pulse width of the zero voltage switching signal SZVS.

[0262] The sixth inverter INV6 triggers the sixth pulse generator PG6 to generate a negative pulse based on the disabled high-bridge drive signal SH. The third D-type flip-flop DF3 outputs the supply voltage VCC based on the rising edge generated by the sixth pulse generator PG6. Furthermore, the disabled pre-low-bridge drive signal pSL is used to reset the output signal of the third D-type flip-flop DF3. The second OR gate OR2 performs a logical OR operation on the zero-voltage switching signal SZVS and the output signal of the third D-type flip-flop DF3 to generate the expected low-bridge drive signal xSL.

[0263] like Figure 5 As shown, the third circuit 500 further includes a fourth AND gate AND4, a seventh inverter INV7, a seventh pulse generator PG7, a fifth AND gate AND5, and a third OR gate OR3. According to one embodiment of the present invention, when the mode signal MODE is at a high logic level, the expected low bridge drive signal xSL is output as the low bridge drive signal SL via the fourth AND gate AND4 and the third OR gate OR.

[0264] According to another embodiment of the present invention, when the mode signal MODE is at a low logic level, the seventh inverter INV7 inverts the low logic level mode signal MODE to generate an inverted mode signal MODEB. The enabled burst signal BURST triggers the seventh pulse generator PG7, causing it to generate a positive pulse. The fifth AND gate AND5 performs a logical AND operation on the inverted mode signal MODEB and the positive pulse generated by the seventh pulse generator PG7. The output signal of the fifth AND gate AND5 is output as the lower bridge drive signal SL through the third OR gate OR3.

[0265] In other words, when the mode signal MODE is at a high logic level, the expected lower bridge driving signal xSL is output as the lower bridge driving signal SL. When the mode signal MODE is at a low logic level, the enabled burst signal BURST triggers the positive pulse of the seventh pulse generator PG7 to briefly enable the lower bridge driving signal SL.

[0266] Figure 6 The waveform diagram of the volt-second circuit and the third circuit according to an embodiment of the present invention is shown below. Figure 1 The power conversion circuit 100, Figure 4 The volt-second circuit 400 and Figure 5 The third circuit 500 is described in detail.

[0267] like Figure 6 As shown, the upper bridge drive signal SH is enabled from the first time point TM1 to the second time point TM2. In other words, the upper bridge transistor 111 is turned on from the first time point TM1 to the second time point TM2. Figure 4As shown, when the upper bridge driving signal SH is enabled, the charging current ICHG charges the first time capacitor CT1, so that the time voltage VTS gradually rises, and the rising slope is determined by the charging current ICHG. The second time point TM2 to the third time point TM3 is a dead time, and the width of the negative pulse generated by the sixth pulse generator PG6 determines the dead time. Figure 5 According to some embodiments of the present application, the dead time of the second time point TM2 to the third time point TM3 is used to achieve zero voltage switching of the lower bridge transistor 112.

[0268] As shown, when the upper bridge driving signal SH is enabled, the charging current ICHG charges the first time capacitor CT1, so that the time voltage VTS gradually rises, and the rising slope is determined by the charging current ICHG. The second time point TM2 to the third time point TM3 is a dead time, and the width of the negative pulse generated by the sixth pulse generator PG6 determines the dead time. Figure 4 Figure 6 As shown, at the second time point TM2, the upper bridge driving signal SH is disabled, and the time voltage VTS at the second time point TM2 is the maximum, so that the output signal of the fourth comparator CMP4 enables the pre lower bridge driving signal pSL. As shown, when the pre lower bridge driving signal pSL is enabled, the third D-type flip-flop DF3 enables the expected lower bridge driving signal xSL and the lower bridge driving signal SL (i.e., turns on the lower bridge transistor 112) based on the rising edge after the negative pulse generated by the sixth pulse generator PG6. Figure 5 Figure 6 As shown, after the second time point TM2, the time voltage VTS gradually decreases, and the falling slope is determined by the discharging current IDCHG of the sixth pulse generator PG6. Figure 5

[0269] As shown, at the fourth time point TM4, the time voltage VTS falls below the first threshold value VL1. As shown, when the time voltage VTS falls below the first threshold value VL1, the trigger signal ZPLS is converted from the low logic level to the high logic level, thereby triggering the second D-type flip-flop DF2 of the zero voltage switching signal SZVS to be enabled (i.e., high logic level). And the adjustment current IADJ and the first current source IF1 charge the second time capacitor CT2, so that the zero voltage switching voltage VZVS rises. Figure 6 Figure 4 As shown, at the fourth time point TM4, the time voltage VTS falls below the first threshold value VL1. As shown, when the time voltage VTS falls below the first threshold value VL1, the trigger signal ZPLS is converted from the low logic level to the high logic level, thereby triggering the second D-type flip-flop DF2 of the zero voltage switching signal SZVS to be enabled (i.e., high logic level). And the adjustment current IADJ and the first current source IF1 charge the second time capacitor CT2, so that the zero voltage switching voltage VZVS rises. Figure 5

[0270] As shown, at the fifth time point TM5, the time voltage VTS falls below the second threshold value VL2. As shown, when the time voltage VTS falls below the second threshold value VL2, the pre lower bridge driving signal pSL is disabled, thereby disabling the third D-type flip-flop DF3 of the sixth pulse generator PG6. Figure 6 Figure 4 As shown, at the fourth time point TM4, the time voltage VTS falls below the first threshold value VL1. As shown, when the time voltage VTS falls below the first threshold value VL1, the trigger signal ZPLS is converted from the low logic level to the high logic level, thereby triggering the second D-type flip-flop DF2 of the zero voltage switching signal SZVS to be enabled (i.e., high logic level). And the adjustment current IADJ and the first current source IF1 charge the second time capacitor CT2, so that the zero voltage switching voltage VZVS rises. Figure 5 Figure 5 ​​​​​​​As shown, since the zero voltage switching signal SZVS is still in the enabled state, it is expected that the lower bridge driving signal xSL and the lower bridge driving signal SL are still maintained in the enabled state.

[0271] like Figure 5 As shown, the second time capacitor CT2 is Figure 6 At the fourth time point TM4, the zero voltage switching signal SZVS is enabled by the trigger signal ZPLS and charging begins, so that the zero voltage switching voltage VZVS continues to increase. At the sixth time point TM6, the zero voltage switching voltage VZVS exceeds the threshold time voltage VTM. Figure 5 As shown, when the zero-voltage switching voltage VZVS exceeds the threshold time voltage VTM, the fifth comparator CMP5 resets the second D-type flip-flop DF2 to disable the zero-voltage switching signal SZVS, thereby disabling the expected low-bridge driving signal xSL and the low-bridge driving signal SL. In other words, at the sixth time point TM6, the low-bridge transistor 112 is turned off.

[0272] like Figure 6 As shown, the sixth time point TM6 to the seventh time point TM7 is the time period during which both the upper bridge transistor 111 and the lower bridge transistor 112 are non-conductive. Furthermore, the duration of the transition from the sixth time point TM6 to the seventh time point TM7 is determined by the adjustment current IADJ, the first current source IF1, and the second timing capacitor CT2. The duration of the transition from the sixth time point TM6 to the seventh time point TM7 can be varied by adjusting the current IADJ. Furthermore, the adjustment current IADJ, the first current source IF1, and the second timing capacitor CT2 can also determine the pulse width of the zero voltage switching signal SZVS (i.e., the pulse width of the lower bridge drive signal SL).

[0273] According to one embodiment of the present invention, when the pulse width of the zero-voltage switching signal SZVS (i.e., the pulse width of the lower bridge drive signal SL) is small, a small circulating current is generated in the transformer TM, which may prevent the upper bridge transistor 111 from achieving zero-voltage switching. According to another embodiment of the present invention, when the pulse width of the zero-voltage switching signal SZVS is large, zero-voltage switching of the upper bridge transistor 111 can be ensured, but this may also result in greater power loss. Therefore, it is necessary to optimize the pulse width of the zero-voltage switching signal SZVS (i.e., the pulse width of the lower bridge drive signal SL) to ensure zero-voltage switching of the upper bridge transistor and improve conversion efficiency, especially under light load conditions.

[0274] Figure 7 A schematic diagram showing an adjustment circuit according to an embodiment of the present invention is shown. According to an embodiment of the present invention, Figure 1 The control circuit 150 includes an adjustment circuit 700. Figure 7As shown, the adjustment circuit 700 includes an eighth inverter INV8, a fourth D-type flip-flop DF4, a seventh switch SW7, a fifth transistor T5, a second fixed current IF2, a third timing capacitor CT3 and an eighth pulse generator PG8.

[0275] The eighth inverter INV8 inverts the lower bridge drive signal SL to generate an inverted lower bridge drive signal SLB. The fourth D-type flip-flop DF4 outputs the supply voltage VCC based on the rising edge of the inverted lower bridge drive signal SLB to turn on the seventh switch SW7. The fifth transistor T5 is not turned on based on the lower bridge drive signal SL, so that the second fixed current IF2 charges the third time capacitor CT3 through the seventh switch SW7 to generate the off-time voltage VPD. The eighth pulse generator PG8 generates a negative pulse signal S3P based on the enabled third signal S3. When the negative pulse signal S3P is at a low logic level, the fourth D-type flip-flop DF4 is reset and the seventh switch SW7 is not turned on. According to one embodiment of the present invention, the third signal S3 corresponds to Figure 2 The third signal S3.

[0276] like Figure 7 As shown, the adjustment circuit 700 further includes a sixth comparator CMP6, a fifth D-type flip-flop DF5, a seventh comparator CMP7, a sixth D-type flip-flop DF6, an eighth comparator CMP8, a seventh D-type flip-flop DF7, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, a fourth OR gate OR4, a ninth AND gate AND9, a tenth AND gate AND10, a fifth OR gate OR5, an up-down counter 710 and an analog-to-digital converter 720.

[0277] The sixth comparator CMP6 is used to compare Figure 2 The second signal S2 and the first high voltage V1H trigger the fifth D-type flip-flop DF5 to generate an up-count signal SU and an inverted up-count signal ISU. The seventh comparator CMP7 compares the second signal S2 with the first low voltage V1L to trigger the sixth D-type flip-flop DF6 to generate an inverted down-count signal ISD and a down-count signal SD. The eighth comparator CMP8 compares the off-time voltage VPD with the threshold voltage VTH to trigger the seventh D-type flip-flop DF7 to generate an additional down-count signal XD and an additional up-count signal XU. Furthermore, when the negative pulse signal S3P is at a low logic level, the fifth D-type flip-flop DF5, the sixth D-type flip-flop DF6, and the seventh D-type flip-flop DF7 are reset.

[0278] The sixth AND gate AND6 generates a not-up signal NUD based on the inverted up count signal ISU and the inverted down count signal ISD. The seventh AND gate AND7, the eighth AND gate AND8, and the fourth OR gate OR4 generate a final up count signal SFU based on the up count signal SU, the inverted down count signal ISD, the not-up signal NUD, and an extra up count signal XU. The ninth AND gate AND9, the tenth AND gate AND10, and the fifth OR gate OR5 generate a final down count signal SFD based on the down count signal SD, the inverted up count signal ISU, the not-up signal NUD, and an extra down count signal XD.

[0279] The up-down counter 710 up counts the digital code B1, B2,..., BN based on the enabled final up count signal SFU and down counts the digital code B1, B2,..., BN based on the enabled final down count signal SFD with the third signal S3 as a clock. The analog-to-digital converter 720 generates the adjustment current IADJ based on the digital code B1, B2,..., BN. In other words, when the final up count signal SFU is enabled and the final down count signal SFD is disabled, the adjustment current IADJ is increased. When the final up count signal SFU is disabled and the final down count signal SFD is enabled, the adjustment current IADJ is decreased.

[0280] According to an embodiment of the present application, when the second signal S2 is lower than the first low voltage VI L, both the down count signal SD and the inverted up count signal ISU are high logic levels, such that the up-down counter 710 down counts based on the final down count signal SFD, resulting in a decrease of the adjustment current IADJ and an increase of the on-time of the lower bridge transistor 112, thereby increasing the circulating current. According to another embodiment of the present application, when the second signal S2 is higher than the first high voltage VI H, both the up count signal SU and the inverted down count signal ISD are high logic levels, such that the up-down counter 710 up counts based on the final up count signal SFU, resulting in an increase of the adjustment current IADJ and a decrease of the on-time of the lower bridge transistor 112, thereby decreasing the circulating current.

[0281] According to yet another embodiment of the present application, when the second signal S2 is between the first high voltage VI H and the first low voltage VI L, the adjustment current IADJ is varied with the second signal S2, such that the on-time of the lower bridge transistor 112 is varied with the second signal S2, thereby varying the circulating current. Figure 6the length of the sixth time point TM6 to the seventh time point TM7. When the turn-off time voltage VPD exceeds the threshold voltage VTH (i.e., the time of the sixth time point TM6 to the seventh time point TM7 exceeds the predetermined time threshold of the corresponding threshold voltage VTH), the adjustment current IADJ is decreased, thereby increasing the turn-on time of the lower bridge transistor 112 and shortening the time of the sixth time point TM6 to the seventh time point TM7. According to some embodiments of the present disclosure, when the adjustment current IADJ is adjusted, the adjusted IADJ is used to adjust the pulse width of the lower bridge drive signal LS (i.e., the turn-on time of the lower bridge transistor 112) of the next cycle.

[0282] When the turn-off time voltage VPD does not exceed the threshold voltage VTH, the adjustment current IADJ is increased, thereby shortening the turn-on time of the lower bridge transistor 112 and increasing the time of the sixth time point TM6 to the seventh time point TM7. By adjusting the adjustment current IADJ to optimize the turn-on time of the lower bridge transistor 112, the circulating current is optimized, thereby ensuring the zero voltage switching of the upper bridge transistor 111 and at the same time improving the conversion efficiency of the power conversion circuit 100. According to an embodiment of the present disclosure, when the circulating current reaches the optimal circulating current, the zero voltage switching of the upper bridge transistor 111 is achieved and at the same time the efficiency of the power conversion circuit 100 is improved.

[0283] Figure 8 A flowchart of a control method according to an embodiment of the present disclosure is shown. The following description of the control method 800 will be made in conjunction with Figures 1-7 for the sake of detailed illustration. First, in response to the upper bridge transistor 111 being turned on, a voltage threshold is generated using the switching signal SX (step S810). As shown in FIG. 8A, when the upper bridge transistor 111 is turned on, the upper bridge drive signal SH is enabled, thereby triggering the first sample-and-hold circuit 210 to sample the switching signal SX to generate the first signal S1, and using the first signal S1 to generate the first low voltage V1L and the first high voltage V1H. According to an embodiment of the present disclosure, the voltage threshold of step S810 corresponds to the first low voltage V1L. Figure 2

[0284] Next, in response to the switching signal SX exceeding the voltage threshold and neither the upper bridge transistor 111 nor the lower bridge transistor 112 being turned on, the upper bridge transistor 111 is turned on (step S820). As shown in FIG. 8B, the second signal S2 is equivalent to the switching signal SX. When the second signal S2 exceeds the voltage threshold (i.e., the first low voltage V1L) and both the upper bridge drive signal SH and the lower bridge drive signal SL are disabled, the third signal S3 is enabled. As shown in FIG. 8C, the third signal S3 is equivalent to the switching signal SX. When the third signal S3 exceeds the voltage threshold (i.e., the first low voltage V1L) and the lower bridge drive signal SL is disabled, the fourth signal S4 is enabled. As shown in FIG. 8D, the fourth signal S4 is equivalent to the switching signal SX. When the fourth signal S4 exceeds the voltage threshold (i.e., the first low voltage V1L) and the upper bridge drive signal SH is disabled, the fifth signal S5 is enabled. As shown in FIG. 8E, the fifth signal S5 is equivalent to the switching signal SX. Figure 2 Figure 3 ​​As shown, when the third signal S3 is enabled and the lower bridge drive signal SL is disabled, the first D-type flip-flop DF1 is enabled by the pulse width of the fifth pulse generator PG5.

[0285] Subsequently, the switching signal SX is compared with the voltage threshold value to adjust the on-time of the lower bridge transistor 112, so that the upper bridge transistor 111 reaches zero voltage switching (step S830). As shown in FIG. 8B, the second signal S2 is compared with the first low voltage VI L to generate the third signal S3. As shown in FIG. 8C, the third signal S3 is used to adjust the adjustment current IADJ. As shown in FIG. 8D, the adjustment current IADJ is used to adjust the rising speed of the zero voltage switching voltage VZVS, thereby adjusting the enable time of the lower bridge drive signal SL. Figure 2 Figure 7 Figure 5 Figure 6

[0286] The present application provides a resonant power conversion circuit and a control method thereof, which adjusts the circulating current of the transformer by adjusting the on-time of the lower bridge transistor, so that the zero voltage switching of the upper bridge transistor is achieved, and the conversion efficiency of the resonant power conversion circuit is increased.

[0287] Although the embodiments of the present application and their advantages have been disclosed, it should be understood that any modifications, combinations, sub-combinations and alterations of the embodiments disclosed are possible, and fall within the scope of the present application. Although specific processes, machines, manufacture, compositions of matter, means, methods, and steps are disclosed, it should be understood that any process, machine, manufacture, composition of matter, means, method, or step that can provide the same or similar function or result as the disclosed embodiments are intended to fall within the scope of the present application. Accordingly, the scope of the present application is not intended to be limited to the described embodiments but is intended to include any and all equivalents falling within the scope of the present application. The disclosure is intended to cover any and all alternatives, combinations, sub-combinations, equivalents, modifications and variations of the disclosed embodiments.​​​​

Claims

1. A power conversion circuit, characterized in that: include: a resonant capacitor coupled between a switching node and a resonant node; a transformer comprising a primary coil and a secondary coil, wherein one end of the primary coil is coupled to the resonant node; an upper bridge transistor, providing an input voltage to the switching node based on an upper bridge driving signal; a lower bridge transistor, coupling the switching node to a ground terminal based on a lower bridge driving signal; a first voltage divider circuit, dividing the voltage of the switching node to generate a switching signal; as well as a control circuit that generates a first signal using the switching signal in response to the upper bridge driving signal being enabled, generates a second signal using the switching signal in response to the lower bridge driving signal being disabled and the upper bridge transistor being non-conductive, and compares the second signal with a voltage threshold to generate a third signal; wherein the voltage threshold corresponds to the first signal; The control circuit uses the upper bridge drive signal and the lower bridge drive signal to charge and discharge the resonant capacitor and the transformer, so that the secondary coil generates an output voltage of the power conversion circuit; The control circuit adjusts the pulse width of the lower bridge driving signal based on the third signal, so that the upper bridge transistor achieves zero voltage switching.

2. The power conversion circuit according to claim 1, wherein: Also includes: A level conversion circuit converts the voltage level of the upper bridge driving signal to turn on the upper bridge transistor when the second signal exceeds the voltage threshold.

3. The power conversion circuit according to claim 1, wherein: The control circuit further includes: a sample-and-hold circuit for sampling the switching signal to generate the first signal; The voltage level of the first signal is related to an input voltage of the voltage conversion circuit.

4. The power conversion circuit according to claim 1, wherein: The control circuit further includes: An up-counting and down-counting counter adjusts the pulse width of the lower bridge driving signal based on the first signal and the second signal.

5. The power conversion circuit according to claim 1, wherein: The control circuit generates an off-time voltage based on the time from when the lower bridge driving signal is disabled to when the upper bridge driving signal is enabled; The control circuit generates a threshold voltage based on a predetermined time threshold; The control circuit adjusts the pulse width of the lower bridge driving signal so that the off-time voltage is equal to the threshold voltage.

6. The power conversion circuit according to claim 5, wherein: The control circuit determines a maximum time from when the lower bridge driving signal is disabled to when the upper bridge driving signal is enabled based on a maximum off-time signal.

7. The power conversion circuit according to claim 5, wherein: The control circuit includes: The one volt-second circuit generates the lower bridge drive signal based on the enable time of the upper bridge transistor, the voltage difference of the primary coil and the output voltage.

8. The power conversion circuit according to claim 7, wherein: The control circuit enables the lower bridge transistor using the lower bridge driving signal to generate a circulating current; The circulating current is used to achieve zero voltage switching of the upper bridge transistor.

9. The power conversion circuit according to claim 8, wherein: The predetermined time threshold is related to an optimal circulating current generated by the lower bridge transistor; The optimal circulating current is used to simultaneously achieve zero voltage switching of the upper bridge transistor and improve the efficiency of the power conversion circuit.

10. The power conversion circuit according to claim 5, wherein: When the time corresponding to the off-time voltage is greater than the predetermined time threshold, the control circuit increases the pulse width of the lower bridge drive signal in the next cycle; When the time corresponding to the off-time voltage is not greater than the predetermined time threshold, the control circuit reduces the pulse width of the lower bridge driving signal in the next cycle.

11. The power conversion circuit according to claim 1, wherein: When the second signal is less than the voltage threshold, the control circuit increases the pulse width of the lower bridge driving signal; When the second signal is not less than the voltage threshold, the control circuit shortens the pulse width of the lower bridge driving signal.

12. A control method for controlling a power conversion circuit, characterized in that: The power conversion circuit includes a resonant capacitor coupled between a switching node and a resonant node, a transformer including a primary coil and a secondary coil, an upper bridge transistor that provides an input voltage to the switching node, and a lower bridge transistor that couples the switching node to a ground terminal. One end of the primary coil is coupled to the resonant node, and the upper bridge transistor and the lower bridge transistor are driven to generate a switching signal corresponding to the switching node, and an output voltage of the power conversion circuit is generated at the secondary coil. The control method includes: In response to the upper bridge transistor being turned on, generating a voltage threshold using the switching signal; In response to the switching signal exceeding the voltage threshold and both the upper bridge transistor and the lower bridge transistor being off, turning on the upper bridge transistor; and The switching signal is compared with the voltage threshold to adjust the on-time of the lower bridge transistor so that the upper bridge transistor achieves zero voltage switching.

13. The control method according to claim 12, wherein: The step of generating the voltage threshold by utilizing the switching signal in response to the upper bridge transistor being turned on comprises: Utilizing a sample-and-hold circuit to sample the switching signal to generate a first signal; and Dividing the first signal to generate the voltage threshold; The voltage level of the first signal is related to an input voltage of the voltage conversion circuit.

14. The control method according to claim 12, wherein include: generating an off-time voltage based on the time from when the lower bridge transistor is turned off to when the upper bridge transistor is turned on; generating a threshold voltage based on a predetermined time threshold; and The on-time of the lower bridge transistor is adjusted so that the off-time voltage is equal to the threshold voltage.

15. The control method according to claim 14, wherein: Also includes: The longest time from when the lower bridge transistor is turned off to when the upper bridge transistor is turned on is determined based on a longest off-time voltage.

16. The control method according to claim 14, wherein: Also includes: driving the lower bridge transistor based on the enable time of the upper bridge transistor, the voltage difference of the primary coil, and the output voltage; When the lower bridge transistor is turned on, a circulating current is generated; The circulating current is used to achieve zero voltage switching of the upper bridge transistor.

17. The control method according to claim 16, wherein: The predetermined time threshold is related to an optimal circulating current generated by the lower bridge transistor; The optimal circulating current is used to simultaneously achieve zero voltage switching of the upper bridge transistor and improve the efficiency of the power conversion circuit.

18. The control method according to claim 14, wherein: Also includes: When the time corresponding to the off-time voltage is greater than the predetermined time threshold, increasing the pulse width of the lower bridge drive signal in the next cycle; as well as When the time corresponding to the off-time voltage is not greater than the predetermined time threshold, the pulse width of the lower bridge driving signal in the next cycle is reduced.

19. The control method according to claim 12, wherein: The step of comparing the switching signal with the voltage threshold to adjust the on-time of the lower bridge transistor further includes: When the switching signal is greater than the voltage threshold, increasing the on-time of the lower bridge transistor in the next cycle; and When the switching signal is not greater than the voltage threshold, the on-time of the lower bridge transistor in the next cycle is reduced.

20. The control method according to claim 12, wherein: The power conversion circuit is an asynchronous half-bridge flyback power converter.

21. The control method according to claim 12, wherein: The power conversion circuit is a resonant power converter.

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