Dual-frequency reconfigurable input amplifier stage circuit, amplifier, chip and system

Abstract

The application discloses a dual-frequency reconfigurable input amplification stage circuit, an amplifier, a chip and a system, wherein the dual-frequency reconfigurable input amplification stage circuit comprises a first matching network, a second matching network, a first transistor, a second transistor, a first transmission line and a second transmission line. One end of the first matching network is a signal 1 input end, the other end of the first matching network is connected with the gate of the first transistor, the drain of the first transistor is connected with one end of the first transmission line, the other end of the first transmission line is connected with one end of the second transmission line, the other end of the second transmission line is connected with the drain of the second transistor, the gate of the second transistor is connected with one end of the second matching network, and the other end of the second matching network is a signal 2 input end. The dual-frequency reconfigurable low-noise amplifier adopts the architecture of the dual-frequency reconfigurable input amplification stage, a reconfigurable matching network and a wideband amplification stage, frequency switching functions are realized by changing the signal input port and the control voltage of the reconfigurable matching network electronic switch, and the dual-frequency reconfigurable low-noise amplifier has good noise performance.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a dual-frequency reconfigurable input amplifier stage circuit, amplifier, chip, and system. Background Technology

[0002] Advances in fifth-generation mobile communication (5G) and satellite communication technologies have significantly improved latency and capacity for global internet access. To ensure compatibility with diverse communication applications, radio frequency (RF) systems supporting multi-frequency and multi-mode operation have become a research hotspot in both academia and industry. Low-noise amplifiers (LNOA), as core circuit units in RF receiver links, directly impact signal reception quality. While broadband LNOA can provide sufficient signal coverage and data transmission capabilities, its performance is limited in its primary operating frequency band, leading to additional power consumption and area overhead, increasing system complexity. Frequency-reconfigurable LNOA, through electrical control, achieves frequency switching, thereby meeting the signal amplification requirements of different communication standards and reducing system cost and power consumption. It represents a highly promising and valuable solution in multi-frequency applications.

[0003] Existing frequency-reconfigurable low-noise amplifiers (LNOA) primarily use transistor switches as the core devices to change the impedance of the matching network, enabling load switching or regulation at different frequencies. However, due to the parasitic effects of transistors or the parasitic resistance introduced by non-ideal turn-on / off states, adding switching devices to the input stage of a LNOA introduces additional noise, degrading system performance. Therefore, the mainstream approach is to use a wideband input matching network, with frequency reconfiguration implemented in the subsequent amplification stage. However, achieving wideband coverage in the input stage inevitably sacrifices some noise performance, still resulting in suboptimal overall RF performance, thus leaving room for further performance improvement. Furthermore, the parasitic resistance of transistor switches reduces the Q value of passive components, increases matching losses, and thus limits the frequency tuning range. Therefore, achieving the largest possible frequency tuning range with fewer switching devices is also a technical challenge for frequency-reconfigurable LNOA amplifiers. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a dual-frequency reconfigurable input amplifier stage circuit, amplifier, chip and system.

[0005] One aspect of this application provides a dual-frequency reconfigurable input amplifier stage circuit, including: a first matching network, a second matching network, a first transistor, a second transistor, a first transmission line, and a second transmission line;

[0006] The first matching network and the second matching network are matched to center frequency 1 and center frequency 2, respectively, for dual-frequency input impedance matching; one end of the first transmission line and the second transmission line are used for circuit combining, function multiplexing and impedance matching.

[0007] In some embodiments, the dual-frequency reconfigurable input amplifier stage circuit provided in this application has one end of the first matching network as the input terminal of signal 1, the other end of the first matching network connected to the gate of the first transistor, the drain of the first transistor connected to one end of the first transmission line, the other end of the first transmission line connected to one end of the second transmission line, the other end of the second transmission line connected to the drain of the second transistor, the gate of the second transistor connected to one end of the second matching network, and the other end of the second matching network as the input terminal of signal 2.

[0008] In some embodiments, the dual-frequency reconfigurable input amplifier circuit provided in this application operates at frequency 1, where the first transistor is in operation and the second transistor is powered off; and operates at frequency 2, where the first transistor is powered off and the second transistor is in operation.

[0009] In some embodiments, the dual-frequency reconfigurable input amplifier stage circuit provided in this application operates at frequency 1, where the impedance from the connection point of the first transmission line and the second transmission line towards the second transmission line participates in the impedance matching of the subsequently connected circuits; and operates at frequency 2, where the impedance from the connection point of the first transmission line and the second transmission line towards the first transmission line participates in the impedance matching of the subsequently connected circuits.

[0010] To achieve the above objectives, another aspect of the embodiments of this application proposes a dual-frequency reconfigurable low-noise amplifier, comprising:

[0011] The first amplifier circuit is implemented using the dual-frequency reconfigurable input amplifier stage circuit described above, wherein the output node of the dual-frequency input amplifier circuit is the connection point between the first transmission line and the second transmission line.

[0012] A reconfigurable matching network, one end of which is connected to the output node of the first amplifier circuit, is used to achieve impedance matching between the first amplifier circuit and the second amplifier circuit at different frequencies.

[0013] The second amplifier circuit includes a third transistor, and the input terminal of the second amplifier circuit is connected to the other end of the reconfigurable matching network.

[0014] The third amplifier circuit includes a fourth transistor. The input terminal of the third amplifier circuit is connected to the output terminal of the second amplifier circuit, and its output terminal serves as the output terminal of the dual-frequency reconfigurable low-noise amplifier.

[0015] In some embodiments, the dual-frequency reconfigurable low-noise amplifier provided in this application includes a reconfigurable matching network comprising a first capacitor, a third transmission line, a first electronic switch, a fourth transmission line, and a second capacitor.

[0016] One end of the first capacitor is connected to the output node of the first amplifier circuit, and the other end of the first capacitor is connected to one end of the third transmission line and one end of the first electronic switch. The other end of the third transmission line is connected to the other end of the first electronic switch and one end of the second capacitor. The other end of the second capacitor is connected to one end of the fourth transmission line and the gate of the third transistor. The other end of the fourth transmission line serves as the gate bias port of the third transistor.

[0017] In some embodiments, the first electronic switch is implemented using a transistor;

[0018] In some embodiments of the present application, the dual-frequency reconfigurable low-noise amplifier provided in the present application further includes a broadband matching network 1 in the second amplifier circuit.

[0019] One end of the broadband matching network 1 is connected to the drain of the third transistor, and the other end of the broadband matching network 1 is connected to the gate of the fourth transistor.

[0020] In some embodiments, the dual-frequency reconfigurable low-noise amplifier provided in this application further includes a negative feedback network and a broadband matching network 2 in the third amplifier circuit.

[0021] One end of the negative feedback network is connected to the gate of the fourth transistor, and the other end of the negative feedback network is connected to the drain of the fourth transistor.

[0022] One end of the broadband matching network 2 is connected to the drain of the fourth transistor, and the other end of the broadband matching network 2 serves as the output of the dual-frequency reconfigurable low-noise amplifier.

[0023] In some embodiments, the dual-frequency reconfigurable low-noise amplifier provided in this application operates at frequency 1, where the input terminal of the dual-frequency reconfigurable low-noise amplifier is the signal 1 input terminal, the first transistor is in operation, the power supply to the second transistor is disconnected, and the first electronic switch in the reconfigurable matching network is turned off; when operating at frequency 2, the input terminal of the dual-frequency reconfigurable low-noise amplifier is the signal 2 input terminal, the power supply to the first transistor is disconnected, the second transistor is in operation, and the first electronic switch in the reconfigurable matching network is turned on.

[0024] To achieve the above objectives, another aspect of the embodiments of this application proposes a chip including the aforementioned dual-frequency reconfigurable input amplifier stage circuit or dual-frequency reconfigurable low-noise amplifier.

[0025] To achieve the above objectives, another aspect of this application provides a radio frequency receiver system including the aforementioned chip.

[0026] The embodiments of this invention offer at least the following advantages: First, compared to broadband low-noise amplifiers, this invention achieves operating frequency switching through input port switching and a reconfigurable matching network, thereby improving out-of-band rejection characteristics and reducing interference from out-of-band signals to the receiver system. Second, compared to the broadband trade-off solution of input noise matching and gain matching in broadband low-noise amplifiers, the embodiments of this invention reduce the difficulty of input noise matching through frequency reconfiguration, thereby reducing noise in the actual operating frequency band and improving the RF performance of the receiver system. Finally, compared to dual-frequency receiver RF systems using two low-noise amplifiers with different operating frequencies, this invention reduces the complexity of dual-frequency or multi-frequency RF receiver systems and lowers system costs through circuit multiplexing. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the dual-frequency reconfigurable receiver low-noise amplifier circuit architecture in Embodiment 2 of the present invention;

[0029] Figure 2 This is a circuit diagram of the dual-frequency reconfigurable receiver low-noise amplifier circuit in Embodiment 2 of the present invention;

[0030] Figure 3 This is the layout of the dual-frequency reconfigurable receiver low-noise amplifier circuit implemented on the GaN process platform in Embodiment 2 of the present invention;

[0031] Figure 4 This is a simulation result diagram of the S21 parameter of the dual-frequency reconfigurable low-noise amplifier in Embodiment 2 of the present invention;

[0032] Figure 5 This is a simulation result diagram of the S11 parameters of the dual-frequency reconfigurable low-noise amplifier in Embodiment 2 of the present invention;

[0033] Figure 6 This is a simulation result diagram of the S22 parameter of the dual-frequency reconfigurable low-noise amplifier in Embodiment 2 of the present invention;

[0034] Figure 7This is a simulation result of the noise figure of the dual-frequency reconfigurable low-noise amplifier in Embodiment 2 of the present invention;

[0035] Figure 8 This is a circuit diagram of the dual-frequency reconfigurable low-noise amplifier in Embodiment 3 of the present invention;

[0036] Figure 9 This is a circuit diagram of the dual-frequency reconfigurable low-noise amplifier in Embodiment 4 of the present invention;

[0037] Figure 10 This is an architecture diagram of the dual-frequency reconfigurable radio frequency receiver system in Embodiment 5 of the present invention. Detailed Implementation

[0038] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the embodiments of this application. The singular forms "a," "described," and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise expressly limited, terms such as "set," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0040] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0042] In the description of this application, "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship.

[0043] Frequency-reconfigurable low-noise amplifiers (NRLAs) achieve frequency switching through electrical control, thereby meeting the signal amplification requirements of communication systems with different communication standards. Existing NRLA designs primarily use transistor switches as the core device to change the impedance of the matching network, enabling load regulation at different frequencies. However, due to the parasitic effects of transistors or the parasitic resistance introduced by non-ideal switching on / off states, the input stage of NRLAs generally employs a wideband matching strategy. Frequency reconfiguration is then implemented in subsequent amplification stages to avoid introducing additional noise and degrading system performance. Achieving wideband coverage inevitably sacrifices some noise performance, but still achieves suboptimal overall RF performance, thus leaving room for further performance improvement. Furthermore, the parasitic resistance of transistor switches reduces the Q value of passive components and increases matching losses, thereby limiting the frequency control range. Therefore, achieving the largest possible frequency control range with fewer switching devices is a significant technical challenge for NRLAs.

[0044] To address the existing technical problems, this invention proposes a dual-frequency reconfigurable input amplifier stage circuit, a dual-frequency reconfigurable low-noise amplifier, a chip, and an RF receiver system. For example... Figure 1 As shown, the dual-frequency reconfigurable low-noise amplifier of the present invention uses a dual-frequency reconfigurable input amplifier stage circuit as the input stage, and cascades a frequency reconfigurable matching network and two broadband amplifier stages to achieve high gain and obtain a low noise figure within the operating frequency band.

[0045] Example 1:

[0046] This embodiment provides a dual-frequency reconfigurable input amplifier stage circuit, characterized in that it includes a first matching network, a second matching network, a first transistor, a second transistor, a first transmission line, and a second transmission line;

[0047] The first matching network and the second matching network respectively realize input impedance matching in the frequency band, which is used for input impedance matching of frequency reconfigurable dual-frequency low-noise amplifiers; one end of the first transmission line and the second transmission line are used for circuit combining, function multiplexing and impedance matching.

[0048] In this embodiment, a high electron mobility transistor (HEMT) is used. When operating in one frequency band, the first transistor is active while the second transistor is powered off. In this case, the second transistor can be simply considered as a small parasitic resistance, or its drain can be considered as grounded. This makes the second transmission line a short circuit, adjusting the output impedance of the dual-frequency reconfigurable input amplifier stage. When operating in another frequency band, the second transistor is active while the first transistor is powered off. In this case, the first transistor can be simply considered as a small parasitic resistance, or its drain can be considered as grounded. This makes the first transmission line a short circuit, adjusting the output impedance of the dual-frequency reconfigurable input amplifier stage. Based on this method, the output impedance of the dual-frequency reconfigurable input amplifier stage can be adjusted to achieve the frequency reconfigurability of the circuit.

[0049] Example 2:

[0050] See Figure 2 This embodiment provides a dual-frequency reconfigurable low-noise amplifier, including:

[0051] The first amplifier circuit includes a first matching network IMN1, a second matching network IMN2, a first transistor T1, a second transistor T2, a first transmission line TL1, and a second transmission line TL2. One end of the first matching network IMN1 is the input terminal for signal 1, and the other end of the first matching network IMN1 is connected to the gate of the first transistor T1. The drain of the first transistor T1 is connected to one end of the first transmission line TL1, and the other end of the first transmission line TL1 is connected to one end of the second transmission line TL2. The other end of the second transmission line TL2 is connected to the drain of the second transistor T2, and the gate of the second transistor T2 is connected to one end of the second matching network IMN2. The other end of the second matching network IMN2 is the input terminal for signal 2.

[0052] The reconfigurable matching network includes a first capacitor C1, a third transmission line TL3, a first electronic switch S1, a fourth transmission line TL4, and a second capacitor C2.

[0053] The second amplifier circuit includes a third transistor T3 and a broadband matching network 1;

[0054] The third amplifier circuit includes a fourth transistor T4, a negative feedback network, and a broadband matching network 2.

[0055] As an optional implementation, one end of the first capacitor C1 is connected to the output node of the first amplifier circuit, and the other end of the first capacitor C1 is simultaneously connected to one end of the third transmission line TL3 and one end of the first electronic switch S1. The other end of the third transmission line TL3 is connected to the other end of the first electronic switch S1 and is also connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to one end of the fourth transmission line TL4 and the gate of the third transistor T3. The other end of the fourth transmission line serves as the gate bias port of the third transistor.

[0056] As an optional implementation, the first amplifier circuit further includes a first bias transmission line TLd1, a second bias transmission line TLd2, and a combining capacitor Cs; one end of the first bias transmission line TLd1 is connected to a bias voltage Vd1, and the other end of the first bias transmission line TLd1 is connected to the drain of the first transistor T1 and one end of the first transmission line TL1; one end of the second bias transmission line TLd2 is connected to a bias voltage Vd2, and the other end of the second bias transmission line TLd2 is connected to one end of the second transmission line TL2 and one end of the combining capacitor Cs, the other end of the combining capacitor Cs is connected to the other end of the first transmission line TL1, and the other end of the second transmission line TL2 is connected to the drain of the second transistor T2.

[0057] See Figure 2 As an optional implementation, the first matching network IMN1, the second matching network IMN2, the broadband matching network 1, the negative feedback matching network, and the broadband matching network 2 also include corresponding specific circuit elements and implementation methods, such as transmission lines, capacitors, and resistors. Furthermore, the embodiments of this application also include an RF grounding capacitor on the bias line. It should be noted that, in addition to using… Figure 2 The method shown can be implemented in other existing ways, but since these components are not important components of this application, they will not be described in detail here.

[0058] (1) Circuit structure description

[0059] like Figure 2As shown, the dual-frequency reconfigurable low-noise amplifier in this embodiment consists of three cascaded amplification stages. The first stage amplification circuit uses two common-source transistors, each with a source-degraded inductor structure (implemented via transmission lines), to amplify the signal. The gate bias lines of all transistors are integrated into the short-circuited transmission lines in the matching network to reduce the circuit area. The circuit in this embodiment has two input terminals (RFin1, RFin2). During operation, a signal is applied to one of them, while the other input terminal is left floating, resulting in a conventional single-ended input, single-ended output circuit. The source of the transistor in the third amplification circuit is directly grounded, and a negative feedback structure is added to improve the high-frequency gain. The entire circuit requires six power supplies (Vg1, Vd1, Vg2, Vd2, Vg3, Vd3), where Vsw is the gate control voltage of the electronic switch, and the remaining power supply ports supply power to the corresponding amplification circuit transistors.

[0060] (2) Explanation of circuit working principle

[0061] The amplifier circuit in this embodiment is a voltage-controlled, frequency-reconfigurable, low-noise amplifier. The first amplifier circuit achieves matching for two operating frequency bands separately, independently optimizing noise performance. When the input signal frequency is f1, the power supplies Vg2 and Vd2 of transistor T2 are disconnected, and the input port RFin2 is floating. At this time, transistor T2 can be equivalent to a small resistor, and the drain of T2 is a low-impedance path. Therefore, transmission line TL2 is connected in parallel with the output signal path of transistor T1 as a short circuit, thus participating in impedance matching at frequency f1. At the same time, the electronic switch S1 in the reconfigurable matching network is turned off by the bias voltage Vsw, thereby achieving impedance matching between the first and second amplifier circuits. When the input signal frequency is f2, the power supplies Vg1 and Vd1 of transistor T1 are disconnected, and the input port RFin1 is floating. The electronic switch S1 in the reconfigurable matching network is turned on by the bias voltage Vsw, thus similarly achieving impedance matching at frequency f2.

[0062] The second amplifier circuit and the third-party circuit achieve impedance matching at frequencies f1 and f2 simultaneously through a broadband matching network 1. Due to the severe high-frequency gain roll-off effect of the transistor, in order to improve the high-frequency gain, the third amplifier circuit adopts a distributed resistance, inductance and capacitance negative feedback based on transmission lines, and then satisfies the impedance matching at frequencies f1 and f2 through a broadband matching network 2.

[0063] In summary, the embodiments of the present invention employ a dual-frequency reconfigurable input stage + reconfigurable matching network + wideband output stage to achieve low-noise signal amplification in two operating frequency bands.

[0064] (3) Map design

[0065] The dual-frequency reconfigurable low-noise amplifier in this embodiment is implemented using GaN MMIC technology, and the circuit layout is as follows: Figure 3 As shown.

[0066] (4) Experimental results

[0067] The amplifier in this embodiment can be used for dual-band wireless system communication in the 18GHz band of satellite communication and the 28GHz band of 5G millimeter wave. The simulation results of parameter S21 are as follows: Figure 4 As shown, the peak gain is 20.5dB and 14.3dB in the 18GHz and 28GHz bands, respectively. Simulation results for S11 parameters are as follows: Figure 5 As shown, S11 has a reflection coefficient of -7dB and -15dB in the 18GHz and 28GHz bands, respectively. The higher reflection coefficient in the 18GHz band is due to the input impedance matching prioritizing noise figure optimization. Simulation results for S22 parameters are shown below. Figure 6 As shown, the S22 has a noise figure of -11dB and -26dB in the 18GHz and 28GHz bands, respectively. The simulation results are as follows: Figure 7 As shown, the noise figures are 1.69dB and 2.48dB in the 18GHz and 28GHz bands, respectively.

[0068] Example 3:

[0069] like Figure 8 As shown, the dual-frequency reconfigurable low-noise amplifier provided in Embodiment 3 has the same circuit structure as that in Embodiment 2, and also adopts a dual-frequency reconfigurable input amplification stage. The difference is that Embodiment 3 modifies the first transmission line TL1 and the second transmission line TL2 in Embodiment 2 into two T-type transmission line structures. This structure in Embodiment 3 can increase the matching degree of the first amplification circuit and the second amplification circuit at two operating frequencies to a certain extent. At the same time, it is more convenient for the power supply design of the first transistor T1 and the second transistor T2, but it increases the circuit area relatively.

[0070] Example 4:

[0071] like Figure 9 As shown, the dual-frequency reconfigurable low-noise amplifier provided in Embodiment 4 has the same circuit structure as that in Embodiment 2, also employing a dual-frequency reconfigurable input amplification stage. The difference lies in that the reconfigurable matching network in Embodiment 4 uses two electronic switches (S1, S2), and adds a parallel short circuit TL9 and a transmission line TL10. Using two electronic switches increases the design freedom of the reconfigurable matching network, achieving better matching characteristics, but it also increases signal path loss, circuit area, and power supply complexity.

[0072] Example 5:

[0073] like Figure 10 As shown, Embodiment 5 provides a possible dual-band reconfigurable RF receiver system architecture, including the dual-band reconfigurable low-noise amplifier, broadband low-noise amplifier, broadband adjustable attenuator, broadband drive amplifier, and broadband digitally controlled direction shifter of the present invention. The dual-band reconfigurable low-noise amplifier of the present invention is implemented on a GaN process platform, while the remaining circuit modules are implemented on a CMOS process platform, and ultimately integrated off-chip into the system to achieve system-level frequency band reconfigurability.

[0074] The dual-frequency reconfigurable low-noise amplifier implemented based on the above embodiments should be independent of integrated circuit technology and assembly method, such as using CMOS, GaAs, GaN, etc., monolithic integration, or integration on a PCB board through die wire bonding.

[0075] It should be noted that the inductors, capacitors, and transmission lines mentioned above are not limited to actual electronic devices, but can also be equivalents through electrical connection methods such as series, parallel, and coupling.

[0076] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0077] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A dual-frequency reconfigurable low noise amplifier, characterized in that, The application relates to a double-frequency reconfigurable low-noise amplifier. The first amplification circuit comprises a first matching network, a second matching network, a first transistor, a second transistor, a first transmission line and a second transmission line; the first matching network and the second matching network are matched with center frequency 1 and center frequency 2 respectively, and are used for double-frequency input impedance matching; the first transmission line and the second transmission line are used for circuit combination, function multiplexing and impedance matching; the output node of the first amplification circuit is the connection point of the first transmission line and the second transmission line; one end of the first matching network is a signal 1 input end, the other end of the first matching network is connected with the gate of the first transistor, the drain of the first transistor is connected with one end of the first transmission line, the other end of the first transmission line is connected with one end of the second transmission line, the other end of the second transmission line is connected with the drain of the second transistor, the gate of the second transistor is connected with one end of the second matching network, and the other end of the second matching network is a signal 2 input end; the source of the first transistor and the source of the second transistor are both connected with the ground through transmission lines; The reconfigurable matching network is connected with the output node of the first amplification circuit, and is used for realizing impedance matching between the first amplification circuit and the second amplification circuit under different frequencies; The second amplification circuit comprises a third transistor, and the input end of the second amplification circuit is connected with the other end of the reconfigurable matching network; The third amplification circuit comprises a fourth transistor, the input end of the third amplification circuit is connected with the output end of the second amplification circuit, and the output end of the third amplification circuit is used as the output end of the double-frequency reconfigurable low-noise amplifier; The reconfigurable matching network comprises a first capacitor, a third transmission line, a first electronic switch, a fourth transmission line and a second capacitor; One end of the first capacitor is connected with the output node of the first amplification circuit, the other end of the first capacitor is simultaneously connected with one end of the third transmission line and one end of the first electronic switch, the other end of the third transmission line is connected with the other end of the first electronic switch and simultaneously connected with one end of the second capacitor, the other end of the second capacitor is connected with one end of the fourth transmission line and the gate of the third transistor, and the other end of the fourth transmission line is used as the gate bias port of the third transistor.

2. The dual-band reconfigurable low noise amplifier of claim 1, wherein, When the circuit works at frequency 1, the first transistor is in working state, and the power supply of the second transistor is disconnected; when the circuit works at frequency 2, the power supply of the first transistor is disconnected, and the second transistor is in working state.

3. The dual-band reconfigurable low noise amplifier of claim 1, wherein, When the circuit works at frequency 1, the impedance of the second transmission line from the connection point of the first transmission line and the second transmission line to the direction of the second transmission line is used for impedance matching of the subsequent connected circuit; when the circuit works at frequency 2, the impedance of the first transmission line from the connection point of the first transmission line and the second transmission line to the direction of the first transmission line is used for impedance matching of the subsequent connected circuit.

4. The dual-band reconfigurable low noise amplifier of claim 1, wherein, The second amplification circuit further comprises a broadband matching network 1; One end of the broadband matching network 1 is connected with the drain of the third transistor, and the other end of the broadband matching network 1 is connected with the gate of the fourth transistor.

5. The dual-band reconfigurable low noise amplifier of claim 1, wherein, The third amplification circuit further comprises a negative feedback network and a broadband matching network 2; One end of the negative feedback network is connected to the gate of the fourth transistor, and the other end of the negative feedback network is connected to the drain of the fourth transistor; One end of the broadband matching network 2 is connected to the drain of the fourth transistor, and the other end of the broadband matching network 2 serves as an output end of the dual-frequency reconfigurable low-noise amplifier.

6. The dual-band reconfigurable low noise amplifier of claim 1, wherein, When working at frequency 1, the input end of the dual-frequency reconfigurable low-noise amplifier is a signal 1 input end, the first transistor is in a working state, the second transistor is powered off, and the first electronic switch in the reconfigurable matching network is closed; when working at frequency 2, the input end of the dual-frequency reconfigurable low-noise amplifier is a signal 2 input end, the first transistor is powered off, the second transistor is in a working state, and the first electronic switch in the reconfigurable matching network is opened.

7. A chip, characterized by The dual-frequency reconfigurable low-noise amplifier as claimed in any one of claims 1-6.

8. A radio frequency receiver system, characterized by The chip as claimed in claim 7.

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