Frequency divider with adjustable output delay
By designing a frequency divider with adjustable output delay, the clock synchronization problem of a wide range of input reference clock frequencies and a multi-clock system in FPGA or ASIC design is solved, frequency adjustment and delay control are achieved, the frequency range of the input clock signal is expanded, and the stability of the PLL loop and the synchronization of the multi-clock system are ensured.
Patent Information
- Application Number
- CN202510895464.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-10-14
AI Technical Summary
In FPGA or ASIC design, low-frequency clocks of different frequencies need to be generated to meet the needs of different modules. However, existing technologies have difficulty handling clock synchronization issues with a wide range of input reference clock frequencies and multi-clock systems.
A frequency divider with adjustable output delay is designed, which includes an input module, a frequency divider module and an output delay adjustment module. Through components such as inverters, capacitors, resistors, programmable frequency dividers and adjustable output delay units, the frequency adjustment and delay time of the input clock signal can be flexibly controlled.
The frequency range of the input clock signal is widened, and the configuration of different division ratios is realized, which ensures the bandwidth stability of the PLL loop and realizes clock synchronization in the multi-clock system to ensure the working timing requirements of each module.
Smart Images
Figure CN120785342A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a frequency divider with adjustable output delay. BACKGROUND
[0002] In FPGA or ASIC design, it is often required to generate low frequency clock from high frequency clock to meet the needs of different modules. In PLL design, the frequency of input reference clock signal has a wide range, and a pre-stage frequency divider with different frequency division ratio is often required to meet the design requirements of PLL system. In multi-clock domain system, in order to ensure the reliability of data transmission, the timing requirements of clock edge are very strict. SUMMARY
[0003] The present application aims to provide a frequency divider with adjustable output delay to solve the problems of wide range of input reference clock frequency required by system and clock synchronization required by multi-clock system.
[0004] To solve the above technical problems, the present application provides a frequency divider with adjustable output delay, comprising: an input module, a frequency division module, an output delay adjustment module.
[0005] The input module isolates the input clock signal from the previous stage circuit, and improves the swing of the input clock signal.
[0006] The frequency division module is used to adjust the frequency of the output clock signal.
[0007] The output delay adjustment module is used to adjust the output delay time of the output clock signal.
[0008] In an embodiment, the input module comprises a first inverter, a first capacitor and a first resistor.
[0009] The input clock signal port CLKIN is connected to the input end of the first inverter through the first capacitor, and the input end of the first inverter is also connected to the output end of the first inverter through the first resistor, and the output end of the first inverter is also connected to the frequency division module.
[0010] In an embodiment, the frequency division module comprises a programmable frequency divider, a first two-input AND gate and a second two-input AND gate; the programmable frequency divider comprises a frequency selection control port S, a frequency division ratio control word port DIV_D <n:0>.
[0011] The clock input end of the programmable frequency divider, the output end of the first inverter and the first input end of the first two-input AND gate are connected; the frequency selection control port S is connected with the second input end of the first two-input AND gate; the output end of the programmable frequency divider is connected with the first input end of the second two-input AND gate; the output end of the first two-input AND gate is connected with the second input end of the second two-input AND gate, and the output end of the second two-input AND gate is connected with the output delay adjustment module.
[0012] In an embodiment, the output delay adjustment module comprises an adjustable output delay unit and a third two-input AND gate; the adjustable output delay unit comprises an output delay selection control port DELAY_D <m:0>and a reset port RESET;
[0013] The input end of the adjustable output delay unit is connected with the output end of the second two-input AND gate, the output end of the adjustable output delay unit is connected with the output end of the third two-input AND gate, and the output end of the third two-input AND gate is connected with the output port CLKOUT. DELAY The second input end of the third two-input AND gate is connected with the output end of the second two-input AND gate, the first input end of the third two-input AND gate is connected with the output end of the second two-input AND gate, and the output end of the third two-input AND gate is connected with the output port CLKOUT.
[0014] In an embodiment, the adjustable output delay unit comprises a decoder, a 2 M+1 stage two-input OR gate, a 2 M+1 stage D flip-flop, and a second resistor.
[0015] The 2 M+1 stage two-input OR gate comprises a 2 M+1 -1 stage two-input OR gate, a 2 M+1 -2 stage two-input OR gate,..., and a 0 stage two-input OR gate. M+1 The 2 M+1 -1 stage D flip-flop, a 2 M+1 -2 stage D flip-flop,..., and a 0 stage D flip-flop.
[0016] The output delay selection control port DELAY_D <m:0>Connected to the decoder input terminal; the decoder output terminal T<2 M+1 -1:0> and 2 M+1 The first input terminal of the second-input OR gate of the stage is connected;
[0017] Clock input signal port CLKB and 2 M+1 The clock input of the D flip-flop is connected; the reset port RESET is connected to the 2 M+1 The reset control terminal of the D flip-flop of the second stage is connected; M+1 The second input terminal of the -1-stage two-input OR gate is connected to the ground through a second resistor;
[0018] The output of each level of two-input OR gate is connected to the input D of the same level D flip-flop; the output Q of each level of D flip-flop is connected to the second input of the next level of two-input OR gate; the output Q of the 0th level D flip-flop is connected to the output delay control output port T DELAY are connected.
[0019] The present invention provides a frequency divider with adjustable output delay, which can widen the frequency range of the input clock signal. When used in a PLL pre-divider, it can achieve different frequency division ratios for a wide range of reference frequencies, thereby ensuring the bandwidth stability of the PLL loop. Secondly, the present invention can improve the flexibility of the output clock delay and can be applied to clock-sensitive multi-clock systems to achieve clock synchronization and ensure the working timing of each module. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of a frequency divider with adjustable output delay provided by the present invention;
[0021] Figure 2 The present invention provides a circuit schematic diagram of an adjustable delay unit in a frequency divider with adjustable output delay. DETAILED DESCRIPTION
[0022] The following is a detailed description of a frequency divider with adjustable output delay proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.
[0023] like Figure 1 As shown, the present invention provides a frequency divider with adjustable output delay, comprising an input module, a frequency dividing module, and an output delay adjusting module.
[0024] The input module comprises an inverter INV1, a capacitor C1 and a resistor R1. The input clock signal port CLKIN is connected to the input end of the inverter INV1 through the capacitor C1, the input end of the inverter INV1 is also connected to the output end of the inverter INV1 through the resistor R1, and the output end of the inverter INV1 is connected to the frequency division module.
[0025] The frequency division module comprises a programmable frequency divider, a two-input AND gate AND1 and a two-input AND gate AND2. The programmable frequency divider comprises a frequency selection control port S, a frequency division ratio control word port DIV_D <n:0>The clock input end of the programmable frequency divider, the output end of the inverter INV1 are connected with the input end A of the two-input AND gate AND1; the frequency selection control port S of the programmable frequency divider is connected with the input end B of the two-input AND gate AND1; the output end of the programmable frequency divider is connected with the input end A of the two-input AND gate AND2; the output end of the two-input AND gate AND1 is connected with the input end B of the two-input AND gate AND2; and the output end of the two-input AND gate AND2 is connected with the output delay adjustment module.
[0026] The output delay adjustment module comprises an adjustable output delay unit and a two-input AND gate AND3. The adjustable output delay unit comprises an output delay selection control port DELAY_D <m:0>The input of the adjustable output delay unit is connected to the output of the two-input AND gate AND2, and the output T DELAY The input terminal A of the two-input AND gate AND3 is connected to the output terminal of the two-input AND gate AND2, and the output terminal of the two-input AND gate AND3 is connected to the output port CLKOUT.
[0027] like Figure 2 As shown, the adjustable delay unit includes a decoder, 2 M+1 Level 2 input OR gate, 2 M+1 D-type flip-flop, resistor R2. Output delay selection control port DELAY_D of adjustable output delay unit <m:0>Connected to the decoder input; the decoder output T<2 M+1 -1:0> and 2 M+1 The input terminal A of the second-level input or gate is connected; the clock input signal port CLKB is connected to 2 M+1 The clock input of the D flip-flop is connected; the reset port RESET is connected to the 2 M+1 The reset control terminal of the D flip-flop of the second stage is connected; M+1 -1 The input terminal B of the two-input OR gate is connected to the ground through the resistor R2; M+1 -1st level two-input OR gate output and 2nd level two-input OR gate output M+1 -1st level D flip-flop input terminal D is connected; M+1 -1st level D flip-flop output Q and 2nd level D flip-flop output Q M+1 -2 level two input OR gate input terminal B is connected; M+1 -2 level two input OR gate output and 2 M+1 -2-stage D flip-flop input terminal D is connected; M+1 -2 stage D flip-flop output Q and 2 M+1 -3 level two-input OR gate input terminal B is connected, and in this way until the output terminal Q of the 0th level D flip-flop is connected to the output delay control output port T DELAY are connected.
[0028] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A frequency divider with adjustable output delay, characterized in that: include: Input module, frequency division module, output delay adjustment module; The input module isolates the input clock signal from the preceding circuit, thereby increasing the swing amplitude of the input clock signal; The frequency division module is used to adjust the frequency of the output clock signal; The output delay adjustment module is used to adjust the output delay time of the output clock signal.
2. The frequency divider with adjustable output delay according to claim 1, wherein: The input module includes a first inverter, a first capacitor, and a first resistor; The input clock signal port CLKIN is connected to the input end of the first inverter through the first capacitor. The input end of the first inverter is also connected to the output end of the first inverter through the first resistor. The output end of the first inverter is also connected to the frequency division module.
3. The frequency divider with adjustable output delay as claimed in claim 2, characterized in that: The frequency division module includes a programmable frequency divider, a first two-input AND gate, and a second two-input AND gate; the programmable frequency divider includes a frequency selection control port S, a frequency division ratio control word port DIV_D <n:0> ，< / n:0> The clock input end of the programmable frequency divider and the output end of the first inverter are simultaneously connected to the first input end of the first two-input AND gate; the frequency selection control port S is connected to the second input end of the first two-input AND gate; the output end of the programmable frequency divider is connected to the first input end of the second two-input AND gate; the output end of the first two-input AND gate is connected to the second input end of the second two-input AND gate, and the output end of the second two-input AND gate is connected to the output delay adjustment module.
4. The frequency divider with adjustable output delay as claimed in claim 3, characterized in that: The output delay adjustment module includes an adjustable output delay unit and a third two-input AND gate; the adjustable output delay unit includes an output delay selection control port DELAY_D <m:0> And reset port RESET;< / m:0> The input end of the adjustable output delay unit is connected to the output end of the second two-input AND gate, and the output end T DELAY The first input terminal of the third two-input AND gate is connected to the output terminal of the second two-input AND gate, and the output terminal of the third two-input AND gate is connected to the output port CLKOUT.
5. The frequency divider with adjustable output delay as claimed in claim 4, characterized in that: The adjustable output delay unit includes a decoder, 2 M+1 Level 2 input OR gate, 2 M+1 Stage D flip-flop, second resistor; 2 M+1 The second-level input OR gate includes: M+1 -1st level two-input OR gate, 2nd M+1 -2nd level two-input OR gate, ..., 0th level two-input OR gate; 2 M+1 The second-stage D flip-flop includes: M+1 -1st level D flip-flop, 2nd M+1 -2nd level D flip-flop, ..., 0th level D flip-flop; The output delay selection control port DELAY_D of the adjustable output delay unit <m:0>Connected to the decoder input terminal; the decoder output terminal T<2 M+1 -1:0> and 2 M+1 The first input terminal of the second-input OR gate of the stage is connected; Clock input signal port CLKB and 2 M+1 The clock input of the D flip-flop is connected; the reset port RESET is connected to the 2 M+1 The reset control terminal of the D flip-flop of the second stage is connected; M+1 The second input terminal of the -1-stage two-input OR gate is connected to the ground through a second resistor; The output of each level of two-input OR gate is connected to the input D of the same level D flip-flop; the output Q of each level of D flip-flop is connected to the second input of the next level of two-input OR gate; the output Q of the 0th level D flip-flop is connected to the output delay control output port T DELAY are connected.