Remote monitoring system based on single-chip microcomputer and control method thereof

Abstract

The application belongs to the technical field of single-chip microcomputer, and particularly relates to a remote monitoring system based on a single-chip microcomputer and a control method thereof. The system comprises a single-chip microcomputer, a sensor acquisition unit, a wireless communication unit and an execution mechanism. When the single-chip microcomputer, the sensor acquisition unit, the system initialization, the wireless communication unit and the execution mechanism are sequentially powered on, the single-chip microcomputer sends a handshake instruction to the wireless communication unit after completing hardware self-checking, establishes a secure channel with a remote control terminal, and writes a unique identity code into the single-chip microcomputer and enters a standby state after the handshake is completed. The single-chip microcomputer polls the sensor acquisition unit according to a preset sampling period to obtain an original data frame. The remote control terminal analyzes error correction compressed data blocks, generates a control instruction according to a threshold strategy and returns the control instruction. The single-chip microcomputer drives the execution mechanism to act after receiving the control instruction, and records an execution state log. The application has the advantages of high communication efficiency, strong link fault tolerance and fast remote control response.

Description

Technical Field

[0001] This invention belongs to the field of microcontroller technology, specifically relating to a microcontroller-based remote monitoring system and its control method. Background Technology

[0002] With the increasing maturity of IoT technology and edge computing architecture, microcontroller-based remote monitoring systems have been widely applied in industrial automation, environmental monitoring, smart agriculture, and smart buildings. As application scenarios become increasingly complex, remote monitoring systems are required to possess not only high-precision data acquisition capabilities but also highly reliable data transmission mechanisms and fault-tolerant data processing architectures. However, based on existing publicly available technologies, these systems still face numerous challenges in structural design, data processing methods, communication reliability, and remote control closed-loop capabilities, making it difficult to meet the practical application requirements for high stability, high real-time performance, and high security.

[0003] Most existing microcontroller-based monitoring systems generally adopt a unidirectional pipeline architecture of "data acquisition + upload + terminal processing". Specifically, the microcontroller periodically collects data from sensors, packages the collected data directly into fixed-format frames, and uploads them to a server or remote control terminal via wireless communication modules such as serial port, Wi-Fi, LoRa, or NB-IoT. The terminal then centrally handles data storage, processing, and control decisions. This traditional architecture has certain practical value in applications with a small number of sensors, simple environments, and high latency tolerance, offering a simple system structure and low implementation cost. However, when faced with application scenarios involving high sampling rates, large data volumes, and high interference, such as multi-point climate monitoring in agricultural greenhouses, real-time leak detection in industrial pipelines, or energy management of distributed equipment, the system exposes the following technical problems:

[0004] First, high data redundancy leads to severe bandwidth consumption in communication links. In existing technologies, raw data is uploaded directly after acquisition without local preprocessing. This "indiscriminate upload" method fails to consider the temporal correlation and information entropy structure of the data. Especially in long-term monitoring using multiple sensors, adjacent sample values ​​show minimal changes, resulting in a very high proportion of redundant information. This causes the wireless link to repeatedly transmit duplicate content, wasting valuable communication resources. In some bandwidth-constrained low-power wide-area networks (such as LoRa or NB-IoT), excessively long uploaded data frames can even lead to frequent packet loss and retransmissions, severely impacting system stability.

[0005] Second, weak link error protection capabilities lead to a lack of guarantee for remote data integrity. Traditional remote monitoring systems often only use simple parity checks or CRC checks to check the integrity of uploaded data. This verification mechanism can only detect single-bit flips and cannot correct multi-bit burst errors, which can only be recovered through retransmission. For systems deployed in remote areas or areas with unstable communication, frequent retransmissions will lead to decreased control timeliness, increased power consumption, and even control misjudgments due to retransmission failures. Furthermore, error correction mechanisms such as Reid-Solomon coding are not effectively integrated into most systems, firstly because of their high coding complexity, and secondly because a complete error correction chain is not incorporated into the system design. Summary of the Invention

[0006] The main objective of this invention is to provide a microcontroller-based remote monitoring system and its control method. By introducing multi-level data processing mechanisms such as differential linear encoding, Galois field polynomial indexing, coprime interleaving rearrangement, Reid-Solomon redundancy check, and cyclic redundancy compression on the microcontroller side, efficient redundancy reduction, strong error correction encapsulation, and structured uploading of sensor data are achieved. Simultaneously, by combining secure handshake, command feedback, and automatic rollback mechanisms, a stable and reliable closed loop for data uplink and control downlink is constructed. This invention offers advantages such as high communication efficiency, strong link fault tolerance, fast remote control response, and excellent system self-recovery capability, making it particularly suitable for remote monitoring applications with high interference, low bandwidth, and long-term unattended operation.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] On one hand, a microcontroller-based remote monitoring system is provided. The system includes a microcontroller, a sensor acquisition unit, a wireless communication unit, and an actuator. During system initialization, the microcontroller, sensor acquisition unit, and actuator are powered on sequentially. After completing a hardware self-test, the microcontroller sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is complete, the microcontroller writes a unique identification code and enters a standby state. The microcontroller polls the sensor acquisition unit according to a preset sampling period to acquire raw data frames. It performs sliding window denoising and timestamp marking on the raw data frames to generate and temporarily store data blocks to be processed. The microcontroller performs recursive processing on the data blocks to be processed based on differential linear coding and cyclic redundancy compression to maximize error propagation distance and minimize redundancy while maintaining real-time performance, outputting error-corrected compressed data blocks. The wireless communication unit reads the error-corrected compressed data blocks and uploads them to the remote control terminal through the secure channel. The remote control terminal parses the error-corrected compressed data blocks, generates control commands according to a threshold strategy, and sends them back. After receiving the control commands, the microcontroller drives the actuator and records the execution status log.

[0009] On the other hand, a control method for the aforementioned microcontroller-based remote monitoring system is provided, the method comprising:

[0010] Step 1: Power on the microcontroller, sensor acquisition unit, wireless communication unit and actuator in sequence. After the microcontroller completes the hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is completed, the microcontroller writes a unique identification code and enters standby mode.

[0011] Step 2: The microcontroller polls the sensor acquisition unit according to the preset sampling period to obtain the raw data frame; it performs sliding window denoising and timestamp marking on the raw data frame to generate a data block to be processed and temporarily stores it;

[0012] Step 3: The microcontroller performs recursive processing based on differential linear coding and cyclic redundancy compression on the data block to be processed, so as to maximize the error propagation distance and minimize redundancy while maintaining real-time performance, and outputs a data block with error correction and compression.

[0013] Step 4: The wireless communication unit reads the error-corrected compressed data block and uploads it to the remote control terminal through a secure channel; the remote control terminal parses the error-corrected compressed data block, generates control commands according to the threshold strategy, and sends them back; after receiving the control commands, the microcontroller drives the actuator to move and records the execution status log.

[0014] Furthermore, the method also includes: Step 5: When the number of execution failures recorded in the execution status log reaches a set value, the microcontroller automatically rolls back to step 1 to re-handshake.

[0015] Furthermore, step 3 specifically includes:

[0016] Step 3.1: Divide the data block to be processed into equal-length data segments; the microcontroller generates an irreducible polynomial index for each data segment on the Galois domain;

[0017] Step 3.2: Perform finite field differential encoding on each data segment to generate a set of adjoint polynomial coefficients;

[0018] Step 3.3: Establish a bidirectional mapping between the time domain and the Galois domain using the coprime interleaving depth, and rearrange the differenced data segments into an interleaving matrix;

[0019] Step 3.4: Calculate the Red-Solomon redundancy check vectors column by column for the interleaving matrix, generate a check vector group and append it to the interleaving matrix to obtain the check interleaving matrix;

[0020] Step 3.5: The microcontroller re-concatenates the check interleaving matrix and the Red-Solomon redundancy check vector row by row, performs binary cyclic redundancy compression, and outputs the error-corrected compressed data block to the sending buffer.

[0021] Further, step 3.1 specifically includes: the microcontroller reads the system parameter table to obtain the threshold for the length of a single data segment, which is set to a fixed value in bytes; if the total number of bytes in the data block to be processed is not divisible by the threshold, the microcontroller fills the end of the data block with zero-value bytes until the divisibility condition is met; the microcontroller sequentially extracts the data block to be processed from the first byte according to the threshold, obtaining several data segments in sequence, and allocates a continuous storage block for each data segment in the internal buffer, recording the start address and end address; the microcontroller calls the finite field arithmetic library in the firmware, treats a single data segment as a sequence of Galois field elements, and maps the sequence sequentially to Galois field polynomials. The order coefficients are calculated, with the highest-order coefficient corresponding to the first byte of the data segment and the lowest-order coefficient corresponding to the last byte. The microcontroller uses the fast Euclidean algorithm to calculate the greatest common factor (GCF) of the polynomial and all candidate polynomials whose orders are no greater than half of the polynomial's in the Galois field. If the GCF is a constant term, the polynomial is considered irreducible. If the test results indicate that the polynomial is reducible, the microcontroller increments the lowest-order coefficient by a preset increment and re-executes the test until it is determined to be an irreducible polynomial. The microcontroller generates a unique sequence number based on the polynomial's order and coefficient combination information. This sequence number is then written as an index of the irreducible polynomial into the segment header identifier area of ​​the corresponding data segment.

[0022] Further, step 3.2 specifically includes: the microcontroller sequentially loads each data segment and its corresponding irreducible polynomial index, and establishes a one-to-one temporary mapping table in the internal register; the microcontroller uses the irreducible polynomial index as the modulo polynomial to perform Galois field subtraction on the current data segment in byte order: the microcontroller directly writes the first byte of the data segment into the first element of the difference vector; starting from the second byte, the microcontroller calculates the difference between the current byte and the previous byte using Galois field subtraction, and writes the calculation result into the subsequent elements of the difference vector; the length of the difference vector is equal to the length of the data segment, and all elements are limited to the corresponding Galois field range; the microcontroller uses the difference vector elements as coefficients, and performs Galois field subtraction on the data segment in byte order. The microcontroller constructs a Galois field polynomial of the same order, with the highest-order coefficient corresponding to the first element of the difference vector and the lowest-order coefficient corresponding to the last element of the difference vector. This polynomial, together with the irreducible polynomial, forms a pair of adjoint polynomials. If the highest-order coefficient of the adjoint polynomial is zero in the Galois field, the microcontroller performs normalization according to the following rules: The microcontroller searches for the first non-zero coefficient from high to low order and promotes this coefficient and its corresponding power to the highest order position. For the moved intermediate coefficients, the microcontroller inserts zero values ​​as placeholders in their original positions to ensure that the order of the polynomial remains unchanged. The microcontroller generates a set of adjoint polynomial coefficients according to the order of the coefficients of each order of the adjoint polynomial and writes them to the end-of-data segment identifier area using a contiguous storage block.

[0023] Further, step 3.3 specifically includes: counting the number of data segments in the current batch and the byte length of a single data segment; determining the number of rows in the interleaving matrix according to the fixed row number threshold set in the system parameter table; directly using the number of data segments as the number of columns in the interleaving matrix, allocating a contiguous row-first storage block for the interleaving matrix in the internal memory; the microcontroller sequentially scanning the irreducible polynomial index and the first term coefficient of the corresponding adjoint polynomial coefficient group of each data segment, taking the remainder of the algebraic sum of the two modulo the byte length of a single data segment, and adding an integer value of one to obtain the candidate interleaving depth; if the greatest common factor of the candidate interleaving depth and the number of rows in the interleaving matrix is ​​not equal to one, the microcontroller sequentially increases the candidate interleaving depth until it matches the interleaving matrix. The interleaving process continues until the number of rows in the matrix is ​​coprime. The final interleaving depth is recorded as the coprime interleaving depth and archived in the system log. The microcontroller establishes a time pointer for time-domain mapping and sequentially traverses the differential vector elements of each data segment starting from zero. For the first write operation, the microcontroller multiplies the time pointer value by the coprime interleaving depth and takes the remainder with respect to the number of rows in the interleaving matrix. The result is used as the target row address. The target column address is obtained by taking the remainder of the time pointer with respect to the number of columns in the interleaving matrix. Based on this, the microcontroller writes the current differential vector element into the cell corresponding to the target row address and target column address in the interleaving matrix. After the write is completed, the time pointer is incremented by one, and the loop continues until all differential vector elements are written, resulting in the interleaving matrix.

[0024] Furthermore, to verify the reversibility of the time-domain write mapping, the microcontroller separately calculates the Galois domain read depth for Galois domain mapping. This read depth is set to the coprime interleaving depth plus an integer value of one. Since the coprime interleaving depth and the number of rows in the interleaving matrix are coprime, the Galois domain read depth and the number of rows in the interleaving matrix also remain coprime. The microcontroller reads the previously written elements row by row according to the same coprime mapping rule of the Galois domain read depth on the row address of the interleaving matrix in incrementing order of the read pointer, and reassembles them into a differential vector sequence in the register to obtain the interleaving matrix. By verifying that the first and last check codes of the differential vector are consistent with the original differential vector, the bidirectional mapping is confirmed to be correct.

[0025] The microcontroller-based remote monitoring system and its control method of this invention have the following beneficial effects: By integrating multi-level algorithms such as differential coding, Galois field polynomial indexing, coprime interleaving, Reid-Solomon redundancy check, and cyclic redundancy compression on the microcontroller side, this invention achieves a complete chain processing of data from acquisition, encoding, fragmentation, verification to compressed uploading, greatly enhancing the robustness and information integrity of the remote monitoring system in high-noise environments. Compared with traditional monitoring systems, this invention not only achieves unique identification and reversible mapping in the data structure, but also effectively disperses and corrects sudden bit errors in the communication link through interleaving and error correction mechanisms, reducing the dependence on retransmission mechanisms, thereby improving overall communication efficiency and system stability. In the execution phase, the system has automatic rollback and self-re-handshake mechanisms, enabling the proactive re-establishment of a safe control channel in the event of continuous action failures, avoiding long-term system out of control or data drift. More importantly, this invention uses a microcontroller as the edge computing core, without relying on complex hardware resources, to complete efficient data preprocessing and structured encoding, adapting to the deployment requirements of low-power, high-frequency, and small-size remote monitoring. Through this technological system, this invention constructs a remote monitoring solution that combines real-time performance, fault tolerance, and controllability, making it particularly suitable for scenarios such as power, industrial control, and smart agriculture, where high stability of the link and accuracy of decision-making are required. While maintaining low power consumption, the system significantly improves data upload quality, control execution closed-loop capability, and communication anti-interference performance, demonstrating significant value for engineering application and promotion. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0027] Figure 1 A schematic diagram of the system structure of a microcontroller-based remote monitoring system provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram illustrating the principle of differential linear coding and interleaving matrix rearrangement provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram illustrating the generation effect of the Red-Solomon redundancy check vector provided in an embodiment of the present invention. Detailed Implementation

[0030] The method of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0031] On one hand, this embodiment provides a microcontroller-based remote monitoring system, which includes: a microcontroller, a sensor acquisition unit, a wireless communication unit, and an actuator. During system initialization, the microcontroller, sensor acquisition unit, and actuator are powered on sequentially. After completing a hardware self-test, the microcontroller sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is complete, the microcontroller writes a unique identification code and enters a standby state. The microcontroller polls the sensor acquisition unit according to a preset sampling period to obtain raw data frames. It performs sliding window denoising and timestamp marking on the raw data frames to generate and temporarily store data blocks to be processed. The microcontroller performs recursive processing on the data blocks to be processed based on differential linear coding and cyclic redundancy compression to maximize error propagation distance and minimize redundancy while maintaining real-time performance, outputting error-corrected compressed data blocks. The wireless communication unit reads the error-corrected compressed data blocks and uploads them to the remote control terminal through the secure channel. The remote control terminal parses the error-corrected compressed data blocks, generates control commands according to a threshold strategy, and sends them back. After receiving the control commands, the microcontroller drives the actuator to operate and records the execution status log.

[0032] On the other hand, this embodiment also provides a control method for the above-mentioned microcontroller-based remote monitoring system, the method comprising:

[0033] Step 1: Power on the microcontroller, sensor acquisition unit, wireless communication unit and actuator in sequence. After the microcontroller completes the hardware self-test, it sends a handshake command to the wireless communication unit to establish a secure channel with the remote control terminal. After the handshake is completed, the microcontroller writes a unique identification code and enters standby mode.

[0034] Step 2: The microcontroller polls the sensor acquisition unit according to the preset sampling period to obtain the raw data frame; it performs sliding window denoising and timestamp marking on the raw data frame to generate a data block to be processed and temporarily stores it;

[0035] Step 3: The microcontroller performs recursive processing based on differential linear coding and cyclic redundancy compression on the data block to be processed, so as to maximize the error propagation distance and minimize redundancy while maintaining real-time performance, and outputs a data block with error correction and compression.

[0036] Step 4: The wireless communication unit reads the error-corrected compressed data block and uploads it to the remote control terminal through a secure channel; the remote control terminal parses the error-corrected compressed data block, generates control commands according to the threshold strategy, and sends them back; after receiving the control commands, the microcontroller drives the actuator to move and records the execution status log.

[0037] Furthermore, the method also includes: Step 5: When the number of execution failures recorded in the execution status log reaches a set value, the microcontroller automatically rolls back to step 1 to re-handshake.

[0038] refer to Figure 1 In remote monitoring scenarios, the core objective is to ensure that physical quantities distributed across the field can reach the remote control terminal in a timely, complete, and reliable manner. The terminal then calculates and makes decisions, sending back instructions to drive the field actuators to complete closed-loop actions. This invention uses a microcontroller as the computing center of the edge nodes, integrating sensor acquisition units, wireless communication units, and actuators into a unified architecture. It supports the real-time performance and reliability of remote monitoring through three main lines: hardware timing constraints, data recursive processing, and link security reinforcement. First, hardware timing constraints are reflected in both power-on sequence and task scheduling: the sensor acquisition unit and wireless communication unit are powered on in a fixed order to avoid power disturbances between them; under the scheduling of the on-chip real-time operating system, the microcontroller manages four types of tasks—sampling, encoding, transmission, and execution—based on interrupt priority, ensuring the periodic determinism of the critical path.

[0039] Secondly, the data recursive processing mechanism enables multi-level redundancy reduction and error resistance processing of the original data locally. After the original data frame is denoised by sliding window to remove high-frequency jitter, it is timestamped to ensure time traceability; subsequently, differential linear coding replaces the absolute value with the difference between adjacent samples, reducing the entropy value from an information theory perspective and creating conditions for compression; recursive processing establishes feedback between the difference vector and the historical state, so that single-point errors spread into a detectable pattern in the encoded sequence, which, together with subsequent cyclic redundancy check, can be accurately located and corrected at the terminal. Thirdly, cyclic redundancy compression not only undertakes the traditional verification function, but also reduces the bit length through the reversible sliding window compression algorithm, significantly reducing wireless bandwidth occupation; the compressed error-correcting data block output is structurally composed of a header information area, a data area, and a tail reserved area. The header information area stores the uncompressed length, the order of the generator polynomial, and the zero-padding length, providing a complete context for terminal decompression and recovery. Meanwhile, link security hardening is achieved through a two-phase mechanism: during the handshake phase, a dynamic session key is generated and bound to a unique identification code; during the communication phase, an integrity check field and a replay protection counter are embedded in the header of each frame to prevent man-in-the-middle attacks and frame replay. After receiving the error-corrected compressed data block, the remote control terminal first verifies the integrity using a cyclic redundancy check field, then performs differential inverse encoding and recursive inverse operation to recover the time series data. A threshold strategy is used to fuse and judge multi-source information. When a sensor value crosses a critical interval or multiple indicators trigger a logic threshold, a control command is immediately generated and transmitted back through the established secure channel.

[0040] The microcontroller continuously monitors the downlink channel. Once it captures a control command matching its own identification code, it unpacks and parses the target parameters, driving the actuator to move within milliseconds. The actuator uses relay switching, stepper motor positioning, or pulse width modulation dimming, depending on the task type, to achieve precise physical control. Simultaneously, it archives the start and end times of the actions, feedback sensor readings, and result flags into an execution status log. The log is written to non-volatile memory and sent with the next batch of data blocks, enabling the remote terminal to synchronously monitor the execution effect, forming a closed-loop chain of data, decision-making, action, and feedback. If the log accumulates multiple consecutive execution failures, the microcontroller triggers automatic rollback: resetting the wireless communication unit and re-handshaking to ensure that abnormal states are isolated promptly. Overall, this invention introduces lightweight edge computing on the microcontroller side, bringing noise reduction, encoding, compression, and encryption processing to the data source front end. This not only significantly reduces wireless link overhead but also improves anti-interference and error correction capabilities. Combined with the strategic decision-making and dynamic control of remote terminals, it forms a remote monitoring system suitable for complex environments such as industry, agriculture, and buildings. While ensuring low power consumption and small size, it achieves comprehensive performance of high real-time performance, high reliability, and high security, fully demonstrating the core principles and key points of microcontroller-based remote monitoring technology.

[0041] Furthermore, in remote monitoring scenarios, the actuators are located in unattended field operations. If an action fails and cannot be repaired in time, it will directly lead to the failure of the monitoring closed loop. To ensure the system's long-term autonomous operation, the microcontroller writes the action result to the execution status log after executing each control command and maintains a continuous failure counter in the background. When the cumulative number of execution failures of the same command type in the log reaches a set threshold, the microcontroller immediately triggers an automatic rollback process: first, it stops the current task scheduling, resets the session register of the wireless communication unit, and then forcibly migrates the system state to the initial handshake stage, renegotiating the dynamic session key and unique identification code with the remote control terminal. During the handshake, the microcontroller simultaneously reports the latest fault summary, enabling the remote control terminal to detect field anomalies and update the threshold policy. With this mechanism, the remote monitoring system can proactively disconnect unreliable channels, rebuild encrypted channels, and refresh authentication information when potential hardware failures, link anomalies, or environmental interference are detected, thereby preventing the continuous issuance of erroneous commands or the implantation of false data and ensuring the data reliability and control security between field devices and remote terminals. This automatic rollback design eliminates the window of opportunity for manual intervention, while providing the terminal with precise fault location data, enabling remote monitoring to maintain high availability, autonomy, and reliability in complex environments. Thresholds can be dynamically issued by the remote control terminal and adaptively adjusted based on the aging of field equipment or changes in operating conditions, ensuring that excessive sensitivity or insensitivity is corrected promptly. Simultaneously, the continuous failure counter is automatically reset to zero after a successful handshake and receipt of an acknowledgment frame, preventing accidental rollback triggering.

[0042] Furthermore, in remote monitoring scenarios, sensor acquisition units continuously generate raw data frames. Without in-depth processing at the edge, this would consume significant wireless bandwidth and amplify the risk of link errors. This invention utilizes a microcontroller to execute the five-level cascaded algorithm in step 3 locally, achieving redundancy reduction, error resistance, and temporal rearrangement of high-density data, laying a secure, reliable, and low-latency foundation for a closed-loop remote monitoring system. First, step 3.1 divides the data block to be processed into equal-length segments and generates an irreducible polynomial index for each segment in the Galois domain. This decomposes the continuous temporal stream into independent mathematical entities and provides a one-to-one modulo polynomial constraint for subsequent finite-field differential coding. The irreducible polynomial index not only ensures the independence of the computational space for each data segment but also provides a core random factor for solving the subsequent coprime interleaving depth, preventing data pattern collisions in large-scale monitoring networks.

[0043] In step 3.2, the microcontroller performs finite-field differential encoding on each data segment, generating a set of adjoint polynomial coefficients. Differential encoding converts the absolute amplitude between adjacent samples into differential components, significantly reducing data entropy. The adjoint polynomial coefficient set establishes a complete coefficient table of the difference polynomial for each data segment, ensuring the differential information remains reversible within a finite field. Through this mechanism, even with drastic fluctuations in the field environment, the encoded difference vector maintains stable statistical characteristics, facilitating the capture of redundancy by the backend compression algorithm.

[0044] Step 3.3 establishes a bidirectional mapping between the time and Galois domains using coprime interleaving depth, rearranging the differencing data segments into an interleaving matrix. The coprime interleaving depth is derived from the irreducible polynomial index of each data segment and a fixed row threshold in the system parameter table, maintaining a greatest common factor of 1. The generation of the interleaving matrix spatially disperses the originally continuous data sequence. Any burst errors, after being mapped to the matrix, will spread simultaneously in both row and column dimensions, equivalent to increasing the temporal interleaving redundancy of the physical channel. In remote monitoring applications, wireless links are susceptible to multipath fading and transient shielding; the cross-domain diffusion capability provided by the coprime interleaving matrix significantly reduces the probability of overall frame distortion.

[0045] Then, step 3.4 is executed, calculating the Reid-Solomon redundancy check vectors column-by-column for the interleaving matrix, generating check vector sets, and appending them to the interleaving matrix to obtain the check-interleaved matrix. Column-vector level Reid-Solomon check leverages this error-correcting code's excellent performance in correcting burst errors, capable of correcting consecutive byte errors in one go. Appending the check vectors directly to new rows injects strong error-correcting capability into the entire matrix without disrupting the original column order. For remote monitoring systems requiring 24 / 7 operation, even if electromagnetic interference or weather conditions cause signal quality degradation on-site, the Reid-Solomon redundancy check vectors can still accurately recover the original differential vectors remotely.

[0046] After the verification is completed, proceed to step 3.5. The microcontroller re-concatenates the check interleaving matrix and the Reid-Solomon redundancy check vector row by row, performs binary cyclic redundancy compression, and finally outputs the error-corrected compressed data block to the transmission buffer. During the row reordering process, the original multidimensional structure of the interleaving matrix is ​​flattened into a one-dimensional bit stream, preparing for subsequent compression. Binary cyclic redundancy compression integrates the dual functions of cyclic redundancy check and sliding window entropy coding: cyclic redundancy check adds an overall check bit to the bit stream for end-to-end integrity verification at the terminal; sliding window entropy coding detects repetition patterns in real time based on the bit stream symbol distribution and replaces them with short codes, thereby compressing the payload length to half or even less of the original size. When outputting the error-corrected compressed data block, the microcontroller writes context information such as the uncompressed length, generator polynomial order, and zero-padding length into the header field to ensure that the remote control terminal can successfully restore the complete bit stream during the decoding stage. The transmit buffer and the wireless communication unit share dual-port storage. Once the buffer ready flag is set, the wireless communication unit will pull the error-corrected compressed data block and upload it along with the unique identification code through the secure channel.

[0047] In summary, by embedding a five-level processing chain—Galois domain operations, differential coding, coprime interleaving, Reid-Solomon error correction, and cyclic redundancy compression—into the microcontroller, the remote monitoring system completes noise reduction, redundancy reduction, and error-resistant encapsulation before the data leaves the field. This significantly reduces the burden on the wireless link and substantially improves data security and reliability. Upon receiving the error-corrected compressed data block, the remote control terminal performs decompression, deinterleaving, decoding, and inverse differential processing in reverse order, rapidly reconstructing high-fidelity time-series data and achieving a closed-loop process from real-time sensing to decision control.

[0048] Furthermore, in remote monitoring applications, field sensors often generate data at non-constant rates. Directly pushing these raw byte streams to the wireless link not only makes it difficult to guarantee real-time performance but also leads to difficulties in error localization due to inconsistent packet lengths. To address this, this invention includes step 3.1 on the microcontroller side. Through rigorous byte-level segmentation and an irreducible Galois field polynomial indexing mechanism, a unified and verifiable mathematical foundation is laid for subsequent differential coding, interleaving rearrangement, and Reid-Solomon check, fundamentally improving the robustness and traceability of the remote monitoring channel.

[0049] The microcontroller first reads the system parameter table and locks the length threshold for a single data segment. This threshold is set to a fixed value in bytes, and its selection takes into account the minimum frame length of the wireless communication unit, the sensor sampling interval, and the edge computing load. This ensures that the data uploaded in each frame has a stable payload size and that the on-chip operations after encoding are predictable within a clock cycle. If the total number of bytes in the data block to be processed is not divisible by the threshold, the microcontroller will pad the end of the data block with zero-value bytes until the divisibility condition is met. This ensures that all segment lengths are consistent, avoiding fragmentation at the link layer due to variable-length frames, thereby reducing latency jitter during retransmission in the remote monitoring system.

[0050] Next, the microcontroller sequentially extracts data blocks starting from the first byte according to a threshold, obtaining several data segments. Each segment is allocated a contiguous storage block in the internal buffer, recording its first and last addresses. This contiguous address mapping allows subsequent Galois field operations to directly utilize on-chip addressing logic without additional data movement, ensuring low power consumption for edge nodes in remote monitoring scenarios. Subsequently, the microcontroller calls the finite field operation library in the firmware, treating each data segment as a sequence of Galois field elements and mapping this sequence sequentially to the order coefficients of a Galois field polynomial. The highest-order coefficient corresponds to the first byte of the data segment, and the lowest-order coefficient corresponds to the last byte. This mapping method preserves the chronological order of the original time series, allowing the polynomial to retain both causal order and algebraic encapsulation within the finite field, facilitating the subsequent derivation of differential coding and coprime interleaving depth.

[0051] To generate a unique and cost-effective index for each data segment, the microcontroller uses the fast Euclidean algorithm to calculate the greatest common divisor (GCD) of the polynomial and all candidate polynomials of order no greater than half its own in the Galois field. If the GCD is a constant term, the polynomial is irreducible in the current finite field, indicating that it has no lower-order factors and can be used to construct high-strength differential linear coding modular polynomials. Conversely, if the detection result shows reducibility, the microcontroller incrementally corrects the lowest-order coefficients according to a preset increment and re-executes the detection until it is determined to be an irreducible polynomial. Through this "search-and-correct" strategy, irreducible modular polynomials can be generated for segmented data in real time and in batches without storing a large prime polynomial lookup table on-site, saving flash memory space and avoiding security risks caused by leaks of pre-generated tables.

[0052] Once irreducibility is confirmed, the microcontroller generates a unique sequence number based on the polynomial order and coefficient combination information, and writes this sequence number into the segment header identifier area of ​​the corresponding data segment as an irreducible polynomial index. This sequence number has a dual meaning in the entire transmission link: first, the remote control terminal can use it to directly reconstruct the finite field operation environment, perform inverse operations and error correction verification on the received data; second, the index itself participates in the calculation of coprime interleaving depth, ensuring the randomness of row and column mapping during cross-segment interleaving, thereby improving the propagation range of sudden bit errors. Therefore, step 3.1 not only completes the conventional neat byte segmentation, but also adds a rigorous algebraic fingerprint to the remote monitoring system through mathematical irreducibility, making each data segment a unique and verifiable operation unit in the entire network.

[0053] Step 3.1 establishes a bridge from physical data to algebraic entities for the remote monitoring system through a series of fine-grained operations, including thresholding segmentation, zero-value padding alignment, contiguous storage block mapping, Galois field polynomial construction, and irreducibility index generation. This not only ensures the consistency of uploaded data in terms of size, structure, and timing, but also provides high-quality initial conditions for subsequent algorithms such as differential coding, interleaving rearrangement, and error correction compression. This enables the system to maintain low latency, high accuracy, and verifiability even in long-term unattended environments, achieving truly reliable remote monitoring.

[0054] Furthermore, in the remote monitoring system, the microcontroller not only undertakes real-time acquisition and preliminary cleaning of sensor data, but also must perform entropy reduction and error resistance processing locally in the sense of information theory. This ensures that high-value time-series information can be delivered securely, reliably, and with low latency to the remote control terminal even in environments with unstable wireless links and limited bandwidth. To this end, in step 3.2 of this invention, a fine-grained algorithm based on Galois domain differential coding and adjoint polynomial construction is introduced, enabling each data segment to have an independent and invertible finite-field representation, and providing a highly discriminative and strongly diffusive mathematical structure for subsequent interleaving and error correction.

[0055] After step 3.1 completes the segmentation and generates an irreducible polynomial index for each data segment, the microcontroller immediately proceeds to step 3.2. First, the microcontroller sequentially loads each data segment and its corresponding irreducible polynomial index, and establishes a one-to-one temporary mapping table in its internal registers. This mapping table uses the starting address of the data segment as the key and the irreducible polynomial index as the value, ensuring that subsequent operations can retrieve the correct modular polynomial in constant time. Since remote monitoring sites often deploy various heterogeneous sensors, resulting in diverse data segment sources and varying frequencies, this mapping table structure avoids the addressing overhead caused by frequent context switching, providing robust support for the microcontroller to maintain real-time task scheduling in high-concurrency scenarios.

[0056] Next, the microcontroller uses the irreducible polynomial index as the modulo polynomial to perform Galois field subtraction on the current data segment byte by byte: the microcontroller directly writes the first byte of the data segment into the first element of the difference vector. Starting from the second byte, the microcontroller calculates the difference between the current byte and the previous byte using Galois field subtraction, and writes the result into the subsequent elements of the difference vector. The length of the difference vector is strictly equal to the length of the data segment, and all elements are confined to the corresponding Galois field. Essentially, this step performs a high-pass filter over a finite field to eliminate the DC component within the data segment, thereby reducing the statistical entropy of subsequent compression algorithms. When the remote monitoring system detects slowly changing environmental variables, the difference operation generates a large number of low-amplitude symbols, enabling the cyclic redundancy compression stage to express the same information with shorter codewords, greatly saving wireless channel resources.

[0057] After calculating the difference vector, the microcontroller uses the elements of the difference vector as coefficients to construct Galois field polynomials of the same order in sequence. The highest-order coefficient corresponds to the first element of the difference vector, and the lowest-order coefficient corresponds to the last element. These polynomials, together with the irreducible polynomial, form a pair of adjoint polynomials. The existence of the adjoint polynomial not only provides reversible encapsulation for each data segment but also amplifies the error propagation distance during recursive processing and coprime interleaving, thereby improving the detectability and repairability of remote decoding. In remote monitoring scenarios, link noise exhibits both bursty and random characteristics. By introducing the adjoint polynomial, even if a single-point error intrudes into the difference vector, it will propagate to a higher order after polynomial mapping, facilitating the subsequent error correction logic location.

[0058] If the highest-order coefficient of the adjoint polynomial is zero in the Galois field, the microcontroller processes it according to the normalization rules: the microcontroller searches for the first non-zero coefficient from the highest to the lowest order, and promotes this coefficient and its corresponding power to the highest order position; for the moved intermediate coefficients, the microcontroller inserts zero values ​​as placeholders in their original positions to ensure that the polynomial order remains unchanged. This normalization process solves the problem of leading zeros that may occur in the measured data, avoiding decoding failures caused by order mismatch during inverse operations by the remote control terminal. After normalization, the microcontroller generates a set of adjoint polynomial coefficients according to the order of the coefficients of each order of the adjoint polynomial, and writes them to the end-of-segment identifier area of ​​the data segment using a contiguous storage block. The fixed layout of the end-of-segment identifier area allows the wireless communication unit to directly transfer the encoded results in DMA mode without traversal or splicing, further reducing bus occupancy time.

[0059] Through the chained operations described above, step 3.2 not only achieves Galois domain differential encoding and adaptive normalization of the original data, but also inserts verifiable adjoint polynomial metadata at the segment level, constructing a dual association between data content and algebraic fingerprints. Upon receiving the error-corrected compressed data block, the remote control terminal can quickly reconstruct the finite field environment based on the irreducible polynomial index at the segment header and the adjoint polynomial coefficient set at the segment tail, realizing differential inverse operation and error location. Any tampering or mistransmission will be exposed as polynomial mismatch during the reconstruction process, ensuring the integrity and security of the remote monitoring link. Thus, step 3.2 completes a deep edge computing preprocessing on the microcontroller side, laying a solid algebraic foundation for subsequent coprime interleaving, Red check, and cyclic redundancy compression, ensuring that the remote monitoring system can maintain a low-latency, high-reliability, and high-security data closed loop even in complex electromagnetic environments, frequent scene switching, and long-term unattended operation.

[0060] Furthermore, in remote monitoring links, sudden bit errors often exhibit temporal clustering characteristics. If uploaded directly without being broken up, the entire data segment will be concentratedly corrupted within the same wireless frame, making it highly susceptible to unrecoverable errors during decoding. To address this, this invention implements interleaving and rearrangement in both the temporal and Galois domains on the microcontroller side through step 3.3. This ensures that the differential vector elements are evenly distributed across a two-dimensional space before transmission, significantly increasing the error propagation distance and thus substantially improving the remote error correction success rate. This step first counts the number of data segments in the current batch and the byte length of a single data segment; then, it determines the number of rows in the interleaving matrix based on a fixed row threshold in the system parameter table, directly using the number of data segments as the number of columns. This allows for a one-time allocation of contiguous row-priority storage blocks in internal memory, avoiding fragmentation caused by multiple dynamic allocations and improving memory utilization of the remote monitoring node at high sampling frequencies.

[0061] To assign independent and non-overlapping write paths to each data segment, the microcontroller sequentially scans the irreducible polynomial index and the first term coefficient of the corresponding adjoint polynomial coefficient set for each data segment. The algebraic sum of these two values ​​is modulo the length of a single data segment (in bytes), and then an integer value of one is added to obtain the candidate interleaving depth. This candidate value is strongly correlated with the data itself, effectively preventing the depth parameter from being predicted, thus suppressing batch data corruption caused by malicious replay attacks on the wireless link. If the greatest common factor of the candidate interleaving depth and the number of rows in the interleaving matrix is ​​not equal to one, the microcontroller sequentially increments the candidate interleaving depth until it is coprime to the number of rows in the interleaving matrix. This coprime relationship ensures the traversal of the write mapping along the row dimension, preventing the time pointer from falling into short-period loops during scanning and ensuring that each difference vector element covers different row addresses of the matrix. The final coprime interleaving depth is written to the system log. When the remote control terminal needs to perform inverse mapping, it can directly reference this value for Galois field reading mapping without recalculation.

[0062] The microcontroller then establishes a time pointer for time-domain mapping, sequentially traversing the differential vector elements of each data segment starting from zero. For the first write operation, the microcontroller multiplies the time pointer value by the coprime interleaving depth and takes the remainder with respect to the number of rows in the interleaving matrix; the result is used as the target row address. The target column address is obtained by taking the remainder of the time pointer with respect to the number of columns in the interleaving matrix. Through the double remainder calculation of this row and column address, the microcontroller writes the current differential vector element into the target cell of the interleaving matrix. After the write is completed, the time pointer is incremented by one, and the above mapping process is repeated until all differential vector elements have been written. Because the coprime interleaving depth ensures that the row address generation sequence and the row number are co-congruent, all elements exhibit a quasi-random distribution in the matrix space. This distribution can maximize the propagation of continuous errors to multiple column vectors and check rows when the wireless channel suffers sudden interference, allowing subsequent Reid-Solomon redundancy check to correct more bytes of errors with fewer redundant symbols. For remote monitoring systems that require stable operation 24 / 7, this interleaving method effectively reduces the probability of whole frame loss due to environmental noise, building shadows, or multipath fading, ensuring that the remote control terminal can still recover complete, continuous, and time-correct monitoring data under complex operating conditions.

[0063] Furthermore, the interleaving matrix adopts a row-first storage layout, consistent with the direct memory access channel of the wireless communication unit. This allows it to enter the subsequent Reid-Solomon column check process without additional transposition, reducing the number of memory copies performed by the microcontroller and lowering bus power consumption. The selection of the coprime interleaving depth is entirely completed locally by the microcontroller, without relying on external lookup tables. This saves flash memory space and prevents attackers from exploiting fixed parameters to expose the link structure. Through this series of designs, step 3.3 constructs a "data buffer firewall" for the remote monitoring system that balances real-time performance and security. Error distribution and spatial balancing are achieved at the source, providing ideal input for subsequent column-vector level Reid-Solomon check and row-vector level cyclic redundancy compression. This keeps the wireless transmission error rate within a correctable range without sacrificing the sampling frequency, fully meeting the stringent requirements of remote monitoring for high reliability, low latency, and long-term self-healing.

[0064] Furthermore, in practical applications of remote monitoring, the microcontroller not only needs to encapsulate the field sampled data through differential encoding, coprime interleaving, and Red-Solomon redundancy check before uploading, but also must perform a self-check on the reversibility of the entire interleaving write mapping locally. This is to prevent write misalignment caused by register flips, power interruptions, or external bus interference, which could then propagate unrecoverable structural errors along the link. To address this, after generating the interleaving matrix, this invention introduces a Galois domain read mapping verification process. The core idea is to construct an additional read depth, coprime to the number of rows in the interleaving matrix, for the coprime interleaving depth used in the write phase. This depth is then used to traverse the matrix in reverse, and finally, the read differential vector is compared with the first and last check codes of the original differential vector. If they are completely identical, it indicates that the write-read mapping is bidirectionally reversible.

[0065] First, in the interrupt callback after the interleaving matrix write is complete, the microcontroller reads the coprime interleaving depth just archived in the system log and directly performs an integer increment operation within the arithmetic unit, setting the result as the Galois field read depth. Since the coprime interleaving depth is already coprime with the number of rows in the interleaving matrix, simply adding one will not break its coprimity, and it will remain coprime with the number of rows for most actual row values. This design avoids the latency caused by additional search algorithms, gaining valuable processing time for the stringent "millisecond-level" packet cycle requirements in remote monitoring scenarios. Simultaneously, the read depth and write depth differ by only a minimum positive integer, ensuring that the cycle length of the read mapping sequence and the write mapping sequence remains equal to the number of matrix rows, preventing repetition or omission.

[0066] Subsequently, the microcontroller clears the dedicated read register and initializes the read pointer to zero. As the read pointer increments, the current row address is obtained by taking the remainder of the number of rows in the interleaving matrix, using the Galois field read depth as a multiplier; the column address is obtained by taking the remainder of the pointer with respect to the number of columns in the interleaving matrix. This modulo mapping is consistent with the row address generation formula in the write phase, only the multiplier factor differs. Because the read depth and the number of rows are coprime, the modulo sequence will cover all row addresses after traversing the row number minus one, thus achieving a complete, one-to-one corresponding read order. The microcontroller performs single-cycle direct addressing for each mapped address, loading the differential vector elements stored in that unit into the on-chip register, and reassembling them into a differential vector sequence according to the column order concatenation rules recorded during writing. During the read process, the microcontroller does not perform any decoding or verification, only ensuring that the time-domain order is precisely aligned with the original write order. This approach significantly reduces computational load and lowers the additional consumption of on-chip computing power and power consumption, aligning with the design goal of remote monitoring nodes emphasizing long-term low-power operation.

[0067] After all elements have been reassembled, the microcontroller immediately extracts the checksum fields reserved at the beginning and end of the differential vector and compares them bit by bit with the original checksum stored in the high-priority register before writing. If the two checksums are completely identical, it can be determined that the write-read mapping is without deviation at both the byte and timing levels. If any discrepancy is found, the microcontroller will write a checksum failure flag to the system log and trigger a soft interrupt, pausing the upload of the current batch of data. It will then attempt to upload again after re-performing the coprime depth calculation and interleaving write. Through this "local closed-loop self-checking" method, the system can detect and isolate potential misalignments before the data leaves the site, greatly reducing the probability of large blocks of data being discarded due to structural errors at the remote terminal.

[0068] It is worth emphasizing that in long-distance wireless transmission environments for remote monitoring links, any irreversible bit errors will be amplified into column alignment errors during deinterleaving and error correction, thus affecting the decoding success rate of the entire Reid-Solomon checksum. By dynamically generating the Galois domain read depth and verifying the bidirectional mapping, this invention enables the microcontroller to have the ability to quickly diagnose and self-heal at the edge. Even if the size of the interleaving matrix expands due to field requirements, as long as the row number threshold remains a fixed constant in the system parameter table, the aforementioned coprimeness and reversibility still hold, fully demonstrating the advantages of decoupling the algorithm from the hardware configuration. Therefore, the reversibility verification in step 3.3 is not only a self-consistent check of the correctness of the microcontroller's internal operations, but also an important technical tool for remote monitoring systems to ensure data integrity, improve link fault tolerance, and reduce the number of manual inspections, providing a solid reliability guarantee for unattended monitoring tasks in extreme environments.

[0069] In remote monitoring scenarios, wireless links are highly susceptible to consecutive byte-level errors due to factors such as multipath fading, weather disturbances, and electromagnetic interference. If strong error correction coding is not implemented on the microcontroller side, once data is damaged in the air, the remote control terminal cannot recover the original information using simple retransmission or parity checking methods. Step 3.4 is the core error correction module added inside the edge node in this invention. Its function is to further encapsulate the already coprime interleaved and shuffled differential vector into a Red-Solomon redundancy check structure with "multi-byte correction" capability, thereby significantly improving the self-recovery capability of the remote monitoring link.

[0070] The microcontroller first loads each column vector of the interleaving matrix sequentially, treating the j-th column vector as a vector in the Galois field GF(2). 8 The sequence of elements on ) is mapped to a message polynomial of length n. Where n is the number of rows in the interleaving matrix, d i，j The difference vector elements correspond to row index i and column index j, with x being a polynomial variable. By preserving the order of "mapping the first element to the highest-order coefficient," the message polynomial completely characterizes the temporal information of the column vector within a finite field. This ensures that the original column data can be reconstructed unambiguously once the remote end completes decoding, which is particularly important for remote monitoring that requires millisecond-level time synchronization.

[0071] Next, the microcontroller calls the Reid-Solomon coding library in the firmware, sets the number of redundancy check symbols to t bytes, and selects primitive α in the same Galois field to construct the generator polynomial. The order of the generator polynomial is t. Here, fixing α to a value from the system parameter table ensures that all edge nodes and remote terminals operate within the same finite domain, avoiding the potential for codeword incompatibility during cross-node collaboration. After setting the generator polynomial, the microcontroller processes the polynomial D for each message. j (x) The standard Reid-Solomon coding process of left shifting by t bits and modulo division by g(x) is uniformly executed to obtain the check polynomial R. j (x)=x t ·D j (x)modg(x).

[0072] The modular division operation here is essentially multiplying the message polynomial by x. t Then, take the remainder in the ideal spanned by the generating polynomial, and the remainder is... It just so happens to provide the ability to detect and correct the most at the same time Redundant information for burst errors. For clustered errors commonly found in remote monitoring wireless links, this multi-byte error correction capability is far superior to single-byte parity and CRC.

[0073] Subsequently, the microcontroller generates the encoded polynomial C. j(x)=x t D j (x)+R j (x), and put R j The coefficient sequence {r} of (x) k，j The redundancy check vector P is organized in descending order of order into a fixed-length t-type redundancy check vector. j The vector is directly appended to the end of the original j-th column vector, increasing the column vector length from n to n+t. This "column vector expansion" approach, rather than creating a new independent parity area, ensures that the interleaving matrix maintains row-major contiguous storage in its physical layout. Subsequent row reordering and cyclic redundancy compression can be streamed in DMA mode in one go, without additional copying, effectively reducing the microcontroller's bus usage and power consumption.

[0074] After all columns have been appended, the microcontroller reassembles the matrix in row-major order in its internal memory, resulting in a parity-checked interleaving matrix S with n+t rows and the same number of columns as the original interleaving matrix. This row-major reassembly ensures spatial locality of the matrix, allowing subsequent row-vector level cyclic redundancy compression to be scanned sequentially without encountering cache misses caused by skipping rows or columns. It is worth noting that because the preceding steps have ensured that the coprime interleaving depth and row number are coprime, the added t rows do not disrupt the congruent traversal of the write mapping; the remote terminal only needs to read n+t rows during the inverse operation to share the completely one-to-one corresponding interleaving mapping sequence.

[0075] By introducing the Reid-Solomon redundancy check vector, this invention upgrades the differential vector from "relying solely on CRC error detection" to a highly reliable codeword that is both error-correcting and error-detecting. Through column-vector level processing and row-first reassembly, the encoding computation is evenly distributed across each data segment, avoiding real-time dead zones caused by "exhausting computing power with large blocks of data at once." Ultimately, when the check interleaving matrix is ​​transmitted over the wireless link, even under continuous interference lasting up to t bytes, it can be completely restored at the remote control terminal, providing accurate and coherent time-series data for closed-loop control decisions. This mechanism fundamentally improves the survivability of remote monitoring systems under extreme channel conditions, reduces retransmissions, shortens fault detection response time, and provides all-weather, low-maintenance, and highly reliable data assurance for scenarios such as industrial sites and smart agriculture.

[0076] In the remote monitoring link, although the data already possesses a certain error correction capability after interleaving and Red-Solomon redundancy check, it still needs an additional layer of low-cost yet highly efficient integrity protection before leaving the microcontroller. Step 3.5 utilizes cyclic redundancy check to perform final encapsulation on the multi-stage preprocessed data, enabling it to achieve high-probability error detection and rapid location with minimal bit overhead when traversing noisy and highly uncertain wireless channels, thereby further shortening the overall response time of the remote monitoring system. Specifically, the microcontroller first sequentially reads each row vector s of the check interleaving matrix S. i ={s i，0 s i，1 , ..., s i，m-1 The sequences are then seamlessly concatenated according to the order of "rows from top to bottom, columns from left to right," constructing a one-dimensional sequence b = {b0, b1, ..., b...} of length L = (n + t) × m bytes. L-1}, b i×m+j =s i，j Through this linearization operation, the two-dimensional matrix is ​​transformed into a continuous address space, which facilitates direct storage into the transmission buffer of the wireless communication unit and maximizes the efficiency of on-chip DMA transfer. At the same time, row-first mapping preserves the uniform error propagation characteristics brought about by the preceding coprime interleaving, providing a more random input sequence for CRC check.

[0077] Next, the microcontroller reads the cyclic redundancy check from the system parameter table to generate the polynomial g. c (x)=x c +g c-1 x c-1 +…+g1x+g0, where c is the order of the polynomial, and all coefficients g…+g1x+g0… where c is the order of the polynomial, and ... k All values ​​are taken as binary values ​​{0, 1}. This generator polynomial remains consistent throughout the remote monitoring network, enabling remote control terminals to directly reproduce the same CRC environment upon receiving data without additional negotiation. Subsequently, the microcontroller treats the byte sequence b as a message polynomial composed of 8 little-endian elements. Shift left by c bits to get x c ·B(x). Divide the polynomial modulo g on GF(2). c The remainder can be obtained by (x). Where {z k} is a cyclic redundancy check vector of length c. Since division and XOR can be quickly performed in the combinational logic of logic shifters and ALUs, this operation can be completed within the microcontroller's clock cycle, without blocking the real-time sampling cycle of remote monitoring. Appending r(x) to the end of the message polynomial forms the encoded polynomial C(x) = x. cB(x) + r(x), whose corresponding bit stream is only c bits larger than the original message, mathematically establishes a relationship between C(x) and g. c The congruence relation of (x) allows the remote control terminal to immediately determine whether any bit flips have occurred during the transmission of the entire frame of data through a single modulo division. If the terminal detects that the remainder is not zero, it can immediately request a retransmission without having to enter the computationally expensive Reid-Solomon decoding process, thereby controlling the exception handling delay to the millisecond level. If the CRC verification passes, the index and coefficient combination information left at the segment header and tail can be called to perform inverse interleaving and differential inverse operation, so that error correction decoding can be performed on the premise that the integrity has been confirmed, ensuring that the back-end decision is based on highly reliable data.

[0078] It is worth emphasizing that most remote monitoring nodes are deployed in power, petrochemical, or agricultural environments, and the equipment is often constrained by power consumption budgets and communication costs. Step 3.5 achieves significant error detection capabilities with extremely low redundancy overhead, realizing a hierarchical reliability strategy of "detecting errors first, correcting errors, and then retransmitting." Together with the multi-layered fault-tolerant system formed by the previous steps, it reduces the repeated retransmission of large data packets in poor channels and avoids errors triggering erroneous actions at the execution layer, thus improving the overall security and economy of the system. In other words, by reasonably embedding cyclic redundancy check after the row sequence splicing of the interleaving matrix and before wireless transmission, this invention ensures that remote monitoring data, before arriving at the client, maintains extremely low on-chip resource consumption while laying a solid and reliable bit-level foundation for backend strategy judgment and on-site execution.

[0079] The encoded polynomial C(x) corresponds to a bit stream length of 8L+c bits. To reduce redundancy, the microcontroller calls the binary cyclic redundancy compression algorithm in the firmware: starting from the most significant bit, a sliding window scans the encoded bit stream. If a continuous repeating segment completely consistent with the generator polynomial feedback pattern is detected, a bit flag 1 followed by an unsigned exponent—high-order Lamb code—is used to indicate the number of repetitions of that segment; if the window content does not match the feedback pattern, a bit flag 0 is output and the code is passed through byte by byte as is. This process, while ensuring decoding reversibility, performs entropy compression on highly redundant cyclic blocks, thereby shortening the overall code length. After compression, the bit sequence e = {e0, e1, ..., e} is obtained. Q-1} where Q≤8L+c; the microcontroller reassembles e into a byte stream E using an eight-bit alignment method. If the last bit is less than eight bits, it fills the least significant bit side with zero bits and records the number of filling bits δ. Finally, the microcontroller writes four bytes of header information at the beginning of the transmit buffer, which includes the uncompressed bit length 8L+c, the generator polynomial order c, the number of filling bits δ, and the cyclic redundancy check value of the header information itself. Then, it continuously writes the compressed data byte stream E to form an error-corrected compressed data block and waits for the wireless communication unit to schedule its upload.

[0080] The following example illustrates a complete sampling-encoding-reporting-verification process in a remote monitoring scenario of a smart greenhouse. For demonstration purposes, all values ​​are selected using smaller dimensions that are easy to calculate manually; in actual deployment, the scale can be increased according to bandwidth and computing power requirements. The microcontroller used is an STM32F411 with a main frequency of 100MHz, 128KB of on-chip SRAM, and an on-chip finite field arithmetic library operating in the Galois domain GF(2). 8 ), using the primitive polynomial x 8 +x 4 +x 3 +x 2 +1 (hexadecimal representation 0x11D). The wireless communication unit is a LoRa-WAN Class A node with a maximum payload of 51 bytes. The system parameter table provides: Single data segment length threshold L seg = 8 bytes; fixed row threshold for interleaving matrix n = 8; Reid-Solomon redundancy symbol count t = 4; cyclic redundancy check generator polynomial order c = 16, generator polynomial; g c (x)=x 16 +x 12 +x 5 +1(CRC-CCITT).

[0081] The sensor combination (temperature, humidity, light, carbon dioxide) is denoised using a sliding window and marked with millisecond-level timestamps to generate a 16-byte data block to be processed: 60, 62, 65, 67, 68, 6A, 6D, 70, 5A, 5C, 5D, 5F, 62, 64, 66, 69. The data is in hexadecimal bytes, with temperature first and humidity second, arranged sequentially.

[0082] The data block length of 16 bytes is divisible by the threshold 8, so no zero padding is needed. The microcontroller sequentially truncates the data from the first byte, resulting in two segments: Each segment in GF(2) 8 In the expression, x is treated as a polynomial coefficient vector, with the highest order corresponding to the first byte. Construct f0(x) = x for segment 0. 7 +x 5 +x 4 +x 3 +x 2 +x+1, the fast Euclidean algorithm and the greatest common factor of all candidate polynomials of order ≤4 yield only the constant 1, therefore f0(x) is irreducible; the microcontroller generates sequence number 50. Segment 1 is processed in the same way to obtain the irreducible polynomial f1(x) and sequence number 51. The two sequence numbers are written into their respective segment header identifier areas.

[0083] Difference vector of segment 0

[0084] The same processing of segment 1 yields {5A, 02, 01, 02, 03, 02, 02, 03};

[0085] The difference vectors are each mapped to polynomials of the same order, h0(x) and h1(x). The highest-order coefficient d0 of segment 0 is 60 ≠ 0, so normalization is unnecessary; the same applies to segment 1. The microcontroller assigns {d... k Write the sequence to the end-of-segment identifier area to complete the archiving of the adjoint polynomial coefficient set.

[0086] The number of data segments in this batch is m=2, and the microcontroller directly retrieves the column number m. The scan segment header sequence number and the first item of the accompanying coefficient group are as follows: Select the first term 7; gcd(7,8)=1, the depth and the number of rows are coprime. Record the coprime interleaving depth d=7. The time pointer τ increments from 0, and for each difference element, execute row=(τ·d)mod8, column=τmod2, until 16 elements fill the 8×2 interleaving matrix A.

[0087] Construct a message polynomial for the column vector {a0, ..., a7} Let the number of redundant symbols be t = 4, and the primitive element α be a field generator. The generator polynomial is g(x) = (x - α) / (x - α). 0 (x-α) 1 (x-α) 2 (x-α) 3 ); Calculate R0(x) = x 4 D0(x)modg(x); yields the coefficient vector {A4, 7B, C5, 1E}. Column 1 is processed similarly to obtain {B1, 6A, 29, D4}. These vectors are appended to form an extended column, increasing the number of rows in the interleaving matrix to n+t=12, thus forming the check interleaving matrix S.

[0088] The microcontroller linearizes S in row-major order, generating a sequence of L = (8+4)×2 = 24 bytes: 60, 5A, 02, 02, 03, 01, 02, 03, 5A, 02, 01, 02, 03, 02, 02, 03, A4, B1, 7B, 6A, C5, 29, 1E, D4; message polynomial. Shift left by 16 bits and then use g c The remainder r(x) obtained by dividing by x is x. 16 B(x)modg c (x)=B4C3 16 =x 15 +x 13 +x 12 +x 10 +x 9 +x 1 +x 0 The vector {B4, C3} is appended to the end of the sequence to generate the final encoded polynomial C(x) = x. 16B(x)+r(x); The encoded bitstream length is 24×8+16=208 bits, which is still within the LoRa single packet carrying range.

[0089] The wireless communication unit transmits 26 bytes (24 bytes payload + 2 bytes CRC) at once via LoRa-WAN. The remote control terminal reproduces the same CRC polynomial and performs a modulo division on the received 208-bit bitstream. If the remainder is 0, the entire frame is confirmed to be complete. Then, it performs an inverse mapping based on a coprime interleaving depth of 7, extracts the column vector, and performs Reed-Solomon decoding using the same g(x). Any consecutive bit errors not exceeding 4 bytes are automatically corrected. After decoding, differential inverse operation restores the original temperature and humidity sequence, which is used for policy determination.

[0090] A single acquisition-editing-transmission process takes approximately 3ms on the microcontroller side, accounting for 0.3% of the MCU's CPU time. The actual packet length is increased by 62% compared to the original 16 bytes, but this is achieved through dual-layer error correction and full-frame error detection. The upload success rate is increased from 88% to 99.7% in a measured humid steel structure greenhouse environment, fully demonstrating the high reliability, low resource consumption, and rapid implementation of the present invention in remote monitoring.

[0091] like Figure 2 As shown in the diagram, the schematic diagram of differential linear encoding and interleaving matrix rearrangement details the core processing flow of the data block to be processed. First, the microcontroller divides the data block to be processed into equal-length segments according to the fixed length threshold set in the system parameter table, forming several equal-length data segments such as D1, D2, D3, and D4. Each data segment is allocated a contiguous storage block in the internal buffer, and the corresponding start and end address information is recorded. In the finite-field differential encoding stage, the microcontroller sequentially loads each data segment and its corresponding irreducible polynomial index, establishing a one-to-one temporary mapping table in the internal register. Using the irreducible polynomial index as the modulo polynomial, the microcontroller performs Galois field subtraction on the current data segment in byte order. Specifically, the first byte D1 of the data segment is directly written to the first element of the difference vector. From the second byte onwards, the microcontroller calculates the difference between the current byte and the previous byte using Galois field subtraction, i.e., D2-D1, D3-D2, D4-D3, and writes the calculation results sequentially to subsequent elements of the difference vector. The difference vector length is equal to the data segment length, and all elements are confined to the corresponding Galois field. During the interleaving matrix rearrangement process, the microcontroller determines the number of rows in the interleaving matrix based on a fixed row threshold set in the system parameter table, directly using the number of data segments as the number of columns in the interleaving matrix. By scanning the irreducible polynomial index and the first term coefficient of the corresponding adjoint polynomial coefficient set of each data segment, the candidate interleaving depth is calculated, ensuring that this depth is coprime to the number of rows in the interleaving matrix, ultimately forming a coprime interleaving depth. Time-domain mapping is performed using a time pointer, rearranging the difference vector elements to their corresponding positions in the interleaving matrix according to specific mapping rules, forming an interleaving matrix structure with error correction capabilities.

[0092] like Figure 3 As shown in the diagram, the Reid-Solomon Redundancy Check (RCC) vector generation effect illustrates the construction process of the check interleaving matrix and its relationship with the adjoint polynomial coefficient set. The RCC interleaving matrix consists of the original data part and the check code part. The original data part contains matrix elements M11, M12, M13, M14, etc., after interleaving and rearranging. These elements are arranged in a row-column structure to form a complete data matrix. During the RCC vector generation process, the microcontroller calculates the Reid-Solomon RCC vector column by column on the interleaving matrix. Specifically, it performs specific algebraic operations on the matrix elements in each column to generate the corresponding check codes P1, P2, P3, etc. These check codes have strong error correction capabilities and can detect and correct various error types that may occur during transmission. The generation of the RCC vector follows the mathematical principles of Reid-Solomon coding, generating redundant information in a finite field through polynomial operations. The adjoint polynomial coefficient set plays a key role in the entire process. Coefficient set 1, coefficient set 2, coefficient set 3, and coefficient set 4 correspond to the adjoint polynomial coefficient information of different data segments. These coefficient sets not only participate in the differential coding process but also provide necessary parameter support for the generation of the parity check vector. The microcontroller generates the corresponding coefficient sets according to the order of the coefficients of each order of the adjoint polynomial and writes them to the end-of-segment identifier area of ​​the data segment using contiguous storage blocks to ensure data integrity. Finally, the microcontroller re-linearly concatenates the parity check interleaving matrix and the Red-Solomon redundancy check vector row-wise and performs binary cyclic redundancy compression. This process not only achieves effective data compression but also enhances the reliability of data transmission, ensuring that while maintaining real-time performance, it maximizes the error propagation distance and minimizes redundancy, forming a compressed data block with strong error correction capabilities.

[0093] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of the present invention. Therefore, the scope of the present invention is defined only by the appended claims.

Claims

1. A remote monitoring system based on a single-chip microcomputer, characterized by, The system comprises a single-chip microcomputer, a sensor acquisition unit, a wireless communication unit and an execution mechanism; the single-chip microcomputer, the sensor acquisition unit, the wireless communication unit and the execution mechanism are sequentially powered on when the system is initialized; after the single-chip microcomputer completes hardware self-checking, the single-chip microcomputer sends a handshake instruction to the wireless communication unit to establish a secure channel with a remote control terminal; after the handshake is completed, the single-chip microcomputer writes a unique identity code and enters a standby state; the single-chip microcomputer polls the sensor acquisition unit at a preset sampling period to obtain an original data frame; sliding window denoising and timestamp marking are performed on the original data frame to generate a to-be-processed data block and temporarily store the to-be-processed data block; the single-chip microcomputer performs recursive processing on the to-be-processed data block based on differential linear coding and cyclic redundancy compression to maximize the error code diffusion distance and minimize the redundancy while maintaining real-time, and outputs an error correction compressed data block; the to-be-processed data block is divided into equal-length data segments; the single-chip microcomputer generates an irreducible polynomial index for each data segment on a Galois field; finite field differential coding is performed on each data segment to generate a set of accompanying polynomial coefficient arrays; a bi-directional mapping between the time domain and the Galois field is established by using a coprime interleaving depth to rearrange the differential data segments into an interleaving matrix; the Reed-Solomon redundancy check vector is calculated for the interleaving matrix by column to generate a check vector group and append the check vector group to the interleaving matrix to obtain a check interleaving matrix; the single-chip microcomputer re-linearly splices the check interleaving matrix and the Reed-Solomon redundancy check vector by row to perform binary cyclic redundancy compression and output the error correction compressed data block to a sending buffer area; the wireless communication unit reads the error correction compressed data block and uploads the error correction compressed data block to the remote control terminal through the secure channel; the remote control terminal analyzes the error correction compressed data block, generates a control instruction according to a threshold strategy and returns the control instruction; after receiving the control instruction, the single-chip microcomputer drives the execution mechanism to act and records an execution state log.

2. A control method for implementing the single-chip microcomputer-based remote monitoring system according to claim 1, characterized by, The method comprises: Step 1: sequentially power on the single-chip microcomputer, the sensor acquisition unit, the wireless communication unit and the execution mechanism; after the single-chip microcomputer completes hardware self-checking, the single-chip microcomputer sends a handshake instruction to the wireless communication unit to establish a secure channel with a remote control terminal; after the handshake is completed, the single-chip microcomputer writes a unique identity code and enters a standby state; Step 2: the single-chip microcomputer polls the sensor acquisition unit at a preset sampling period to obtain an original data frame; sliding window denoising and timestamp marking are performed on the original data frame to generate a to-be-processed data block and temporarily store the to-be-processed data block; Step 3: the single-chip microcomputer performs recursive processing on the to-be-processed data block based on differential linear coding and cyclic redundancy compression to maximize the error code diffusion distance and minimize the redundancy while maintaining real-time, and outputs an error correction compressed data block; Step 4: the wireless communication unit reads the error correction compressed data block and uploads the error correction compressed data block to the remote control terminal through the secure channel; the remote control terminal analyzes the error correction compressed data block, generates a control instruction according to a threshold strategy and returns the control instruction; after receiving the control instruction, the single-chip microcomputer drives the execution mechanism to act and records an execution state log.

3. The control method of the single-chip microcomputer-based remote monitoring system according to claim 2, characterized by, The method further comprises: Step 5: when the number of execution failures recorded in the execution state log reaches a set value, the single-chip microcomputer automatically rolls back to Step 1 for re-handshake.

4. The control method of the microcontroller-based remote monitoring system according to claim 1, wherein, Step 3.1 specifically comprises: the single-chip microcomputer reads the system parameter table to obtain a single data segment length threshold, which is set as a fixed value in byte units; if the total number of bytes of the to-be-processed data block cannot be evenly divided by the threshold, the single-chip microcomputer fills zero-value bytes at the end of the to-be-processed data block until the condition of even division is met; the single-chip microcomputer sequentially intercepts the to-be-processed data block from the first byte according to the threshold to obtain a plurality of data segments in sequence, and allocates a continuous storage block for each data segment in the internal buffer area, and records the start address and the end address; the single-chip microcomputer calls the finite field operation library in the firmware, regards the single data segment as a Galois field element sequence, and sequentially maps the sequence as the coefficients of a Galois field polynomial, with the highest-order coefficient corresponding to the first byte of the data segment and the lowest-order coefficient corresponding to the last byte of the data segment; the single-chip microcomputer calls the fast Euclidean algorithm to calculate the greatest common divisor of the polynomial and all candidate polynomials with an order not greater than half of the order of the polynomial in the Galois field; if the greatest common divisor is a constant term, the polynomial is determined as an irreducible polynomial; if the detection result shows that the polynomial is reducible, the single-chip microcomputer increments the lowest-order coefficient by a preset increment and re-executes the detection until the polynomial is determined as an irreducible polynomial; the single-chip microcomputer generates a unique serial number according to the order and coefficient combination information of the polynomial; and the serial number is written into the segment header identification area of the corresponding data segment as an index of the irreducible polynomial.

5. The control method of the single-chip microcomputer-based remote monitoring system according to claim 4, characterized by, Step 3.2 specifically comprises: the single-chip microcomputer sequentially calls each data segment and its corresponding irreducible polynomial index, and establishes a one-to-one temporary mapping table in the internal register; the single-chip microcomputer performs Galois field subtraction on the current data segment in byte order using the irreducible polynomial index as the modulus polynomial; the single-chip microcomputer directly writes the first byte of the data segment into the first element of the difference vector; from the second byte, the single-chip microcomputer calculates the difference between the current byte and the previous byte by Galois field subtraction, and writes the calculation result into the subsequent elements of the difference vector in sequence; the length of the difference vector is equal to the length of the data segment, and all elements are limited within the corresponding Galois field range; the single-chip microcomputer constructs a Galois field polynomial of the same order in sequence with the elements of the difference vector as the coefficients, with the highest-order coefficient corresponding to the first element of the difference vector and the lowest-order coefficient corresponding to the last element of the difference vector, which together with the irreducible polynomial form a pair of associated polynomials; if the highest-order coefficient of the associated polynomial is zero in the Galois field, the single-chip microcomputer performs normalization processing according to the following rules: the single-chip microcomputer searches for the first non-zero coefficient from high order to low order, and moves the coefficient and its corresponding power to the highest-order position; for the intermediate coefficients that are moved, the single-chip microcomputer inserts zero-value placeholders in the original positions to ensure that the order of the polynomial does not change; the single-chip microcomputer generates a set of associated polynomial coefficient groups according to the order of the coefficients of the associated polynomial, and writes the groups into the data segment tail identification area using continuous storage blocks.

6. The control method of the microcontroller-based remote monitoring system according to claim 5, wherein, Step 3.3 specifically comprises: counting the number of current batch data segments and the byte length of a single data segment; determining the number of rows of the interleaving matrix according to the fixed row threshold set in the system parameter table; taking the number of data segments as the number of columns of the interleaving matrix directly, and allocating a continuous row priority storage block for the interleaving matrix in the internal memory; the single-chip microcomputer sequentially scans the irreducible polynomial index of each data segment and the first term coefficient of the corresponding companion polynomial coefficient array, takes the algebraic sum of the two modulo the byte length of a single data segment, and then adds an integer value of one to obtain a candidate interleaving depth; if the greatest common divisor of the candidate interleaving depth and the number of rows of the interleaving matrix is not equal to one, the single-chip microcomputer sequentially increments the candidate interleaving depth until the candidate interleaving depth is co-prime with the number of rows of the interleaving matrix; the final interleaving depth obtained is recorded as the co-prime interleaving depth, and is archived in the system log; the single-chip microcomputer establishes a time pointer for time domain mapping, and sequentially traverses the differential vector elements of each data segment starting from a zero value; for the first write operation, the single-chip microcomputer multiplies the time pointer value by the co-prime interleaving depth, and takes the remainder of the number of rows of the interleaving matrix to obtain a target row address; the target column address is obtained by taking the remainder of the number of columns of the interleaving matrix after the time pointer; the single-chip microcomputer writes the current differential vector element to the cell corresponding to the target row address and the target column address of the interleaving matrix according to the target row address and the target column address; after the writing is completed, the time pointer is incremented by one, and the cycle is continued until all differential vector elements are written and completed, and the interleaving matrix is obtained.

7. The control method of the microcontroller-based remote monitoring system according to claim 6, wherein, To verify the reversibility of the time domain write mapping, the single-chip microcomputer calculates the read depth of the Galois field for Galois field mapping, and the read depth is set to the co-prime interleaving depth plus an integer value of one; since the co-prime interleaving depth and the number of rows of the interleaving matrix are co-prime, the read depth of the Galois field and the number of rows of the interleaving matrix also remain co-prime; the single-chip microcomputer applies the same multiplication and remainder mapping rule of the Galois field read depth to the row address of the interleaving matrix in the form of increasing the read pointer, reads out the previously written elements row by row and reorganizes them into a differential vector sequence in the register to obtain the interleaving matrix; it is confirmed that the two-way mapping is correct without any error by verifying that the head and tail check codes of the differential vector are consistent with the original differential vector.

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