Power saving method of high-definition multimedia interface and high-definition multimedia interface receiving device

Abstract

The invention provides a power saving method of a high-definition multimedia interface and a high-definition multimedia interface receiving device. The receiving device is provided with at least one HDMI port. The receiving device is used for receiving a data frame through a fixed rate link (FRL). The method comprises the following steps: when an effective pixel is detected, turning off a power supply of an HDMI port in a power-off interval; and after the power-off interval is completed, turning on a power supply of the HDMI port in a power-on interval. The power-on interval comprises at least one messy code reset interval (TSR) and a high bandwidth digital content protection (HDCP) interval, and the high bandwidth digital content protection (HDCP) interval is arranged in the power-on interval.

Description

TECHNICAL FIELD

[0001] The present application relates to High Definition Multimedia Interface (HDMI), and in particular to a power saving method for High Definition Multimedia Interface. BACKGROUND

[0002] High Definition Multimedia Interface (HDMI) is an audio or video connector interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI source device (such as a display controller or a personal computer) to an HDMI sink device (such as a computer monitor, a digital television or a digital audio device). The HDMI sink device can include multiple HDMI ports to receive video content from different HDMI source devices. One of the HDMI ports in the HDMI sink device can be selected to provide video content at any given time, and thus, if the displayed video content is intended to be changed, the HDMI sink device will switch to another HDMI port.

[0003] In the prior art, when switching between HDMI ports, the user needs to wait for several seconds to display the new screen, resulting in a poor user experience. In the prior art, in order to switch HDMI ports without waiting, the power supply of each HDMI port needs to be kept on, thereby increasing power consumption. SUMMARY

[0004] One embodiment of the present application discloses a power saving method for switching High Definition Multimedia Interface (HDMI) ports on a sink device. The sink device has at least one HDMI port. The sink device is configured to receive data frames in a fixed rate link (FRL) mode through a fixed rate link (FRL). The method includes turning off the power supply of the HDMI port for a power-off interval when a valid pixel in the data frame is detected in the fixed rate link mode, and turning on the power supply of the HDMI port for a power-on interval of the data frame after the power-off interval is completed. The power-on interval of the data frame in the fixed rate link mode includes at least one random code reset interval (TSR) and high bandwidth digital content protection (HDCP) encryption enable information.

[0005] According to another embodiment of the present application, a high-definition multimedia interface (HDMI) receiving device includes at least one HDMI port and a controller. The controller is coupled to the at least one HDMI port and configured to turn off power to the HDMI port for a power-off interval upon detecting a valid pixel and to turn on power to the HDMI port for a power-on interval after the power-off interval is completed. The power-on interval includes at least one time stamp reset interval (TSR) and HDCP enable information.

[0006] The present application turns on power only during HDCP synchronization and data descrambling, and turns off power most of the time during the active region of a data frame, thereby reducing power consumption.

[0007] These and other objects of the present application will no doubt become obvious to those skilled in the art after a reading of the following detailed description of the preferred embodiments that are shown in a variety of drawings both schematic and structural. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram of a high-definition multimedia interface (HDMI) receiving device according to an embodiment of the present application is shown.

[0009] Figure 2 A connection diagram of the HDMI receiving device and a source device in a FRL 4 channel mode in Figure 1

[0010] Figure 3 A diagram of a superblock in a time stamp reset interval (TSR) is shown.

[0011] Figure 4 A diagram of a superblock in Figure 3

[0012] Figure 5 A flow diagram of high-band digital content protection (HDCP) encryption is shown.

[0013] Figure 6 A flow diagram of a power saving method for switching an HDMI port on the HDMI receiving device in Figure 1

[0014] Figure 7 A diagram of a history data frame and a current data frame of the HDMI receiving device in Figure 1

[0015] Figure 8 A diagram of a current data frame in Figure 7

[0016] Figure 9 A diagram of a high-definition multimedia interface (HDMI) receiving device according to another embodiment of the present application is shown.​​​​​Figure 7 a schematic diagram of a current frame of data in

[0017] Figure 10 shows a schematic diagram of a current frame of data in Figure 7

[0018] Figure 11 shows a schematic diagram of a current frame of data in Figure 7 DETAILED DESCRIPTION

[0019] Figure 1 shows a block diagram of a high-definition multimedia interface (HDMI) sink device 100 according to an embodiment of the present application. The HDMI sink device 100 can include an HDMI interface 110, a controller 120, and a display device 130. The HDMI interface 110 can include HDMI ports 111-114 connected to HDMI source devices 201-204. The HDMI source devices 201-204 can provide different video contents. For example, the HDMI source device 201 can be a game console, the HDMI source device 202 can be a set-top box, the HDMI source device 203 can be a personal computer, and the HDMI source device 204 can be unused. The HDMI ports 111-113 can receive video contents from the HDMI source devices 201-203, respectively.

[0020] The HDMI ports 111-114 can receive power to operate, and the power of each of the HDMI ports 111-114 can be turned off if not in use to save power consumption. The controller 120 can be connected to the HDMI ports 111-114 and the display device 130, and the power of the HDMI ports 111-114 can be controlled when switching different HDMI source devices for display. For example, if the HDMI port 111 is selected, the controller 120 keeps the power of the HDMI port 111 on and turns off the power of the HDMI ports 112-114 when not in use to keep the HDMI port 111 operating to decode and pass data frames from the HDMI source device 201 to the display device 130 while reducing power waste of the HDMI ports 112-114. The display device 130 can be a liquid crystal display, a light-emitting diode (LED) display, or other electronic display for displaying video according to the decoded data frames.

[0021] ​​The HDMI sink device 100 can receive data frames in a fixed rate link (FRL) mode through a fixed rate link (FRL). FRL is a signal technology used to replace the traditional transition minimized differential signaling (TMDS) in HDMI. FRL uses three channels or four channels to provide a maximum bandwidth of 48 Gbps, while TMDS uses three channels to provide a maximum bandwidth of 18 Gbps. Data frames are transmitted between the HDMI sink device 100 and the HDMI source devices 201-204 through the FRL 3-channel mode or the FRL 4-channel mode.

[0022] Figure 2 A connection diagram between the HDMI sink device 100 and the HDMI source device 201 in the FRL 4-channel mode is shown, but the present application is not limited thereto. In the FRL 4-channel mode, the HDMI source device 201 transmits data frames to the HDMI sink device 100 using channels 0-3 at a fixed data rate.

[0023] The HDMI source device 201 receives video, audio, and control signals. The HDMI source device 201 can include an HDMI port 202 as a transmitter for transmitting video, audio, and control signals through channels 0-3. The HDMI port 111 in the HDMI sink device 100 can be a receiver configured to receive video, audio, and control signals from the HDMI port 202. If the HDMI port 111 is selected for display, the controller 120 can continuously turn on the power of the HDMI port 111. If the HDMI port 111 is not selected for display, the controller 120 can turn on the power of the HDMI port for a power-on interval to obtain High-bandwidth Digital Content Protection (HDCP) information, and then turn off the power of the HDMI port 111 for a power-off interval to reduce power waste. Details of the HDCP information, the power-on interval, and the power-off interval will be discussed in subsequent paragraphs.

[0024] Video data, audio data, and / or control data can be encapsulated in data frames transmitted through channels 0-3. Each data frame contains a plurality of super blocks. Figure 3A diagram showing 33 super blocks (super block 0 to super block 32) in a scramble reset interval TSR is shown. Each super block starts with a start character, followed by 4 blocks of characters. The start character can be a scramble reset (SR) character or a start super block (SSB), and can be transmitted simultaneously on channel 0 to channel 3 for character alignment. In each scramble reset interval TSR, the SR character appears in super block 0, and the SSB character appears in super block 1 to super block 32. That is, the SR character appears periodically once every 33 super blocks. In super block 0, the SR character is preceded by 4 blocks of characters, and the SR character is transmitted simultaneously on channel 0 to channel 3 at the start of super block 0. In each of super block 1 to super block 32, the SSB character is preceded by 4 blocks of characters, and the SSB character is transmitted simultaneously on channel 0 to channel 3 at the start of each of super block 1 to super block 32.

[0025] Figure 4 A diagram showing super blocks in a Figure 3 A diagram showing super blocks in a

[0026] Figure 5 A diagram showing a HDCP encryption process is shown. The HDMI source device 201 can perform HDCP encryption on data frames to provide digital protection, and transmit the HDCP encrypted data frames to the HDMI sink device 100. After the HDMI sink device 100 receives the HDCP encrypted data frames, the HDCP encrypted data frames are decrypted for subsequent use.

[0027] At the HDMI source device 201, the HDCP encrypted data frame is generated using the Advanced Encryption Standard counter mode (AES-CTR) according to the frame count and the data count. The frame count is a 38-bit number indicating the number of frames processed, and the data count is a 26-bit number indicating the number of 5-pixel units processed. For example, the initial value of the frame count is 0, and it becomes 1 when the first frame is encrypted. The data count is initially 0 at the beginning of a frame, and it becomes 1 when the first group of pixels is encrypted. A group of pixels can contain 5 pixels. The data count can be reset at an opportunity window time slot. The riv is an initial vector. The combination of the initial vector, the frame count, and the data count can be a 128-bit input P. K denotes a key that performs the AES-CTR. After performing the AES-CTR, a key stream is generated, which can be used as a cipher code to encrypt the data frame. Thus, the cipher code is generated according to the frame count and the data count.

[0028] To implement the HDCP decryption, the frame count and the data count of the data frame need to be synchronized at the HDMI sink device 100 to generate the cipher code. Even if the HDMI port is not selected, the power of the HDMI port is turned on for a short time to obtain the HDCP information so as to synchronize the frame count and the data count for the HDCP decryption. The information of the frame count and the data count can be generated according to the HDCP information, which is obtained in the HDCP interval of the data frame, as shown in Figures 7 to 11 The details of obtaining the HDCP information will be explained in the subsequent paragraphs.

[0029] Figure 6 A flowchart of the power saving method 6 of switching the HDMI port on the HDMI sink device 1 is shown. The power saving method 6 includes steps S601 to S606. Any reasonable variation or adjustment of the steps is within the scope of the present application. The steps S601 to S606 are explained as follows:

[0030] Step S601: turning on the power of the HDMI port;

[0031] Step S602: detecting the scrambled reset character to descramble the current data frame;

[0032] Step S603: obtaining the HDCP information;

[0033] Step S604: detecting the first valid pixel;

[0034] Step S605: turning off the power of the HDMI port for the power-off interval.

[0035] The power saving method 6 refers to the HDMI sink device 100 and Figure 7The data frame interpretation of the HDMI port 111 as the target HDMI port is shown in FIG. 6. Figure 7 The schematic diagram of the previous data frame F1 and the current data frame F2 received by the HDMI port 111 according to an embodiment of the present application is shown in FIG. 6. The HDMI port 111 is not selected for display. In Figure 7 In some embodiments, the pixels in the data frame can be compressed or not compressed. In some embodiments, the pixels in the data frame can be compressed according to the display stream compression (DSC) standard. DSC is an image compression algorithm used to increase the frame rate. However, since the pixels in the data frame are encapsulated in data packets, if the data packets are not processed, it is not possible to know how many pixels have been received by the HDMI port 111. Therefore, the time to turn on the power can be estimated by estimating the number of pixels in the FRL field according to the number of pixels in the TMDS field after the power of the HDMI port 111 is turned off.

[0036] In step S601, the controller 120 turns on the power of the HDMI port 111 for the power-on interval Ton2. The power-on interval Ton2 includes at least the scrambled reset interval TSR and the HDCP interval. The details of the scrambled reset interval TSR and the HDCP interval will be explained in the subsequent paragraphs.

[0037] In step S602, during the scrambled reset interval TSR, the SR characters are detected to descramble the current data frame F2. The scrambled reset interval TSR is in the power-on interval Tonp of the previous data frame F1.

[0038] In step S603, after the current data frame F2 is descrambled, the HDMI receiving device 100 searches the descrambled current data frame F2 for the Vsync active edge Vsync2 to identify the start point of the current data frame F2. The Vsync signal is the vertical synchronization signal of the data frame, and the Vsync active edge is the start edge of the Vsync signal. The HDMI receiving device 100 acquires the HDCP information HDCP2 in the HDCP interval. The HDCP interval is between 512 to 528 pixels after the Vsync active edge. The Vsync is the vertical synchronization signal. As shown in FIG. 6, the HDMI port 111 receives the previous data frame F1 and the current data frame F2. The HDMI port 111 is not selected for display. In Figure 7As shown, the HDCP interval HDCP2 is between 512 and 528 pixels after the Vsync active edge Vsync2, i.e., 16 pixels in length. The HDCP information HDCP2 includes information of frame count and data count. The HDCP information HDCP2 can be used to decide whether to decode the current data frame F2 if the HDMI sink device 100 switches from another HDMI port (e.g., HDMI port 112) to the HDMI port 111 for display. If the HDCP information HDCP2 indicates that the current data frame F2 is HDCP encrypted, the HDMI sink device 100 can increase the frame count by 1. If the HDCP information HDCP2 indicates that the current data frame F2 is not HDCP encrypted, the HDMI sink device 100 can keep the frame count.

[0039] In step S604, the HDMI sink device 100 decodes the current data frame F2 using the HDCP information HDCP2 and detects the first active pixel P1 from the decoded current data frame F2. The pixel P1 is the first active pixel of the active area.

[0040] In step S605, the controller 120 turns off the power of the HDMI port 111 for the power-off interval Toff2 when the first active pixel P1 in the current data frame F2 is detected in step S604. The pixel P1 is the first active pixel of the active area. The power of the HDMI port 111 is turned off until almost the time when the SR character and the HDCP information HDCP2 are detected, thereby saving power. The power-off interval Toff2 can be about 96% of the total time of the data frame.

[0041] The SR character is first detected to locate the other SSBs and to descramble the current data frame F2 so as to obtain the HDCP information from the descrambled current data frame F2. The descramble reset interval TSR is the duration required to find the SR character. The descramble reset interval TSR can be calculated according to the character rate, the FRL rate and the frame rate. The descramble reset interval TSR can be expressed in lines by equation Eq (1):

[0042] TSR = ceil(superblock number * character number per superblock per channel * frame rate * total vertical line number / character rate) Eq (1);

[0043] where ceil() is the ceiling function.

[0044] For example, if the number of super blocks is 33, the number of characters per super block per lane is (510 characters of 1 character block * 4 character blocks + 4 SSB) / 4 lanes = (510 + 1), the frame rate is 60 Hz, the total number of vertical lines in a data frame is 2048, the character rate is FRL rate / 18, and the FRL rate is 6*109, then the random code reset interval TSR is 7 lines (= ceil(33*511*60*2048*18) / (6*109)), indicating that 7 lines are needed to find the SR character SR.

[0045] Figure 8 A schematic diagram of a current data frame F2 in a display device 200 according to an embodiment of the present application is shown. Figure 7 A schematic diagram of a current data frame F2 in a display device 200 according to an embodiment of the present application is shown.

[0046] Figure 9 A schematic diagram of a current data frame F2 in a display device 200 according to another embodiment of the present application is shown. Figure 7 A schematic diagram of a current data frame F2 in a display device 200 according to another embodiment of the present application is shown.

[0047] Figure 10 A schematic diagram of a current data frame F2 in a display device 200 according to another embodiment of the present application is shown. Figure 7Schematic diagram of the current data frame F2 in FIG. In this embodiment, the power-off interval Toff2 is obtained by subtracting the garbled reset interval TSR, the clock stabilization interval Tclk, and the margin interval Tmg from the interval Tact of the vertical active line in the display data frame. The margin interval Tmg corresponds to the maximum error (=492 three bytes) between the amount of data transmitted by the FRL three-byte and the amount of data transmitted by the TMDS three-byte, where each three-byte represents the data of one pixel. Specifically, HDMI 2.1 data flow metering stipulates that the FRL three-byte rate is approximately equal to the TMDS three-byte rate, and the difference between the FRL three-byte rate and the TMDS three-byte number is less than 492 three-bytes. Since the FRL three-byte is transmitted in the form of data packets, the power-off interval can be approximated by the number of TMDS three-bytes received. For example, the pixels in the active area may be 4096x2048, the pixels in the garbled reset interval TSR may be 4096x7, the pixels in the clock stable interval Tclk may be 4096x1, and the pixels in the marginal interval Tmg may be 492. Therefore, the HDMI receiving device 100 can calculate the time duration of 8355384 (=4096x2048-4096x7-4096-492) TMDS pixels to approximate the power-off interval Toff2.

[0048] Figure 11 Another embodiment of the present invention is shown Figure 7 Schematic diagram of the current data frame F2 in . Figure 11 In the current data frame F2, multiple blank lines are included as variable refresh rate (VRR) and Fast VActive (FVA) processing areas to achieve variable refresh rate. VRR processing allows dynamic displays to continuously and seamlessly change refresh rates. Displays that support a specific range of refresh rates are called variable refresh rate ranges (VRR ranges). VRR processing allows the refresh rate to change seamlessly and continuously within this range. FVA processing allows image frames to be sent from the source to the sink faster, reducing overall latency.

[0049] Embodiments of the present invention disclose a power-saving method for switching HDMI ports on an HDMI receiver. The HDMI receiver receives data frames via FRL. After detecting the first valid pixel in the previous data frame, the receiver turns off the power to the HDMI port during a power-off interval. After the power-off interval is complete, the receiver turns on the power to the HDMI port during a power-on interval. This method turns on the power only during HDCP synchronization and data descrambling, leaving it off during the majority of the active data frame period, thereby reducing power consumption.

[0050] Those skilled in the art will readily observe that numerous modifications and variations can be made to the apparatus and method while retaining the teachings of the invention. Therefore, the above disclosure should be interpreted only within the scope of the appended claims.

Claims

1. A power saving method for a high-definition multimedia interface, characterized in that: Used on a receiving device having at least one High Definition Multimedia Interface (HDMI) port, the method comprises: Receiving a data frame in a fixed rate link (FRL) mode; When a valid pixel in the data frame is detected in the FRL mode, powering off the HDMI port within a power-off interval; and The HDMI port is powered on within a power-on interval of the data frame in the FRL mode, wherein the power-on interval includes at least one garbled code reset interval and one High-bandwidth Digital Content Protection (HDCP) encryption enabling information.

2. The method according to claim 1, wherein The power-on interval begins before the HDCP encryption enabling information.

3. The method according to claim 1, wherein The power-off interval is derived by subtracting the garbled reset interval from the interval of vertical valid lines in a display data frame.

4. The method according to claim 1, wherein The power-off interval is derived by subtracting the garbled code reset interval and a frequency stabilization interval from the interval of vertical valid lines in the display data frame; In the frequency stabilization range, the frequency of the HDMI port is stabilized after being woken up.

5. The method according to claim 1, wherein The power-off interval is obtained by subtracting the garbled code reset interval, a frequency stabilization interval and a marginal interval from the interval of the vertical valid line in the display data frame; In this frequency stabilization range, the clock of the HDMI port is stable after waking up; The margin interval corresponds to the maximum error between the amount of data transmitted in three bytes of the FRL and the amount of data transmitted in three bytes of the transition-minimized differential signal TMDS.

6. The method according to claim 1, wherein Further including: In the garbled code reset interval, a garbled code reset character is detected to de-garble a current data frame.

7. The method according to claim 6, wherein Further including: After the current data frame is descrambled, if the receiving device switches from another HDMI port to the HDMI port for display, HDCP information is obtained in the HDCP interval to decode the current data frame.

8. The method according to claim 6, wherein The current data frame further includes a plurality of blank lines preceding a vertical sync active edge.

9. The method according to claim 1, wherein The valid pixels in the data frame are compressed according to the Display Stream Compression (DSC) standard.

10. The method according to claim 1, wherein The data frame is transmitted between the sink device and a source device via the FRL 3-channel mode or the FRL 4-channel mode.

11. A high-definition multimedia interface receiving device, characterized in that: include: At least one HDMI port; as well as a controller connected to the at least one HDMI port and configured to shut down power to the HDMI port during a power-off interval when a valid pixel in a data frame is detected in the FRL mode; and Turn on the power of the HDMI port for the power-on interval of the data frame in FRL mode; The power-on interval includes at least a garbled code reset interval and HDCP encryption activation information.

12. The high-definition multimedia interface receiving device according to claim 11, wherein: The power-on interval begins before the HDCP encryption enabling information.

13. The high-definition multimedia interface receiving device according to claim 11, wherein: The power-off interval is obtained by subtracting the garbled reset interval from the interval of vertical valid lines in the display data frame.

14. The high-definition multimedia interface receiving device according to claim 11, wherein: The power-off interval is obtained by subtracting a garbled reset interval and a clock stabilization interval from an interval of vertical valid lines in a display data frame; In the clock stabilization interval, the clock of the HDMI port is stable after being awakened.

15. The high-definition multimedia interface receiving device according to claim 11, wherein: The power-off interval is obtained by subtracting a garbled reset interval, a clock stabilization interval, and a margin interval from an interval of vertical valid lines in a display data frame; In the clock stabilization interval, the clock of the HDMI port is stable after being woken up; The margin interval corresponds to the maximum error between the amount of data transmitted in three bytes of FRL and the amount of data transmitted in three bytes of TMDS.

16. The high-definition multimedia interface receiving device according to claim 11, wherein: Further including: In the garbled code reset interval, a detector detects the garbled code reset character to degarble the current data frame; The current data frame further includes a plurality of blank lines before the vertical synchronization effective edge to achieve a variable refresh rate.

17. The high-definition multimedia interface receiving device according to claim 16, wherein: Further including: After the current data frame is descrambled, HDCP information is obtained in the HDCP interval, and the HDCP information is configured to decode the current data frame if the receiving device switches from another HDMI port to the HDMI port for display.

18. The high-definition multimedia interface receiving device according to claim 11, wherein: The valid pixels in the data frame are compressed according to the DSC standard.

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