Semiconductor device, forming method, and memory system

Abstract

The invention provides a semiconductor device, a forming method and a storage system, and relates to the technical field of semiconductors. The semiconductor device comprises a first semiconductor structure and a second semiconductor structure, the first semiconductor structure comprises a stacked structure and a transistor, the stacked structure comprises first conductive layers and second conductive layers which are alternately stacked in the first direction, the transistor is arranged on one side of the stacked structure, and the transistor is connected with one first conductive layer; and the first connecting structure penetrates through the stacking structure along the first direction and is connected with the second conductive layer. According to the technical scheme, the manufacturing process of the planar capacitor formed by alternately stacking the two conductive layers is simple and easy to implement, the common electrode led out through the first connecting structure does not occupy the effective area of the first conductive layer and the effective area of the second conductive layer, and the obtained planar capacitor has large capacitance capacity.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor device, a method of forming a semiconductor device, and a memory system. BACKGROUND

[0002] The 1T1C structure is a commonly used memory cell structure in DRAM (Dynamic Random Access Memory), which is composed of a transfer gate and a capacitor. However, as the capacitor size is reduced and the number of stacked layers is increased, the manufacturing difficulty is further increased, making it difficult to increase the capacity of the capacitor, which in turn affects the storage performance of the DRAM.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to provide a semiconductor device and a method of forming the same, and a memory system, which at least partially solves the problem of limited application due to the difficulty in manufacturing a capacitor connected to a vertical transistor.

[0005] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor structure comprising a stacked structure and a transistor, the stacked structure comprising first conductive layers and second conductive layers alternately stacked along a first direction, the transistor being disposed on one side of the stacked structure, the transistor being connected to one of the first conductive layers; and a first connection structure penetrating the stacked structure along the first direction and connected to the second conductive layers.

[0007] In some embodiments, the stacked structure further comprises: a dielectric layer between the first conductive layers and the second conductive layers.

[0008] In some embodiments, the first semiconductor structure further comprises: a second connection structure penetrating the stacked structure along the first direction and connected to the first conductive layers and the transistor, respectively.

[0009] In some embodiments, the stacked structure further comprises: a first isolation layer disposed between the second connection structure and the second conductive layers.

[0010] In some embodiments, the stack structure comprises a plurality of layers of the first conductive layer, each layer of the first conductive layer being connected to the second connection structure.

[0011] In some embodiments, the first semiconductor structure comprises a plurality of groups of the second connection structure, each group of the second connection structure being connected to a layer of the first conductive layer.

[0012] In some embodiments, the plurality of groups of the second connection structure are arranged side by side along a second direction perpendicular to the first direction.

[0013] In some embodiments, the stack structure further comprises a first communication portion arranged between the connected second connection structure and a layer of the first conductive layer.

[0014] In some embodiments, the stack structure further comprises a second isolation layer arranged between the isolated second connection structure and a layer of the first conductive layer.

[0015] In some embodiments, the second connection structure is a columnar structure.

[0016] In some embodiments, the stack structure further comprises a third isolation layer arranged between the first connection structure and the first conductive layer.

[0017] In some embodiments, the stack structure comprises a plurality of layers of the second conductive layer, the plurality of layers of the second conductive layer being connected to the same first connection structure.

[0018] In some embodiments, the first connection structure is a slit structure extending along a third direction perpendicular to the first direction.

[0019] In some embodiments, the stack structure comprises a plurality of groups of the first connection structure, the stack structure comprising a plurality of layers of the second conductive layer, each layer of the second conductive layer being connected to a group of the first connection structure.

[0020] In some embodiments, the stack structure further comprises a second communication portion arranged between the connected group of the first connection structure and a layer of the second conductive layer.

[0021] In some embodiments, the stack structure further comprises a fourth isolation layer arranged between the isolated group of the first connection structure and a layer of the second conductive layer.

[0022] In some embodiments, the plurality of groups of the first connection structure are arranged side by side along a second direction perpendicular to the first direction.

[0023] In some embodiments, the first connection structure is a columnar structure.

[0024] In some embodiments, the first semiconductor structure further comprises: an isolation structure penetrating through the stack structure along the first direction and extending along a third direction perpendicular to the first direction.

[0025] In some embodiments, the transistor comprises a vertical transistor comprising a semiconductor body extending along the first direction, and a gate layer in contact with at least one side surface of the semiconductor body.

[0026] In some embodiments, the vertical transistor further comprises a source and a drain disposed at two ends of the semiconductor body along the first direction; one of the source and the drain is connected with one of the first conductive layers.

[0027] In some embodiments, further comprising: a word line connected with the gate layer; and a bit line connected with the other one of the source and the drain.

[0028] In some embodiments, further comprising: a metal layer disposed on the other side of the stack structure away from the transistor.

[0029] In some embodiments, further comprising: a second semiconductor structure located on the other side of the first semiconductor structure away from the transistor, the second semiconductor structure being hybrid bonded with the first semiconductor structure.

[0030] According to another aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a first semiconductor structure comprising: forming a semiconductor body of a transistor and a stack structure comprising first sacrificial layers, dielectric layers, second conductive layers and the dielectric layers alternately stacked along a first direction; forming a first electrode on the semiconductor body, the first electrode being one of a source and a drain of the transistor; replacing the first sacrificial layers with first conductive layers, one of the first conductive layers being connected with the first electrode; and forming a first connection structure connected with the second conductive layers and penetrating through the stack structure.

[0031] In some embodiments, forming the first electrode on the semiconductor body further comprises: forming a connection hole extending to the semiconductor body through the stack structure along the first direction; forming a first isolation layer and a second isolation layer in an inner wall of the connection hole, the first isolation layer isolating the second conductive layers, and the second isolation layer isolating the first sacrificial layers not having a connection relationship; and forming a second connection structure connected with one of the first sacrificial layers and the first electrode respectively in the connection hole.

[0032] In some embodiments, forming the connection hole extending to the semiconductor body through the stack structure along the first direction further comprises: forming an initial slit penetrating through the stack structure along the first direction.

[0033] In some embodiments, before forming the second connection structure in the connection hole for connecting to one of the first sacrificial layer and the first electrode, the method further comprises: depositing a second sacrificial layer in the connection hole and the initial gap.

[0034] In some embodiments, forming the second connection structure in the connection hole for connecting to one of the first sacrificial layer and the first electrode comprises: removing the second sacrificial layer deposited in the connection hole, and filling the connection hole to form the second connection structure.

[0035] In some embodiments, forming the semiconductor body and the stack structure of the transistor further comprises: forming a third sacrificial layer in contact with the semiconductor body in a second direction perpendicular to the first direction.

[0036] In some embodiments, the method further comprises: removing the second sacrificial layer in the initial gap; etching the inner wall of the initial gap to form an intermediate gap exposing the first sacrificial layer and the third sacrificial layer; replacing the first sacrificial layer with a first conductive layer, and further comprising: replacing the third sacrificial layer with a gate layer.

[0037] In some embodiments, the method further comprises: removing a substrate of the semiconductor body away from the stack structure to expose the semiconductor body; forming a second electrode at an exposed end of the semiconductor body, the second electrode for connecting to a bit line, the second electrode being the other one of the source and the drain of the transistor.

[0038] In some embodiments, the stack structure has a first layer away from the semiconductor body and a second layer close to the semiconductor body, and forming the connection hole extending through the stack structure to the semiconductor body in the first direction comprises: forming a plurality of groups of first sub-holes extending through the first layer in the first direction, one group of the first sub-holes stopping at one of the first sacrificial layers; depositing a conductive material at the bottom of the first sub-holes to form a first communication part in contact with the first sacrificial layer; forming a second sub-hole extending through the first communication part in the first direction and through the second layer, the first sub-holes and the second sub-hole being in communication to form the connection hole.

[0039] In some embodiments, forming a first isolation layer and a second isolation layer in an inner wall of the connection hole includes: forming a first groove at a first inner wall in the connection hole, the first inner wall being located at the first sacrificial layer not connected to the first communication part, depositing a second isolation layer in the first groove to isolate the first sacrificial layer; forming a second groove at a second inner wall in the connection hole, the second inner wall being located at the second conductive layer, depositing the first isolation layer in the second groove to isolate the second conductive layer.

[0040] In some embodiments, further comprising: forming a third groove at a third inner wall in the middle gap, the third inner wall being located at the first conductive layer, depositing a third isolation layer in the third groove to isolate the first conductive layer, and correspondingly forming a target gap; and forming the first connection structure connected to the second conductive layer and penetrating through the stack structure includes: filling the target gap to form the first connection structure.

[0041] In some embodiments, further comprising: depositing a metal layer on a side of the stack structure away from the transistor.

[0042] In some embodiments, further comprising: forming a second semiconductor structure; and hybrid bonding the first semiconductor structure and the second semiconductor structure.

[0043] According to still another aspect of the present disclosure, a memory system is provided, including: a semiconductor device and a controller, the semiconductor device including: a first semiconductor structure including a stack structure, a transistor, and a first connection structure, the stack structure including first conductive layers and second conductive layers alternately stacked along a first direction, the transistor being disposed on a side of the stack structure, the transistor being connected to one of the first conductive layers, the first connection structure penetrating through the stack structure along the first direction and being connected to the second conductive layers; a bit line and a word line connected to the transistor, respectively; and the controller coupled to the semiconductor device and configured to control the semiconductor device.

[0044] In some embodiments, the stack structure further includes: a dielectric layer between the first conductive layers and the second conductive layers.

[0045] In some embodiments, the first semiconductor structure further includes: a second connection structure penetrating through the stack structure along the first direction and connected to the first conductive layers and the transistor, respectively.

[0046] In some embodiments, the stack structure includes a plurality of the first conductive layers, each of the first conductive layers being connected to the second connection structure.

[0047] In some embodiments, a plurality of groups of the second connection structure are included, each group of the second connection structure being connected to one of the first conductive layers.

[0048] In some embodiments, the stack structure includes a plurality of the second conductive layers, the plurality of the second conductive layers being connected to the same first connection structure.

[0049] In some embodiments, the first connection structure is a slit structure extending along a third direction perpendicular to the first direction.

[0050] In some embodiments, a plurality of groups of the first connection structure are included, the stack structure including a plurality of the second conductive layers, each of the second conductive layers being connected to one of the groups of the first connection structure.

[0051] In some embodiments, the transistor includes a vertical transistor including a semiconductor body extending along the first direction, and a source and a drain disposed at two ends of the semiconductor body in the first direction; one of the source and the drain is connected to the first conductive layer; the other of the source and the drain is connected to the bit line.

[0052] In some embodiments, the vertical transistor further includes a gate in contact with at least one side surface of the semiconductor body, the word line being connected to the gate along a second direction perpendicular to the first direction.

[0053] In some embodiments, further comprising: a metal layer disposed on the other side of the stack structure away from the transistor.

[0054] In some embodiments, further comprising: a second semiconductor structure on the side of the first semiconductor structure away from the transistor, the second semiconductor structure being hybrid bonded to the first semiconductor structure.

[0055] Other features and advantages of the present disclosure, as well as the structure and operation of various embodiments of the present disclosure, are described in detail below with reference to the accompanying drawings. It is noted that the present disclosure is not limited to the specific embodiments described herein. The embodiments presented herein are presented for purposes of illustration only. Numerous additional embodiments, modifications, and improvements will readily occur to those skilled in the art having the benefit of the teachings contained herein. BRIEF DESCRIPTION OF DRAWINGS

[0056] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is to be noted that the drawings shown below are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0057] Figure 1 A structural schematic of a memory cell is shown in accordance with some embodiments of the present disclosure;

[0058] Figure 2 A structural schematic of another memory cell is shown in accordance with some embodiments of the present disclosure;

[0059] Figure 3 A structural schematic of yet another memory cell is shown in accordance with some embodiments of the present disclosure;

[0060] Figure 4 A plan view of a memory cell array is shown in accordance with some embodiments of the present disclosure;

[0061] Figure 5 A structural schematic of a memory system is shown in accordance with some embodiments of the present disclosure;

[0062] Figure 6 A plan view of another memory cell array is shown in accordance with some embodiments of the present disclosure;

[0063] Figure 7 A structural schematic of another memory system is shown in accordance with some embodiments of the present disclosure;

[0064] Figures 8-31 A manufacturing process of a semiconductor device is shown in accordance with some embodiments of the present disclosure;

[0065] Figures 32-70 A manufacturing process of a semiconductor device is shown in accordance with some embodiments of the present disclosure;

[0066] Figure 71 A flowchart of a method for forming a semiconductor device is shown in accordance with some embodiments of the present disclosure;

[0067] Figure 72 A flowchart of a method for forming a semiconductor device is shown in accordance with some embodiments of the present disclosure;

[0068] Figure 73 A schematic of a memory system is shown in accordance with some embodiments of the present disclosure;

[0069] Figure 74 A schematic of a memory card is shown in accordance with one embodiment of the present disclosure;

[0070] Figure 75 A schematic of a solid state drive (SSD) is shown in accordance with one embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] Although specific configurations and arrangements are discussed, it should be understood that this is done for exemplary purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure also can be employed in a variety of other applications.

[0072] It is noted that the recitations "one embodiment," "an embodiment,” “one example embodiment,” “some embodiments,” etc., indicate that the embodiment(s) so described can include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrases “one embodiment,” “an embodiment,” or “some embodiments,” does not necessarily refer to the same embodiment, although it can. In addition, meaning of “adapted to” and “configured to,” can depend upon the implementation and are intended to cover embodiments where the structure is specifically (purposefully) designed to perform a certain function, even if only statistically related, in addition to instances where the structure is chemically induced or forced to perform a certain function.

[0073] Generally, the terminology can be understood at least in part from usage in context. For example, terms used herein, such as “one or more” can be used to describe either a singular number of a feature, structure, or characteristic or, alternatively, a combination of plural number of features, structures, or characteristics, depending at least in part on the context in which the terms are used. Similarly, terms such as “a” or “the” can be understood to convey a singular usage, or alternatively, a plural usage, depending at least in part on the context in which the terms are used.

[0074] It should be readily understood that the terms “on,” “over,” and “above,” in the present disclosure, are to be interpreted in the broadest relative terms such that “on” a thing not only means “directly on” the thing, but also includes the meaning of being “on” the thing with intervening features or layers therebetween, and “over” or “above” a thing not only means the meaning of being “over” or “above” the thing, but also can include the meaning of being “over” or “above” the thing without intervening features or layers therebetween (i.e., directly over the thing).

[0075] In addition, spatially relative terms, such as “beneath,” “below,” “lower,” “over,” “upper” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0076] As used herein, the term "substrate" refers to a material to which subsequent material is added or otherwise disposed. The substrate itself can be patterned. Material disposed on (e.g., on top of) the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0077] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, a stack of layers can include one or more conductor and contact layers (in which contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0078] As used herein, the term "nominal / nominally" refers to a desired or target value for a characteristic or parameter of a component or process operation that is set during a design phase of production or process, and a range of values above and / or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates values that can vary from a given quantity based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0079] As used herein, a "semiconductor device" is a semiconductor device having vertically oriented strings (referred to herein as "memory strings," e.g., NAND strings) of memory cell transistors in a lateral orientation on a substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to a lateral surface of the substrate.

[0080] As used herein, the term "horizontal / horizontally / lateral / laterally" means nominally parallel to a lateral surface of the substrate, and the term "vertical" or "vertically" means nominally perpendicular to a lateral surface of the substrate.

[0081] As used herein, a "semiconductor device" may specifically be a "3D memory device," which refers to a semiconductor device having a vertically oriented memory cell transistor string (such as a NAND memory string) on ​​a laterally oriented substrate, such that the memory string is delayed in a vertical direction relative to the substrate.

[0082] like Figure 1 As shown, in the DRAM process, the memory cell structure in the semiconductor device can be a 1T1C structure (i.e., 1 transistor 10A and 1 capacitor 10B), the word line (WL) is used to control the opening and closing of the transistor 10A, and the bit line (BL) is used to read and write data in the memory cell. The capacitor is usually formed in a vertical tube manner. Due to the limitations of the punching process, it is currently difficult to increase the capacitor capacity, and the process window is very small. In addition, due to the structural limitations of the DRAM vertical capacitor, the capacitance of its memory cell is also relatively small.

[0083] To address one or more of the aforementioned problems, the present disclosure introduces a novel design of a memory cell in a semiconductor device. The existing 1T1C memory structure is changed to an nTnC design, i.e., the memory cell is designed to include n transistors and n capacitors, and the n transistors and n capacitors 106 are connected one by one.

[0084] In some embodiments of the present disclosure, Figure 2 A schematic diagram of a semiconductor device having a memory cell structure (n=3) with an “nTnC design” according to some embodiments of the present disclosure is shown. Each memory cell includes three transistors and three capacitors, and each transistor is connected to a word line 102 and a bit line 104, respectively. This enables the memory cell structure based on the “nTnC design” to provide higher storage density and better reliability.

[0085] Reference Figure 3 The first electrode 304 of the transistor (one of the source and the drain) is connected to the first electrode plate of the capacitor, that is, the first conductive layer 202, the second electrode 306 of the transistor (the other of the source and the drain) is connected to the bit line 104, the gate 308 of the transistor is connected to the word line 102, and the second electrode plate of the capacitor, that is, the second conductive layer 204 is connected to the common electrode 1202.

[0086] In some embodiments, the gate of the transistor is coupled to a word line, one of the source and drain of the vertical transistor is coupled to one electrode of the capacitor, the other of the source and drain of the vertical transistor is coupled to a bit line, and the other electrode of the capacitor is coupled to ground. In some embodiments, the capacitor can have a stacked structure as described in detail below.

[0087] It should be noted that Figures 4 to 70 The x, y, and z axes are included in the figure to illustrate the spatial relationship of components in the semiconductor device. The z direction corresponds to the first direction, the x direction corresponds to the second direction, and the y direction corresponds to the third direction. The x direction and the y direction are two orthogonal directions in the semiconductor plane: the x direction is the word line direction. The z axis is perpendicular to the x and y axes. As used herein, when a substrate (e.g., a substrate) is located in the lowest plane of the semiconductor device in the z direction (a vertical direction perpendicular to the xy plane), whether a component of the semiconductor device is "on," "above," or "below" another component (e.g., a layer or device) in the z direction can be determined relative to the substrate of the semiconductor device. Throughout this disclosure, the same concept for describing spatial relationships is applied.

[0088] Figure 4 shows a schematic side cross-sectional view of a semiconductor device according to one embodiment of the present disclosure, Figure 5 Shown Figure 4 Schematic plan cross-sectional view of the semiconductor device shown in .

[0089] like Figure 4 As shown, the semiconductor device includes a first semiconductor structure 10, the first semiconductor structure 10 includes a stacking structure 20 and a transistor 30, the stacking structure includes a first conductive layer 202 and a second conductive layer 204 alternately stacked along a first direction, the transistor 30 is arranged on one side of the stacking structure 20, and the transistor is connected to one first conductive layer 202.

[0090] In the stacked structure 20, adjacent first conductive layers 202 (also known as first electrode plates) and second conductive layers 204 (also known as second electrode plates) form a planar capacitor stacked in a planar configuration. The stacked structure 20 forms multiple planar capacitors, with the first electrode plate in each planar capacitor connected to a transistor to form a memory cell structure comprising multiple capacitors and multiple transistors. The manufacturing process of alternating the two conductive layers in a single direction is simple and easy.

[0091] In some embodiments, the first conductive layer or the second conductive layer may be generated when the initial stacking structure is formed, or a sacrificial layer may be formed first when the initial stacking structure is formed, and then the first conductive layer or the second conductive layer may be generated by replacing the sacrificial layer.

[0092] In some embodiments, each first conductive layer and each second conductive layer has the same thickness nominally between approximately 25 nm and approximately 40 nm, for example, the same thickness between 25 nm and 40 nm (e.g., 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, any range bounded by the lower ends of these values, or in any range bounded by any two of these values).

[0093] In some embodiments, the first conductive layer and the second conductive layer may include multiple conductive layers, for example, a W layer located above a TiN layer. In some embodiments, the first conductive layer and the second conductive layer may include the same conductive material. In some other embodiments, the first conductive layer may include a first conductive material, and the second conductive layer may include a second conductive material different from the first conductive material.

[0094] In some embodiments, as Figure 4 As shown, the stack structure 20 further includes a dielectric layer 206 located between the first conductive layer 202 and the second conductive layer 204 .

[0095] In some embodiments, the dielectric layer can be directly grown when forming the initial stack structure.

[0096] In some embodiments, the dielectric layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0097] In some embodiments, each dielectric layer has the same thickness nominally between about 15 nm and about 30 nm, such as the same thickness between 15 nm and 30 nm (e.g., 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, any range bounded by the lower end of these values, or in a range bounded by any two of these values).

[0098] In some embodiments, as Figure 4 As shown, the stacked structure 20 includes alternating conductive layers and dielectric layers. The conductive layer is a first conductive layer 202 when connected to the transistor as a first electrode plate, and a second conductive layer 204 when connected to the common electrode as a second electrode plate. A dielectric layer 206 is provided between the two conductive layers. Figure 4As shown, when the stack structure as a whole, one end of the stack structure is attached to the metal layer 110, the other end of the stack structure is close to the transistor 30 and is arranged in parallel with the gate layer 308 of the transistor 30, and the stack structure 20 and the gate layer 308 are also filled with a dielectric.

[0099] As shown, the first conductive layer 202A, the dielectric layer 206A and the second conductive layer 204A form a planar capacitor, the second conductive layer 204A, the dielectric layer 206B and the first conductive layer 202B can form a planar capacitor, and the first conductive layer 202B, the dielectric layer 206C and the second conductive layer 204B can form a planar capacitor. Figure 4

[0100] In this embodiment, the first conductive layer and the second conductive layer are respectively used as electrode plates, the dielectric layer and the first conductive layer and the second conductive layer on both sides form a planar capacitor, the planar capacitor is used for storing electric charge or data, the first connecting structure longitudinally penetrates through the entire stack structure, one side of the planar capacitor is the first conductive layer, the other side of the planar capacitor is connected with the first connecting structure as a common electrode, the first conductive layer as the other side of the planar capacitor is used for connecting the transistor, by adjusting the number of conductive layers connected to the transistor, the capacity of the planar capacitor in the storage unit can be adjusted, and when the number of conductive layers connected to the transistor is adjusted, it is beneficial to realize the improvement of the storage density.

[0101] In some embodiments, the initial stack structure including the alternately stacked second conductive layer, the dielectric layer, the sacrificial layer and the dielectric layer can be formed by alternately depositing the second conductive layer, the dielectric layer, the sacrificial layer and the dielectric layer on the substrate based on the SEG (Selective Epitaxial Growth) process.

[0102] In some embodiments, the sacrificial layer is replaced to obtain the first conductive layer, the sacrificial layer is SIN, and the conductive layer includes but is not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide or any combination thereof. Or is POLY, a conductive metal or a metal compound, such as a W layer or a POLY layer.

[0103] In some embodiments, as shown in Figure 4 As shown, the first semiconductor structure 10 further includes a first connecting structure 402, the first connecting structure 402 penetrates through the stack structure 20 along the first direction and is connected with the second conductive layer 204, and the first connecting structure 402 is used as a common electrode connected with the second electrode plate of the planar capacitor. The common electrode drawn out does not occupy the effective area of the first conductive layer and the second conductive layer, so that the planar capacitor obtained has a larger capacitance capacity, and the preparation process can be simplified by connecting the common electrode with multiple second conductive layers.​

[0104] In some embodiments, the first connection structure 402 is connected to the second conductive layer 204 along a second direction.

[0105] In some embodiments, as shown in FIG. 4B, the stack structure 20 includes a plurality of second conductive layers 204 connected to the same first connection structure 402. Figure 4

[0106] In some embodiments, one implementation of the first connection structure is a slit structure, as shown in FIG. 4C, the slit structure 402 extends through the first conductive layer 202, the dielectric layer 206 and the second conductive layer 204 along a first direction, and the gate layer 308. Figure 4 Figure 5 As shown in FIG. 4C, the slit structure 402 extends along a third direction.

[0107] Referring to FIG. 4D, Figure 4 Each slit structure 402 can extend vertically in the y direction to separate the stack structure into memory blocks. In one memory block, the first conductive layer as the first electrode plate and the plurality of second conductive layers are connected to the same slit structure.

[0108] In some embodiments, the slit structure 402 can include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide.

[0109] In some embodiments, to form the slit structure, in the process of forming the connection hole, an initial slit extending through the stack structure along the first direction and extending to the substrate is formed, after the second connection structure is formed, the inner wall of the initial slit is etched to form an intermediate slit, a third recess is formed at a third inner wall in the intermediate slit, a third isolation layer isolating the first conductive layer and the word line is deposited in the third recess to form a target slit, the target slit is filled to form the first connection structure 402.

[0110] In some embodiments, the first connection structure can include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide.

[0111] In some embodiments, the slit is formed in the stack structure, and the first connection structure is formed by filling the slit, so that the first connection structure formed does not reduce the effective area of the capacitance between the upper and lower conductive layers.

[0112] In some embodiments, as shown in FIG. 4E, Figure 4 ​​As shown, the first semiconductor structure 10 further includes a second connection structure 50 , which penetrates the stack structure 20 along the first direction and is respectively connected to the first conductive layer 202 and the transistor 30 .

[0113] In some embodiments, the second connection structure may be a columnar structure or a plate-like structure.

[0114] In some embodiments, the second connection structure may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide.

[0115] In some embodiments, in order to form a second connection structure, a connection hole can be formed by the SCT (Use Stair Step (SS) Etch Process to accurately place Contact Hole on each WL) process. Based on the different generation processes, the connection hole includes a first sub-hole and a second sub-hole. The first sub-hole can be formed in the previous process, and the second sub-hole can be formed along the first sub-hole in the subsequent process.

[0116] In some embodiments, the stack structure 20 includes multiple first conductive layers 202 , and each first conductive layer 202 is connected to the second connection structure 50 .

[0117] In some embodiments, the first semiconductor structure 10 includes a plurality of groups of second connection structures 50 , and each group of second connection structures 50 is respectively connected to one layer of the first conductive layer 202 .

[0118] In some embodiments, in a memory cell architecture having multiple conductive layers, there may be multiple second connection structures, and one first conductive layer is connected to one transistor through one second connection structure.

[0119] In some embodiments, as Figure 4 As shown, a first connecting portion 702 is provided between the connected second connecting structure 50 and one first conductive layer 202 .

[0120] In some embodiments, the first connecting portion is formed in a process between the first sub-hole process and the second sub-hole process. For example, a conductive material is deposited on the bottom of the first sub-hole to form the first connecting portion. At this time, the first conductive layer exists in the state of a sacrificial layer, and the first connecting portion is connected to the corresponding sacrificial layer.

[0121] In some embodiments, the first via, the second connection structure, and the first conductive layer may include the same conductive material.

[0122] In some embodiments, in a stacked structure having multiple groups of first conductive layers, dielectric layers, and second conductive layers, one or one group of second connecting structures is connected to only one of the first conductive layers. Therefore, for one or one group of second connecting structures, for the first conductive layer with a connection relationship, a first connecting portion connected to the first conductive layer needs to be formed on the periphery in the horizontal direction. For the first conductive layer and the second conductive layer that do not have a connection relationship, an insulating portion needs to be formed on the periphery, such as Figure 4 As shown, the insulating portion provided between the second connection structure 50 and the second conductive layer 204 is recorded as a first insulating layer 602 , and the insulating portion provided between the isolated second connection structure 50 and one layer of the first conductive layer 202 is recorded as a second insulating layer 604 .

[0123] Reference Figure 4 If other first conductive layers and second conductive layers are arranged on the upper side of the first connecting portion 702, it is necessary to form a first insulating layer 602 on the inner wall of the first sub-hole to isolate the second conductive layer 204, and to form a second insulating layer 604 to isolate the other first conductive layers.

[0124] Reference Figure 4 If other first conductive layers and second conductive layers are arranged on the lower side of the first connecting portion 702, it is necessary to form a first insulating layer 602 on the inner wall of the second sub-hole to isolate the second conductive layer 204, and to form a second insulating layer 604 to isolate the other first conductive layers.

[0125] In some embodiments, an oxide (OX) material may be used as an insulating material for the first and second isolation layers and may be generated by ALD (Atomic Layer Deposition). OX may be aluminum oxide (Al2O3). In the stacked structure, the first and second isolation layers are formed respectively by depositing ALD OX, so that the second connection structure is isolated from the second conductive layer and the first conductive layer that has no connection relationship.

[0126] In some embodiments, multiple groups of second connection structures 50 are arranged side by side along a second direction perpendicular to the first direction.

[0127] The second connection structure can be a plurality of groups, and the plurality of groups of second connection structures are arranged side by side along the second direction, i.e., the x direction. For each group of second connection structures, a plurality of second connection structures are arranged along the third direction, i.e., the y direction, so that the second connection structures form an array structure arranged along the x direction and the y direction respectively. Figure 5 , the plurality of transistors 30 correspond to a plurality of second connection structures (not shown in the figure), and the plurality of second connection structures form an array structure.

[0128] In some embodiments, the second connection structure 50 is a columnar structure.

[0129] In some embodiments, as Figure 4 As shown, the stack structure 20 further includes a third isolation layer 606 . The third isolation layer 606 is disposed between the first connection structure 402 and the first conductive layer 202 to isolate the first connection structure 402 from the first conductive layer 202 .

[0130] In some embodiments, the third isolation layer can be generated using ALD (Atomic Layer Deposition) oxide (OX) material as an insulating material. OX can be aluminum oxide (Al2O3). In the stacked structure, three isolation layers are formed by depositing ALD OX to isolate the first connection structure from the first conductive layer.

[0131] In some embodiments, transistor 30 may be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0132] In some embodiments, as Figure 4 As shown, the vertical transistor 30 includes a semiconductor body 302 extending along a first direction, for example, the semiconductor body 302 can have a cubic shape to expose its four sides. It will be understood by those skilled in the art that the semiconductor body 302 can have any suitable 3D shape, such as a polyhedron shape or a cylindrical shape. That is, the cross-section of the semiconductor body 302 in a plan view (for example, in the xy plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape) or any other suitable shape. It should be understood that, consistent with the scope of the present disclosure, for a semiconductor body having a circular or elliptical cross-section in a plan view, the semiconductor body can still be considered to have multiple sides, so that the gate structure contacts more than one side of the semiconductor body. The semiconductor body 302 can be formed from a substrate (for example, by etching or epitaxy) and therefore has the same semiconductor material (for example, crystalline silicon) as the substrate (for example, a silicon substrate).

[0133] In some embodiments, as Figure 4 As shown, the vertical transistor 30 also includes a source and a drain (S / D, doped regions, also known as source electrodes and drain electrodes) arranged at both ends of the semiconductor body in a first direction (z direction); one of the source and the drain 304 is connected to the first conductive layer 202, and the other of the source and the drain 306 is connected to the bit line 100.

[0134] The source and drain may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As).

[0135] In some embodiments, as Figure 4 As shown, the vertical transistor further includes a gate layer 308 in contact with at least one side surface of the semiconductor body, and the word line 90 is connected to the gate layer 308 along a second direction perpendicular to the first direction.

[0136] The vertical transistor 30 may further include a gate layer 308 in contact with one or more sides of the semiconductor body 302, i.e., the semiconductor body 302 may be at least partially surrounded by the gate layer 308. The gate layer 308 may include a gate electrode. The gate electrode may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode may include doped polysilicon, i.e., gate polysilicon. It will be appreciated by those skilled in the art that in some examples, the gate electrode and the word line may be a continuous conductive structure. That is, the gate electrode may be considered as part of the word line forming the gate layer 308, or the word line may be considered as an extension of the gate electrode to couple to peripheral circuitry.

[0137] The source and drain can be separated in a first direction (z-direction) by a gate layer 308. That is, the gate layer 308 is formed between the source and drain. One of the source and drain is disposed opposite the substrate so that after the substrate is removed, the semiconductor body 302 is exposed. The exposed ends of the semiconductor body are doped to form the source and drain, as well as the corresponding connected bit lines 100.

[0138] In some embodiments, vertical transistors are used instead of conventional planar transistors as switches and selection devices in memory cell arrays in DRAM or other memory devices. Vertically arranged transistors can reduce the area of ​​the transistors and simplify the layout of the interconnect structure.

[0139] A memory cell array with vertical transistors and its peripheral circuitry can be formed on separate wafers and bonded together in a face-to-face arrangement. Stacking the memory cell array and peripheral circuitry can also reduce chip size compared to a side-by-side arrangement, and combined with the use of planar capacitors, can improve array efficiency.

[0140] In some embodiments, due to the vertical arrangement of transistors, word lines and bit lines are set close to the bonding interface. The vertically arranged transistors can be coupled to peripheral circuits through a large number (e.g., millions) of parallel bonding contacts passing through the bonding interface. Direct, short-distance (e.g., micron-level) electrical connections can be made between the memory cell array and the peripheral circuits to increase the throughput and input / output (I / O) speed of the memory device.

[0141] Reference Figure 5The plurality of transistors 30 form a transistor array, each transistor being connected to a bit line 100 and a word line 90, one of the source and drain of the transistor 30 being connected to the first connection structure 402, the other of the source and drain of the transistor 30 being connected to the bit line 100, the gate of the transistor 30 being connected to the word line 90. In some embodiments, as shown in FIG. 1C, the semiconductor device further comprises a metal layer 110 disposed on the other side of the stack structure 20 away from the transistor 30, and a second semiconductor structure 120 hybrid-bonded to the first semiconductor structure 10 through the metal layer 110. Figure 4 In some embodiments, as shown in FIG. 1C, the semiconductor device further comprises a metal layer 110 disposed on the other side of the stack structure 20 away from the transistor 30, and a second semiconductor structure 120 hybrid-bonded to the first semiconductor structure 10 through the metal layer 110.

[0142] The metal layer can serve as a bonding interface for bonding to the second semiconductor structure. The bonding interface can be a layer having a thickness that includes a top surface of a bonding layer of the second semiconductor structure and a bottom surface of a bonding layer of the first semiconductor structure.

[0143] It can be appreciated that the bonding interface is formed between the second semiconductor structure 120 and the first semiconductor structure 10 in the 3D memory device, and the second semiconductor structure 120 and the first semiconductor structure 10 are vertically joined by the bonding (e.g., hybrid bonding). Hybrid bonding (also referred to as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can achieve both metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding. Data transfer between the array of memory cells in the first semiconductor structure and the peripheral circuitry in the second semiconductor structure can be performed through interconnects (e.g., bonding contacts) through the bonding interface.

[0144] Hybrid bonding (also referred to as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can achieve both metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding. Data transfer between the array of memory cells in the first semiconductor structure 10 and the peripheral circuitry in the second semiconductor structure 120 can be performed through interconnects (e.g., bonding contacts) through the bonding interface, i.e., the metal layer 110.

[0145] The second semiconductor structure 120 includes peripheral circuitry configured to control and sense the memory array devices on the memory array chip. The peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry to facilitate 3D memory device operation, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, the peripheral circuitry can include transistors that are high-speed devices formed with advanced logic processes (e.g., 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc. technology nodes).

[0146] In some embodiments, as shown in FIG. 1A, the second semiconductor structure 120 includes complementary metal-oxide-semiconductor (CMOS) 1204, various types of peripheral circuitry formed based on CMOS technology, e.g., which can be implemented with logic processes (e.g., 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), which can be coupled to the first semiconductor structure 10 through bit lines, word lines, common electrodes of planar capacitors, and any other suitable metal wiring. It is noted that the one or more peripheral circuitries can include any suitable circuitry to facilitate operation of the disclosed memory devices by applying and sensing voltage and / or current signals to and from each memory cell via word lines and bit lines. Figure 4

[0147] The peripheral circuitry (also referred to as control and sensing circuitry) can include any suitable digital, analog, and / or mixed-signal circuitry to facilitate operation of the memory cell array. For example, the peripheral circuitry can include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the above functional circuitry (e.g., sub-circuitry), or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0148] ​In addition, those skilled in the art will appreciate that, in some embodiments, the semiconductor device may further include any other circuits compatible with advanced logic processes, including logic circuits such as processors and programmable logic devices (PLDs) or memory circuits such as static random access memories (SRAMs).

[0149] Figure 6 shows a schematic side cross-sectional view of a semiconductor device according to another embodiment of the present disclosure, Figure 7 Shown Figure 6 Schematic plan cross-sectional view of the semiconductor device shown in .

[0150] like Figure 6 As shown, the semiconductor device includes a first semiconductor structure 10, the first semiconductor structure 10 includes a stacking structure 20 and a transistor 30, the stacking structure includes a first conductive layer 202 and a second conductive layer 204 alternately stacked along a first direction, the transistor 30 is arranged on one side of the stacking structure 20, and the transistor is connected to one first conductive layer 202.

[0151] In the stacked structure 20, adjacent first conductive layers 202 (also known as first electrode plates) and second conductive layers 204 (also known as second electrode plates) form a planar capacitor stacked in a planar configuration. The stacked structure 20 forms multiple planar capacitors, with the first electrode plate in each planar capacitor connected to a transistor to form a memory cell structure comprising multiple capacitors and multiple transistors. The manufacturing process of alternating the two conductive layers in a single direction is simple and easy.

[0152] In some embodiments, a sacrificial layer is first formed when forming the initial stack structure, and the first conductive layer or the second conductive layer is generated by replacing the sacrificial layer.

[0153] In some embodiments, each first conductive layer and each second conductive layer has the same thickness nominally between approximately 25 nm and approximately 40 nm, for example, the same thickness between 25 nm and 40 nm (e.g., 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, any range bounded by the lower ends of these values, or in any range bounded by any two of these values).

[0154] In some embodiments, the first conductive layer and the second conductive layer may include multiple conductive layers, for example, a W layer located above a TiN layer. In some embodiments, the first conductive layer and the second conductive layer may include the same conductive material. In some other embodiments, the first conductive layer may include a first conductive material, and the second conductive layer may include a second conductive material different from the first conductive material.

[0155] In some embodiments, as shown in FIG. 1, the stack structure 20 further comprises a dielectric layer 206 between the first conductive layer 202 and the second conductive layer 204. Figure 6

[0156] In some embodiments, the dielectric layer can be generated directly when the initial stack structure is formed.

[0157] In some embodiments, the dielectric layer can comprise a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0158] In some embodiments, each dielectric layer has a same thickness nominally between about 15 nm and about 30 nm, such as a same thickness between 15 nm and 30 nm (e.g., 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, any range bounded by a lower end of these values, or a range defined in any two of these values).

[0159] In some embodiments, as shown in FIG. 1, the stack structure 20 further comprises a dielectric layer 206 between the first conductive layer 202 and the second conductive layer 204. Figure 6 Figure 6 In some embodiments, as shown in FIG. 1, the stack structure 20 comprises alternating conductive layers and dielectric layers, the conductive layer as the first conductive layer 202 when connected to the transistor as the first electrode plate, the conductive layer as the second conductive layer 204 when connected to the common electrode as the second electrode plate, and the dielectric layer 206 between the two conductive layers. As shown in FIG. 1, one end of the overall stack structure is attached to the metal layer 110, and the other end is close to the transistor 30 and is arranged opposite to the gate layer 308 of the transistor 30.

[0160] In this embodiment, the first conductive layer and the second conductive layer respectively serve as electrode plates, the dielectric layer and the first conductive layer and the second conductive layer on both sides form a planar capacitor, the planar capacitor is used to store electric charge or data, the first connection structure passes through the entire stack structure in the longitudinal direction, one side of the planar capacitor is the first conductive layer, the other side of the planar capacitor is connected to the first connection structure as the common electrode, the first conductive layer as the other side of the planar capacitor is used to connect the transistor, by adjusting the number of conductive layers connected to the transistor, the capacity of the planar capacitor in the storage unit is adjustable, and when the number of conductive layers connected to the transistor is adjusted, it is beneficial to realize the improvement of the storage density.

[0161] In some embodiments, as shown in FIG. 1, the stack structure 20 further comprises a dielectric layer 206 between the first conductive layer 202 and the second conductive layer 204. Figure 6 ​​As shown, the first semiconductor structure 10 further includes another first connection structure 404, which penetrates the stack structure 20 along the first direction and is connected with the second conductive layer 204, and the first connection structure 404 serves as a common electrode connected with the second electrode plate of the planar capacitor. The leading-out common electrode does not occupy the effective area of the first conductive layer and the second conductive layer, so that the planar capacitor obtained has a larger capacitance capacity, and the preparation process can be simplified by connecting the common electrode with multiple second conductive layers.

[0162] In some embodiments, the stack structure 20 includes multiple layers of the second conductive layer 204, and each layer of the second conductive layer 204 is connected with a group of the first connection structure 404.

[0163] In some embodiments, the multiple groups of the first connection structure are arranged side by side along a second direction perpendicular to the first direction. The first connection structure can be a columnar structure or a plate structure.

[0164] In some embodiments, as shown in FIG. 1B, the first semiconductor structure 10 further includes a second connection structure 50, which penetrates the stack structure 20 along the first direction and is connected with the first conductive layer 202 and the transistor 30, respectively. Figure 6 As shown, the multiple first connection structures 402 are led out from the stack structure and connected with the common electrode 1202.

[0165] In some embodiments, as shown in FIG. 1B, the first semiconductor structure 10 further includes a second connection structure 50, which penetrates the stack structure 20 along the first direction and is connected with the first conductive layer 202 and the transistor 30, respectively. Figure 7 As shown, the first connection structure 404 and the second connection structure 50 are alternately arranged along the y direction. Specifically, one group of the first connection structure and one group of the second connection structure can be alternately arranged along the y axis, or multiple groups of the first connection structure and multiple groups of the second connection structure can be alternately arranged along the y axis.

[0166] In some embodiments, as shown in FIG. 1B, the first semiconductor structure 10 further includes a second connection structure 50, which penetrates the stack structure 20 along the first direction and is connected with the first conductive layer 202 and the transistor 30, respectively. Figure 6 As shown in FIG. 1B, the first semiconductor structure 10 further includes a second connection structure 50, which penetrates the stack structure 20 along the first direction and is connected with the first conductive layer 202 and the transistor 30, respectively.

[0167] In some embodiments, the second connection structure can include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide. In some embodiments, the first connection structure 404 and the second connection structure 50 are both columnar structures.

[0168] In some embodiments, the first connection structure 404, the second conductive layer 204, the first conductive layer 202, and the second connection structure 50 have a one-to-one corresponding connection relationship.

[0169] In some embodiments, the plurality of first connection structures and the plurality of second connection structures are formed simultaneously and have the same structure and material. When there are multiple second conductive layers in the stacked structure, one second conductive layer is correspondingly connected to one group of first connection structures.

[0170] In some embodiments, in order to form the second connection structure, the first connection hole can be formed first. Based on the different generation processes, the first connection hole includes a first sub-hole and a second sub-hole. The first sub-hole can be formed in a previous process, and then the second sub-hole can be formed along the first sub-hole in a subsequent process. In order to form the first connection structure, the second connection hole is formed at the same time as the first connection hole. Based on the different generation processes, the second connection hole includes a third sub-hole and a fourth sub-hole. The first sub-hole and the third sub-hole can be formed in a previous process, and then the second sub-hole and the fourth sub-hole can be formed along the first sub-hole in a subsequent process. In some embodiments, as Figure 6 As shown, a first connecting portion 702 is provided between the connected second connection structure 50 and one first conductive layer 202 .

[0171] In some embodiments, as Figure 6 As shown, a second connecting portion 704 is provided between the connected first connecting structures 404 and one of the second conductive layers 204 , and the first connecting portions 702 and the second connecting portions 704 are alternately provided along the first direction.

[0172] In some embodiments, the first connecting portion 702 , the second connecting portion 704 , the first and second connecting structures 404 and 50 , the first conductive layer 202 , and the second conductive layer 204 may comprise the same conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof.

[0173] In some embodiments, the first communicating portion is formed in a process between the first sub-hole process and the second sub-hole process, and the second communicating portion is formed in a process between the third sub-hole process and the fourth sub-hole process.

[0174] like Figure 6 As shown, the transistor 30 is connected to the first electrode plate of the planar capacitor, that is, the first conductive layer 202, through the second connecting structure 50 and the first connecting portion 702. The second electrode plate of the planar capacitor, that is, the second conductive layer 204, is connected to the common electrode 1202 through the second connecting portion 704 and the first connecting structure 404, corresponding to the formation of a storage unit based on a transistor array structure, and is connected to the word line 90 through the gate layer 308 of the transistor 30.

[0175] like Figure 7As shown, the first connection structures 404 and the second connection structures 50 are staggered, each second connection structure 50 is connected to a transistor (not shown in the figure) which is connected to the word line 90 and the bit line 100 through the transistor, and the plurality of first connection structures 404 are connected to the common electrode 1202.

[0176] In some embodiments, in the stack structure with a plurality of groups of first conductive layers, dielectric layers and second conductive layers, one or a group of second connection structures is connected to only one layer of first conductive layers, so for the one or a group of second connection structures, a first communication part connected to the first conductive layer with a connection relationship needs to be formed in the horizontal direction on the periphery, and for the first conductive layer and the second conductive layer without a connection relationship, an insulating part needs to be formed on the periphery, such as Figure 6 As shown, the insulating part between the second connection structure 50 and the second conductive layer 204 is denoted as a first isolation layer 602, and the insulating part between the isolated second connection structure 50 and one layer of first conductive layers 202 is denoted as a second isolation layer 604.

[0177] In some embodiments, for the first isolation layer and the second isolation layer, an oxide (OX) material can be used as the insulating material, and an ALD (Atomic Layer Deposition) method can be used for generation. The OX can be aluminum oxide (Al2O3). In the stack structure, the first isolation layer and the second isolation layer are formed by depositing ALD OX respectively, so as to isolate the second connection structure from the second conductive layer and the first conductive layer without a connection relationship respectively.

[0178] In some embodiments, as shown in Figure 6 The stack structure 20 further includes a third isolation layer 606, which is arranged between the first connection structure 404 and the first conductive layer 202 to isolate the first connection structure 404 and the first conductive layer 202.

[0179] In some embodiments, as shown in Figure 6 The stack structure 20 further includes a fourth isolation layer 608, which is arranged between the isolated first connection structure 404 and one layer of second conductive layers 204.

[0180] As shown in Figure 56 The fourth isolation layer 608 is used to isolate the first connection structure 404 which is not connected and the second conductive layer 204.

[0181] In some embodiments, the third isolation layer and the fourth isolation layer can be formed using ALD (Atomic Layer Deposition) oxide (OX) material as the insulating material. OX can be aluminum oxide (Al2O3). In the stacked structure, three isolation layers are formed by depositing ALD OX to isolate the first connection structure from the first conductive layer. Four isolation layers are formed by depositing ALD OX to isolate the first connection structure that has no connection relationship from the second conductive layer.

[0182] In some embodiments, the first semiconductor structure 10 further includes an isolation structure 80, such as Figure 6 As shown, the isolation structure 80 penetrates the stack structure 20 along the first direction. Figure 7 As shown, the isolation structure 80 extends along a third direction perpendicular to the first direction. Those skilled in the art will appreciate that the isolation structure 80 serves to separate the stack structure into memory blocks.

[0183] In some embodiments, transistor 30 may be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0184] In some embodiments, as Figure 6 As shown, the semiconductor device further includes: a metal layer 110 disposed on the other side of the stack structure 20 away from the transistor 30 ; and a second semiconductor structure 120 hybrid-bonded to the first semiconductor structure 10 through the metal layer 110 .

[0185] The metal layer may serve as a bonding interface for bonding with the second semiconductor structure. The bonding interface may be a layer with a certain thickness, which includes a top surface of the bonding layer of the second semiconductor structure and a bottom surface of the bonding layer of the first semiconductor structure.

[0186] It is understood that a bonding interface is formed between the second semiconductor structure 120 and the first semiconductor structure 10 in the 3D memory device, and the second semiconductor structure 120 and the first semiconductor structure 10 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding (also known as "metal / dielectric hybrid bonding") is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can simultaneously obtain metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding. Data transfer between the memory cell array in the first semiconductor structure and the peripheral circuit in the second semiconductor structure can be performed through interconnections (e.g., bonding contacts) passing through the bonding interface.

[0187] Hybrid bonding (also known as "metal / dielectric hybrid bonding") is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) that can simultaneously achieve metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding. Data transfer between the memory cell array in the first semiconductor structure 10 and the peripheral circuit in the second semiconductor structure 120 can be performed through interconnects (e.g., bonding contacts) across the bonding interface 110.

[0188] The second semiconductor structure 120 includes peripheral circuits configured to control and sense the memory array devices on the memory array chip. The peripheral circuits can be any appropriate digital, analog, and / or mixed-signal control and sensing circuits for facilitating the operation of the 3D memory device, including but not limited to page caches, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, the peripheral circuits may include transistors that are high-speed devices formed using advanced logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes).

[0189] In some embodiments, as Figure 6 As shown, the second semiconductor structure 120 includes a complementary metal-oxide-semiconductor (CMOS) 1204. Various types of peripheral circuits are formed based on CMOS technology. For example, they can be implemented using a logic process (e.g., 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). The peripheral circuits can be coupled to the first semiconductor structure 10 through bit lines, word lines, common electrodes of planar capacitors, and any other appropriate metal wiring. It should be noted that the one or more peripheral circuits may include any appropriate circuits for facilitating the operation of the disclosed memory device by applying and sensing voltage signals and / or current signals to and from each memory cell via word lines and bit lines.

[0190] The peripheral circuitry (also referred to as control and sense circuitry) can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating operation of the array of memory cells. For example, the peripheral circuitry can include one or more of a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuitry), or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0191] Additionally, those skilled in the art will appreciate that, in some embodiments, the semiconductor device can also include any other circuitry compatible with advanced logic processes, including logic circuitry such as processors and programmable logic devices (PLDs) or memory circuitry such as static random access memory (SRAM).

[0192] Figures 8 to 31 A manufacturing process of a semiconductor device according to embodiments of the present disclosure is shown. Figure 71 A flowchart of an exemplary method for forming a semiconductor device according to some embodiments of the present disclosure is shown. Figures 8 to 31 and Figure 71 The semiconductor device shown in Figure 4 and Figure 5 The semiconductor device shown in

[0193] Referring to Figure 71 , a process of forming a first semiconductor structure in a method for forming a semiconductor device is provided, comprising:

[0194] At step S7102, a semiconductor body of a transistor and an initial stack structure are formed, the initial stack structure comprising first sacrificial layers, dielectric layers, second conductive layers, and dielectric layers alternately stacked along a first direction.

[0195] In some implementations as shown in Figure 8 , the semiconductor body 302 and the initial stack structure 140 are formed on a substrate 130, the initial stack structure 140 comprising first sacrificial layers 1402, dielectric layers 206, second conductive layers 204, and dielectric layers 206 alternately stacked along a first direction, the substrate 130 can comprise silicon (e.g., single-crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0196] In some implementations as shown in Figure 8 , a third sacrificial layer 1406 parallel to the initial stack structure 140 is also formed in the process of forming the semiconductor body 302.

[0197] In some embodiments, when the initial stacking structure is taken as a whole, one end of the initial stacking structure is the upper surface, and the other end of the initial stacking structure is close to the semiconductor body 302 and is arranged relatively parallel to the third sacrificial layer 1406, and a dielectric is also filled between the initial stacking structure and the third sacrificial layer 1406.

[0198] In some embodiments, the alternating first sacrificial layer 1402, dielectric layer 206, second conductive layer 204, and dielectric layer 206 can be formed by various thin film deposition processes such as CVD, PVD, ALD, etc. The second conductive layer 204 can include any suitable conductive material, such as a metal (e.g., W, Cu, Al, etc.) or a metal compound (e.g., TiN, TaN, etc.), and the dielectric layer 206 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first sacrificial layer 1402 can be an insulating layer comprising any suitable insulating material having an etching ratio different from the etching ratio of the material of the dielectric layer 206 and the second conductive layer 204 during one or more selective etching processes. In some embodiments, the first sacrificial layer 1402 comprises silicon nitride.

[0199] In such Figure 8 In some embodiments shown in FIG, semiconductor body 302 can extend above the top surface of substrate 130. As described below with respect to the manufacturing process, semiconductor body 302 can be formed from the substrate (e.g., by etching or epitaxy) and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate). In some embodiments, to form the semiconductor body, an opening extending through the stack of dielectric layers is etched to expose a portion of the substrate, and the semiconductor body is epitaxially grown from the exposed portion of the substrate in the opening. The manufacturing process for epitaxially growing semiconductor body 302 can include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combination thereof. Epitaxy can proceed upward (toward the positive z-direction) from the exposed portion of substrate 130 in the opening. Depending on the shape of the opening, semiconductor body 302 can have the same shape as the opening, such as a cubic shape or a cylindrical shape.

[0200] Re-reference Figure 71 The method further includes step S7104, forming a first electrode on the semiconductor body, the first electrode being one of the source and the drain of the transistor, and after the first sacrificial layer is replaced by the first conductive layer, the first electrode is used to couple with the first conductive layer.

[0201] In some embodiments, forming a first electrode on the semiconductor body further includes: forming a connection hole extending through the stack structure along the first direction to the semiconductor body.

[0202] In such Figure 9 In some embodiments shown in , a side of the stacked structure away from the third sacrificial layer 1406 is a first layer 1408, and a side close to the third sacrificial layer 1406 is a second layer 1410, forming a connection hole extending through the stacked structure along a first direction to the semiconductor body, including: forming multiple groups of first sub-holes 1502 extending through the first layer along the first direction, the first sub-holes 1502 first stopping on different second conductive layers 204. In some embodiments, multiple columns of first sub-holes 1502 are formed along the second direction (x direction), each column of first sub-holes 1502 is arranged along the third direction (y direction), and each column of first sub-holes 1502 stops on the same second conductive layer 204. In some embodiments, as Figure 9 As shown, the second conductive layer 204 where the first sub-hole stays is sequentially lowered.

[0203] In some embodiments, the upper surface layer of the initial stacked structure 140 and the first layer 1408 are sequentially etched using photolithography and etching processes to form the first sub-hole 1502, which is aligned with the semiconductor body. In some embodiments, for example, based on the design of the word lines and bit lines, a photolithography process is performed to pattern the opening of the connection hole using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) are performed to penetrate the first sacrificial layer 1402, the dielectric layer 206, the second conductive layer 204, and the dielectric layer 206 to stop at the designated second conductive layer 204 and expose the second conductive layer 204.

[0204] In such Figure 10 In some embodiments shown, a first recess 610 is formed within the first sub-hole 1502 at a sidewall of the first sacrificial layer 1402. In some implementations, the first sacrificial layer 1402 is etched away through the first sub-hole 1502. For example, a wet etchant can be applied through the first sub-hole 1502 to selectively wet-etch the first sacrificial layer 1402 to form the first recess 610.

[0205] In such Figure 11 In some embodiments shown, a second isolation layer 604 is deposited in the first groove 610 , and the second isolation layer 604 is used to isolate the structure in the hole and the first sacrificial layer 1402 , so as to isolate the structure in the hole and the first conductive layer 202 when the first sacrificial layer 1402 is replaced by the first conductive layer 202 .

[0206] For example, deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.

[0207] In such Figure 12 In some embodiments shown, a second groove 612 is formed on the sidewalls of the second conductive layer 204 within the connection hole 150. A first bottom groove 616 is formed on each remaining layer of the second conductive layer 204. In some embodiments, the second conductive layer 204 is etched away through the first sub-hole 1502. For example, a wet etchant can be applied through the first sub-hole 1502 to selectively wet-etch the second conductive layer 204.

[0208] In such Figure 13 In some embodiments shown, insulating material is deposited in the first bottom trench 616 and the second groove 612 to deposit a first insulating layer 602 that isolates the second conductive layer 204. The second inner wall is located on the second conductive layer 204. In some embodiments, an oxide (OX) material can be used as the insulating material and formed using ALD (Atomic Layer Deposition). OX can be aluminum oxide (Al2O3).

[0209] In such Figure 14 In some embodiments shown, the first isolation layer 602 formed by the first bottom trench 616 is used as the upper surface, and the first sub-hole 1502 is continuously etched downward, passing through the first isolation layer 602 and the dielectric layer 206 and stopping on the next first sacrificial layer 1402 .

[0210] In such Figure 15 In some of the embodiments shown, Figure 14 A groove 1506 is formed on each first sacrificial layer 1402 at the bottom of the first sub-hole 1502 formed in the first sacrificial layer 1402 .

[0211] In such Figure 16 In some of the illustrated embodiments, a conductive material is deposited on the groove 1506 at the bottom of the first sub-hole to form the first connecting portion 702 in contact with the first sacrificial layer. For example, the conductive material deposition may include depositing the conductive material by one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof).

[0212] In such Figure 17In some embodiments as shown, a second sub-hole 1504 is formed through the first communication portion 702 extending in the first direction and through the second layer 1510, the first sub-hole 1502 and the second sub-hole 1504 communicate to form a connection hole 150.

[0213] In some embodiments as shown, a connection hole is formed extending through the stack structure in the first direction to the semiconductor body, the second layer 1410 is located near a side of the semiconductor body, and further comprising: forming an initial slit 1602 extending through the stack structure in the first direction, the initial slit 1602 stops on the substrate 130. In some embodiments, the initial slit 1602 is patterned and etched by using a lithography and etching process. Figure 17

[0214] In some embodiments as shown, further comprising: depositing a second sacrificial layer 1404 in the connection hole 150 and the initial slit 1602. In some embodiments, the second sacrificial layer 1404 can be formed by any appropriate deposition process such as CVD, PVD, ALD, etc., and a subsequent chemical mechanical polishing (CMP) process. As shown, Figure 18 Figure 19 In some embodiments as shown, a protective layer 170 is formed at an end of the initial stack structure 140 away from the substrate 130. And by further etching the protective layer 170, the end of the connection hole 150 and the initial slit 1602 filled with the second sacrificial layer 1404 are exposed. In some embodiments, the second sacrificial layer 1404 deposited in the connection hole forms a second connection structure after removal. In some embodiments as shown, Figure 20

[0215] In some embodiments as shown, by removing the second sacrificial layer 1404 in the connection hole, an implantation process and / or a thermal diffusion process are performed through the connection hole 150 to dope P-type dopants or N-type dopants to the exposed upper end of the semiconductor body 302 to form a source / drain, i.e., a first electrode 304. In some embodiments, by performing a silicidation process at the exposed upper end of the semiconductor body 302, a silicide layer is formed on the first electrode 304. Figure 20

[0216] In some embodiments as shown, a first isolation layer 602 is continuously deposited in the connection hole 150 to insulate the second conductive layer 204, and a second inner wall is located at the second conductive layer 204. In some embodiments, an oxide (OX) material can be used as the insulating material, and an ALD (Atomic Layer Deposition) method is used to generate the OX, which can be aluminum oxide (Al2O3). Figure 21 ​​​​In some embodiments as shown, a second isolation layer 604 is deposited in the connection hole 150, which is used to isolate the in-hole structure and the first sacrificial layer 1402, so as to isolate the in-hole structure and the first conductive layer 202 when the first sacrificial layer 1402 is replaced by the first conductive layer 202. For example, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. After the second isolation layer 604 is formed, the protective layer 170 is removed.

[0217] Referring back to Figure 71 , the method further includes a step S7106 of replacing the first sacrificial layer with the first conductive layer, one of the first conductive layers being connected with the first electrode.

[0218] As shown in Figure 22 , before the first sacrificial layer is replaced by the first conductive layer, a second connection structure 50 is formed in the connection hole, which is connected with one of the first sacrificial layers 1402 and the first electrode 304. The side of the second connection structure 50 is connected with the horizontal first communication part 702, so as to be connected with the horizontal first sacrificial layer 1402. The end of the second connection structure is connected with the first electrode 304, so as to be connected with the transistor. After the first sacrificial layer 1402 is replaced by the first conductive layer, the electrical connection between the first conductive layer and the transistor in the flat panel capacitor is further realized. In some embodiments, a deposition process such as CVD, PVD, ALD, etc. can be performed to deposit W and perform chemical mechanical polishing in the connection hole 150, so as to form the second connection structure 50.

[0219] After the second connection structure 50 is formed, the second sacrificial layer 1404 in the initial gap 1602 is removed to expose the initial gap 1602, as shown in Figure 23 .

[0220] Before the first connection structure is formed, the initial gap 1602 needs to be expanded. Since the first sacrificial layer 1402 and the dielectric layer 206 can be insulating layers, and the second conductive layer 204 is a conductive layer, the insulating layer and the conductive layer can be etched respectively during the expansion process, as shown in Figure 24 , after the insulating layer is etched, a groove 1604A is formed, as shown in Figure 25 , after the conductive layer is etched, an intermediate gap 1604 is formed, and the first sacrificial layer 1402 and the third sacrificial layer 1406 are exposed.

[0221] As shown in Figure 26As shown, the method further includes forming a gate dielectric 310, in some embodiments, after removing the third sacrificial layer 1406, exposing the sidewall of the semiconductor body 302, and oxidizing the semiconductor body 302 sidewall to form the gate dielectric 310. The gate dielectric 310 can completely circumscribe the corresponding semiconductor body 302. In some embodiments, a wet oxidation and / or dry oxidation process (e.g., ISSG) is performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 302 (e.g., single crystalline silicon) as the gate dielectric 310. In some embodiments, the gate dielectric 310 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0222] At the sidewall of the intermediate gap 1604, there are portions of the first and third sacrificial layers exposed. The sacrificial layers are removed to form a horizontal trench (not shown in the figure); through the exposed portions, the first conductive layer 202 and the gate layer 308 are formed in the horizontal trench, as shown in Figure 26

[0223] In addition, after the first conductive layer 202 is formed, the initial stack structure 140 is configured as the stack structure 20.

[0224] Referring back to Figure 71 , the method further includes a step S7108 of forming a first connection structure connected with the second conductive layer and penetrating through the stack structure.

[0225] The first connection structure needs to be electrically connected with the second conductive layer as a common electrode, and therefore needs to be electrically isolated from the first conductive layer and the gate layer. In order to achieve electrical isolation between the first connection structure and the first conductive layer and the gate layer, as Figure 27 shown, the sidewall of the intermediate gap 1604 belonging to the first conductive layer 202 and the gate layer 308 is etched to form a third recess 614.

[0226] In some embodiments as Figure 28 shown, a third isolation layer 606 isolating the first conductive layer 202 and the gate layer 308 is deposited in the third recess 614, and a target gap 1606 is correspondingly formed, in some embodiments, a deposition process such as CVD, PVD, ALD, etc. can be performed. In some embodiments, the third isolation layer can be generated using an ALD (Atomic Layer Deposition) oxide (OX) material as an insulating material, and the OX can be aluminum oxide (Al2O3).

[0227] In some embodiments as Figure 29 ​In some embodiments shown, forming a first connecting structure connected to the second conductive layer and penetrating the stacked structure includes filling the target gap 1606 to form a first connecting structure 402. In some embodiments, the first connecting structure 402 includes, but is not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof, or may be POLY, a conductive metal, or a metal compound, such as a W layer or a POLY layer.

[0228] In such Figure 30 In some of the embodiments shown, after the first connection structure 402 is formed, in order to cover the exposed surfaces of the first connection structure 402 and the second connection structure 50, in some implementations, a dielectric layer 206A can be formed by various thin film deposition processes such as CVD, PVD, ALD, etc. to cover the exposed surfaces of the first connection structure 402 and the second connection structure 50.

[0229] Continue as Figure 30 As shown, the method also includes: depositing a metal layer 110 on a side of the stack structure 140 away from the transistor as a bonding interface. In some embodiments, the metal layer 110 can serve as a bonding interface for bonding with the second semiconductor structure. The bonding interface can be a layer with a certain thickness, which includes the top surface of the bonding layer of the second semiconductor structure and the bottom surface of the bonding layer of the first semiconductor structure.

[0230] In some embodiments, the method further includes: removing the substrate on a side of the semiconductor body away from the stack structure to expose the semiconductor body, for example, by removing the substrate 130 using a planarization process and / or an etching process.

[0231] A second electrode 306 is formed at the exposed end of the semiconductor body 302. The second electrode 306 is used to connect to the bit line 100. The second electrode is the other of the source and the drain of the transistor. Figure 31 As shown, the exposed upper end of each semiconductor body 302 (i.e., one of the two ends of the semiconductor body 302 facing away from the carrier substrate 130 in the vertical direction (z-direction)) is doped to form another source / drain, i.e., a second electrode 306. In some embodiments, an implantation process and / or a thermal diffusion process is performed to dope P-type dopants or N-type dopants into the exposed upper end of the semiconductor body 302 to form the second electrode 306. In some embodiments, a silicide layer is formed on the second electrode 306 by performing a silicidation process on the exposed upper end of the semiconductor body 302. According to some embodiments, a vertical transistor 30 is thus formed having the semiconductor body 302, a source, a drain, a gate layer 308, and a gate dielectric 310, wherein the second electrode 306 is connected to the bit line 100, and the gate layer 308 is connected to the word line 90.

[0232] Continue asFigure 31 As shown, in some embodiments, the method further includes: forming a second semiconductor structure 120; hybrid bonding the first semiconductor structure 10 and the second semiconductor structure 120. And the first connection structure 402 is led out as a common electrode 1202. In some embodiments, the second semiconductor structure 120 includes a complementary metal oxide semiconductor 1204, and the complementary metal oxide semiconductor 1204 includes a peripheral circuit. Hybrid bonding (also known as "metal / dielectric hybrid bonding") is a direct bonding technology (for example, forming a bond between surfaces without using an intermediate layer (for example, solder or adhesive)) and can simultaneously obtain metal-metal (for example, copper-copper) bonding and dielectric-dielectric (for example, silicon oxide-silicon oxide) bonding. Data transmission between the memory cell array in the second semiconductor structure and the peripheral circuit in the second semiconductor structure 120 can be performed through the interconnection (for example, bonding contact) of the metal layer 110. Figures 32 to 70 The following illustrates a manufacturing process of a semiconductor device according to various embodiments of the present disclosure. Figure 72 A flowchart illustrating an exemplary method for forming a semiconductor device according to some embodiments of the present disclosure is shown. Figures 32 to 70 and Figure 72 The semiconductor devices shown in FIG include Figure 6 and Figure 7 The semiconductor device shown.

[0233] refer to Figure 72 , providing another method for forming a semiconductor device, a process of forming a first semiconductor structure, comprising:

[0234] Step S7202 : forming a semiconductor body and an initial stacked structure of a transistor, wherein the stacked structure includes sacrificial layers and dielectric layers alternately stacked along a first direction.

[0235] In such Figure 32 In some embodiments shown in , a semiconductor body 302 and an initial stacked structure 180 are formed on a substrate 130. The initial stacked structure 180 includes sacrificial layers 182 and dielectric layers 206 alternately stacked along a first direction. The substrate 130 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0236] In some embodiments, alternating sacrificial layers 182 and dielectric layers 206 can be formed by various thin film deposition processes such as CVD, PVD, ALD, etc. Dielectric layers 206 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Sacrificial layers 182 can be insulating layers comprising any suitable insulating material that has an etching ratio different from the etching ratio of the material of dielectric layers 206 during one or more selective etching processes. In some embodiments, sacrificial layers 182 include silicon nitride.

[0237] In such Figure 32 In some embodiments shown in , during the process of forming the semiconductor body 302 , a third sacrificial layer 184 is further formed parallel to the initial stack structure 180 .

[0238] When the initial stacking structure is taken as a whole, one end of the initial stacking structure is the upper surface, and the other end of the initial stacking structure is close to the semiconductor body 302 and arranged relatively parallel to the third sacrificial layer 184. The initial stacking structure and the third sacrificial layer 184 are also filled with a dielectric.

[0239] In such Figure 32 In some embodiments shown in FIG, semiconductor body 302 can extend above the top surface of substrate 130. As described below with respect to the manufacturing process, semiconductor body 302 can be formed from the substrate (e.g., by etching or epitaxy) and thus have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate). In some embodiments, to form the semiconductor body, an opening extending through the stack of dielectric layers is etched to expose a portion of the substrate, and the semiconductor body is epitaxially grown from the exposed portion of the substrate in the opening. The manufacturing process for epitaxially growing semiconductor body 302 can include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combination thereof. Epitaxy can proceed upward (toward the positive z-direction) from the exposed portion of substrate 130 in the opening. Depending on the shape of the opening, semiconductor body 302 can have the same shape as the opening, such as a cubic shape or a cylindrical shape.

[0240] Re-reference Figure 72 The method further includes step S7204, forming a first connection structure and a second connection structure that penetrate the alternately stacked sacrificial layer and the dielectric layer. In some embodiments, the first connection structure and the second connection structure can be formed simultaneously. Figure 7As shown in the array of the first connection structures 404 and the second connection structures 50, the first connection holes and the second connection holes need to be generated first, wherein the first connection holes include first sub-holes and second sub-holes, and the second connection holes include third sub-holes and fourth sub-holes, as shown in Figure 33 and Figure 34 As shown, the first sub-holes 1902 and the third sub-holes 2002 can be formed in the initial stack structure 180 respectively, and the first sub-holes 1902 and the third sub-holes 2002 are alternately located on different sacrificial layers 182. In some embodiments, a plurality of columns of the first sub-holes 1902 and a plurality of columns of the third sub-holes 2002 are formed along the second direction (x direction), and each column of the first sub-holes 1902 and each column of the third sub-holes 2002 are arranged along the third direction (y direction), and each column of the connection holes is located on the same sacrificial layer 182.

[0241] In some embodiments, the first sub-holes 1902 and the third sub-holes 2002 are formed by patterning and etching the upper surface layer, the first layer 186, and the underlying sacrificial layer 182 and dielectric layer 206 of the initial stack structure 180 in sequence using photolithography and etching processes. The first sub-holes 1902 are aligned with the semiconductor body. In some implementations, for example, based on a word line and bit line design, a photolithography process is performed to pattern the openings of the connection holes using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etch (RIE)) are performed to pass through the sacrificial layer 182 and the dielectric layer 206.

[0242] In some embodiments, as shown in Figure 35 the fourth recess 1904 is formed at the sidewall belonging to the sacrificial layer 182A within the first sub-hole 1902, and the fifth recess 1906 is formed at the sidewall belonging to the sacrificial layer 182B. In some implementations, the sacrificial layer 182 is etched away via the first sub-hole 1902. For example, a wet etchant can be applied through the first sub-hole 1902 to selectively wet etch the sacrificial layer 182 to form the fourth recess 1904 and the fifth recess 1906.

[0243] In some embodiments, as shown in Figure 36 the sixth recess 2004 is formed at the sidewall belonging to the sacrificial layer 182A within the third sub-hole 2002, and the seventh recess 2006 is formed at the sidewall belonging to the sacrificial layer 182B. In some implementations, the sacrificial layer 182 is etched away via the third sub-hole 2002. For example, a wet etchant can be applied through the third sub-hole 2002 to selectively wet etch the sacrificial layer 182 to form the sixth recess 2004 and the seventh recess 2006.

[0244] In some embodiments, as shown in Figure 37In some embodiments as shown, a first isolation layer 602 is formed by depositing within the fourth recess 1904, the first isolation layer 602 is configured to isolate the in-hole structure and the sacrificial layer 182A, a second isolation layer 604 is formed by depositing within the fifth recess 1906, the second isolation layer 604 is configured to isolate the in-hole structure and the sacrificial layer 182B, so as to isolate the second connection structure and the conductive layer when replacing the sacrificial layer with the conductive layer and forming the second connection structure.

[0245] In some embodiments as shown, Figure 38 In some embodiments as shown, a fourth isolation layer 608 is formed by depositing within the sixth recess 2004, the fourth isolation layer 608 is configured to isolate the in-hole structure and the sacrificial layer 182A, a third isolation layer 606 is formed by depositing within the seventh recess 2006, the third isolation layer 606 is configured to isolate the in-hole structure and the sacrificial layer 182B, so as to isolate the first connection structure and the conductive layer when replacing the sacrificial layer with the conductive layer and forming the first connection structure.

[0246] For example, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0247] In some embodiments as shown, Figure 39 In some embodiments as shown, a second bottom groove 1908 is formed on the sacrificial layer 182B that stays in the first sub-hole 1902. In some embodiments, the bottom sacrificial layer 182 is etched away via the first sub-hole 1902. For example, a wet etchant can be applied through the first sub-hole 1902 to selectively wet etch the sacrificial layer 182.

[0248] In some embodiments as shown, Figure 40 In some embodiments as shown, a third bottom groove 2008 is formed on the sacrificial layer 182A that stays in the third sub-hole 2002. In some embodiments, the bottom sacrificial layer 182 is etched away via the third sub-hole 2002. For example, a wet etchant can be applied through the third sub-hole 2002 to selectively wet etch the sacrificial layer 182.

[0249] In some embodiments as shown, Figure 41 In some embodiments as shown, a first communication portion 702 in contact with the first sacrificial layer 182B is formed by depositing conductive material in the second bottom groove 1908, for example, the conductive material deposition can include conductive material deposited by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof.

[0250] In some embodiments as shown, Figure 42In some embodiments shown, conductive material deposition is performed in the third bottom trench 2008 to form the second connecting portion 704 in contact with the first sacrificial layer 182A. For example, the conductive material deposition may include depositing the conductive material by one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof).

[0251] In such Figure 43 In some embodiments shown, a second sub-hole 1910 is formed extending through the first connecting portion 702 along the first direction and extending to the semiconductor body. The first sub-hole 1902 and the second sub-hole 1910 are connected to form a first connecting hole 190 .

[0252] In such Figure 44 In some embodiments shown, during the process of forming the second sub-hole 1910, the process also includes: forming a fourth sub-hole 2010 extending along the first direction through the second connecting portion 704 and extending to the substrate 130, and the third sub-hole 2002 and the fourth sub-hole 2010 are connected to form the second connection hole 200. In some embodiments, during the process of forming the second sub-hole 1910, the process also includes: forming an initial slit 2102 penetrating the initial stacking structure along the first direction, and the initial slit 2102 remains on the substrate 130. In some embodiments, the initial slit 2102 is patterned and etched by using photolithography and etching processes.

[0253] In such Figure 45 In some embodiments shown, a second sacrificial layer 1404 is further deposited in the first connection hole 190. In some embodiments, the second sacrificial layer 1404 can be formed by any suitable deposition process such as CVD, PVD, ALD, etc., followed by a chemical mechanical polishing (CMP) process.

[0254] In such Figure 46 In some embodiments shown, the second sacrificial layer 1404 is further deposited in the second connection hole 200 and the initial gap 2102. In some embodiments, the second sacrificial layer 1404 can be formed by any suitable deposition process such as CVD, PVD, ALD, etc., followed by a chemical mechanical polishing (CMP) process.

[0255] like Figure 47 and 48As shown, in some embodiments, the method further includes forming a protective layer 170 at one end of the initial stack structure 180 away from the substrate 130. The protective layer 170 is further etched to expose the ends of the first connection hole 190 and the second connection hole 200 filled with the second sacrificial layer 1404. In some embodiments, the second sacrificial layer 1404 deposited in the connection hole is removed to form a second connection structure. Figure 49 In some embodiments shown, the second sacrificial layer 1404 within the first connection hole 190 is removed.

[0256] In such Figure 50 In some embodiments shown, the second sacrificial layer 1404 within the second connection hole 200 is removed.

[0257] In such Figure 51 In some embodiments shown, a fourth recess 1904 is formed on the sidewalls of the sacrificial layer 182A within the second sub-hole 1910, and a fifth recess 1906 is formed on the sidewalls of the sacrificial layer 182B. In some implementations, the sacrificial layer 182 is etched away through the second sub-hole 1910. For example, a wet etchant can be applied through the second sub-hole 1910 to selectively wet-etch the sacrificial layer 182 to form the fourth recess 1904 and the fifth recess 1906.

[0258] In such Figure 52 In some embodiments shown, a sixth recess 2004 is formed on the sidewalls of the sacrificial layer 182A within the fourth sub-hole 2010, and a seventh recess 2006 is formed on the sidewalls of the sacrificial layer 182B. In some implementations, the sacrificial layer 182 is etched away through the fourth sub-hole 2010. For example, a wet etchant can be applied through the fourth sub-hole 2010 to selectively wet-etch the sacrificial layer 182 to form the sixth recess 2004 and the seventh recess 2006.

[0259] In such Figure 53 In some of the embodiments shown, a first isolation layer 602 is deposited in the fourth groove 1904, and a second isolation layer 604 is used to isolate the structure in the hole and the sacrificial layer 182A. A second isolation layer 604 is deposited in the fifth groove 1906, and the second isolation layer 604 is used to isolate the structure in the hole and the sacrificial layer 182B, so as to isolate the second connection structure and the conductive layer when the sacrificial layer is replaced with a conductive layer and a second connection structure is formed.

[0260] In such Figure 54In some of the embodiments shown, a fourth isolation layer 608 is deposited in the sixth groove 2004 to isolate the structure in the hole and the sacrificial layer 182A. A third isolation layer 606 is deposited in the seventh groove 2006 to isolate the structure in the hole and the sacrificial layer 182B, so as to isolate the first connection structure and the conductive layer when the sacrificial layer is replaced with a conductive layer and the first connection structure is formed.

[0261] For example, deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.

[0262] In such Figure 53 and Figure 54 In some embodiments shown, an implantation process and / or a thermal diffusion process is performed through the first connection hole 190 to dope P-type dopants or N-type dopants into the exposed upper end portion of the semiconductor body 302 to form a source / drain, i.e., a first electrode 304. In some implementations, a silicide layer is formed on the first electrode by performing a silicide process on the exposed upper end portion of the semiconductor body.

[0263] In some embodiments, an oxide (OX) material may be used as the insulating material and may be formed by ALD (Atomic Layer Deposition), and OX may be aluminum oxide (Al 2 O 3 ).

[0264] In such Figure 53 and Figure 54 In some of the illustrated embodiments, the process further includes removing the protective layer 170 .

[0265] In such Figure 55 In some embodiments shown, a second connection structure 50 connected to a sacrificial layer 182B and the first electrode 304 is formed within the first connection hole 190. The side of the second connection structure 50 is connected to the horizontal sacrificial layer 182B by connecting to the first horizontal connection portion 702. The end of the second connection structure is connected to the first electrode 304 to achieve connection with the transistor. After the sacrificial layer 182B is replaced with the first conductive layer, the electrical connection between the first conductive layer and the transistor in the planar capacitor is further achieved. In some embodiments, a deposition process such as CVD, PVD, ALD, etc. can be performed to perform W deposition and chemical mechanical polishing in the first connection hole 190 to form the second connection structure 50.

[0266] In such Figure 56In some embodiments as shown, a first connecting structure 404 connected with the sacrificial layer 182A is formed in the second connecting hole 200. The side of the first connecting structure 404 is connected with the horizontal second communicating part 704 to realize the connection with the horizontal sacrificial layer 182A, and the end of the first connecting structure 404 extends to the substrate 130 to realize the electrical connection between the second conductive layers in the flat plate capacitor after the sacrificial layer 182A is replaced by the second conductive layer. In some embodiments, a deposition process such as CVD, PVD, ALD, etc. can be performed to deposit W and chemical mechanical polishing in the second connecting hole 200 to form the second connecting structure 50.

[0267] Referring back to Figure 72 , the method further includes a step S7206 of replacing the sacrificial layer with the first conductive layer and the second conductive layer located on both sides of the dielectric layer, respectively, wherein one first conductive layer is connected with one second connecting structure, and one second conductive layer is connected with one first connecting structure.

[0268] After the first connecting structure 404 and the second connecting structure 50 are formed, as shown in Figure 56 and Figure 57 , the second sacrificial layer 1404 is removed to re-form the initial gap 2102.

[0269] Further, the initial gap 2102 needs to be reamed. Since the sacrificial layer 182 and the dielectric layer 206 can be insulating layers, the reaming process can be achieved by etching the insulating layer. As shown in Figure 58 , after the etching of the insulating layer is completed, the intermediate gap 1604 is formed, and the sacrificial layer 182 and the third sacrificial layer 184 are exposed.

[0270] As shown in Figure 59 and Figure 60 , the portions of the first sacrificial layer and the third sacrificial layer exposed at the sidewall of the intermediate gap 2104 are removed to form a horizontal trench (not shown in the figure); the first conductive layer 202, the second conductive layer 204 and the gate layer 308 are formed in the horizontal trench through the exposed portions. The first conductive layer 202 is connected with the first electrode 304 through the first communicating part 702 and the second connecting structure 50, and the second conductive layer 204 is connected with the first connecting structure 404 through the second communicating part 704. As shown in Figure 60 , during the formation of the first conductive layer 202 and the second conductive layer 204, the conductive material 220 is formed on the upper surface of the stacked structure.

[0271] In addition, after the first conductive layer 202 and the second conductive layer 204 are formed, the initial stacked structure 180 is constructed into a stacked structure.

[0272] As shown in Figure 59As shown, the method further includes forming a gate dielectric 310, in some embodiments, after removing the third sacrificial layer 1806, exposing the sidewall of the semiconductor body 302, and oxidizing the semiconductor body 302 sidewall to form the gate dielectric 310. The gate dielectric 310 can completely circumscribe the corresponding semiconductor body 302. In some embodiments, a wet oxidation and / or dry oxidation process (e.g., ISSG) is performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 302 (e.g., single crystalline silicon) as the gate dielectric 310. In some embodiments, the gate dielectric 310 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0273] As shown, Figure 61 the conductive material 220 of the stack layer surface is removed.

[0274] In some embodiments, as shown in Figure 62 the method further includes filling the intermediate gap 2104 to form an isolation structure 80. In some embodiments, the isolation structure 80 includes, but is not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Or is a POLY, a conductive metal or a metal compound, such as a W layer or a POLY layer.

[0275] In some embodiments, as shown in Figure 63 after forming the isolation structure 80, to cover the exposed surfaces of the first connection structure 404, the second connection structure 50, and the isolation structure 80, in some embodiments, a dielectric layer 206A can be formed to cover the exposed surfaces of the first connection structure 402, the second connection structure 50, and the isolation structure 80 by various thin film deposition processes such as CVD, PVD, ALD, etc.

[0276] As shown, Figure 64 the method further includes depositing a metal layer 110 on the side of the stack structure away from the transistor as a bonding interface, in some embodiments, the metal layer 110 can serve as a bonding interface for bonding with a second semiconductor structure, the bonding interface can be a layer with a certain thickness, which includes the top surface of the bonding layer of the second semiconductor structure and the bottom surface of the bonding layer of the first semiconductor structure.

[0277] In some embodiments, as shown in Figure 65 and Figure 66 the method further includes removing the substrate 130 from the side of the semiconductor body away from the stack structure, exposing the surface of the semiconductor body 302.

[0278] In some embodiments, at the exposed end of the semiconductor body 302, a second electrode 306 is formed, the second electrode 306 is for connecting with the bit line 100, the second electrode is the other one of the source and the drain of the transistor. As shown in Figure 67 and Figure 68 The exposed upper end of each semiconductor body 302 (i.e., one of the two ends of the semiconductor body 302 away from the carrier substrate 130 in the vertical direction (z direction)) is doped to form the other source / drain, i.e., the second electrode 306. In some implementations, an implantation process and / or a thermal diffusion process is performed to dope P-type dopants or N-type dopants to the exposed upper end of the semiconductor body 302 to form the second electrode 306. In some implementations, a silicide layer is formed on the second electrode 306 by performing a silicidation process at the exposed upper end of the semiconductor body 302. According to some implementations, the vertical transistor 30 with the semiconductor body 302, the source / drain 304 and 306, the gate layer 308, and the gate dielectric 310 is thereby formed, wherein the second electrode 306 is connected with the bit line 100, and the gate layer 308 is connected with the word line 90.

[0279] Continuing as shown in Figure 69 and Figure 70 In some embodiments, the method further includes: forming a second semiconductor structure 120; hybrid bonding the first semiconductor structure 10 and the second semiconductor structure 120. And the first connection structure 404 is led out as a common electrode 1202. In some embodiments, the second semiconductor structure 120 includes a complementary metal-oxide semiconductor 1204, which includes a peripheral circuit. Hybrid bonding (also referred to as "metal / dielectric hybrid bonding") is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)), and can simultaneously obtain metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding. Data transfer between the memory cell array in the second semiconductor structure and the peripheral circuit in the second semiconductor structure 120 can be performed through the interconnections (e.g., bonding contacts) of the metal layer 110.

[0280] A memory system according to one embodiment of the present disclosure includes: a semiconductor device and a controller. The semiconductor device includes: a first semiconductor structure including a stack structure, a transistor, and a first connection structure, the stack structure including first conductive layers and second conductive layers alternately stacked along a first direction, the transistor disposed at one side of the stack structure, the transistor connected with one of the first conductive layers, the first connection structure penetrating through the stack structure along the first direction and connected with the second conductive layers; a bit line and a word line connected with the transistor, respectively; and the controller coupled to the semiconductor device and configured to control the semiconductor device.

[0281] In some embodiments, the stack structure includes multiple layers of the second conductive layer, and the multiple layers of the second conductive layer are connected to the same first connection structure. The first connection structure is a slit structure extending along a third direction perpendicular to the first direction.

[0282] In some embodiments, the first semiconductor structure includes multiple groups of the first connection structure, and the stack structure includes multiple layers of the second conductive layer, each layer of the second conductive layer connecting one group of the first connection structure. The first connection structure is a columnar structure.

[0283] In some embodiments, the stack structure further includes a dielectric layer between the first conductive layer and the second conductive layer.

[0284] The dielectric layer can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0285] In some embodiments, each dielectric layer 108 has a same thickness nominally between about 15 nm and about 30 nm, such as a same thickness between 15 nm and 30 nm (e.g., 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, any range bounded by a lower end of these values, or a range defined in any two of these values).

[0286] In this embodiment, the first conductive layer, the dielectric layer, and the second conductive layer form a planar capacitor for storing charge or data, and the connection structure extending longitudinally through the stack structure has one side of the planar capacitor as a common electrode and the first conductive layer as the other side of the planar capacitor for connecting the transistor.

[0287] In some embodiments, the first semiconductor structure further includes a second connection structure extending through the stack structure along the first direction and connected to the first conductive layer and the transistor, respectively.

[0288] In some embodiments, the first connection structure is a slit structure extending along a third direction perpendicular to the first direction, and the multiple second connection structures form an array structure.

[0289] In some embodiments, the first semiconductor structure includes multiple groups of the first connection structure, and the multiple first connection structures and the second connection structure are arranged alternately along the y direction.

[0290] The second connection structure can be a columnar structure or a plate structure.

[0291] In some embodiments, the stack structure includes a plurality of first conductive layers, each of which is connected to a second connection structure.

[0292] In some embodiments, the stack structure includes a plurality of first conductive layers, each of which is connected to a second connection structure.

[0293] In some embodiments, the stack structure includes a plurality of first conductive layers, each of which is connected to a second connection structure.

[0294] In some embodiments, the stack structure includes a plurality of first conductive layers, each of which is connected to a second connection structure.

[0295] In some embodiments, the stack structure includes a plurality of second conductive layers, each of which is connected to the same first connection structure.

[0296] In some embodiments, the stack structure includes a plurality of first conductive layers, each of which is connected to a second connection structure.

[0297] In some embodiments, the first connection structure is a slit structure extending in a third direction perpendicular to the first direction.

[0298] In some embodiments, the stack structure includes a plurality of first connection structures, and the stack structure includes a plurality of second conductive layers, each of which is connected to a group of first connection structures.

[0299] In some embodiments, the transistor includes a vertical transistor including a semiconductor body extending in a first direction, and a source and a drain disposed at both ends of the semiconductor body in the first direction; one of the source and the drain is connected to the first conductive layer; the other of the source and the drain is connected to the bit line.

[0300] In some embodiments, the vertical transistor further includes a gate in contact with at least one side surface of the semiconductor body, and the word line is connected to the gate in a second direction perpendicular to the first direction.

[0301] In some embodiments, the stack structure further includes: a metal layer disposed on the other side of the stack structure away from the transistor.

[0302] In some embodiments, the method further includes: a second semiconductor structure located on a side of the first semiconductor structure away from the transistor, and the second semiconductor structure and the first semiconductor structure are hybrid-bonded.

[0303] In addition, embodiments of the present application further provide a storage system. The storage system includes at least one semiconductor device according to any of the above embodiments, and a controller electrically connected to the memory, namely, a logic control unit described below, wherein the logic control unit is also connected to an external host, and the external host can transmit user instructions and stored data to the logic control unit. The user instructions may include write instructions, erase instructions, and read instructions, etc. The logic control unit can determine which storage location in the semiconductor device to write, erase, and read based on these contents.

[0304] For example, Figure 73 A block diagram of a storage system provided in an embodiment of the present disclosure. The storage system 7300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 73 As shown in FIG, a storage system 7300 may include a host 7304 and a storage subsystem 7302. The storage subsystem 7302 includes one or more memories 7302A and a controller 7302B. The memory 7302A includes a memory cell array and multiple page buffers. The host 7304 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 7304 may be configured to send data to or receive data from the memory 7302A.

[0305] The semiconductor device of the present disclosure is a memory 7302A, or a portion of the memory 7302A. According to some embodiments, the controller 7302B is coupled to the memory 7302A and the host 7304 and is configured to control the memory. The controller 7302B can manage the data stored in the memory and communicate with the host 7304. In some embodiments, the controller 7302B is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 7302B is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablet computers, laptop computers, etc. and an enterprise storage device. The controller 7302B can be configured to control the operations of the memory 7302A, such as read, erase, and program operations. The controller 7302B may also be configured to manage various functions related to data stored or to be stored in the memory 7302A, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 7302B may also be configured to process error correction code (ECC) for data read from or written to the memory 7302A. The controller 7302B may also perform any other suitable functions, such as formatting the memory 7302A. The controller 7302B may communicate with an external device (e.g., the host 7304) according to a specific communication protocol. For example, the controller 7302B may communicate with the external device using at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, and the like.

[0306] The controller 7302B and one or more memories 7302A can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). In other words, the storage subsystem 7302 can be implemented and packaged into different types of terminal electronic products.

[0307] Figure 74 A schematic diagram of a memory card provided by an embodiment of the present disclosure. Figure 74In one example shown in FIG, a controller 7302B and a single memory 7302A may be integrated into a memory card 7400. The memory card 7400 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 7400 may also include a computer that connects the memory card 7400 to a host (e.g., Figure 74 1008 in the host) coupled to the memory card connector 7402.

[0308] Figure 75 A schematic diagram of a solid-state drive (SSD) provided in an embodiment of the present disclosure. Figure 75 As shown in FIG, a controller 7302B and a plurality of memories 7302A may be integrated into an SSD 7500. The SSD 7500 may also include a processor that connects the SSD 7500 to a host (e.g., Figure 73 In some embodiments, the storage capacity and / or operating speed of 7500 is greater than the storage capacity and / or operating speed of memory card 7400.

[0309] It should be noted that the memory structure described above is merely an exemplary structure, and other types of memories, or memories with other structures, are also applicable to the operating method of this application.

[0310] The above description of specific embodiments will fully demonstrate the general nature of the present disclosure, so that others can easily modify and / or adjust such specific embodiments for various applications by applying knowledge within the technical scope of the art without undue experimentation and without departing from the general concepts of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for illustrative purposes only and not for limiting purposes, and thus the terms or wording of this specification will be interpreted by the skilled person in accordance with the teachings and guidance.

[0311] The embodiments of the present disclosure have been described above with the aid of functional building blocks, which illustrate implementation methods for specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for the purpose of convenience of description. Alternative boundaries can be defined as long as the specified functions and their relationships are appropriately performed.

[0312] The Summary and Abstract sections can set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0313] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: The invention comprises a first semiconductor structure comprising: A stacked structure and a transistor, wherein the stacked structure includes first conductive layers and second conductive layers alternately stacked along a first direction, the transistor is disposed on one side of the stacked structure, and the transistor is connected to one of the first conductive layers; The first connecting structure penetrates the stacking structure along the first direction and is connected to the second conductive layer.

2. The semiconductor device according to claim 1, wherein The stacking structure further includes: A dielectric layer is located between the first conductive layer and the second conductive layer.

3. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes: The second connecting structure penetrates the stack structure along the first direction and is respectively connected to the first conductive layer and the transistor.

4. The semiconductor device according to claim 3, wherein The stacking structure further includes: The first insulating layer is arranged between the second connecting structure and the second conductive layer.

5. The semiconductor device according to claim 3, wherein The stacked structure includes multiple layers of the first conductive layer, and each layer of the first conductive layer is connected to the second connection structure.

6. The semiconductor device according to claim 3, wherein It includes a plurality of groups of the second connection structures, and each group of the second connection structures is respectively connected to one layer of the first conductive layer.

7. The semiconductor device according to claim 3, wherein A plurality of groups of the second connection structures are arranged side by side along a second direction perpendicular to the first direction.

8. The semiconductor device according to claim 3, wherein The stacking structure further includes: A first connecting portion is provided between the second connecting structure and one layer of the first conductive layer.

9. The semiconductor device according to claim 3, wherein The stacking structure further includes: The second insulating layer is arranged between the isolated second connecting structure and one layer of the first conductive layer.

10. The semiconductor device according to claim 3, wherein The second connection structure is a columnar structure.

11. The semiconductor device according to claim 1, wherein The stacking structure further includes: A third insulating layer is provided between the first connecting structure and the first conductive layer.

12. The semiconductor device according to claim 1, wherein The stacked structure includes a plurality of second conductive layers, and the plurality of second conductive layers are connected to the same first connection structure.

13. The semiconductor device according to claim 12, wherein: The first connection structure is a gap structure extending along a third direction perpendicular to the first direction.

14. The semiconductor device according to claim 1, wherein The stacked structure includes a plurality of groups of the first connection structures, and the stacked structure includes a plurality of layers of the second conductive layers, each layer of the second conductive layer is connected to a group of the first connection structures.

15. The semiconductor device according to claim 14, wherein: The stacking structure further includes: The second connecting portion is provided between a group of the first connecting structures and a layer of the second conductive layer.

16. The semiconductor device according to claim 15, wherein: The stacking structure further includes: A fourth isolation layer is provided between the isolated group of the first connection structures and a layer of the second conductive layer.

17. The semiconductor device according to claim 14, wherein: A plurality of groups of the first connection structures are arranged side by side along a second direction perpendicular to the first direction.

18. The semiconductor device according to claim 14, wherein: The first connection structure is a columnar structure.

19. The semiconductor device according to claim 14, wherein The first semiconductor structure further includes: The isolation structure penetrates the stack structure along the first direction and extends along a third direction perpendicular to the first direction.

20. The semiconductor device according to claim 1, wherein The transistor includes a vertical transistor including a semiconductor body extending along the first direction and a gate layer contacting at least one side surface of the semiconductor body.

21. The semiconductor device according to claim 20, wherein: The vertical transistor further includes a source and a drain disposed at both ends of the semiconductor body in the first direction; One of the source electrode and the drain electrode is connected to one of the first conductive layers.

22. The semiconductor device according to claim 21, wherein Also includes: a word line connected to the gate layer; A bit line is connected to the other of the source and the drain.

23. The semiconductor device according to claim 1, wherein Also includes: The metal layer is disposed on the other side of the stack structure away from the transistor.

24. The semiconductor device according to claim 1, wherein Also includes: The second semiconductor structure is located on a side of the first semiconductor structure away from the transistor, and the second semiconductor structure and the first semiconductor structure are hybrid-bonded.

25. A method for forming a semiconductor device, characterized in that: include: forming a first semiconductor structure, comprising: forming a semiconductor body and a stacked structure of a transistor, the stacked structure comprising a first sacrificial layer, a dielectric layer, a second conductive layer, and the dielectric layer alternately stacked along a first direction; forming a first electrode on the semiconductor body, the first electrode being one of a source and a drain of the transistor; Replacing the first sacrificial layer with a first conductive layer, wherein the first conductive layer is connected to the first electrode; A first connecting structure is formed, which is connected to the second conductive layer and penetrates the stacked structure.

26. The method according to claim 25, characterized in that forming a first electrode on the semiconductor body, further comprising: forming a connection hole extending through the stack structure to the semiconductor body along the first direction; forming a first insulating layer and a second insulating layer in the inner wall of the connecting hole, wherein the first insulating layer isolates the second conductive layer, and the second insulating layer isolates the first sacrificial layer which has no connection relationship; A second connection structure connected to one of the first sacrificial layers and the first electrode is formed in the connection hole.

27. The method according to claim 26, characterized in that forming a connection hole extending through the stack structure and extending to the semiconductor body along the first direction, further comprising: An initial gap is formed along the first direction and penetrates the stack structure.

28. The method according to claim 27, characterized in that Before forming a second connection structure connected to one of the first sacrificial layers and the first electrode in the connection hole, the method further includes: A second sacrificial layer is deposited in the connection hole and the initial gap.

29. The method according to claim 28, characterized in that A second connection structure connected to one of the first sacrificial layers and the first electrode is formed in the connection hole, comprising: The second sacrificial layer deposited in the connection hole is removed, and the connection hole is filled to form the second connection structure.

30. The method according to claim 28, wherein The semiconductor body and stack structure forming the transistor also include: A third sacrificial layer is formed in contact with the semiconductor body in a second direction perpendicular to the first direction.

31. The method according to claim 30, wherein Also includes: removing the second sacrificial layer within the initial gap; Etching an inner wall of the initial gap to form a middle gap exposing the first sacrificial layer and the third sacrificial layer; Replacing the first sacrificial layer with a first conductive layer also includes: replacing the third sacrificial layer with a gate layer.

32. The method according to claim 25, wherein Also includes: removing the substrate on a side of the semiconductor body away from the stack structure to expose the semiconductor body; A second electrode is formed at the exposed end portion of the semiconductor body. The second electrode is used to be connected to a bit line. The second electrode is the other of the source and the drain of the transistor.

33. The method according to claim 26, wherein The stack structure has a first layer on a side away from the semiconductor body and a second layer on a side close to the semiconductor body, and a connection hole is formed along the first direction through the stack structure and extends to the semiconductor body, including: forming a plurality of groups of first sub-holes extending through the first layer along the first direction, wherein one group of the first sub-holes resides on a layer of the first sacrificial layer; Depositing a conductive material on the bottom of the first sub-hole to form a first connecting portion in contact with the first sacrificial layer; A second sub-hole is formed through the first connecting portion, extending along the first direction and passing through the second layer. The first sub-hole and the second sub-hole are connected to form the connecting hole.

34. The method according to claim 33, wherein Forming a first insulating layer and a second insulating layer in the inner wall of the connecting hole, comprising: forming a first groove at a first inner wall in the connecting hole, depositing a second insulating layer in the first groove to isolate the first sacrificial layer, wherein the first inner wall is located on the first sacrificial layer not connected to the first connecting portion; A second groove is formed at the second inner wall in the connecting hole, the first isolation layer is deposited in the second groove to isolate the second conductive layer, and the second inner wall is located in the second conductive layer.

35. The method according to claim 31, wherein Also includes: forming a third groove at a third inner wall in the middle gap, depositing a third insulating layer for isolating the first conductive layer in the third groove, and correspondingly forming a target gap, wherein the third inner wall is located in the first conductive layer; Forming a first connection structure connected to the second conductive layer and penetrating the stacked structure includes: filling the target gap to form the first connection structure.

36. The method according to any one of claims 25 to 35, characterized in that Also includes: A metal layer is deposited on a side of the stack structure away from the transistor.

37. The method according to any one of claims 25 to 35, characterized in that Also includes: forming a second semiconductor structure; The first semiconductor structure and the second semiconductor structure are hybrid-bonded.

38. A storage system, characterized in that: include: A semiconductor device and a controller, wherein the semiconductor device comprises: a first semiconductor structure including a stacked structure, a transistor, and a first connecting structure, wherein the stacked structure includes first and second conductive layers alternately stacked along a first direction, the transistor being disposed on one side of the stacked structure and connected to one of the first conductive layers, and the first connecting structure penetrating the stacked structure along the first direction and connected to the second conductive layer; A bit line and a word line are connected to the transistors respectively; The controller is coupled to the semiconductor device and is configured to control the semiconductor device.

39. The storage system according to claim 38, wherein: The stacking structure further includes: A dielectric layer is located between the first conductive layer and the second conductive layer.

40. The storage system according to claim 38, wherein: The first semiconductor structure further includes: The second connecting structure penetrates the stack structure along the first direction and is respectively connected to the first conductive layer and the transistor.

41. The storage system according to claim 40, wherein: The stacked structure includes multiple layers of the first conductive layer, and each layer of the first conductive layer is connected to the second connection structure.

42. The storage system according to claim 40, wherein: It includes a plurality of groups of the second connection structures, and each group of the second connection structures is respectively connected to one layer of the first conductive layer.

43. The storage system according to claim 38, wherein: The stacked structure includes a plurality of second conductive layers, and the plurality of second conductive layers are connected to the same first connection structure.

44. The storage system according to claim 43, wherein: The first connection structure is a gap structure extending along a third direction perpendicular to the first direction.

45. The storage system according to claim 38, wherein: The stacked structure includes a plurality of groups of the first connection structures, and the stacked structure includes a plurality of layers of the second conductive layers, each layer of the second conductive layer is connected to a group of the first connection structures.

46. ​​The storage system according to claim 38, wherein: The transistor includes a vertical transistor including a semiconductor body extending along the first direction and a gate layer contacting at least one side surface of the semiconductor body, the gate layer being connected to the word line.

47. The storage system according to claim 46, wherein: The vertical transistor further includes a source and a drain disposed at both ends of the semiconductor body in the first direction; One of the source electrode and the drain electrode is connected to one of the first conductive layers; The other of the source and the drain is connected to the bit line.

48. The storage system according to claim 38, wherein: Also includes: The metal layer is disposed on the other side of the stack structure away from the transistor.

49. The storage system according to claim 38, wherein: Also includes: The second semiconductor structure is located on a side of the first semiconductor structure away from the transistor, and the second semiconductor structure and the first semiconductor structure are hybrid-bonded.

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