Semiconductor device with vertical body contact and method of manufacturing same

Abstract

Methods, apparatus, and systems related to memory devices having transistor body contacts extending vertically across stacked circuit layers and connected to body portions of data access transistors are described. A memory device may include memory cells and corresponding access circuitry on each of the stacked layers. When the data access transistor is turned off, the vertically extending transistor body contact may provide routing for leakage away from the data storage circuit.

Description

TECHNICAL FIELD

[0001] The disclosed embodiments relate to devices, and in particular, to semiconductor devices having vertical body contacts and methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices can include one or more circuits fabricated in or embedded in a semiconductor material, such as combinations of connected transistors, capacitors, and other like circuit components. Some examples of semiconductor devices can include semiconductor dies, packages, systems-on-a-chip, circuit cards, or the like, that include semiconductor-based circuitry. Such semiconductor devices can be configured for various functions, such as for a processor or a memory device (e.g., a volatile memory device, a non-volatile memory device, or a combination device).

[0003] As technology advances and applications increase, the market continues to seek faster, more efficient, and smaller devices. To meet market demands, semiconductor devices are being pushed to the limit through various improvements. Generally, improving a device can include increasing circuit density, reducing circuit footprint, increasing operating speed or otherwise reducing run-time latency, increasing reliability, reducing power consumption, or reducing manufacturing costs, among other metrics. For example, three-dimensional (3D) architectures are being investigated for semiconductor device design. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 is a block diagram of an apparatus in accordance with embodiments of the present technology.

[0005] Figure 2 is a perspective cutaway view of an example 3D semiconductor device having vertical body contacts in accordance with embodiments of the present technology.

[0006] Figure 3 is a perspective view of an example circuit cell within a 3D semiconductor device in accordance with embodiments of the present technology. Figure 2

[0007] Figure 4 is a top view of a first example arrangement of adjacent circuit cells in accordance with embodiments of the present technology.

[0008] Figure 5 is a top view of a second example arrangement of adjacent circuit cells in accordance with embodiments of the present technology.

[0009] Figures 6 to 18 is an example stage of manufacturing an example 3D semiconductor device in accordance with embodiments of the present technology.

[0010] Figures 19A to 19C is an illustration of various details regarding a first example 3D semiconductor device in accordance with embodiments of the present technology.

[0011] Figure 20A ​and Figure 20B is an illustration of an adjusted example stage for fabricating a second example 3D semiconductor device according to embodiments of the present technology.

[0012] Figure 21 is a schematic illustration of an example aspect of a 3D semiconductor device according to embodiments of the present technology.

[0013] Figure 22 is a flowchart illustrating an example method of fabricating a semiconductor device having a vertically extending body contact according to embodiments of the present technology.

[0014] Figure 23 is a schematic illustration of a system incorporating a semiconductor device according to embodiments of the present technology. DETAILED DESCRIPTION

[0015] As described in greater detail below, the technology disclosed herein relates to semiconductor devices having vertically extending body contacts, such as memory systems, systems having memory devices, and related methods.

[0016] In some embodiments, a semiconductor device can have a 3D architecture that includes transistors arranged in overlapping or stacked layers. To improve control over current flow, the transistors in the 3D architecture can have a gate-all-around (GAA) thin-film transistor (TFT) structure. The GAA structure can have the gate surround three or more faces of a channel at which current flows.

[0017] Using a memory device (e.g., random access memory (RAM)) as an illustrative example, transistors configured to control access (e.g., read, write, or both) to each memory cell can have a GAA TFT structure. In some embodiments, each memory cell can be connected to a corresponding digit line (DL) across a laterally extending semiconductor substrate. A structure of word lines (WLs) can be disposed between and around the semiconductor substrate. The memory device can include a vertically extending body contact that contacts the semiconductor substrate at a location across the WLs from the memory cells and closer to the DLs. Thus, in the 3D architecture, the vertically extending body contact can be connected to the semiconductor substrate and to corresponding memory access circuitry that is arranged or aligned on multiple layers and along columns.

[0018] The vertically extending body contact can provide reduced floating body effects that degrade retention of the memory cells. Moreover, the vertically extending body contact can improve current flow (e.g., “on” current or I on ) through the memory access circuitry while improving I on by allowing higher doping of the digital junction and by removing (e.g., placing adjacent to) the body contact from the path of I off .

[0019] Figure 1 is a block diagram of a device 100 (e.g., a semiconductor die assembly, including a three-dimensional integrated (3DI) device or a die stack package) in accordance with an embodiment of the present technology. For example, the device 100 can include a DRAM or a portion thereof including one or more dies / chips.

[0020] The device 100 can include a memory cell array, such as the memory array 150. The memory array 150 can include a plurality of memory banks (e.g., memory banks 0-15), and each memory bank can include a plurality of WLs, a plurality of DLs, and a plurality of memory cells arranged at intersections of word lines and bit lines. The memory cells can include any of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, or the like. Details regarding the structure of the WLs, DLs, and memory cells are described below.

[0021] Selection of the word lines WL can be performed by the row decoder 140, and selection of the digit lines DL can be performed by the column decoder 145. Sensing amplifiers (SAMPs) can be provided for the coupled digit lines DL and connected to at least one respective pair of local I / O lines (LIOT / B), which in turn can be coupled to at least one respective pair of main I / O lines (MIOT / B) via transfer gates (TGs) that can act as switches. The sensing amplifiers and transfer gates can operate based on control signals from decoder circuitry, which can include the command decoder 115, the row decoder 140, the column decoder 145, any control circuitry of the memory array 150, or any combination thereof. The memory array 150 can also include plate lines and related circuitry for managing its operation.

[0022] The device 100 can employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus to receive command signals (CMD) and address signals (ADDR). The device 100 can further include a chip select terminal to receive a chip select signal (CS), clock terminals to receive clock signals CK and CKF, data clock terminals to receive data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, DMI, power supply terminals VDD, VSS, and VDDQ.

[0023] The command terminals and the address terminals can be externally supplied with address signals and bank address signals (BA) to select a bank of the memory array 150. The command terminals can be externally supplied with command signals (CMD) to select a command to be performed by the device 100. The command signals can include a row command (RCMD) to select a row of the memory array 150, a column command (CCMD) to select a column of the memory array 150, a read command (READ) to read data from the memory array 150, a write command (WRITE) to write data to the memory array 150, a refresh command (REF) to refresh the memory array 150, and the like. Figure 1The address signals and bank address signals supplied to the address terminals can be transferred to the address decoder 110 via command / address (CA) input circuitry 105. The address decoder 110 can receive the address signals and supply a decoded row address signal (XADD) to the row decoder 140 and a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the bank address signals and supply the bank address signals to both the row decoder 140 and the column decoder 145.

[0024] The command and address terminals can be supplied with command signals (CMD), address signals (ADDR), and chip select signals (CS) from a memory controller and / or a malicious chipset. The command signals can represent various memory commands from the memory controller, including access commands, which can include read commands and write commands. The chip select signals can be used to select the device 100 to respond to the commands and addresses provided to the command and address terminals. When an active chip select signal is provided to the device 100, the commands and addresses can be decoded and memory operations can be performed. The command signals can be provided to the command decoder 115 as internal command signals ICMD via the command / address input circuitry 105. The command decoder 115 can include circuitry to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals to select word lines and column command signals to select bit lines. The command decoder 115 can further include one or more registers to track various counts or values, such as counts of refresh commands received by the device 100 or self-refresh operations performed by the device 100.

[0025] Read data can be read from memory cells in the memory array 150 designated by a row address (e.g., an address provided with an active command) and a column address (e.g., an address provided with a read). The read command can be received by the command decoder 115, which can provide internal commands to the input / output circuitry 160 so that read data can be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifiers 155 and the input / output circuitry 160 according to the RDQS clock signal. The read data can be provided at a time defined by read latency information RL, which can be programmed in the device 100, such as in a mode register (not shown). The read latency information RL can be defined in terms of clock cycles of the CK clock signal. For example, the read latency information RL can be a number of clock cycles of the CK signal when the associated read data is provided after a read command is received by the device 100. Figure 1

[0026] ​Write data can be supplied to data terminals DQ, DBI, and DMI based on the WCK and WCKF clock signals. A write command can be received by command decoder 115, which can provide an internal command to input / output circuit 160 so that the write data can be received by a data receiver in input / output circuit 160 and supplied to memory array 150 via input / output circuit 160 and read / write amplifier 155. The write data can be written to the memory cells specified by the row address and column address. The write data can be supplied to the data terminals at a time defined by write delay information WL. The write delay information WL can be programmed in device 100, for example, in a mode register. The write delay information WL can be defined based on clock cycles of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by device 100 when the associated write data is received.

[0027] The power supply terminal can be supplied with a power supply potential V DD and V SS These power supply potentials V DD and V SS The internal voltage generator circuit 170 can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can be based on the power supply potential V DD and V SS Generate various internal potentials V PP 、V OD 、V ARY 、V PERI And similar. Internal potential V PP Can be used in row decoder 140, internal potential V OD and V ARY can be used in a sense amplifier included in the memory array 150, and the internal potential V PERI Can be used in many other circuit blocks.

[0028] The power supply terminal may also be supplied with a power supply potential V DDQ . Power supply potential V DDQ It can be supplied to the input / output circuit 160 together with the power supply potential VSS. In one embodiment of the present technology, the power supply potential V DDQ can be connected to the power supply potential V SS In another embodiment of the present technology, the power supply potential V DDQ can be connected to the power supply potential V DD However, the dedicated power supply potential V DDQ It can be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0029] Clock terminals and data clock terminals can be supplied with external clock signals and complementary external clock signals. External clock signals CK, CKF, WCK, WCKF can be supplied to clock input circuitry 120. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and transition between opposite clock levels at the same time. For example, when a clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Further, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0030] Input buffers included in clock input circuitry 120 can receive external clock signals. For example, an input buffer can receive a clock / enable signal when enabled by a clock / enable signal from command decoder 115. Clock input circuitry 120 can receive external clock signals to generate an internal clock signal ICLK. Internal clock signal ICLK can be supplied to internal clock circuitry 130. Internal clock circuitry 130 can provide various phase and frequency controlled internal clock signals based on the received internal clock signal ICLK and clock enable signals from command / address input circuitry 105 (not shown in FIG. 1). For example, internal clock circuitry 130 can include clock paths (not shown in FIG. 1) that receive internal clock signal ICLK and provide various clock signals to command decoder 115. Internal clock circuitry 130 can further provide an input / output (IO) clock signal. The IO clock signal can be supplied to input / output circuitry 160 and can be used as a timing signal for determining output timing of read data and / or input timing of write data. The IO clock signal can be provided at multiple clock frequencies so that data can be output from and input to device 100 at different data rates. Higher clock frequencies can be desired when high memory speeds are needed. Lower clock frequencies can be desired when lower power consumption is needed. Internal clock signal ICLK can also be supplied to internal clock circuitry 130 and thus various internal clock signals can be generated. Figure 1 Figure 1

[0031] ​​Device 100 can be connected to any of a number of electronic devices or components thereof capable of utilizing memory to temporarily or persistently store information. For example, a host device of device 100 can be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device can be directly connected to device 100; but in other embodiments, the host device can be indirectly connected to the memory device (e.g., through a networked connection or through an intermediary device).

[0032] Figure 2 is an example 3D semiconductor device 200 having vertical body contacts 202 according to embodiments of the present technology (e.g., Figure 1 a perspective cutaway view of device 100 or a portion thereof, e.g., Figure 1 memory array 150 of FIG. 1) according to embodiments of the present technology. Vertical body contacts 202 can include electrical connections for body portions of one or more transistors. For example, device 200 can have an electrical circuit including transistors arranged in stacked layers 204. One or more of the transistors in each layer, or portions thereof, can be located at matching locations, thereby having the transistors arranged along columns across the stacked layers. This organization can be utilized to have vertical body contacts 202 provide electrical body connections to the transistors along the columns.

[0033] Using device 100 as an example, each of circuit layers 204 can include one or more data storage devices 212 (e.g., capacitors or similar circuitry) each connected to access circuitry 214. Each of storage devices 212 can include memory cells configured to have a variety of states (e.g., charge storage, magnetic, or resistive states, or similar) representing stored data (e.g., '0', '1', or combinations thereof). Access devices 214 can include circuitry, such as transistors, configured to set and / or read the states of connected storage devices 212.

[0034] The memory devices 212 may be arranged (1) laterally across the layers, (2) vertically across the layers (e.g., along one or more columns), or a combination thereof. Accordingly, the access devices 214 may be arranged both laterally and vertically (e.g., along columns). For one or more such columns, the device 200 may include a vertical body contact 202 that extends across the layers and connects the vertically aligned access devices 214 to provide a transistor body connection. For example, the vertical body contact 202 may contact the semiconductor substrate or body across the WL at a location opposite or distal to the connected memory cells. In other words, the vertical body contact 202 and DL may be on one side of the WL and the memory cells may be on the opposite side of the WL.

[0035] To facilitate electrical body connection, the body contact 202 may comprise a conductive or semiconductive material, such as P- / P+ polysilicon, silicon, silicon germanium (SiGe), a metal material, and / or the like. In some embodiments, the body contact 202 may comprise a combination of materials (e.g., semiconductive polysilicon and a metal material). For example, the body contact may comprise a P+ polysilicon liner followed by a conductive metal material, thereby reducing the resistance of the body contact 202.

[0036] To further describe the vertical body contact 202, Figure 3 According to an embodiment of the present technology Figure 2 2 is a perspective view of an example circuit cell 300 within the 3D semiconductor device 200. The cell 300 may represent one example of a storage circuit 212 (eg, a memory cell) and an associated or connected example of an access circuit 214.

[0037] The access circuit 214 may include a plurality of interconnects between the storage circuit 212 and the connection DL 304 along a lateral direction (eg, along Figure 2 2. The access circuit 214 may further include a WL structure 306 located between the storage circuit 212 and the DL 304. The WL structure 306 may be a double-sided, three-sided, or four-sided GAA structure. Alternatively, the WL structure 306 may be a single-sided structure, such as other transistor architectures. The access circuit 214 may include a transistor having the WL structure 306 coupled to or used as a control or gate terminal, the DL 304 coupled to a first end terminal (e.g., one of a source or a drain), and the storage circuit 212 coupled to a second end terminal (e.g., the remaining source or drain complementary to the first end terminal).

[0038] The body 302 can generally be neutral or not specifically doped except at and near various connections. In some embodiments, the body 302 can have a matching doping type (e.g., n-type) at locations that contact the access circuit 214 and the DL 304. The doping can be attenuated (e.g., have a gradient pattern for the doping state) away from the connection contacts and remain generally neutral between the contacts. For example, the portion of the body 302 that overlaps the WL structure 306 can be neutral. Thus, the access circuit 214 can effectively be a transistor with (1) the WL structure 306 coupled to or functioning as the gate of the transistor and (2) the storage circuit 212 and the DL 304 coupled to the source and drain of the transistor. Thus, upon activation of the WL through structure 306, the body 302 can facilitate creating a channel between the storage circuit 212 and the DL 304.

[0039] As described above, each circuit cell 300 can be connected to the vertical body contact 202 with the access circuit 214 and the DL 304. The vertical body contact 202 can be connected to the body 302 at a location opposite the access circuit 214 across the WL structure 306. In other words, the circuit cell 300 can have the storage circuit 212 on one side of the WL architecture 306 and the DL 304 and the vertical body contact 202 at the opposite side of the WL architecture 306. The body 302 at or near the vertical body contact 202 can be oppositely doped (e.g., p-type) from the portion at or near the DL 304. Thus, the vertical body contact 202 can prevent a floating state of the body 302 and provide a path away from the storage circuit 212 for leakage from the DL 304, e.g., when the WL is inactive / off. In contrast, other conventional devices with floating bodies can experience a reduction in data retention as leakage current has no other path but to flow from / flow to the connected data cell. As such, the vertical body contact 202 can provide at least an increase in data retention capacity, a reduction in data error rate, and a reduction in refresh rate and related power consumption.

[0040] Figure 4 is a top view of a first example arrangement 400 of adjacent circuit cells (e.g., Figure 3 of the circuit cell 300) of the first arrangement 400. For the first arrangement 400, each circuit cell can have at least one instance of the vertical body contact 202. For example, the first circuit cell 300a can have the vertical body contact 202 along the left side of the WL structure 306. The second circuit cell 300b can have the vertical body contact 202 along the right side of the WL structure 306. The third circuit cell 300c can have the vertical body contact 202 along the bottom side of the WL structure 306. The fourth circuit cell 300d can have the vertical body contact 202 along the top side of the WL structure 306. Figure 2202a, and the second circuit unit 300b is adjacent to the first circuit unit 300a. The first circuit unit 300a may include (1) a first storage circuit 212a configured to store one bit in a given storage word, and (2) a first DL 304a configured to access data at the first storage circuit 212a. Similarly, the second circuit 300b may include a second storage circuit 212b and a second DL 304b configured to store different / adjacent bits of the stored word. Each of the first and second units may include separate body contacts. In other words, the first circuit unit 300a may include a first body contact 202a, and the second circuit unit 300b may include a second body contact 202b separate from the first body contact 202a.

[0041] In some embodiments, the vertical body contact 202 may be Figure 3 The DL 304 of each circuit cell can be attached between the WL structure 306 and the vertical body contact 202, for example, at an end of the body 302 opposite the storage circuit 212. In other words, the body 202 can have a length with the storage circuit 212 attached to one end of the length and the vertical body contact 202 attached to the other end of the length. Figure 4 Thus, the vertical body contact 202 can be positioned relatively closer to the DL 304 to remove leakage while remaining out of the channel between the DL 304 and the storage circuit 212.

[0042] Additionally, a deliberately placed dielectric film 203 may be disposed between the vertical body contact 202 and the body 302. The dielectric film 203 may have a thickness (e.g., measured parallel to the length of the body 302 and the direction of current flow) that is controlled to enable hole conduction while inhibiting dopant diffusion (e.g., from the P-type contact region into the channel or body). In other words, the dielectric film 203 may have a thickness that is less than a predetermined threshold (e.g., 5, 10, or more times less than the dimension of the body 302 measured along a parallel direction), which is sufficient to block the movement / diffusion of dopants but not sufficient to block the movement of electrical holes.

[0043] Figure 5 is an adjacent circuit unit (e.g., Figure 3 For the second configuration 500, each vertical body contact 202 can be shared by two or more instances of a circuit unit 300. For example, the first circuit unit 300 a1 May include a first storage circuit 212 a1 and the first DL 304 a1 , and the second circuit unit 300 a2The second storage circuit 212 a2 and the second DL 212 a2 The first circuit unit 300 a1 and the second circuit unit 300 a2 may be connected to the first shared body contact 202a. Based on the shared connection with the first shared body contact 202a, the first circuit unit 300 a1 and the second circuit unit 300 a2 may belong to a first unit grouping 300a. The first unit grouping 300a can be adjacent to a second unit grouping 300b that similarly includes a second set of circuit units 300 b1 and 300 b2 .

[0044] In some embodiments, a common body contact (e.g., common body contacts 202a and 202b) can be located between the lengths of connected or included circuit units. Using the first unit grouping 300a as an example, the first common body contact 202a can be located between the first circuit unit 300 a1 and the second circuit unit 300 a2 , and contact a mirror or facing example of a side peripheral edge or sidewall of the body. The first unit grouping 300a can be connected between the WL structure and the DL. For such an arrangement, the current carrying capability of the vertical body contact 202 (via, for example, contact size or dimensions, size of the body contact structure, distance between the body contact and the WL, channel width compared to body width, or other similar physical parameters) can be controlled to reduce the impact of the vertical body contact 202 on the current channel.

[0045] As described above, a dielectric film 203 can be disposed between the vertical body contact 202 and the body 302. For the second example arrangement 500, the thickness of the dielectric film 203 can be measured in a direction parallel to the length of the body 302 extending between two adjacent channels. The dielectric film 203 can have a thickness configured to enable hole conduction while inhibiting dopant diffusion.

[0046] In other embodiments, the vertical body contact 202 can be located at one end of the length, similar to the unit 300 of Figure 3 , and electrically or physically connected to multiple circuit units. For example, Figure 4 The body contacts 202a and 202b of may be replaced by a single integrated structure connected to the substrates of the circuit units 300a and 300b.

[0047] Figures 6 to 18 is an example stage of manufacturing a 3D semiconductor device according to an embodiment of the present technology. For example, Figures 6 to 18Aspects of the processes described in the middle can be used to manufacture Figure 4 a first example arrangement 400, Figure 5 a second example arrangement 500 and / or other similar devices that include shared body contacts.

[0048] Figure 6 is a perspective view of a portion of a structure 600 associated with (e.g., derived from) a stack deposition phase (e.g., for depositing silicon (Si) and / or SiGe). The structure 600 can further include one or more hard masks for patterning or etching purposes. The structure 600 can further include a foundation having individual layers of semiconductor material (e.g., Si and / or SiGe) surrounded by portions of mask / insulating material, e.g., on top and bottom faces of a planar semiconductor material.

[0049] Figure 7 is a perspective view of a portion of a structure 700 associated with a patterning phase, e.g., for forming deep trench isolation (DTI) and / or dielectric fill. Oxide material can be deposited or formed in one or more of the patterned recesses (e.g., within the DTI). Thus, the structure 700 can include a foundation for separating adjacent circuitry within each layer and for providing one or more vertical connections that extend through the layers.

[0050] Figure 8 is a perspective view of a portion of a structure 800 associated with a phase for further trench patterning and etching, e.g., to prepare for forming WL-related structures. In other words, the structure 800 can include one or more WL-forming trenches 802 formed according to related patterning and etching (using, e.g., chemical, light or laser or the like) sub-phases. The WL-forming trenches 802 can be vertical and extend through / across the layers, thereby allowing portions of each layer to be laterally accessible and shaped. The WL-forming trenches 802 can expose one side of the dielectric fill.

[0051] Figure 9 is a perspective view of a portion of a structure 900 associated with a phase for digging out portions of semiconductor material (e.g., Si and / or SiGe) from one or more of the layers. The semiconductor structures 902 can be formed by removing insulating material and exposing portions of semiconductor material of Figure 8 Thus, the structure 900 can have cavities intended to house storage circuitry 212 of Figure 2 and / or access circuitry 214 of Figure 2 Removing the semiconductor material can expose additional (e.g., peripheral) portions of the dielectric fill. In some embodiments, the exposed semiconductor structures 902 can be further shaped, e.g., to control or adjust thicknesses of one or more of the semiconductor structures 902.

[0052] Figure 10is a perspective view of a portion of structure 1000 associated with an oxide stamp etch phase. For example, after removing exposed portions of the dielectric fill, structure 1000 can correspond to Figure 9 structure 900. Thus, the cavities therein can be further enlarged.

[0053] Figure 11 is a perspective view of a portion of structure 1100 associated with a phase for forming insulating material 1102, such as silicon nitride (SiN). Insulating material 1102 can be formed or deposited into exposed surfaces and / or cavities of semiconductor structures 902. Additionally, an oxide layer 1104 can be formed or deposited over exposed portions of insulating material 1102. Thus, laterally extending portions of semiconductor material 900 can provide a foundation for forming Figure 2 a body 302 of access circuit 214. Figure 3

[0054] Figure 12 is a perspective view of a portion of structure 1200 associated with a phase for etching away portions of oxide layer 1104 of Figure 11 structure 900. Structure 1200 can have oxide boundaries 1202 at end portions of each semiconductor structure 902. Based on the etching, top and bottom faces of semiconductor structures 902 can be exposed. Insulating material 1204 remaining at a height between semiconductor structures 902 can be associated with boundaries of layers above and below insulating material 904. In some embodiments, insulating material 1204 can be reshaped or recessed such that semiconductor structures 902 laterally extend beyond peripheral edges of insulating material 904 at or near where WLs form trenches 802.

[0055] Figure 13 is a perspective view of a portion of structure 1300 associated with a phase for initially forming one or more portions of access circuit 214. For example, structure 1300 can include gate oxide and metal deposits 1302 that effectively provide a foundation for Figure 3 WL structures 306 of structure 900.

[0056] Figure 14 is a perspective view of a portion of structure 1400 associated with a phase for forming gate or WL portions of access circuit 214. Structure 1400 can include WL structures 306 that result from removing portions of metal deposits 1302 of Figure 13 structure 900. Remaining portions of metal deposits 1302 and / or reshaping results thereof can represent or act as WL structures 306. Based on the shape of the cavities and the etching process, resulting WL structures 306 can face or overlap semiconductor structures 902 of structure 900 on one, two, three, or four surfaces. Figure 12

[0057] Figure 15 ​​is a perspective view of a portion of structure 1500 associated with a stage for filling and shaping semiconductor portions. For example, structure 1500 can be formed by filling cavities (e.g., resulting from removal of portions of metal deposit 1302) of structure 1400 with oxide or other insulating material (e.g., SiN) Figure 14 . The deposited material can be etched or shaped to expose semiconductor structures 902 at or around WL formation trenches 802. In other words, semiconductor structures 902 can extend beyond the peripheral edges of the insulating material and into WL formation trenches 802. Figure 13

[0058] Figure 16 is a perspective view of a portion of structure 1600 associated with a stage for forming one or more body contact nodes 1602. For example, structure 1600 can be a result of filling WL formation trenches 802 with doped semiconductor material, e.g., by depositing P+ polysilicon material. Thus, body contact nodes 1602 can represent or include vertical body contacts 202 of structure 1400, and extend in a vertical direction and across multiple layers. Vertical body contacts 202 can directly contact semiconductor structures 902 at one end of WL structures 306 of structure 1400, Figure 15 Figure 2 Figure 15 Figure 12 Figure 2 Figure 15

[0059] Figure 17 is a perspective view of a portion of structure 1700 associated with a stage for forming DL contact vias 1702. DL contact vias 1702 can extend in a vertical direction and across / through various layers. DL contact vias 1702 can be formed using chemical or light-based agents that etch away material across / through layers. DL contact vias 1702 can be formed using chemical or light-based agents that etch away material across / through layers. In a lateral direction, DL contact vias 1702 can be located between WL structures 306 and vertical body contacts 202 of structure 1400. Furthermore, DL contact vias 1702 can be located at sidewalls of each of semiconductor structures 902 of structure 1400. Figure 16 Figure 15

[0060] Figure 18 is a perspective view of a portion of structure 1800 associated with a stage for forming DL contact nodes 1802. For example, structure 1800 can be a result of filling DL contact vias 1702 with doped semiconductor material, e.g., by depositing P+ polysilicon material. Thus, DL contact nodes 1802 can represent or include vertical DL contacts 202 of structure 1400, and extend in a vertical direction and across multiple layers. Vertical DL contacts 202 can directly contact WL structures 306 of structure 1400, Figure 3 ​​​​​​​​​FIG1 is a perspective view of a portion of structure 1800 associated with a vertical DL connection 1802 of DL 304. Vertical DL connection 1802 can be formed by depositing a metal or dopant material (e.g., n+ polysilicon) in DL contact via 1702. Alternatively or in addition, vertical DL connection 1802 can be formed by vapor phase doping through DL contact via 1702.

[0061] Figures 19A to 19C is a first example 3D semiconductor device (eg, Figure 18 Structure 1800, Figure 4 Arrangement of 400 and / or Figure 2 Illustration of various details of the device 200). Figure 19A yes Figure 18 A top view of a portion of a layer within structure 1800 is shown. Figure 19B It is along Figure 19A A cross-sectional view taken along the dotted line A. Figure 19C It is along Figure 19A A cross-sectional view taken along the dotted line B.

[0062] Now let’s refer to Figures 19A to 19C The vertical body contact 202 may have a width extending across the lateral direction. The semiconductor structures 902 may be arranged in rows on opposite sides of the vertical body contact 202. End portions of the semiconductor structures 902 may extend into the vertical body contact 202 and directly contact the vertical body contact 202.

[0063] The semiconductor structure 902 can be connected to components to form individual circuit units (eg, Figure 3 3D semiconductor devices can have sidewalls of the DL 1702 contact the semiconductor structure 902 (and the channel / drain), such as Figure 19C As described in .

[0064] Figure 20A and Figure 20B is a method for manufacturing a second example 3D semiconductor device (e.g. Figure 5 For example, Figure 20A is a perspective view of a portion of a structure 2000 associated with a stage for forming a body contact via 2002. The structure 2000 can be used to manufacture the second example arrangement 500. Additionally, the structure 2000 can be similar to the structure used to manufactureFigure 4 of the first example arrangement 400 Figure 17 of the structure 1700. Thus, the manufacturing process before and after the structure 2000 can be similar to the manufacturing process described above.

[0065] For the second example embodiment, the body contact via 2002 can extend along the vertical direction and across / through the layers, and the digit line 304 can occupy the remaining portion of the trench 802. In other words, the positions and / or orientations of the body contact 202 and the digit line 304 can be interchanged between the structure 2000 and the structure 1700. Figure 15 The body contact via 2002 can be formed using a chemical or light-based agent that etches away the material across / through the layers. The body contact via 2002 can be formed using a chemical or light-based agent that etches away the material across / through the layers. In the lateral direction, the body contact via 2002 can be located between the WL structure 306 and the vertical body contact 202 of the structure 1700. Furthermore, the body contact via 2002 can be located between and / or expose one or more sidewalls of the semiconductor structure 902 of the structure 1700.

[0066] Figure 16 Figure 15

[0067] In some embodiments, the body contact via 2002 can be located between and / or expose opposing sidewalls of the semiconductor structure. Thus, compared to the DL contact via 1702 of the structure 1700, the body contact via 2002 can have a longer dimension, e.g., to contact opposing sidewalls simultaneously. Furthermore, the structure 2000 can have a smaller number of body contact vias 2002 than the number of DL contact vias 1702 in the structure 1700 having an equivalent number of channels (e.g., half as many). Figure 17 For the structure 2000, the digit line 304 can occupy the remaining portion of the trench 802. Thus, the digit line 304 can contact the body 302 at a terminal end distal from the memory circuit 212 of the structure 1700. The digit line 304 can be a unitary / continuous and conductive structure (e.g., copper) that extends vertically across the layers and contacts the terminal portions of a set of aligned channels. In some embodiments, as illustrated in

[0068] Figure 3 Figure 2 Figure 20A In other embodiments, a unitary / continuous structure can contact the terminal ends of a set of opposing channels. In other words, the insulator 2004 and the pair of digit lines 304 can be replaced by a continuous / unitary structure that includes a conductive material (e.g., copper). ​​​​​​

[0069] The digit lines 304 may be electrically connected to routing connections 2006 that extend in a lateral direction. For example, for the first configuration, routing connections 2006 may provide electrical connections that are accessible from one or more peripheral portions of the resulting structure, rather than directly from the digit lines 304. Figure 18 The top portion of structure 1802 is proximate to digit line 304. Routing connection 2006 can be formed using masks, trenches, and material deposition methods similar to those described above.

[0070] Figure 20B is a top cross-sectional view of the second example arrangement 500 taken below the routing connection 2006 . Figure 20B Can be similar to Figure 19A , but for the second example arrangement 500 instead of Figure 19A As described in Figure 4 Take the first example arrangement 400 as an example. Figure 20B It can be explained that the conductive material is filled Figure 20A The main body contacts the through hole 2002 to form Figure 5 and Figure 20B The inner portion of the second example arrangement 500 is generated after the main body contact 202 is formed. The main body contact 202 can be located between and in contact with a pair of adjacent circuit units. For example, the first main body contact 202a can be located in the first circuit unit 300. a1 With the second circuit unit and 300 a2 In addition, the second main body contact 202b can be located between the first circuit unit 300 and electrically connected thereto. b1 and the second circuit unit 300 b2 between and electrically connected thereto.

[0071] Each of the circuit cells may be connected to DL 304 at a terminal edge. For example, circuit cell 300 a1 DL304 a1 is connected to the end of the length opposite to the storage unit. Similarly, the circuit unit 300 a2 Can have DL 304 a2 , circuit unit 300 b1 Can have DL 304 b1 , and the circuit unit 300 b2 Can have DL 304 b2 , and so on to the corresponding end.

[0072] Furthermore, each of the circuit cells may have a routing connection 2006 (in the example of FIG. 1 ) that is above, overlaps, and / or parallel to the length of the routing connection. Figure 20B For example, the routing connection 2006 a1Can be located in the circuit unit 300 a1 Additionally or alternatively, routing connection 2006 a1 Can be parallel to the circuit unit 300 a1 Length extension. Routing Connection 2006 a2 , 2006 b1 and 2006 b2 Relative to 300 a2 , 300 b1 and 300 b2 Arranged similarly.

[0073] For example, Figure 20A is a perspective view of a portion of a structure 2000 associated with a stage for forming a body contact via 2002. The structure 2000 can be used to manufacture the second example arrangement 500. Additionally, the structure 2000 can be similar to the structure used to manufacture Figure 4 The first example arrangement 400 Figure 17 Therefore, the manufacturing process before and after the structure 2000 can be similar to the manufacturing process described above.

[0074] Figure 21 is a schematic diagram of example aspects of a 3D semiconductor device according to embodiments of the present technology. Figure 21 Describes structures with 3D or vertical body connections (e.g. Figure 1 The memory array 150, Figure 2 3D semiconductor device 200, Figure 4 A first example arrangement 400, Figure 5 Example portion 2100 of a second example arrangement 500 or other semiconductor device). The structure represented may include Figure 2 2. The access circuitry 214 is formed around a silicon structure 2102 disposed between insulating layers 2104 (e.g., oxide layers) that vertically electrically separate the access circuitry 214. The combination of the silicon structure 2102 and the insulating layer 2104 can be on and / or integral with a silicon substrate 2106.

[0075] As described above, the structure shown may include a vertical body contact 202 that electrically connects the access circuit 214. Figure 3 The vertical body contact 202 may directly contact the silicon structure 2102 on multiple layers and provide a connection to, for example, electrical ground for reducing a floating body effect.

[0076] In some embodiments, the 3D semiconductor device 200 can include a vertical body contact 202 that directly contacts and / or is electrically coupled to a portion of the silicon substrate 2106. For example, the vertical body contact 202 directly contacts and / or is electrically coupled to a conductive portion 2116 (e.g., a P-well P+ doped region) of the silicon substrate 2106. The conductive portion 2116 can provide a path or lateral layer / plane of electrical coupling to the vertical body contact 202. At least one of the insulating layers 2104 can be disposed between the silicon structure 2102 and the conductive portion 2116, thereby preventing any direct contact between the conductive portion 2116 and the silicon structure 2102.

[0077] The conductive portion 2116 can extend along a lateral direction and be electrically coupled to a vertical connector 2122 (e.g., a P-well). Thus, the conductive portion 2116 can electrically couple the vertical body contact 202 to the vertical connector 2122, e.g., for connecting the vertical body contact 202 to a common potential (e.g., ground) or an external circuit and / or bonding structure. In some embodiments, the vertical connector 2122 can be located at an end or peripheral portion of the array 150. Further, a peripheral portion or surface of the vertical connector 2122 can be covered by a dielectric structure 2124, e.g., for isolating or controlling connections / contact with the vertical connector 2122.

[0078] Figure 22 is a flowchart illustrating an example method 2200 of fabricating a semiconductor device (e.g., the device 100 of Figure 2 , the 3D semiconductor device 200 of Figure 1 , the apparatus 100 of Figure 18 , the structure 1800 ofor a combination thereof) having a vertical body contact (e.g., the vertical body contact 202 of Figures 6 to 18 ). The method 200 can be related to (e.g., represent one or more portions or combinations of) the stages illustrated in

[0079] The method 2200 can include providing a stacked semiconductor structure (e.g., the structure 600 of Figure 6 ), as illustrated at block 2202. The provided structure can include layers of semiconductor material (e.g., Si / SiGe) disposed between oxide layers. Each layer of semiconductor material and a surrounding portion of the oxide layers can represent a circuit layer. In some embodiments, the provided structure can include a conductive portion 2116 (e.g., a P-well) of the silicon substrate 2106. Figure 21 Figure 21

[0080] At block 2204, semiconductor strips can be formed by shaping the semiconductor material layers, the oxide layers, or a combination thereof. For example, the semiconductor strips can be formed by etching the DTI and depositing a dielectric filler, as described above with respect to Figure 7 the structure 600 of. The resulting strips can be arranged in rows and columns.

[0081] At block 2206, one or more vertical trenches (e.g., Figure 8 The resulting trenches may extend vertically through the semiconductor strip, the oxide layer, or a combination thereof, thereby dividing the semiconductor strip into two portions extending laterally from the data storage portion toward the trenches. Figure 9 In addition, vertical trenches can be used to further form lateral cavities, as described above with respect to Figure 9 and / or Figure 10 Thus, one or more portions of the semiconductor body 902 may be exposed by the trenches and the lateral cavities.

[0082] At block 2208, a WL structure (eg, Figure 3 and Figure 14 For the portion laterally located between the data storage portion and the trench, the WL structures may be formed adjacent to or overlap one or more surfaces of the corresponding portion in the semiconductor body. Figure 11 Insulation material 1102 and Figure 11 The oxide layer 1104 may be as described above for Figure 11 and Figure 12 formed and shaped as described. Figure 12 The oxide boundary 1202 may be formed to define a lateral end portion of the WL structure. In addition, etching of the oxide layer 1104 may form a laterally extending cavity between adjacent semiconductor bodies, such as Figure 12 Thus, the laterally extending cavity may expose one or more surfaces of each of the semiconductor bodies along a portion of the length of the semiconductor bodies.

[0083] The laterally extending cavity may be filled with gate oxide material and metal material ( Figure 13 of metal deposits 1302), as described above for Figure 13 The deposited metal material can be shaped, for example, by Figure 14 The removal or etching described. The remaining portion of the metal material may represent or become a WL structure 306. Based on the configuration of the laterally extending cavity, the WL structure 306 may face and overlap one, two, or more surfaces of the semiconductor body. In some embodiments, the WL structure 306 may wrap around a portion of the length of each of the semiconductor bodies, such as for a GAA transistor structure. Furthermore, the WL structure 306 may extend laterally across a row of n semiconductor bodies representing n memory circuits that together store a data word. Any remaining portion of the laterally extending cavity may be filled with an insulating material, which may be further shaped / recessed, as described above for Figure 14 and Figure 15 described.

[0084] At block 2210, one or more continuous vertical body contacts can be formed, e.g., by filling one or more vertical trenches with a metal material or doped polysilicon material, as described above for Figure 16 . The resulting vertical body contacts can be connected to columns of the semiconductor body.

[0085] At block 2212, DLS (e.g., vertical DL connections 1802 of Figure 18 ) can be formed. As described above for Figure 17 and Figure 18 , the vertical DL connections 1802 can be formed by etching DL contact vias 1702 of Figure 17 and then filling them by depositing a metal or doped material (e.g., n+ polysilicon). Each of the resulting DLS can represent or include a DL 304 of Figure 4 and contact a semiconductor body 302 of Figure 3 . The DLS can match one or more sets of n to n storage circuits of a data word. The semiconductor body can be doped (1) with a first type (e.g., n+) at portions that contact the DLS and portions that interface with data storage portions, and (2) with a second type (p+) at portions that contact the vertical body contacts.

[0086] Figure 23 is a schematic diagram of a system that includes devices in accordance with embodiments of the present technology. Any of the foregoing devices (e.g., memory devices) described above with reference to Figures 1 to 22 may be incorporated into any of a large number of larger and / or more complex systems, representative examples of which are the systems 2380 schematically shown in Figure 23 . The systems 2380 can include memory devices 2300, power supplies 2382, drivers 2384, processors 2386, and / or other subsystems or components 2388. The memory devices 2300 can include features generally similar to those of the devices described above with reference to Figures 1 to 22 , and thus can include various features for performing direct read requests from host devices. The resulting systems 2380 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 2380 can include, without limitation, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the systems 2380 can be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the systems 2380 can also include remote devices and any of a wide variety of computer-readable media.

[0087] From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but well-known modifications can be made by those skilled in the art. Additionally, certain aspects of the novel technology described in the context of one particular embodiment can be combined or eliminated in other embodiments. Moreover, although advantages of the technology are indicated, a particular embodiment of the technology can not necessarily exhibit all of these advantages. Accordingly, the disclosure and associated technology can encompass other embodiments that do not exhibit all of these advantages.

[0088] In the above described embodiments, the apparatus has been described in the context of a DRAM device. However, apparatus configured in accordance with other embodiments of the technology can include other types of suitable storage media in addition to or instead of DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase change storage media, ferroelectric storage media, etc.

[0089] The term "processing," as used herein, includes manipulation of signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, computing results, executing instructions, assembling, shifting, and / or manipulating data structures. The term data structure includes information arranged as bits, words or code words, blocks, files, input data, system generated data (e.g., computed or generated data), and program data.

[0090] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, the skilled artisan will understand that the technology can have additional embodiments and can be practiced without Figures 1 to 23 Several details of the described embodiments have been set forth in order to provide a thorough understanding of the technology. However, the skilled artisan will understand that the technology can be practiced without these details.

Claims

1. A three-dimensional integrated semiconductor memory device, comprising: vertically stacked circuit layers, each of which includes at least one circuit unit, wherein each circuit cell includes (1) a storage circuit configured to store one or more data bits and (2) an access circuit configured to provide access to and / or from the storage circuit, the access circuit having a semiconductor body, and wherein said access circuits across said layers are aligned in a vertical direction; and A vertical body contact extends vertically and is connected to the semiconductor body of the at least one access circuit aligned across two or more layers, wherein the vertical body contact is configured to provide transistor body contacts for multiple access circuits located on different layers.

2. The apparatus of claim 1 , wherein the access circuit comprises: the semiconductor body having a length and coupled to the storage circuit at at least one end of the length; a word line (WL) structure facing and coupled to at least one side of the semiconductor body; a digit line (DL) connected from the memory circuit to the semiconductor body at a first location across the WL structure; and The vertical body contact is connected from the storage circuit to the semiconductor body at a second location across the WL structure.

3. The device according to claim 2, wherein: The second position of the vertical body contact is at an opposite end of the length; and The first location of the DL is on a portion of a sidewall of the semiconductor body and between the second location and the WL structure.

4. The device according to claim 2, wherein: The first position of the DL contact is at opposite ends of the length; and The second location of the vertical body contact is on a portion of a sidewall of the semiconductor body and between the first location and the WL structure.

5. The device according to claim 4, wherein: The at least one circuit unit on each of the layers includes at least two circuit units positioned adjacent to each other; and The vertical body contact is a shared body contact that (1) is located between the two circuit cells and (2) is connected to a mirror image portion of a sidewall on the semiconductor body of the at least two circuit cells.

6. The device according to claim 4, wherein: Each of the circuit layers includes a maximum number of circuit cells; and The device includes half the maximum number of vertical body contacts.

7. The apparatus according to claim 2, wherein: The access circuit includes a transistor formed on or integral with the semiconductor body; The storage circuit is a capacitor connected to the first terminal of the transistor; The WL structure corresponds to a gate terminal of the transistor; The DL corresponds to the second terminal of the transistor; and The vertical body contact corresponds to the transistor body contact, which is configured to route leakage current away from the capacitor when the transistor is turned off. 8 . The device of claim 7 , wherein the WL structure surrounds the semiconductor body along a portion of the length of a gate-all-around (GAA) transistor structure.

9. The device of claim 2 , wherein the semiconductor body (1) is doped to n+ type at the first location for the DL and at the one end of the length for the storage circuit, and (2) is doped to p+ type at the second location for the vertical body contact.

10. The apparatus according to claim 2, wherein: Each layer includes a group of circuit cells arranged along a lateral direction, the group of circuit cells including n storage circuits configured to store a group of bits corresponding to a stored data word; The WL structure extends across the set of circuit cells along the lateral direction and is configured to simultaneously control n access circuits in the set of circuit cells; and The DLs include n DLs that (1) extend vertically across the layers and (2) are each coupled to an instance of the storage circuit corresponding to a unique bit position in the set of bits on each of the layers.

11. The device of claim 1 , wherein portions of the semiconductor body connected to the storage circuit and the vertical body contact are doped with complementary dopant types.

12. The apparatus of claim 1, further comprising: a semiconductor substrate comprising a conductive top surface, wherein the vertically stacked circuit layers are stacked on the semiconductor substrate, and Wherein the conductive top surface is electrically coupled to the vertical body contact and is configured to laterally route electrical signals to or from the vertical body contact.

13. The apparatus according to claim 12, further comprising: A vertical metal connection is electrically coupled to the conductive top surface at a location laterally displaced from the vertical body contact, wherein the vertical metal connection is configured to electrically couple the vertical body contact to an external electrical connection.

14. The device of claim 12, wherein the conductive top surface comprises a P+ doped P-well on a top portion of the semiconductor substrate.

15. The apparatus of claim 1, further comprising: A dielectric film is disposed between the semiconductor body and the vertical body contact, wherein the dielectric film has a thickness configured to (1) enable conduction of charges or holes while (2) inhibiting dopant diffusion between the semiconductor body and the vertical body contact.

16. A three-dimensional integrated semiconductor device comprising: vertically stacked circuit layers, each comprising at least one transistor, wherein each of the at least one transistor comprises a first terminal connected to or integral with a semiconductor body, a second terminal and a gate terminal, the first terminal and the second terminal serving as endpoints of a current channel, and wherein the at least one transistor on each of the layers is aligned in a vertical direction; and A vertical body contact extends vertically across the layers and is connected to the semiconductor body of the at least one transistor on each of the layers, wherein the vertical body contact is configured to provide transistor body contacts for the transistors on different layers.

17. The apparatus according to claim 16, wherein: the first terminal corresponding to a first end portion of the semiconductor body; the vertical body contact being connected to a second end portion of the semiconductor body opposite the first end portion; The gate terminal corresponds to a structure facing a section of at least one surface of the semiconductor body between the first end portion and the second end portion; and The second terminal corresponds to a portion of the semiconductor body between the gate terminal and the vertical body contact.

18. The apparatus of claim 16, wherein: The first terminal comprises a first end portion of the semiconductor body; the second terminal comprising a second end portion of the semiconductor body opposite the first end portion; The gate terminal includes a structure of a section between the first end portion and the second end portion facing at least one surface of the semiconductor body; and The vertical body contact is connected to a portion of the semiconductor body between the gate terminal and the second terminal.

19. The apparatus of claim 16, wherein: At least one of the layers includes two or more transistors arranged laterally adjacent to each other; and The vertical body contact is located between and connected to the two laterally adjacent transistors for providing a shared body contact for the two adjacent transistors in addition to the transistors aligned along the vertical direction.

20. The device of claim 16, wherein the semiconductor body (1) is doped with a first dopant type at the first terminal and the second terminal and (2) is doped with a second dopant type at locations contacting the vertical body contact.

21. A method for manufacturing a three-dimensional integrated semiconductor memory device, the method comprising: providing a stacked semiconductor structure having semiconductor material layers disposed between oxide layers; forming semiconductor strips based on shaping the semiconductor material layer, the oxide layer, or a combination thereof, wherein the formed semiconductor strips are arranged in rows and columns; etching a trench extending vertically through the semiconductor strip, the oxide layer, or a combination thereof, wherein the trench divides the semiconductor strip into semiconductor bodies extending laterally from corresponding data storage portions toward the trench, each of the semiconductor bodies being configured to provide a basis for access circuitry for the corresponding data storage portion; forming word line (WL) structures each adjacent to a corresponding one of the semiconductor bodies and laterally interposed between the data storage portion and the trench; forming a continuous vertical body contact based on filling the trench with a conductive material or a doped polysilicon material, wherein the vertical body contact is connected to the semiconductor body; and A vertically extending digit line (DL) is formed for each column of the semiconductor bodies, wherein each of the vertically extending DLs (1) contacts the semiconductor body in the corresponding column and (2) is located between the WL structure for the contacted semiconductor body and the continuous vertical body contact.

22. The method of claim 21 , wherein forming the WL structure comprises: forming a laterally extending cavity at least between said semiconductor bodies; filling the laterally extending cavity with a metallic material; and A portion of the metal material is removed from the laterally-extending cavity, wherein a remaining portion of the metal material corresponds to the WL structure.

23. The method of claim 22, wherein: The laterally extending cavity exposes all sides of each of the semiconductor bodies along a portion of the length of the semiconductor bodies; and The WL structure surrounds the portion of the length of each of the semiconductor bodies for a gate all around (GAA) transistor structure.

24. The method of claim 21, wherein the semiconductor body (1) is doped with a first type at portions contacting the DL and interfacing with the data storage portion, and (2) is doped with a second type at portions contacting the vertical body contact.

25. The method of claim 21, wherein: each of the formed WL structures extends across a row of n semiconductor bodies corresponding to n storage circuits that together store a data word; and Forming the DL for each column of the semiconductor bodies includes forming n DLs, each corresponding to one of the semiconductor bodies in the row for providing access to a corresponding bit in the data word.

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