Multi-channel electrophysiological signal acquisition system and acquisition method thereof

Abstract

The application discloses a kind of multi-channel electrophysiological signal acquisition system and its acquisition method, wherein multi-channel electrophysiological signal acquisition system, including: with the power supply module of controller electrical connection, analog front-end chip set, filter module, analog-digital conversion module;Analog front-end chip set is used to obtain analog signal, and analog signal is pretreated;The pretreated analog signal is converted into digital signal by filter module and analog-digital conversion module, and digital signal is transmitted to controller;Filter module is used for filtering denoising;The timer module of controller connection generates sampling frequency, and sampling frequency is delivered to analog-digital conversion module, and time sequence signal is provided to analog-digital conversion module.The application discloses a kind of multi-channel electrophysiological signal acquisition system, under the constraint of maintaining system total power consumption, solve high-density electrode array synchronous sampling time sequence control, eliminate the signal phase deviation caused by clock jitter between multiple channels;Realize real-time power frequency interference suppression.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded bioengineering technology, in particular to a multi-channel electrophysiological signal acquisition system and an acquisition method thereof. BACKGROUND

[0002] Brain-computer interface (BCI) technology realizes information interaction between human brain and external devices by collecting central nervous system bioelectric signals (such as EEG, EMG, LFP), and has important application value in the fields of neural rehabilitation and motion control. A high-performance multi-modal electrophysiological acquisition system is the technical basis for the above applications, but the existing schemes have significant limitations in channel density, noise suppression, dynamic configuration capability and power consumption control.

[0003] Existing technical solutions and defects:

[0004] First, a multi-channel acquisition system based on a traditional MCU; a modular architecture is adopted, and a peak detection rate of 62.5kS / s is achieved through wireless transmission, with an input reference noise of 8µVrms (<100Hz-10kHz bandwidth). However, this way has limited channel number (≤64 channels), which is difficult to meet the demand of high-density bioelectric signal synchronous acquisition; the noise level is relatively high (8µVrms), which cannot meet the detection accuracy of µV-level weak signals (such as EEG); the bandwidth of wireless transmission is limited, which is difficult to support real-time transmission of full data rate of more than 128 channels.

[0005] Second, an application-specific integrated circuit (ASIC) scheme; high channel density is achieved through ASIC, with single-channel power consumption of 5μW and support for 200Mbps data transmission. However, the hardware parameters of this way are fixed (such as gain / bandwidth), which cannot dynamically adapt to multi-modal signal characteristics (such as EEG low frequency / EMG high frequency); the UWB transmission distance is limited (≤5 meters), and the anti-interference ability is insufficient, which is easily affected by environmental noise.

[0006] Third, a high-bandwidth BCI system; an electrode array is implanted through a neurosurgical robot. However, this way needs invasive implantation, which is not suitable for surface electrophysiological signal (such as SEMG) acquisition; the system complexity is high, and the power consumption and volume are difficult to meet the demand of wearable devices.

[0007] Fourth, a domestic low-power front-end design, 8-channel AFE circuit of 65nm CMOS process, single-channel power consumption 1.97μW; based on low-power mixed signal design, dynamic range and noise performance are optimized. However, the channel number of this way is severely insufficient (≤8 channels), which cannot support high-density electrode array; it lacks real-time power frequency interference suppression capability, resulting in signal quality degradation.

[0008] The existing electrophysiological acquisition system has the following core defects:

[0009] 1. Poor channel scalability: It is difficult for traditional MCU or ASIC solutions to achieve >100 channel synchronous acquisition under low power consumption constraints.

[0010] 2. Insufficient noise suppression: Existing power frequency filtering solutions (such as notch filters) introduce phase distortion or high computational overhead, and cannot balance real-time performance and accuracy (noise ≥ 5µV).

[0011] 3. Lack of dynamic adaptation: Hardware parameters are fixed and cannot be dynamically configured according to signal spectral characteristics (such as EEG 0.5-100Hz vs. EMG 20-500Hz).

[0012] 4. Transmission bottleneck: Wireless solutions (UWB) have limited bandwidth, and wired solutions (such as USB2.0) cannot meet the 128-channel, 20kHz, 480Mbps data throughput requirements. SUMMARY

[0013] The present application overcomes the shortcomings of the prior art and provides a multi-channel electrophysiological signal acquisition system that solves the synchronous sampling timing control of high-density electrode arrays under the constraint of maintaining the total power consumption of the system, eliminates the signal phase deviation caused by clock jitter between multiple channels, and realizes real-time power frequency interference suppression.

[0014] To achieve the above-mentioned purposes, the technical scheme adopted by the present application is as follows: a multi-channel electrophysiological signal acquisition system, comprising: a controller, and a power supply module, an analog front-end chip set, a filter module, and an analog-to-digital conversion module electrically connected to the controller; the analog front-end chip set is used to obtain an analog signal and pre-process the analog signal to obtain a pre-processed analog signal; the pre-processed analog signal is converted into a digital signal through the filter module and the analog-to-digital conversion module, and the digital signal is transmitted to the controller; the controller transmits the obtained digital signal to a processing mechanism; wherein the filter module is used for filtering and denoising; the controller is connected to a timer module to generate a sampling frequency, which is transmitted to the analog-to-digital conversion module to provide a timing signal to the analog-to-digital conversion module.

[0015] Specifically, the pre-processing of the analog front-end chip set includes amplifying and conditioning the obtained analog signal; the processing mechanism includes an upper computer or a computer.

[0016] In a preferred embodiment of the present application, the analog front-end chip set includes multiple analog front-end chips; the output end of the analog front-end chip is connected to the controller through a cascaded SPI bus, and the input end of the analog front-end chip is connected to a data transmission interface for obtaining the analog signal of the measured object.

[0017] In one preferred embodiment of the present application, the power supply module includes a power supply, the power supply is introduced through a power supply interface, one pin of the power supply interface is grounded, and the other pin is led out through a power supply switch to supply power supply, the power supply supplies power to the analog LDO circuit and the digital LDO circuit respectively, the analog LDO circuit outputs an AVCC power supply, and the AVCC power supply is grounded through an AVCC filter circuit, and the digital LDO circuit outputs a DVCC power supply which is grounded through a DVCC filter circuit.

[0018] In one preferred embodiment of the present application, the controller includes an MCU control chip, a crystal oscillator circuit is connected to the crystal oscillator end of the MCU control chip, the CLK pin, the NSS pin, the MISO pin and the MOSI pin of the IO port group PA, the IO port group PB, the IO port group PC and the IO port group PD of the MCU control chip are respectively connected to the FPC connector of the corresponding data transmission interface through the channel digital isolator of the corresponding analog front-end chip group; the MCU control chip is further connected to a USB interface circuit; the debugging interface of the MCU control chip is further connected to an FPC connector; the DVCC power supply is connected to the warning end of the MCU control chip through the series connection of the current limiting resistor R4 and the indicator lamp LED2.

[0019] In one preferred embodiment of the present application, the filter module includes a filter, and the filter is a cascaded comb filter.

[0020] In one preferred embodiment of the present application, each stage of the cascaded comb filter has the same delay length K; the filter realizes high-frequency attenuation through twice subtraction, and forms a transfer function H(z)=(1-z -K ) 2 ; Z is a complex frequency variable of a discrete system; in real-time processing, a circular buffer delay line is used to reduce memory overhead.

[0021] In one preferred embodiment of the present application, a multi-channel electrophysiological signal acquisition method is realized by using a multi-channel electrophysiological signal acquisition system, and includes the following steps:

[0022] The analog signal of the measured object is collected through the data transmission interface connected to the input end of the analog front-end chip group; the analog signal is pretreated by the analog front-end chip group and then introduced into the filter module and the analog-to-digital conversion module as the pretreated analog signal, and the pretreated analog signal is converted into a discrete digital signal;

[0023] The converted digital signal is connected to the controller through the cascaded SPI bus;

[0024] The obtained digital signal is analyzed through the control method in the controller;

[0025] The timer module connected with the controller generates a sampling frequency, and the sampling frequency is transmitted to the analog-digital conversion module to provide a timing signal for the analog-digital conversion module, so that the multi-channel electrophysiological signal acquisition is realized.

[0026] In one preferred embodiment of the present application, the algorithm of the filter comprises:

[0027] Step one, processing the input sample and generating an intermediate output;

[0028] Step two, processing the output of step one and generating a final output; the step comprises calculating the output, updating the delay line and updating the pointer.

[0029] In one preferred embodiment of the present application, step one is the first level processing:

[0030] Calculating the output of step one: using the formula y1=x n -h1[ptr1]; wherein: x n is the current input sample, h1[ptr1] is the value at the position of the pointer ptr1 in the first level delay line, representing the input delayed by K samples, i.e. x[n-K]; the difference equation y1[n]=x[n]-x[n-K], i.e. the current input sample minus the input sample delayed by K samples; the current input sample is written into the current position of the first level delay line, i.e. x n is written into h1[ptr1]; ensuring that in the next sampling period, the value at the writing position represents the new delayed input, and the delay line is updated; the pointer is incremented in a loop, i.e. (ptr1+1)modK is updated to update ptr1; the pointer is ensured to be in the range of 0 to K-1 and circulate, realizing efficient buffer management;

[0031] Step two is the second level processing:

[0032] Calculating the output of step two: using the formula y2=y1-h2[ptr2];

[0033] wherein: y1 is the first level output sample, h2[ptr2] is the value at the position of the pointer ptr2 in the second level delay line, representing the first level output delayed by K samples, i.e. y1[n-K]; realizing the difference equation y2[n]=y1[n]-y1[n-K], i.e. the first level output sample minus the value of the sample delayed by K samples;

[0034] The current first level output sample y1 is written into the current position of the second level delay line, i.e. y1 is written into h2[ptr2], updating the delay line; the pointer is incremented in a loop, i.e. (ptr2+1)modK is updated to update ptr2, updating the pointer;

[0035] y2 is the final output sample after filtering, and the output result;

[0036] Each sample is subtracted twice and written twice in memory; 2K words per channel are used to store delay line h1 and delay line h2; K samples are introduced by the first stage processing.

[0037] In a preferred embodiment of the present application, the zero point frequency is , ; wherein: f s is the sampling rate, k is the integer index; K is the delay length; the zero point frequency represents the point where the filter gain is zero.

[0038] The present application solves the defects in the technical background, and has the beneficial technical effects of:

[0039] A multi-channel electrophysiological signal acquisition system, under the constraint of maintaining the total power consumption of the system, solves the synchronous sampling timing control of high-density electrode arrays, eliminates the signal phase deviation caused by clock jitter between multiple channels, and realizes real-time power frequency interference suppression. The present application can realize strict synchronous acquisition and ultra-low power consumption control of multi-channel electrophysiological signals. Under the constraint of maintaining the total power consumption of the system, the problem of synchronous sampling timing control of high-density electrode arrays is solved, and the signal phase deviation caused by clock jitter between multiple channels is eliminated. BRIEF DESCRIPTION OF DRAWINGS

[0040] The present application will be further described below in combination with the drawings and examples.

[0041] Figure 1 The figure is a block diagram of the multi-channel electrophysiological signal acquisition system in the preferred embodiment of the present application;

[0042] Figure 2 The figure is a working process of the multi-channel electrophysiological signal acquisition system in the preferred embodiment of the present application Figure 1 ;

[0043] Figure 3 The figure is a working process of the multi-channel electrophysiological signal acquisition system in the preferred embodiment of the present application Figure 2 ;

[0044] Figure 4 The figure is a data processing flowchart of the multi-channel electrophysiological signal acquisition system in the preferred embodiment of the present application;

[0045] Figure 5 The figure is an 8mv lithium battery input ripple graph of the multi-channel electrophysiological signal acquisition system in the preferred embodiment of the present application;

[0046] Figure 6 The figure is a 0.8mv front-end acquisition input ripple graph of the multi-channel electrophysiological signal acquisition system in the preferred embodiment of the present application;

[0047] Figure 7Waveform before SPI isolation in multi-channel electrophysiological signal acquisition system in preferred embodiments of the application

[0048] Figure 8 Waveform after SPI isolation in multi-channel electrophysiological signal acquisition system in preferred embodiments of the application

[0049] Figure 9 Waveform after SPI isolation in multi-channel electrophysiological signal acquisition system in preferred embodiments of the application

[0050] Figure 10 Sampling rate control waveform of multi-channel electrophysiological signal acquisition system in preferred embodiments of the application

[0051] Figure 11 Verification data collected by multi-channel electrophysiological signal acquisition system in preferred embodiments of the application (the sampling rate of 2KHZ of the upper computer is shown, and the stability of data sampling is indicated by the leftmost timestamp)

[0052] Figure 12 2-time comb filter effect diagram of multi-channel electrophysiological signal acquisition system in preferred embodiments of the application

[0053] Figure 13 Data diagram for using on-chip CACHE hardware to accelerate data reading of multi-channel electrophysiological signal acquisition system in preferred embodiments of the application

[0054] Figure 14 Oscilloscope verification sampling rate of multi-channel electrophysiological signal in preferred embodiments of the application, the horizontal coordinate is 100us, one period is 500us, and the sampling rate is 2khz (indicating that 32 channels are collected for 500us, and the stable sampling rate is 2KHZ)

[0055] Figure 15 Electromyographic signal collected in the field by multi-channel electrophysiological signal acquisition system in preferred embodiments of the application (the shape conforms to the electromyographic signal and meets the number of field collection)

[0056] Figure 16 32-channel field potential signal amplitude variation curve obtained by multi-channel electrophysiological signal acquisition system in preferred embodiments of the application (the amplitude characteristic conforms to the shape of LFP field potential signal)

[0057] Figure 17 Time domain variation curve obtained by multi-channel electrophysiological signal acquisition system in preferred embodiments of the application (the signal spikes are concentrated in the low frequency range (5Hz-35Hz) by the relationship between power spectrum and time, which conforms to the LFP field potential range)

[0058] Figure 18 The circuit diagram of the multi-channel electrophysiological signal acquisition system in a preferred embodiment of the present invention is shown below. Figure 1 ;

[0059] Figure 19 The circuit diagram of the multi-channel electrophysiological signal acquisition system in a preferred embodiment of the present invention is shown below. Figure 2 ;

[0060] Figure 20 The circuit diagram of the multi-channel electrophysiological signal acquisition system in a preferred embodiment of the present invention is shown below. Figure 3 . Detailed Implementation

[0061] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention and therefore only show the components relevant to the present invention.

[0062] It should be noted that if directional indicators (such as up, down, bottom, top, etc.) are involved in the embodiments of the present invention, these directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Unless otherwise explicitly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in the present invention can be understood according to the specific circumstances.

[0063] Example 1, as Figures 1-3 As shown, a multi-channel electrophysiological signal acquisition system includes: a controller, and a power supply module, an analog front-end chipset, a filter module, and an analog-to-digital converter module electrically connected to the controller. The analog front-end chipset is used to acquire analog signals and preprocess them to obtain preprocessed analog signals; the filter module and the analog-to-digital converter module convert the preprocessed analog signals into digital signals and transmit the digital signals to the controller; the controller transmits the acquired digital signals to the processing unit; wherein, the filter module is used for filtering and noise reduction; the timer module connected to the controller generates a sampling frequency and sends the sampling frequency to the analog-to-digital converter module to provide timing signals to the analog-to-digital converter module.

[0064] Specifically, the pre-processing of the analog front-end chip set includes amplifying and conditioning the acquired analog signals; the processing mechanism includes an upper computer or a computer. The analog front-end chip set includes multiple analog front-end chips; the output end of the analog front-end chip is connected with the controller through cascaded SPI buses, and the input end of the analog front-end chip is connected with the data transmission interface for acquiring the analog signals of the measured object.

[0065] Further, as shown in Figure 18 , the power supply module includes a power supply (3.7V lithium battery), the power supply is introduced through a power supply interface CN1, one pin of the power supply interface CN1 is grounded, and the other pin is led out as a power supply through a power switch SW1, the power supply respectively supplies power to an analog LDO circuit (including a resistive voltage difference linear stabilizer chip U2) and a digital LDO circuit (including a resistive voltage difference linear stabilizer chip U3), the analog LDO circuit outputs an AVCC power supply, and the input end of the AVCC power supply is grounded and filtered through a capacitor C27; the output end of the AVCC power supply is grounded through an AVCC filtering circuit (capacitors C3 and C28 in parallel); the input end of the digital LDO circuit is grounded and filtered through a capacitor C29; and the output end of the DVCC power supply is grounded through a DVCC filtering circuit (capacitors C4 and C30 in parallel). As shown in Figure 18 、 Figure 19 , the DVCC power supply is connected with the warning end of the MCU control chip (chip U1) through a series-connected current-limiting resistor R4 and an indicator lamp LED2. The digital LDO circuit outputs a DVCC power supply which is also connected with capacitors C11, C12, C13, C14 and C15 in parallel and grounded at a common point to realize power filtering. The analog LDO circuit outputs an AVCC power supply which is also connected with capacitors C16 and C17 in parallel and grounded at a common point to realize power filtering.

[0066] Further, as shown in Figure 19 、 Figure 20 , the controller includes an MCU control chip (control chip U1), the crystal oscillator circuit (including a crystal oscillator chip X1) is connected with the crystal oscillator end of the MCU control chip (control chip U1), and the CLK pin, the NSS pin, the MISO pin and the MOSI pin of the IO port group PA, the IO port group PB, the IO port group PC and the IO port group PD of the MCU control chip are respectively connected with the FPC connector (including connector FPC2 chip, connector FPC3 chip, connector FPC4 chip and connector FPC5 chip) of the corresponding data transmission interface through the corresponding channel digital isolator (including channel digital isolator U4 chip, channel digital isolator U5 chip, channel digital isolator U6 chip and channel digital isolator U7 chip) of the corresponding analog front-end chip set.

[0067] As shown in Figure 19As shown, the MCU control chip is also connected with a USB interface circuit (including a USB3 chip); the debugging interface of the MCU control chip is also connected with an FPC connector (connector FPC1). The FPC connector adopts the product in the prior art, which will not be described one by one and listed with specific model selection.

[0068] In embodiment two, on the basis of embodiment one, as Figure 1 As shown, the analog front-end chip set adopts four analog front-end chips, and the model of the analog front-end chip is INTAN RHD2132. The model of the controller adopted is STM321723VGT6 controller. The model of the isolation chip adopted is IS07041. The model of the data transmission interface adopted is TSB3.0. The model of the voltage conversion chip adopted by the analog LDO circuit and the digital LDO circuit is SPX3819 voltage conversion chip. The selection of the component model is not limited to this, and in other embodiments, the product model in the prior art can be selected according to the actual use demand, as long as the function of the corresponding chip in the embodiment can be basically realized. Figure 1 In the embodiment, the filter is a power frequency filter for 50HZ, and the filtering operation is realized on the KEIL5 embedded operation platform. The specific implementation process is that the discrete-time digital signal after collection is subjected to two-stage delay and subtraction operation, so as to suppress the signal of a specific frequency.

[0069] Further, in the embodiment, one end of the resistor R3 is connected to the analog ground, and the other end is connected to the digital ground. The resistor R3 is a 0-ohm resistor, which is physically isolated and single-ended connected. The resistor R3 is used to single-ended connect the analog circuit and the digital circuit in the circuit diagram, so as to avoid the interference of the digital signal on the analog signal. The two ends of the inductor L1 are connected to the digital ground, which is used to connect the negative electrode of the power supply and the negative electrode of the digital circuit, and to suppress the influence of the high-frequency signal in the digital circuit on the power supply.

[0070] In embodiment three, on the basis of embodiment one or embodiment two, the filter adopted is a two-stage cascaded comb filter, each stage having the same delay length K. The filter realizes high-frequency attenuation through two subtraction operations, and forms a transfer function H(z)=(1-z -K ) 2 wherein Z is a complex frequency variable of a discrete system; in real-time processing, a circular buffer is used to efficiently manage the delay line, so as to reduce the memory overhead. The output of the filter has significant attenuation at zero frequencies, which is suitable for anti-aliasing or harmonic suppression in signal processing.

[0071] The specific algorithm includes two steps:

[0072] Step one, processing the input sample and generating intermediate output; step two, processing the output of step one and generating final output. Each step includes calculating output, updating delay line and updating pointer.

[0073] Specifically, step one is first level processing (corresponding to step1):

[0074] Calculating the output of step one (first level): using the formula y1=x n -h1[ptr1] where:

[0075] x n is the current input sample, h1[ptr1] is the value at the position of pointer ptr1 in the first level delay line, representing the input delayed by K samples (i.e. x[n-K], K is the delay length). This formula implements the difference equation y1[n]=x[n]-x[n-K], i.e. the current input sample minus the input sample delayed by K samples.

[0076] Updating the delay line: write the current input sample, x n into the current position of the first level delay line, i.e. x

[0077] Updating the pointer: increment the pointer in a circular manner, i.e. (ptr1+1)mod K updates ptr1. Ensure that the pointer is within the range of 0 to K-1, and implement efficient buffer management.

[0078] Specifically, step two is second level processing (corresponding to step2):

[0079] Calculating the output of step two (second level processing): using the formula y2=y1-h2[ptr2]. Where:

[0080] y1 is the first level output sample, h2[ptr2] is the value at the position of pointer ptr2 in the second level delay line, representing the first level output delayed by K samples (i.e. y1[n-K]). Implement the difference equation y2[n]=y1[n]-y1[n-K], i.e. the first level output sample minus its value delayed by K samples.

[0081] Updating the delay line: write the current first level output sample y1 into the current position of the second level delay line, i.e. y1 is written into h2[ptr2].

[0082] Updating the pointer: increment the pointer in a circular manner, i.e. (ptr2+1)mod K updates ptr2.

[0083] Output result: y2 as the final output sample after filtering.

[0084] Based on the implementation, the key computational characteristics of the filter are as follows: 2 subtractions per sample (one per step) and 2 memory writes (to update the delay lines). No multiplication or addition, high computational efficiency.

[0085] Memory requirement: 2K words per channel (for storing two delay lines h1 and h2).

[0086] Delay: K samples (mainly introduced by the first stage processing, because the output depends on the history input).

[0087] Zero frequency: , ; where: f s is the sampling rate, k is the integer index (e.g. k = 0, 1, 2,...); K is the delay length; the zero frequency represents the point where the filter gain is zero (e.g. when f s = 2kHz, K = 40, the zero points are at 0Hz, 50Hz, 100Hz,...).

[0088] Embodiment four, a multi-channel electrophysiological signal acquisition method, using a multi-channel electrophysiological signal acquisition system of embodiment three to realize, comprising the following steps:

[0089] Through the data transmission interface connected with the input end of the analog front-end chip set, the analog signal of the measured object is collected; the analog signal is pretreated by the analog front-end chip set and introduced into the filter module and the analog-digital conversion module as the pretreated analog signal, and the pretreated analog signal is converted into discrete digital signal;

[0090] And the converted digital signal is connected with the controller through the cascaded SPI bus;

[0091] The digital signal obtained is analyzed by the control method in the controller;

[0092] The timer module connected with the controller generates a sampling frequency, which is delivered to the analog-digital conversion module to provide a timing signal for the analog-digital conversion module, realizing the acquisition of multi-channel electrophysiological signal.

[0093] Embodiment five, on the basis of embodiment four, as Figures 1-3 shown, the present application provides a multi-channel electrophysiological signal acquisition system and its acquisition method, which adopts a multi-stage SPI timing chain and a zero-copy DMA transmission architecture; four IntanRHD2132 chips are connected in parallel (each chip has 32 channels), and an STM32H723VGT6 main controller is connected through a cascaded SPI bus.

[0094] As Figure 4As shown, the present application reads the timing logic alignment of the INTAN RHD2132 on-chip ROM verification SPI, and the data obtained by shorting the input end with REF is analyzed by the matlab analysis system noise of 2.6854uvrms, compared with the noise of 2.4uvrms of the INTAN chip. , wherein V is the sampling voltage value, is the voltage average value, N is the number of sampling points, the signal generator outputs the sin wave as shown in Figure 4 , the finger electromyographic signal is collected, and the baseline drift phenomenon occurs, and then the high-pass filter is processed; further, the high-pass filter utilizes the on-chip DSP high-pass filter of the INTAN RHD2132, and the baseline drift is eliminated.

[0095] As shown in Figure 5 , Figure 6 , Figure 5 is the 8mv lithium battery input ripple, Figure 6 is the 0.8mv front-end collection input ripple, and the DC signal has the greatest influence on the analog circuit of the front end through the digital and electrical mode isolation, USB isolation and power isolation.

[0096] As shown in Figures 7-9 , the SPI isolation can eliminate the peak noise and ringing effect. Further, as shown in Figure 19 , the ultra-low power digital isolator of the isolated CMOS, the logic input and output buffer of each isolation channel are isolated by double-capacitance silicon dioxide insulated gate.

[0097] As shown in Figure 10 , the sampling rate of the present application is controllable, , the time stamp is aligned, and as shown in Figure 11 , the empty collection is 10min without packet loss or multiple packets. The effect of 2 times comb filtering is as shown in Figure 12 , the single-channel empty collection is verified in the laboratory, and the filtering effect is verified. The amplitude is obviously smaller before and after filtering, and the FFT transform is performed on the data before and after filtering, and it can be obviously seen that the signal is obviously attenuated at 50HZ machine harmonic. The present application realizes the compression of about half of the electrophysiological signal on the MCU, and the bandwidth can be theoretically improved by one time.

[0098] As shown in Figure 13 , the present application utilizes the on-chip CACHE hardware (high-speed buffer memory, SPX3819 chip in Figure 17 , the ripple is 800uv, and the LDO with lower ripple output can be replaced. Figure 19The SPI isolation chip in ISO7041 is replaced by a higher speed SPI isolation chip to realize a higher sampling rate) to accelerate data reading, perfect the 128-channel electrophysiological signal acquisition device, and plan to go to Shanghai Traditional Chinese Medicine this week to collect 128-channel electroencephalogram signals; replace the LDO with a higher common-mode rejection ratio, and replace the SPI isolation chip with a higher speed (i.e., the ripple output of the LDO can be reduced from 800uv to about 10uv, and the communication speed of the SPI isolation chip can be increased from 2M to 150M), to realize a sampling rate of 30k / 128ch, transmit through USB3.0 wired transmission, and simultaneously utilize a data compression algorithm to compress the bandwidth to realize the first block wireless transmission module.

[0099] Working principle:

[0100] The application can realize strict synchronous acquisition and ultra-low power consumption control of 128-channel electrophysiological signals. Under the constraint of maintaining the total power consumption of the system <0.3mW (2kS / s / channel), the synchronous sampling timing control problem of a high-density electrode array (>=128 channels) is solved, and the signal phase deviation caused by clock jitter (>+ / -5ns) among multiple channels is eliminated.

[0101] The application realizes real-time power frequency interference suppression with O(1) computational complexity. The time complexity, the execution time of the algorithm, is independent of the input size, and is constant level complexity. The present scheme needs 0(K) multiplication and addition calculations, while the operation steps of the present scheme only need 6 steps, which are independent of K. If K=200 under 10KHZ sampling, the present scheme needs 150ns, and the traditional scheme needs 400 operations, 10us. Under the condition of limited microcontroller resources, a filtering method with constant level computational complexity (only 2 times of subtraction per sample) is provided for 50 / 60Hz and harmonic interference, which achieves >40dB attenuation, while retaining the characteristics of bioelectric signals in the 0.5-500Hz frequency band (passband fluctuation <0.5dB).

[0102] The application supports dynamic parameter configuration of multi-modal signal acquisition; an adaptive adjustment mechanism based on the spectral characteristics of target signals (EEG: 0.5-100Hz, SEMG: 20-500Hz, LFP: 0.1-500Hz) is constructed to realize online reconstruction of sampling rate (1-20kHz), gain (PGA192) and bandwidth, and replace the fixed parameter mode of the existing ASIC scheme. The sampling rate is controlled by an on-chip timer (such as Figure 10 The gain amplification is realized by the INTAN RHD2132 front-end fixed amplification.

[0103] The present application guarantees stable throughput of 128 channels full data rate transmission; establishes 480Mbps continuous transmission channel with zero packet loss rate, satisfies 128 channels, 20kHz / 16-bit sampling generates ≥41Mbps data flow, overcomes the defects of low efficiency of USB2.0 protocol and limited transmission distance (≤5 meters) of UWB wireless transmission.

[0104] The above specific embodiments are specific supports for the scheme idea of the present application, and cannot be used to limit the protection scope of the present application. Any equivalent change or equivalent modification made on the basis of the technical scheme of the present application according to the technical idea of the present application still belongs to the protection scope of the technical scheme of the present application.

Claims

1. A multi-channel electrophysiological signal acquisition system, characterized by, include: A controller, and a power supply module, an analog front-end chipset, a filter module, and an analog-to-digital conversion module electrically connected to the controller; The analog front-end chipset is used to acquire analog signals and preprocess the analog signals to obtain preprocessed analog signals. The pre-processed analog signal is converted into a digital signal through the filter module and the analog-to-digital converter module, and the digital signal is transmitted to the controller. The controller transmits the acquired digital signals to the processing unit; The filter module is used for filtering and noise reduction. The timer module connected to the controller generates a sampling frequency and sends the sampling frequency to the analog-to-digital converter module to provide timing signals to the analog-to-digital converter module; The filter module includes filters, which are cascaded comb filters. Each stage of a cascaded comb filter has the same delay length K; The filter attenuates high frequencies by two subtractions, forming the transfer function H(z) = (1 - z -K ) 2 ; Z is the complex frequency variable of the discrete system; In real-time processing, a circular buffer delay line is used to reduce memory overhead.

2. The multi-channel electrophysiological signal acquisition system of claim 1, wherein: The analog front-end chipset includes multiple analog front-end chips; the output of the analog front-end chips is connected to the controller via a cascaded SPI bus, and the input of the analog front-end chips is connected to a data transmission interface for acquiring analog signals from the device under test.

3. The multi-channel electrophysiological signal acquisition system of claim 1, wherein: The power supply module includes a power supply, which is introduced through a power interface. One pin of the power interface is grounded, and the other pin leads out the power supply through a power switch. The power supply supplies power to the analog LDO circuit and the digital LDO circuit respectively. The analog LDO circuit outputs AVCC power, and the AVCC power is grounded through an AVCC filter circuit. The digital LDO circuit outputs DVCC power, which is grounded through a DVCC filter circuit.

4. The multi-channel electrophysiological signal acquisition system of claim 3, wherein: The controller includes an MCU control chip, the crystal oscillator terminal of the MCU control chip is connected to a crystal oscillator circuit, and the CLK pin, NSS pin, MISO pin, and MOSI pin of the IO port group PA, IO port group PB, IO port group PC, and IO port group PD of the MCU control chip are respectively connected to the FPC connector of the corresponding data transmission interface through the channel digital isolator of the corresponding analog front-end chip group. The MCU control chip is also connected to a USB interface circuit; the debugging interface of the MCU control chip is also connected to an FPC connector. The DVCC power supply is connected to the warning terminal of the MCU control chip through a series current-limiting resistor R4 and indicator light LED2.

5. A method of multichannel electrophysiological signal acquisition, characterized by: The multi-channel electrophysiological signal acquisition system according to any one of claims 1-4 is used, comprising the following steps: The analog signal of the device under test is acquired through the data transmission interface connected to the input of the analog front-end chipset; the analog signal is preprocessed by the analog front-end chipset and then fed into the filter module and analog-to-digital converter module to convert the preprocessed analog signal into a discrete digital signal. The converted digital signal is then connected to the controller via a cascaded SPI bus. The acquired digital signals are analyzed using the control methods in the controller; The timer module connected with the controller generates a sampling frequency, and the sampling frequency is transmitted to the analog-digital conversion module to provide a timing signal for the analog-digital conversion module, so that the multi-channel electric physiological signal acquisition is realized.

6. The method of claim 5, wherein: The algorithm of the filter comprises: Step 1, processing input samples and generating intermediate output; Step 2, processing the output of step 1 and generating final output; the step comprises calculating output, updating delay line and updating pointer.

7. The method of claim 6, wherein: Step 1 is first-level processing: Compute the output of step one: use the formula y1 = x n - h1[ptr1]; where: x n is the current input sample, h1[ptr1] is the value at the location of the pointer ptr1 in the first delay line, representing the input delayed by K samples, i.e. x[n-K]; the difference equation y1[n] = x[n] - x[n-K], i.e. the current input sample minus the input sample delayed by K samples; Write the current input sample into the current position of the first delay line, i.e. x n Write h1[ptr1]; make sure that the value of the write position represents the new delayed input at the next sampling period, update the delay line; The pointer is increased in a loop mode, that is, (ptr1+1)modK is used to update ptr1; the pointer is ensured to be in the range of 0 to K-1 and to be looped, so that efficient buffer management is realized; Step 2 is second-level processing: The output of step 2 is calculated by using the formula y2=y1-h2[ptr2]; Wherein: y1 is the first-level output sample, h2[ptr2] is the value of the pointer ptr2 in the second-level delay line, and represents the first-level output delay K samples, that is, y1[n-K]; the difference equation y2[n]=y1[n]-y1[n-K] is realized, that is, the first-level output sample is subtracted by the value of the delay K samples; The current first-level output sample y1 is written into the current position of the second-level delay line, that is, y1 is written into h2[ptr2], and the delay line is updated; the pointer is increased in a loop mode, that is, (ptr2+1)modK is used to update ptr2, and the pointer is updated; y2 is used as the final output sample after filtering, and the output result is obtained; Each sample is subjected to twice subtraction and twice memory writing; 2K words are used for storing the delay line h1 and the delay line h2 per channel; K samples are introduced by the first-level processing.

8. The method of claim 7, wherein: The zero frequency is , ; where: f s is the sampling rate, k is an integer index; K is the delay length; the zero frequency represents the point at which the filter gain is zero.

Images