A time domain airborne electromagnetic induction B-field signal acquisition system and method

Abstract

The application belongs to the field of airborne electromagnetic detection, and particularly relates to a time-domain airborne electromagnetic induction B-field signal collection system and method, which comprises the following units: a signal input stage unit, which converts the amplified collection signal into a single-ended induction voltage signal; a reference compensation unit, which outputs a bipolar reference compensation voltage signal; a signal integration unit, which receives the single-ended induction voltage signal and the reference compensation voltage signal, converts the signals into current signals through an integration resistance network, and then outputs an integrated reconstructed B-field signal; an analog-to-digital conversion unit, which converts the single-ended induction voltage signal into 24-bit dB / dt collection data and converts the integrated reconstructed B-field signal into 24-bit integrated reconstructed B-field collection data; and a digital control logic unit, which generates compensation data, adds the compensation data to the 24-bit integrated reconstructed B-field collection data, and obtains large-dynamic-range compensation reconstructed B-field collection data. The application significantly improves the measurement dynamic range of the induction B-field signal and improves the deep target body detection capability.

Description

Technical Field

[0001] This application belongs to the field of airborne electromagnetic detection, specifically a time-domain airborne electromagnetic induction B-field signal acquisition system and method. Background Technology

[0002] Current research indicates a significant difference in the detection capabilities of magnetic field strength B and magnetic induction dB / dt for underground good conductors, with B-field data exhibiting stronger detection capability for deep good conductors compared to dB / dt. This includes: from the perspective of electromagnetic methods, B-field data has a single solution within a uniform half-space model; B-field data reflects deep good conductors earlier, has larger anomalous amplitudes, and is less affected by background noise from the geomagnetic field; from a frequency composition perspective, the power spectrum of the B-field excitation waveform with the same total power has more energy at low frequencies than the dB / dt power spectrum; and in the time constant domain of the B-field response, the principal time constant range is superior to that for detecting targets with large time constants.

[0003] The measurement of inductive B-field can be divided into numerical integration methods and analog integration methods. Most current research focuses on numerical integration of sampled values ​​of magnetic induction dB / dt, followed by checking or fitting. In numerical integration methods, if the sampling rate of the integrand data magnetic induction dB / dt is too low, it will lead to an increase in the error of the integration result; while a high sampling rate may cause a large accumulation of quantization error during the reconstruction process, forming a contradictory relationship that is difficult to balance.

[0004] In the existing technology, the induced magnetic field value is obtained by integration through analog integrating circuits. However, the comparison results show that the advantages of analog integration method over digital integration method are not obvious. Furthermore, the complexity of analog integration method requires dedicated hardware circuits, which limits its applicability. Summary of the Invention

[0005] The first aspect of this application provides a time-domain airborne electromagnetic induction B-field signal acquisition system, which overcomes the shortcomings of the aforementioned background technology in inductive B-field measurement.

[0006] The second aspect of this application also provides a time-domain airborne electromagnetic induction B-field signal acquisition method.

[0007] A time-domain airborne electromagnetic induction type B-field signal acquisition system according to an embodiment of the first aspect of this application includes:

[0008] The signal input stage unit selects different channels according to the type of preamplifier the acquired signal passes through, and converts the amplified acquired signal into a single-ended induced voltage signal.

[0009] The reference compensation unit outputs a bipolar reference compensation voltage signal;

[0010] The signal integration unit receives the single-ended induced voltage signal and the reference compensation voltage signal, converts them into current signals through an integrating resistor network, and then outputs the integrated reconstructed B-field signal through a sensitivity-adjustable integrator.

[0011] The analog-to-digital conversion unit converts the single-ended induced voltage signal into 24-bit dB / dt acquisition data and the integral reconstruction B-field signal into 24-bit integral reconstruction B-field acquisition data.

[0012] The digital control logic unit resets the state of the sensitivity adjustable integrator before the start of each measurement cycle. During signal acquisition, it monitors the signal amplitude of the 24-bit integral reconstruction B-field acquisition data in real time. When it detects that the 24-bit integral reconstruction B-field acquisition data is close to saturation, it triggers the compensation mechanism, selects the reference compensation unit to output a positive or negative reference compensation voltage signal, and generates 24+N-bit compensation data. This data is then added to the 24-bit integral reconstruction B-field acquisition data to obtain the 24+N-bit compensated reconstruction B-field acquisition data.

[0013] Furthermore, the signal input stage unit includes an instrumentation amplifier, a voltage follower, and a gating switch K1. When the preamplifier outputs a differential TEM induced voltage signal, the signal is selected to be input to the instrumentation amplifier. When the preamplifier outputs a single-ended TEM induced voltage signal, the signal is selected to be input to the voltage follower. The gating switch K1 switches between the instrumentation amplifier and the voltage follower connected to the signal integration unit.

[0014] Furthermore, the reference compensation unit includes a bipolar reference source and a decoding switch K2, and the decoding switch K2 is controlled by a digital control logic unit to select and output a bipolar reference compensation voltage signal.

[0015] Further: The signal integration unit includes an integrating resistor network R1, an integrating resistor network R2, and a sensitivity-adjustable integrator. The integrating resistor network R1 receives a single-ended induced voltage signal from the signal input stage unit, and the integrating resistor network R2 receives a reference compensation voltage signal from the reference compensation unit. The output terminals of the integrating resistor networks R1 and R2 are connected to the input terminal of the sensitivity-adjustable integrator.

[0016] Further: The sensitivity-adjustable integrator includes: a differential amplifier U1, an operational amplifier U2, a sensitivity gating switch K4, three capacitors C1, C2, and C3 with different capacitance values, a discharge resistor R3, a discharge switch K3, a low-pass filter, an adjustment resistor R4, and an adjustment resistor R5; wherein, the inverting input terminal of the differential amplifier U1 serves as the input terminal of the sensitivity-adjustable integrator, the non-inverting input terminal is grounded, and the positive and negative output terminals are respectively connected to the non-inverting and inverting input terminals of the operational amplifier U2; the common terminal of the sensitivity gating switch K4 is connected to the inverting input terminal of the differential amplifier U1, and the switching terminal of the sensitivity gating switch K4 is connected to one end of capacitor C1, capacitor C2, or capacitor C3 by switching. The other ends of capacitors C1, C2, and C3 are connected together to the output of operational amplifier U2. The discharge resistor R3 and discharge switch K3 form a series structure, which is then connected in parallel with the sensitivity selection switch K4 and the series structure of three capacitors C1, C2, or C3 with different capacitance values. The entire parallel structure serves as a feedback loop. The control terminal of discharge switch K3 is connected to the digital control logic unit. The input terminal of the low-pass filter is connected to the inverting input terminal of differential amplifier U1, and the output terminal is connected to the positive output terminal of differential amplifier U1 through adjusting resistor R4. The negative output terminal of differential amplifier U1 is grounded through adjusting resistor R5. The resistance values ​​of adjusting resistor R5 and adjusting resistor R4 are equal to balance the input resistance value of operational amplifier U2.

[0017] Further: The digital control logic unit includes a positive comparator, a negative comparator, a first D flip-flop, a second D flip-flop, an adder / subtractor, a multiplier, and an adder. The positive and negative comparators respectively determine whether the input 24-bit integral reconstruction B-field acquisition data is greater than a set positive or negative limit value, and output corresponding positive or negative limit value judgment flag signals. The output of the positive comparator is connected to the input of the first D flip-flop, and the output of the negative comparator is connected to the input of the second D flip-flop. The first and second D flip-flops synchronize the positive and negative limit value judgment flag signals with the sampling clock and output them to the decoding switch K2. The adder / subtractor subtracts the total number of times the positive and negative limit value judgment flag signals are counted within one integration cycle to obtain the count difference. The multiplier converts the count difference into the total integral value within the integration cycle, and then converts it into 24+N bit compensation data quantized in the same way as the analog-to-digital conversion unit.

[0018] Furthermore: the sampling clock, through a counter, outputs a cycle reset signal to the sensitivity adjustable integrator for a short period before the end of each measurement cycle, thereby resetting the sensitivity adjustable integrator.

[0019] A time-domain airborne electromagnetic induction B-field signal acquisition method according to a second aspect of this application includes:

[0020] Depending on the type of preamplifier the acquired signal passes through, different channels are selected to convert the amplified acquired signal into a single-ended induced voltage signal.

[0021] Output a bipolar reference compensation voltage signal;

[0022] The system receives a single-ended induced voltage signal and a reference compensation voltage signal, converts them into current signals, and then outputs the integrated B-field signal via a sensitivity-adjustable integrator.

[0023] The single-ended induced voltage signal is converted into 24-bit dB / dt acquisition data, and the integral reconstruction B-field signal is converted into 24-bit integral reconstruction B-field acquisition data.

[0024] Before the start of each measurement cycle, the state of the sensitivity adjustable integrator is reset. During the signal acquisition process, the signal amplitude of the 24-bit integral reconstruction B-field acquisition data is monitored in real time. When the 24-bit integral reconstruction B-field acquisition data is detected to be close to saturation, the compensation mechanism is triggered, the reference compensation unit is selected to output a positive reference compensation voltage signal or a negative reference compensation voltage signal, and 24+N-bit compensation data is generated and added to the 24-bit integral reconstruction B-field acquisition data to obtain 24+N-bit compensated reconstruction B-field acquisition data.

[0025] Compared with the prior art, the beneficial effects of this application are as follows: The embodiments of this application reconstruct the B-field signal through a hardware synchronous integration architecture, and combine periodic charge reset and closed-loop reference voltage compensation, which will significantly improve the measurement dynamic range of the inductive B-field signal in airborne electromagnetic detection and enhance the detection capability of deep targets. Attached Figure Description

[0026] Figure 1 A schematic diagram of the time-domain airborne electromagnetic induction B-field signal acquisition system provided for this application;

[0027] Figure 2 Circuit diagram of the time-domain airborne electromagnetic induction B-field signal acquisition system provided for this application;

[0028] Figure 3 Circuit diagram of a sensitivity-adjustable integrator provided in the embodiments of this application;

[0029] Figure 4 This is a schematic diagram illustrating the effect of data compensation and reconstruction provided in an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0031] Combination Figure 1 and Figure 2 As shown, this application provides a time-domain airborne electromagnetic induction B-field signal acquisition system, comprising:

[0032] The signal input stage unit selects different channels according to the type of preamplifier the acquired signal passes through, and converts the amplified acquired signal into a single-ended induced voltage signal.

[0033] The reference compensation unit outputs a bipolar reference compensation voltage signal;

[0034] The signal integration unit receives the single-ended induced voltage signal and the reference compensation voltage signal, converts them into current signals through an integrating resistor network, and then outputs the integrated reconstructed B-field signal through a sensitivity-adjustable integrator.

[0035] The analog-to-digital conversion unit converts the single-ended induced voltage signal into 24-bit dB / dt acquisition data and the integral reconstruction B-field signal into 24-bit integral reconstruction B-field acquisition data.

[0036] The digital control logic unit resets the state of the sensitivity adjustable integrator before the start of each measurement cycle. During signal acquisition, it monitors the signal amplitude of the 24-bit integral reconstruction B-field acquisition data in real time. When it detects that the 24-bit integral reconstruction B-field acquisition data is close to saturation, it triggers the compensation mechanism, selects the reference compensation unit to output a positive or negative reference compensation voltage signal, and generates 24+N-bit compensation data. This 24+N-bit compensation data is then added to the 24-bit integral reconstruction B-field acquisition data to obtain the 24+N-bit compensated reconstruction B-field acquisition data.

[0037] The signal input stage unit includes an instrumentation amplifier, a voltage follower, and a gating switch K1. It can select and process the input signal of the entire circuit as a differential TEM (transient electromagnetic) induced voltage signal or a single-ended TEM induced voltage signal, convert the input signal into a single-ended signal and perform the first stage of amplification, and output the amplified single-ended induced voltage signal.

[0038] The reference compensation unit includes a bipolar reference source and a decoding switch K2. The decoding switch K2 is controlled by a digital control logic unit to select and output a bipolar reference compensation voltage signal.

[0039] The signal integration unit includes an integrating resistor network R1, an integrating resistor network R2, and a sensitivity-adjustable integrator. The integrating resistor network R1 receives a single-ended induced voltage signal from the signal input stage unit, and the integrating resistor network R2 receives a reference compensation voltage signal from the reference compensation unit. The output terminals of the integrating resistor networks R1 and R2 are connected to the input terminals of the sensitivity-adjustable integrator, which outputs the integrated reconstructed B-field signal.

[0040] The analog-to-digital conversion unit includes a 24-bit dual-channel analog-to-digital converter, which converts the amplified single-ended induced voltage signal output from the signal input stage and the integral reconstructed B-field signal output from the signal integration unit into 24-bit dB / dt acquisition data and 24-bit integral reconstructed B-field acquisition data, respectively.

[0041] The digital control logic unit includes a positive comparator, a negative comparator, a first D flip-flop, a second D flip-flop, an adder / subtractor, a multiplier, and an adder. The positive and negative comparators determine whether the input 24-bit integral reconstruction B-field acquisition data is greater than a set positive or negative limit value, and output the corresponding positive or negative limit value judgment flag signal. The output of the positive comparator is connected to the input of the first D flip-flop, and the output of the negative comparator is connected to the input of the second D flip-flop. The first and second D flip-flops synchronize the positive and negative limit value judgment flag signals with the sampling clock and output them to the decoding switch K2, respectively.

[0042] The addition and subtraction unit subtracts the total number of positive limit value judgment flag signals and negative limit value judgment flag signals within one integration cycle to obtain the difference in the number of times.

[0043] The multiplier converts the difference in number of times into the total integral value within the integration period, and then into 24+N bits of compensation data that is quantized in the same way as the analog-to-digital conversion unit.

[0044] The sampling clock, through a counter, outputs a cycle reset signal to the sensitivity-adjustable integrator a short period before the end of each measurement cycle, thereby resetting the sensitivity-adjustable integrator.

[0045] In this embodiment, firstly, an additional preamplifier should be provided to collect the induced electromotive force in the receiving coil. Due to the different structures of the preamplifier, it may output a single-ended TEM induced voltage signal or a differential TEM induced voltage signal. Therefore, an effective channel should be selected through an external control signal. For example, the differential TEM induced voltage signal will be converted into a single-ended signal by an instrumentation amplifier, buffered by a voltage follower, and output a uniformly amplified single-ended signal with a voltage range of ±10V.

[0046] The reference compensation unit outputs a bipolar reference compensation voltage signal. The bipolar reference voltage source can be implemented by integrating a reference voltage chip and an inverting amplifier. The settling time deviation of the decoding switch K2 can be eliminated by pre-calibration. Alternatively, a bipolar current source structure can be used to replace the bipolar reference voltage source and the integrating resistor network R2.

[0047] The pre-calibration stage also uses a bipolar reference voltage source as the calibration source. In the calibration of the integration stage, the enable decoder switch K2 is connected to the reference voltage for a period of time, and the actual integration time constant is calculated by the output value data of the sensitivity adjustable integrator.

[0048] The sensitivity-adjustable integrator should be of a type with extremely low leakage current, such as a high-quality audio crossover capacitor. The integrating resistor networks R1 and R2 should have low relative accuracy and low relative temperature coefficient.

[0049] See the adjustable sensitivity integrator. Figure 3 As shown, the system includes: a differential amplifier U1, an operational amplifier U2, a sensitivity gating switch K4, three capacitors C1, C2, and C3 with different capacitance values, a discharge resistor R3, a discharge switch K3, a low-pass filter, and adjustment resistors R4 and R5. The inverting input of the differential amplifier U1 serves as the input of the sensitivity-adjustable integrator, while the non-inverting input is grounded. The positive and negative outputs are connected to the non-inverting and inverting inputs of the operational amplifier U2, respectively. The common terminal of the sensitivity gating switch K4 is connected to the inverting input of the differential amplifier U1. The switching terminal of the sensitivity gating switch K4 is connected to one end of either capacitor C1, C2, or C3. The other ends of capacitors C1, C2, and C3 are all connected to the output of the operational amplifier U2.

[0050] After the discharge resistor R3 and the discharge switch K3 form a series structure, they are then connected in parallel with the sensitivity selection switch K4 and three capacitors C1, C2, or C3 of different capacitance values ​​in a series structure. The entire parallel structure serves as a feedback loop. The control terminal of the discharge switch K3 is connected to the digital control logic unit. The input terminal of the low-pass filter is connected to the inverting input terminal of the differential amplifier U1, and the output terminal is connected to the positive output terminal of the differential amplifier U1 through the adjusting resistor R4. The negative output terminal of the differential amplifier U1 is grounded through the adjusting resistor R5. The adjusting resistor R5 has the same resistance value as the adjusting resistor R4 to balance the input resistance value of the operational amplifier U2.

[0051] Sensitivity conditions are achieved by switching different capacitance values ​​of the integrating capacitor using the gating switch K1. The resistance value and settling time of the gating switch K1 will cause deviations in the output value of the integrating circuit, which can be eliminated in the pre-calibration stage. In the adjustable sensitivity integrator, the differential amplifier U1 and operational amplifier U2 form a two-stage amplification structure. The differential amplifier U1 provides high input impedance characteristics and should use a JFET input type operational amplifier or a discrete JFET differential amplifier circuit. The operational amplifier U2 increases the driving capability and should have low noise characteristics.

[0052] To eliminate the high input bias voltage characteristic of differential amplifier U1 and prevent the influence of bias voltage from accumulating in the integrating capacitor, a low-pass filter is used to sample the DC component of the input side of differential amplifier U1. The output bias compensation voltage is compensated in real time at the differential output of differential amplifier U1 through adjusting resistors R4 and R5. The low-pass filter samples the input DC component, and its cutoff frequency can be set to be lower than the fundamental frequency of the aviation electromagnetic system. A zero-bias operational amplifier is used as the input stage of the low-pass filter. Adjusting resistors R4 and R5 should be designed as adjustable resistors in advance. The resistance values ​​of adjusting resistors R4 and R5 are determined by testing the compensation results, thus forming a zero-drift, sensitivity-adjustable integrator.

[0053] The periodic reset in the sensitivity-adjustable integrator is achieved through a series connection of discharge switch K3 and discharge resistor R3. During the last short period of each measurement cycle (which can be preset), a reset signal sent by the digital control logic unit turns on discharge switch K3, triggering the discharge operation. The discharge time constant is determined by discharge resistor R3, the on-resistance of the discharge switch, and capacitance. The voltage decay during discharge follows the zero-input response of an RC series circuit. For better reset performance, the resistance of discharge resistor R3 should be as small as possible.

[0054] The analog-to-digital conversion unit uses a 24-bit Σ-Δ ADC chip, with a ±10V input drive circuit at its front end and an integrated anti-aliasing filter. The clocks of the two acquisition channels are strictly synchronized. The operating mode of the ADC chip can be flexibly configured through the bus interface of the digital logic control unit.

[0055] In this embodiment, the digital control logic unit, including the positive and negative comparators, determines the limit value in each sampling clock cycle. The limit value is set under the condition that, after reaching the limit, the output of the sensitivity-adjustable integrator will not saturate even after the reference compensation voltage signal and the single-ended induced voltage signal of the same polarity are simultaneously injected for another sampling clock cycle. The width of the counter should be sufficient to count the product of the sampling clock frequency and the on-time. The arithmetic logic unit, counter, multiplier, and adder should also be synchronized with the sampling clock signal.

[0056] The multiplier and adder form a multiply-add relationship. The multiplier is used to adjust the effect of the injected reference compensation voltage signal on the output of the sensitivity-adjustable integrator to the same quantization as the analog-to-digital converter unit, before the addition operation can be performed. The effect of the reference compensation voltage signal on the output of the sensitivity-adjustable integrator within one sampling clock cycle is used as the minimum quantization value. ,in The sampling clock frequency, The reference compensation voltage signal value corresponds to the minimum quantization value of the analog-to-digital converter unit. .

[0057] Before the start of each measurement cycle, the digital control logic unit resets the state of the sensitivity-adjustable integrator. During signal acquisition, the digital control logic unit monitors the signal amplitude in real time, and immediately triggers the compensation mechanism when it detects near-saturation. After a complete measurement cycle, 24+N bit compensated data is generated and added to the 24-bit integrally reconstructed B-field acquisition data to obtain 24+N bit compensated reconstructed B-field acquisition data, as shown in the figure. Figure 4 As shown, Figure 4 The dashed line represents the 24-bit integral reconstruction B-field acquisition data, and the solid line represents the 24+N-bit compensated reconstruction B-field acquisition data. It can be seen that a measurement cycle includes the on-time, off-time, and reset time. During the on-time, the clamped 24-bit integral reconstruction B-field acquisition data is compensated to obtain the 24+N-bit compensated reconstruction B-field acquisition data with complete amplitude.

[0058] If no compensation and reconstruction process is required, and only the counter and sampling clock provide periodic integration and reset in the digital control logic unit, the sensitivity-adjustable integrator can be set to low sensitivity by utilizing the regularity of the differential TEM induced voltage signal. This involves selecting the capacitor with the highest capacitance among capacitors C1, C2, and C3, thus achieving non-saturation of the sensitivity-adjustable integrator output while always disabling the reference compensation voltage signal. Special attention needs to be paid to the selection of the integrating resistor R1 and the low-sensitivity capacitor. When the emitted current waveform is a trapezoidal or triangular wave, the selection conditions are as follows:

[0059] ,in and These are the input and output voltages of the sensitivity-adjustable integrator, respectively. The rise time for transmitting a trapezoidal or triangular wave. Indicates a sampling period. This refers to the capacitor in the sensitivity-adjustable integrator.

[0060] This application achieves B-field integral reconstruction through a sensitivity-adjustable integrator: a low-pass filter is added to the sensitivity-adjustable integrator, and the high input bias voltage characteristic of the differential amplifier U1 is removed by sampling input bias to prevent the influence of bias voltage from accumulating in the integrating capacitor; a discharge switch K3 and a resistor R3 are added to the sensitivity-adjustable integrator to form a periodic charge discharge circuit.

[0061] The 24+N bit compensated reconstruction B-field acquisition data closed-loop compensation loop achieves high resolution. The reference compensation unit responds to the decoding command and outputs a positive or negative reference compensation voltage to the signal integration unit. The integrated reconstruction B-field signal output by the signal integration unit is converted into 24-bit integrated reconstruction B-field acquisition data by the analog-to-digital converter. The digital control logic unit enables the positive or negative reference compensation voltage or the negative reference compensation voltage in real time according to the 24-bit integrated reconstruction B-field acquisition data, so that the integrated reconstruction B-field signal is away from the power rail. The adjustment amount of the reference compensation voltage is quantized into 24+N bit compensation data through counters and multipliers, and added to the 24-bit integrated reconstruction B-field acquisition data to obtain the 24+N bit compensated reconstruction B-field acquisition data, realizing the acquisition of 24+N bit compensated reconstruction B-field acquisition data with high dynamic range.

[0062] On the other hand, embodiments of this application provide a time-domain airborne electromagnetic induction type B-field signal acquisition method, including: selecting different channels according to the different types of preamplifiers through which the acquired signal passes, and converting the amplified acquired signal into a single-ended induced voltage signal;

[0063] Output a bipolar reference compensation voltage signal;

[0064] The system receives a single-ended induced voltage signal and a reference compensation voltage signal, converts them into current signals, and then outputs the integrated B-field signal via a sensitivity-adjustable integrator.

[0065] The single-ended induced voltage signal is converted into 24-bit dB / dt acquisition data, and the integral reconstruction B-field signal is converted into 24-bit integral reconstruction B-field acquisition data.

[0066] Before the start of each measurement cycle, the state of the sensitivity adjustable integrator is reset. During the signal acquisition process, the signal amplitude of the 24-bit integral reconstructed B-field acquisition data is monitored in real time. When the 24-bit integral reconstructed B-field acquisition data is detected to be close to saturation, the compensation mechanism is triggered, the reference compensation unit is selected to output a positive reference compensation voltage signal or a negative reference compensation voltage signal, and 24+N-bit compensation data and 24-bit integral reconstructed B-field acquisition data are generated and added together to obtain 24+N-bit compensated reconstructed B-field acquisition data.

[0067] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A time-domain airborne electromagnetic induction type B-field signal acquisition system, characterized in that, include: The signal input stage unit selects different channels according to the type of preamplifier the acquired signal passes through, and converts the amplified acquired signal into a single-ended induced voltage signal. The reference compensation unit outputs a bipolar reference compensation voltage signal; The signal integration unit receives the single-ended induced voltage signal and the reference compensation voltage signal, converts them into current signals through an integrating resistor network, and then outputs the integrated reconstructed B-field signal through a sensitivity-adjustable integrator. The analog-to-digital conversion unit converts the single-ended induced voltage signal into 24-bit dB / dt acquisition data and the integral reconstruction B-field signal into 24-bit integral reconstruction B-field acquisition data. The digital control logic unit resets the state of the sensitivity adjustable integrator before the start of each measurement cycle. During signal acquisition, it monitors the signal amplitude of the 24-bit integral reconstruction B-field acquisition data in real time. When it detects that the 24-bit integral reconstruction B-field acquisition data is close to saturation, it triggers the compensation mechanism, selects the reference compensation unit to output a positive or negative reference compensation voltage signal, and generates 24+N-bit compensation data. This data is then added to the 24-bit integral reconstruction B-field acquisition data to obtain the 24+N-bit compensated reconstruction B-field acquisition data.

2. The time-domain airborne electromagnetic induction type B-field signal acquisition system according to claim 1, characterized in that, The signal input stage unit includes an instrumentation amplifier, a voltage follower, and a gating switch K1. When the preamplifier outputs a differential TEM induced voltage signal, the input is selected to the instrumentation amplifier. When the preamplifier outputs a single-ended TEM induced voltage signal, the input is selected to the voltage follower. The gating switch K1 switches between the instrumentation amplifier and the voltage follower connected to the signal integration unit.

3. The time-domain airborne electromagnetic induction type B-field signal acquisition system according to claim 1, characterized in that, The reference compensation unit includes a bipolar reference source and a decoding switch K2. The decoding switch K2 is controlled by a digital control logic unit to select and output a bipolar reference compensation voltage signal.

4. The time-domain airborne electromagnetic induction type B-field signal acquisition system according to claim 1, characterized in that, The signal integration unit includes an integrating resistor network R1, an integrating resistor network R2, and a sensitivity-adjustable integrator. The integrating resistor network R1 receives a single-ended induced voltage signal from the signal input stage unit, and the integrating resistor network R2 receives a reference compensation voltage signal from the reference compensation unit. The output terminals of the integrating resistor networks R1 and R2 are connected to the input terminal of the sensitivity-adjustable integrator.

5. A time-domain airborne electromagnetic induction type B-field signal acquisition system according to claim 3, characterized in that, The sensitivity-adjustable integrator includes: a differential amplifier U1, an operational amplifier U2, a sensitivity gating switch K4, three capacitors C1, C2, and C3 with different capacitance values, a discharge resistor R3, a discharge switch K3, a low-pass filter, and adjustment resistors R4 and R5. The inverting input of the differential amplifier U1 serves as the input of the sensitivity-adjustable integrator, the non-inverting input is grounded, and the positive and negative outputs are connected to the non-inverting and inverting inputs of the operational amplifier U2, respectively. The common terminal of the sensitivity gating switch K4 is connected to the inverting input of the differential amplifier U1. The switching terminal of the sensitivity gating switch K4 is connected to one end of either capacitor C1, C2, or C3. The other ends of capacitors C1, C2, and C3 are all connected to the output of the operational amplifier U2. After the discharge resistor R3 and the discharge switch K3 form a series structure, they are then connected in parallel with the sensitivity selection switch K4 and the series structure of three capacitors C1, C2 or C3 with different capacitance values. The entire parallel structure serves as a feedback loop, and the control terminal of the discharge switch K3 is connected to the digital control logic unit. The input terminal of the low-pass filter is connected to the inverting input terminal of the differential amplifier U1, and the output terminal is connected to the positive output terminal of the differential amplifier U1 through the adjusting resistor R4. The negative output terminal of the differential amplifier U1 is grounded through the adjusting resistor R5. The adjusting resistor R5 and the adjusting resistor R4 have the same resistance value to balance the input resistance value of the operational amplifier U2.

6. A time-domain airborne electromagnetic induction type B-field signal acquisition system according to claim 1, characterized in that, The digital control logic unit includes a positive comparator, a negative comparator, a first D flip-flop, a second D flip-flop, an adder / subtractor, a multiplier, and an adder. The positive and negative comparators determine whether the input 24-bit integral reconstruction B-field acquisition data is greater than a set positive or negative limit value, and output the corresponding positive or negative limit value judgment flag signal. The output of the positive comparator is connected to the input of the first D flip-flop, and the output of the negative comparator is connected to the input of the second D flip-flop. The first and second D flip-flops synchronize the positive and negative limit value judgment flag signals with the sampling clock and output them to the decoding switch K2, respectively. The addition and subtraction unit subtracts the total number of positive limit value judgment flag signals and negative limit value judgment flag signals within one integration cycle to obtain the difference in the number of times. The multiplier converts the difference in number of times into the total integral value within the integration period, and then into 24+N bit compensation data that is quantized in the same way as the analog-to-digital conversion unit.

7. A time-domain airborne electromagnetic induction type B-field signal acquisition system according to claim 6, characterized in that: The sampling clock, through a counter, outputs a cycle reset signal to the sensitivity-adjustable integrator a short period before the end of each measurement cycle, thereby resetting the sensitivity-adjustable integrator.

8. A time-domain airborne electromagnetic induction B-field signal acquisition method, employing the time-domain airborne electromagnetic induction B-field signal acquisition system according to any one of claims 1-7, characterized in that: Depending on the type of preamplifier the acquired signal passes through, different channels are selected to convert the amplified acquired signal into a single-ended induced voltage signal. Output a bipolar reference compensation voltage signal; The system receives a single-ended induced voltage signal and a reference compensation voltage signal, converts them into current signals, and then outputs the integrated B-field signal via a sensitivity-adjustable integrator. The single-ended induced voltage signal is converted into 24-bit dB / dt acquisition data, and the integral reconstruction B-field signal is converted into 24-bit integral reconstruction B-field acquisition data. Before the start of each measurement cycle, the state of the sensitivity adjustable integrator is reset. During the signal acquisition process, the signal amplitude of the 24-bit integral reconstruction B-field acquisition data is monitored in real time. When the 24-bit integral reconstruction B-field acquisition data is detected to be close to saturation, the compensation mechanism is triggered, the reference compensation unit is selected to output a positive reference compensation voltage signal or a negative reference compensation voltage signal, and 24+N-bit compensation data is generated and added to the 24-bit integral reconstruction B-field acquisition data to obtain 24+N-bit compensated reconstruction B-field acquisition data.

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