Circuit board manufacturing process monitoring method and system, terminal and storage medium

Abstract

The invention provides a circuit board manufacturing process monitoring method and system, a terminal and a storage medium, and belongs to the technical field of circuit board manufacturing, and the method comprises the steps: selecting a key process node as a target support plate process node, and defining an abnormal state in advance based on a process specification or historical data; after the nodes are processed, process information is obtained, and associated monitoring information is extracted; comparing the monitoring information with a preset threshold value, and if the monitoring information exceeds the preset threshold value, triggering an exception handling process; and collecting and processing data in real time, obtaining a processing effect, evaluating the response capability of the processing process in combination with monitoring information, and finally performing feedback optimization. Through abnormal state adjustment, abnormity definition, multi-level threshold comparison and closed-loop feedback, monitoring accuracy and timeliness are improved, and hysteresis of traditional static monitoring is avoided. And in combination with evaluation indexes and historical data tracing, quantitative evaluation and continuous optimization of the exception handling capacity are realized, and the stability and reliability of the IC carrier plate manufacturing process are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit board manufacturing, and particularly relates to a circuit board manufacturing process monitoring method and system, a terminal and a storage medium. BACKGROUND

[0002] IC carrier boards, as a key component of chip packaging, play an extremely important role in the semiconductor industry. Its main function is to provide electrical connection, mechanical support and heat dissipation channel for chips, and it is a bridge for efficient interconnection and intercommunication between chips and external circuits, directly affecting the performance and reliability of electronic products.

[0003] In terms of process, IC carrier board manufacturing process is complex and requires high standards, similar to PCB process. Common processes include subtractive process and additive process. The subtractive process forms a circuit on the substrate through full plating, pattern plating or hybrid plating; the additive process is divided into full additive, semi-additive and partial additive, among which semi-additive process (SAP) and modified semi-additive process (mSAP) are widely used.

[0004] In the current processing technology, the plating node and the drilling node are identified by equipment number record, which is easy to be tampered with or the old equipment is eliminated, and the historical data of the old equipment is still used to identify the new equipment, resulting in that the abnormal data of the copper thickness of the new equipment is incorrectly associated with the historical defect record of the old equipment, and finally misjudges the new equipment "insufficient copper thickness" to trigger unnecessary downtime maintenance, delaying production.

[0005] In some processes, the threshold for determining abnormal state is usually set based on the initial process specification, without considering factors such as equipment aging and environmental changes, which may increase processing errors and affect product quality. After the execution of some abnormal processing procedures, only whether the final parameters meet the standards is verified, without analyzing the adjustment time and process switching times of the processing process, resulting in repeated occurrence of similar abnormalities and reduced production line efficiency. Moreover, the correlation between abnormal state and monitoring indicators is fixed, and the triggering conditions are not adjusted according to the influence level of abnormal types. SUMMARY

[0006] The application provides a circuit board manufacturing process monitoring method, which clearly defines abnormal determination standards to improve the targeting of monitoring, and timely acquires and extracts key information to improve abnormal identification efficiency and accuracy.

[0007] The method comprises: Step S101: In each key process node of the IC carrier board manufacturing process, at least one is selected as a target carrier board process node; for each target carrier board process node, its corresponding carrier board process abnormal state is defined in advance according to the process specification or historical abnormal state data; Step S102: After the target carrier board process node completes the current carrier board process treatment process, target carrier board process information stored in the node is acquired; Step S103: Carrier board process monitoring information directly associated with the abnormal state of the carrier board process is extracted from the target carrier board process information; Step S104: The carrier board process monitoring information is compared with the determination threshold of the abnormal state of the carrier board process set in advance for the target carrier board process node, and if the monitoring information exceeds the determination threshold range, the carrier board process abnormal processing flow for the target carrier board process node is triggered; Step S105: During the execution of the carrier board process abnormal processing flow, monitoring data of the processing process is collected in real time, and final processing effect data is acquired after the processing is completed; Step S106: The processing effect data is compared and verified with the process specification requirement of the target carrier board process node, the response capability of the target carrier board process treatment process to the abnormal state of the carrier board process is evaluated in combination with the carrier board process monitoring information and the processing process monitoring data, and feedback is performed.

[0008] Preferably, step S101 further comprises the following steps: A candidate carrier board process node set of the IC carrier board manufacturing process is determined; Process correlation analysis is performed on the preliminary screening target node to evaluate its dependence relationship with upstream and downstream processes, and in combination with its key path position in the overall process flow, a core node with an impact weight ≥ 30% on the final carrier board quality is further selected from the preliminary screening target node as a final target carrier board process node; For each final target carrier board process node, key quality characteristics in its process specification file are extracted, and historical abnormal state data of the node in a preset time period is collected to establish a mapping relationship between the process specification requirement and the historical abnormal state characteristics; Based on the mapping relationship between the process specification requirement and the historical abnormal state characteristics, a specific carrier board process abnormal state type and a corresponding abnormal triggering condition are defined for each target carrier board process node; According to real-time process fluctuation data, the triggering condition of the carrier board process abnormal state is adjusted to ensure that the abnormal state definition is adapted to the current process environment.

[0009] Preferably, step S101 further comprises the following steps: In the IC carrier board manufacturing process, a node identity token is set for each key process node, and the token is fixed with the node type, device number and process sequence code; All abnormal state records and parameter drift records of the node in the historical running period are collected, and the abnormal state type, occurrence frequency and parameter limit value are written into the node exclusive abnormal state register as the first data source for defining the carrier board process abnormal state; An association field is established between the node identity token and the exception state register, and the association field allows the exception state register content to be read or updated only after the node identity token is verified successfully; According to the exception state register content, an exception state description file is generated for each node, and the exception state description file is indexed by the node identity token and is synchronized and migrated with the node; When the node enters the target board process node candidate pool, the identity token is verified and the consistency check is performed on the exception state description file, and only when the two are completely matched, the node is allowed to be selected as the target board process node, thereby completing the node locking.

[0010] Preferably, step S104 specifically comprises the following steps: Classify the board process exception state of the target board process node, and configure an exception type; Assign corresponding board process monitoring information indicators to each exception type; Obtain the historical process data of the target board process node, and calculate the determination threshold value corresponding to each exception type; Compare each indicator in the board process monitoring information with the determination threshold value of the corresponding exception type, and record the exception indicators exceeding the threshold value and their deviation degrees; According to the deviation degree of the exception indicators and the influence level of the exception type, it is comprehensively judged whether to trigger the board process exception handling process.

[0011] Preferably, step S106 further comprises the following steps: Determine a target backup process node in the target board process node; Read the data stored in the target backup process node through a preset target interface to obtain initial board process monitoring information; Modify the data stored in the target backup process node, and introduce the board process exception state in the target backup process node; Determine the modified data backed up in the target backup process node as target board process information, and extract board process monitoring information from the target board process information; the board process monitoring information includes at least one of a process parameter deviation value corresponding to the exception feature, a data integrity mark, or a processing timeliness indicator; When the board process exception state includes an exception of the target backup process node, store the modified data backed up in the target backup process node into other backup process nodes except the target backup process node; read other substrate process monitoring information stored in the other backup process nodes through the target interface, compare the initial substrate process monitoring information with the other substrate process monitoring information to obtain a first comparison result; determine whether the abnormal response capability of the target substrate process control flow of the target substrate process node is normal based on the first comparison result; if the first comparison result indicates that the two information are the same, it is determined that the abnormal response capability is normal; if they are different, it is determined that the abnormal response capability is abnormal.

[0012] Preferably, step S106 further comprises the following steps: Define an evaluation index system, including abnormal handling success rate, handling timeliness compliance rate, and process parameter eligibility rate after handling; Adjust the weight of each evaluation index according to the type of the abnormality; Synchronize the evaluation result to the process control device of the circuit board process to generate a monitoring feedback containing optimization suggestions; Store the evaluation result of this time in association with historical evaluation data to form a historical database of abnormal handling effects; the historical database is used as a reference basis for optimizing evaluation index weights or adjusting decision thresholds in monitoring; When the evaluation result of the same type of abnormality continuously falls below a preset standard, trigger the process optimization flow of the circuit board process.

[0013] Preferably, step S106 further comprises the following steps: For the target substrate process node, divide a plurality of evaluation information according to its process specification requirements; Correspond the handling effect data, substrate process monitoring information, and processing process monitoring data to each evaluation information respectively, and calculate the actual value of each evaluation information; Set a weight value for each evaluation information; Multiply the actual value of each evaluation information by the corresponding weight value and accumulate to obtain a comprehensive score of the response capability of the target substrate process handling process to the abnormal state of the substrate process; Generate feedback information according to the interval in which the comprehensive score falls; the feedback containing process parameter maintenance suggestions when the score is higher than a first score threshold, the feedback containing parameter fine-tuning scheme when the score is between the first score threshold and a second score threshold, and the feedback containing abnormal handling flow optimization instructions when the score is lower than the second score threshold, and synchronize the feedback information to the process control device and the corresponding target substrate process node.

[0014] The application also provides a circuit board manufacturing process monitoring system, which comprises: A node locking module is used to select at least one as a target substrate process node in each key process node of the IC substrate manufacturing process; for each target substrate process node, its corresponding substrate process abnormal state is defined in advance according to the process specification or historical abnormal state data; An original data acquisition module is configured to acquire target carrier board process information stored by a node after a target carrier board process node completes a current carrier board process treatment process; An abnormal feature extraction module is configured to extract carrier board process monitoring information directly associated with an abnormal state of a carrier board process from the target carrier board process information; A threshold comparison triggering module is configured to compare the carrier board process monitoring information with a judgment threshold of an abnormal state of a carrier board process pre-set by the target carrier board process node, and if the monitoring information exceeds the range of the judgment threshold, trigger a carrier board process abnormality treatment process for the target carrier board process node to be started; A process monitoring acquisition module is configured to acquire monitoring data of a treatment process in real time during the execution of the carrier board process abnormality treatment process, and acquire final treatment effect data after the treatment is completed; A response evaluation feedback module is configured to compare and verify the treatment effect data with process specification requirements of the target carrier board process node, evaluate the response capability of the target carrier board process treatment process to the abnormal state of the carrier board process in combination with the carrier board process monitoring information and the monitoring data of the treatment process, and provide feedback.

[0015] According to another embodiment of the present application, a terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the circuit board manufacturing process monitoring method when executing the program.

[0016] According to another embodiment of the present application, a terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the circuit board manufacturing process monitoring method when executing the program.

[0017] From the above technical solutions, the present application has the following advantages: The circuit board manufacturing process monitoring method provided by the present application ensures the uniqueness of a target carrier board process node and the data tamper resistance by using a node identity token, and solidifying the association field design of node types, equipment numbers, process sequence codes, and abnormal state registers, thereby avoiding the monitoring failure problem caused by the confusion of node identities or the tampering of data in traditional processes. The judgment threshold generated based on historical defect records replaces the fixed threshold, and adapts to the process fluctuations caused by equipment aging and changes in environmental temperature and humidity. Through abnormal type classification and monitoring index matching, combined with the trigger judgment of the influence level, redundant processing is avoided, and the abnormal response time is shortened. Through comparison and verification of the treatment effect data and the process specification, feedback containing optimization suggestions and parameter correction values is generated, thereby improving the process stability.

[0018] The application simulates the exception through the backup node, does not need to trigger the exception in the actual production node, guarantees the continuity of the IC carrier plate manufacturing process, verifies the processing effect of the process control flow on the exception data through the preset exception characteristics and the comparison of the redundant node data, and ensures the safety of the data storage through the design of the redundant backup node, so that the monitoring is not interrupted due to the single node failure. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the present application, the drawings needed to be used in the description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0020] Figure 1 The flow chart of the circuit board manufacturing process monitoring method; Figure 2 The schematic diagram of the circuit board manufacturing process monitoring system; Figure 3 The schematic diagram of the terminal. DETAILED DESCRIPTION

[0021] The IC carrier plate manufacturing process involved in the circuit board manufacturing process monitoring method provided in the present application covers more than ten processes such as material preparation, circuit processing, lamination, drilling, electroplating, and surface treatment.

[0022] Process nodes are set at each process of the IC carrier plate manufacturing process as the monitoring points of the process data. The terminal is set at the monitoring point, and the terminal is a device capable of automatically performing numerical calculation and / or information processing according to the pre-set or stored instructions. The hardware of the terminal includes but is not limited to microprocessors, application specific integrated circuits, programmable gate arrays, digital processors, embedded devices, etc.

[0023] Specifically, the data mainly monitored by the substrate and core plate processing nodes are as follows: material parameters: CTE (Z-axis direction is usually 10-18 ppm / ℃), Dk (dielectric constant, such as PTFE carrier plate Dk≈2.1), Df (loss factor, ≤0.001), Tg (glass transition temperature, ≥180℃), copper foil type (rolled copper RCF or electrolytic copper EDC). Size data: core plate thickness (such as 0.1mm, 0.2mm), dimensional tolerance (±0.1mm).

[0024] The data monitored by the inner layer circuit manufacturing node includes: circuit parameters: line width (L) / line spacing (S) (such as 5 / 5 μm, 3 / 3 μm), line thickness (copper thickness, such as 12 μm), annular ring (such as not less than 8 μm). Abnormal state data: the number of short circuit / short circuit detected by AOI, gap / spur size (such as a gap length > 20 μm is determined as defective).

[0025] The data monitored by the drilling node includes: hole parameters: hole diameter (such as 80 μm, 50 μm), hole site accuracy (deviation from design coordinate ≤±15 μm), hole depth (blind hole depth tolerance ±20 μm), hole wall roughness (Ra≤0.5 μm). Drilling quality: number of holes (such as 50-200 holes per square centimeter), uniformity of hole density distribution.

[0026] The data monitored by the electroplating node includes: plating thickness: chemical copper plating layer thickness (5-10 μm), full-plate electroplated copper thickness (20-35 μm), electroplated nickel layer thickness (3-6 μm), electroplated gold layer thickness (0.05-3 μm). Electroplating uniformity: copper thickness deviation on the same panel (≤±5%), hole copper coverage (≥95%).

[0027] The data monitored by the outer layer circuit manufacturing node includes: circuit accuracy: outer layer L / S (such as 3 / 3 μm), circuit edge roughness (LER≤10 μm). Pattern alignment accuracy: outer layer and inner layer circuit alignment deviation (≤±20 μm).

[0028] The data monitored by the surface treatment manufacturing node includes: plating thickness: chemical gold Ni thickness (3-6 μm), Au thickness (0.05-0.15 μm); electroplated gold Ni thickness (3-6 μm), Au thickness (0.5-3 μm). Surface performance: solderability (wetting time ≤3 s), bonding force (no peeling in grid test).

[0029] The data monitored by the forming and testing node includes: forming size: carrier plate length and width (such as 10 mm×10 mm), thickness (such as 0.2 mm), shape tolerance (±20 μm). Electrical parameters: on-resistance (≤50 mΩ), insulation resistance (≥100 MΩ). Reliability data: crack rate after temperature cycle test (≤0.1%), plating layer peeling area after thermal shock (≤0.01%).

[0030] The circuit board manufacturing process monitoring method related to the present application will be described in detail below. For the purpose of illustration but not for the purpose of limitation, specific details such as specific system structures, technologies, etc. are presented in order to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details.

[0031] It should be understood that the word "comprise" or "comprising" or "including" or "including" or "has" or "having" as stated in the specification herein specifies the presence of stated features, integers, steps, operations, elements, or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. The terms "comprise", "include", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0032] The phrase "one embodiment" or "some embodiments" appearing in the specification of the present application means that the particular feature, structure or characteristic described in the embodiment is included in one or more embodiments of the present application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in some other embodiments" appearing in the specification of the present application are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized.

[0033] In embodiments of the present application, computer program code for carrying out operations of the present disclosure can be written in one or more programming languages or combinations thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" language or similar programming languages. Program code can be executed entirely on a user computer, partially on a user computer, as a separate software package, partially on a user computer and partially on a remote computer, or entirely on a remote computer. In the case of remote computers, the remote computer can be connected to the user computer through any kind of network, including local area network (LAN) or wide area network (WAN), or can be connected to external computers (for example, using an Internet service provider to connect through the Internet).

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0035] Please refer to Figure 1 The flowchart of the line board manufacturing process monitoring method in a specific embodiment is shown, and the method comprises: Step S101: In each key process node of the IC carrier manufacturing process, at least one target carrier process node is selected; for each target carrier process node, its corresponding carrier process abnormal state is defined in advance according to the process specification or historical abnormal state data.

[0036] In some embodiments, the key monitoring nodes are selected from the key processes of the IC carrier manufacturing, and the abnormal state judgment basis is set for the key monitoring nodes.

[0037] Specifically, the key processes in the whole process, such as substrate processing, drilling, electroplating, etc., are sorted out, and the target nodes are selected in combination with the influence degree of each node on product quality, historical fault frequency and other factors; then the specific performance of each abnormal state is determined according to the parameter standard in the process specification and the historical abnormal state data, for example, the drilling aperture exceeding the design value ± 5 μm is defined as the abnormal state of the drilling node.

[0038] The step S101 provided in the application also involves the following specific steps, specifically including: Step S1011: In the IC carrier manufacturing process, a node identity token is set for each key process node, the token is fixed with the node type, equipment number and process sequence code, so that the node has a unique and tamper-proof identity in the network; Step S1012: Collect all abnormal state records and parameter drift records of the node in the historical running period, write the abnormal state type, occurrence frequency and parameter limit value into the node exclusive abnormal state register as the first data source for defining the carrier process abnormal state; Step S1013: An association field is established between the node identity token and the abnormal state register, and the content of the abnormal state register can only be read or updated after the node identity token is verified successfully, to prevent unauthorized external writing; Step S1014: According to the content of the abnormal state register, a replaceable abnormal state description file is generated for each node, the abnormal state description file is indexed by the node identity token, and is synchronized and migrated with the node; Step S1015: When the node enters the target carrier process node candidate pool, the consistency check of the identity token and the abnormal state description file is verified, and only when the two are completely matched, the node is allowed to be selected as the target carrier process node, so as to complete the node locking.

[0039] The step S101 of the embodiment realizes strong binding of node identity and abnormal state history by assigning an uncopyable identity token to each key process node and solidifying an abnormal state register inside the node; before a node is selected as a target carrier board process node, a bidirectional consistency check of the identity token and the abnormal state description file must be completed to ensure that the source of the abnormal state is real and has not been tampered with; this method can complete node screening and abnormal definition on site without a central database, reducing data coupling degree and improving on-site adaptability.

[0040] Step S102: After the target carrier board process node completes the current carrier board process treatment process, the target carrier board process information stored by the node is obtained.

[0041] In some embodiments, after the target node completes the current process treatment, the process information generated by the target node is collected. Specifically, when the target node completes a batch of product treatment, the data in the treatment process of the batch is obtained through the data storage module built in the node or the database connected with the node, including the treatment time, the concentration of the chemical reagent used, the equipment operation parameter, etc.

[0042] Step S103: Extracting carrier board process monitoring information directly related to the abnormal state of the carrier board process from the target carrier board process information.

[0043] In some embodiments, the data directly related to the preset abnormal state is screened from the target process information, and the key monitoring indicators are focused. Specifically, according to the carrier board process abnormal state defined in step S101, the corresponding parameters are extracted from the target carrier board process information, for example, if the abnormal state includes weak plating layer adhesion, the adhesion test data is extracted; if the abnormal state involves dimensional deviation, the feature size measurement value is extracted, etc.

[0044] Step S104: Comparing the carrier board process monitoring information with the determination threshold of the carrier board process abnormal state preset by the target carrier board process node, if the monitoring information exceeds the determination threshold range, triggering the printed circuit board process to start the carrier board process abnormal treatment process for the target carrier board process node.

[0045] In some embodiments, by comparing the monitoring information with the determination threshold, it is determined whether there is an abnormality, and then the corresponding processing process is triggered to realize timely response to the abnormality. Specifically, the carrier board process monitoring information extracted in step S103 is compared with the determination threshold set in step S101, if the monitoring information exceeds the threshold range, the abnormality treatment process for the target node is started, such as adjusting the drilling equipment parameters or suspending production for maintenance. Through the comparison of the clear threshold, the rapid identification of the abnormality and the timely triggering of the processing process are realized, avoiding the expansion of the abnormality to cause more product abnormal states, and improving the process stability.

[0046] Step S105: During the execution of the carrier board process exception handling flow, real-time acquisition of monitoring data of the processing process is performed, and final processing effect data is obtained after the processing is completed.

[0047] In some embodiments, relevant data is collected during the exception handling process and after the processing, to provide a basis for evaluating the processing effect. Specifically, during the execution of the carrier board process exception handling flow, monitoring data such as parameter adjustment during the processing process and device running state changes is recorded in real time; after the processing is completed, secondary detection data of the product, processing time consumption and other effect data are obtained.

[0048] Step S106: The processing effect data is compared and verified with the process specification requirements of the target carrier board process node, the response capability of the target carrier board process handling process to the abnormal state of the carrier board process is evaluated in combination with the carrier board process monitoring information and the processing process monitoring data, and feedback is performed.

[0049] In some embodiments, the response capability of the process to the exception is evaluated in combination with relevant data by comparing the processing effect with the process specification, and the result is fed back to realize continuous optimization.

[0050] Specifically, the processing effect data is compared with the process specification requirements of the target node, and at the same time, the carrier board process monitoring information and the processing process monitoring data are combined to analyze the rationality of parameter adjustment during the processing process, whether the processing time consumption is within a reasonable range, etc., to evaluate the response capability and form a feedback report, such as suggesting to adjust the parameter adjustment amplitude in the abnormal handling flow. Through evaluation and feedback, the process handling process and the exception response mechanism are continuously optimized, the processing capability of the process to the exception is improved, the continuous improvement of the IC carrier board manufacturing process is realized, and the product quality and production efficiency are improved.

[0051] In some specific embodiments, step S106 specifically includes the following steps: S1061. Define an evaluation index system, including an exception handling success rate, a processing time efficiency compliance rate, and a processing after parameter compliance rate; Among them, the exception handling success rate is calculated based on the ratio of the number of nodes actually eliminating the exception to the number of nodes triggering the exception handling flow, the processing time efficiency compliance rate is calculated based on the ratio of the actual processing time consumption to the preset standard time consumption, and the processing after parameter compliance rate is calculated based on the compliance degree of the processing after parameter to the process specification allowable range.

[0052] S1062. Adjust the weight of each evaluation index according to the exception type; for example, for parameter deviation type exception, the weight of the processing after parameter compliance rate is increased; for time efficiency sensitive exception, the weight of the processing time efficiency compliance rate is increased; the weight adjustment is set based on the correlation analysis result of different exception types and evaluation indexes in historical exception data.

[0053] S1063. Synchronize the evaluation result to the process control device of the circuit board process to generate monitoring feedback containing optimization suggestions; the optimization suggestions include at least one of adjusting the process parameter threshold of the target circuit board process node, modifying the trigger condition of the abnormality processing flow, or updating the monitoring rule of the process control device.

[0054] S1064. Store the evaluation result of this time in association with historical evaluation data to form a historical database of abnormality processing effect; the historical database is used as a reference basis for optimizing evaluation index weight or adjusting decision threshold in monitoring.

[0055] S1065. Trigger the process optimization flow of the circuit board process when the evaluation result of the same type of abnormality continuously falls below the preset standard; the process optimization flow includes at least one of adjusting the equipment parameter of the target circuit board process node, redefining the circuit board process abnormality state, or adding a redundant verification step of the abnormality processing flow.

[0056] In step S106 of the embodiment, the circuit board process abnormality processing capability is evaluated and optimized, multi-dimensional evaluation indexes including success rate, time limit compliance rate, and parameter qualification rate are defined, and the weight of each index is adjusted according to the abnormality type; the evaluation result is synchronized to the process control device to generate optimization suggestions, and is stored in the historical database; when the evaluation result continuously fails to meet the standard, the process optimization flow is triggered to adjust the equipment parameter or the abnormality processing rule. Through evaluation and feedback, subjectivity in evaluation is avoided, and continuous optimization of abnormality processing capability is realized.

[0057] In an embodiment of the present application, based on step S104, a possible embodiment will be given below to non-limitingly describe the specific implementation scheme. Step S104 specifically includes the following steps: Step S1041: Classify the circuit board process abnormality state of the target circuit board process node, and configure the abnormality type.

[0058] Optionally, the abnormality type involves specific abnormality types such as circuit short circuit, hole wall roughness exceeding the standard, copper thickness deficiency, weak plating layer adhesion, or size deviation exceeding the limit. According to the common problems of IC circuit board manufacturing process, the circuit board process abnormality state is divided into specific identifiable abnormality types, and the representation form of each abnormality is determined.

[0059] Step S1042: Assign corresponding circuit board process monitoring information indexes to each abnormality type.

[0060] Optionally, the circuit board process monitoring information indexes include but are not limited to: circuit short circuit corresponding line width / line spacing deviation value, hole wall roughness exceeding the standard corresponding roughness measurement value, copper thickness deficiency corresponding copper thickness detection value, weak plating layer adhesion corresponding adhesion test value, and size deviation exceeding the limit corresponding feature size deviation amount.

[0061] For each abnormal type, the monitoring information index that best reflects the severity of the abnormal type is screened out, such as the Ra value corresponding to the hole wall roughness exceeding the standard, the copper thickness measurement value corresponding to the insufficient copper thickness, and the monitoring index corresponding to the abnormal type.

[0062] Step S1043: Obtain the historical process data of the target carrier board process node, and calculate the determination threshold value corresponding to each abnormal type.

[0063] The setting method of the determination threshold value can be based on the mean value ± 3 times the standard deviation of the historical normal data, or a fixed threshold range set according to the process specification.

[0064] Step S1044: Compare each index in the carrier board process monitoring information with the dynamic determination threshold value of the corresponding abnormal type, and record the abnormal index and its deviation degree that exceeds the threshold value.

[0065] The deviation degree includes: the line width deviation value is +8μm, the upper limit of the threshold value is +5μm, and the deviation degree is +3μm; the Ra roughness measurement value is 0.6μm, the upper limit of the threshold value is 0.5μm, and the deviation degree is +0.1μm.

[0066] Step S1045: According to the deviation degree of the abnormal index and the influence level of the abnormal type, it is comprehensively judged whether to trigger the carrier board process abnormality processing flow.

[0067] It should be noted that the carrier board process abnormality processing flow involves triggering immediately when the deviation degree of the key abnormal index exceeds 50% of the threshold range, and triggering when the deviation degree of the secondary abnormal index exceeds 100% of the threshold range.

[0068] Exemplarily, according to the influence level of the abnormal type, the line width abnormality affects the product yield by 15%, which is a key abnormality; the Ra abnormality affects the yield by 5%, which is a secondary abnormality, and the line width deviation exceeds 50% of the threshold value, i.e. +2.5μm, and the Ra deviation exceeds 100% of the threshold value, i.e. +0.1μm, and it is comprehensively judged whether to trigger the abnormality processing flow.

[0069] The step S104 of the embodiment adjusts the threshold value by using the historical data, and comprehensively evaluates the multi-dimensional monitoring index according to the influence level of the abnormal type, so as to ensure that the processing flow is triggered only when the abnormality that truly affects the process quality occurs, and invalid intervention is avoided.

[0070] In an embodiment of the present application, based on step S106, a possible embodiment will be given below to non-limitingly illustrate the specific implementation scheme. Step S106 further includes the following steps: S2061: According to the process specification requirements of the target carrier board process node, a plurality of evaluation information is divided, including the parameter compliance rate after abnormality processing, the deviation rate of the processing process time and the standard time length, and the change rate of the abnormal state quantity before and after processing.

[0071] S2062: The processing effect data, carrier board process monitoring information and processing process monitoring data are respectively corresponded to each evaluation information, and the actual value of each evaluation information is calculated, wherein the parameter compliance rate is the proportion of the number of compliant parameter items to the total number of parameter items, the deviation rate is the ratio of (actual time length-standard time length) to the standard time length, and the change rate is the ratio of (abnormal state number before processing-abnormal state number after processing) to the abnormal state number before processing.

[0072] S2063: A weight value is set for each evaluation information, and the weight value is determined according to the influence degree of the dimension on the process stability, such as the parameter compliance rate weight is set to 40%, the deviation rate weight is set to 30%, and the change rate weight is set to 30%, and the sum of the weight values of each dimension is 100%.

[0073] S2064: The actual value of each evaluation information is multiplied by the corresponding weight value and then accumulated to obtain the comprehensive score of the response ability of the target carrier board process to the abnormal state of the carrier board process.

[0074] Optionally, the calculation method of the comprehensive score is parameter compliance rate x 40% + (1-|deviation rate|) x 30% + change rate x 30%, wherein the absolute value of the deviation rate is taken to avoid positive and negative offset, 1-|deviation rate| ensures that the closer the time length is to the standard, the higher the score is, and the evaluation information of multiple dimensions is realized by weighted integration.

[0075] S2065: According to the interval where the comprehensive score is located, feedback information is generated, the feedback of the score higher than the first score threshold value contains process parameter maintenance suggestion, the feedback of the first score threshold value to the second score threshold value contains parameter fine-tuning scheme, and the feedback of the score lower than the second score threshold value contains abnormality processing flow optimization instruction, and the feedback information is synchronized to the process control device and the corresponding target carrier board process node.

[0076] It should be noted that the comprehensive score is compared with the preset threshold value, such as the first score threshold value is 80 points and the second score threshold value is 60 points, different intervals correspond to different feedback strategies, the high score interval indicates that the current processing flow is effective, the middle and low score intervals correspond to parameter fine-tuning or flow reconstruction respectively, and the feedback information is written through the interface of the process control device to directly guide subsequent process adjustment.

[0077] The embodiment evaluates the response effect of the target carrier board process to the abnormal state, combines the importance of each dimension to obtain evaluation information, generates targeted feedback information, and realizes the continuous optimization of the process.

[0078] In an embodiment of the present application, based on step S101, a possible embodiment will be given below to specifically illustrate the non-limiting embodiment. Step S101 further comprises the following steps: Step S2011: Determine the candidate substrate process node set of the IC substrate manufacturing process, which contains all the key process nodes, and through process complexity evaluation and historical abnormal state rate statistics, select the nodes with high process complexity and historical abnormal state rate ≥5% as the preliminary screening target nodes.

[0079] This embodiment lists all the key process nodes, excludes the nodes with simple process and low abnormal state rate through process complexity evaluation and historical abnormal state rate statistics, and retains the preliminary screening nodes with complex process and high abnormal state rate.

[0080] Optionally, the key process nodes can be substrate and core plate processing, drilling, electroplating, outer layer circuit processing, surface treatment, molding and testing, etc. The process complexity is the number of process steps, equipment precision requirement and operation difficulty.

[0081] Step S2012: Perform process correlation analysis on the preliminary screening target nodes, evaluate their dependence on upstream and downstream processes, and further select core nodes with an impact weight ≥30% on the final substrate quality from the preliminary screening target nodes as the final target substrate process nodes based on their key path position in the overall process flow.

[0082] Step S2013: For each final target substrate process node, extract the key quality characteristics in its process specification file, collect the historical abnormal state data of the node within a preset time period, and establish the mapping relationship between the process specification requirements and the historical abnormal state characteristics.

[0083] It should be noted that the key quality characteristics refer to the CTE value range of substrate and core plate processing, the hole diameter tolerance of drilling, and the copper thickness target value of electroplating. The historical abnormal state data includes abnormal state type, occurrence frequency and severity.

[0084] For each node, extract the key quality characteristics in the process specification, collect the historical abnormal state data, and establish the mapping relationship between the abnormality and yield loss.

[0085] Step S2014: Based on the mapping relationship between the process specification requirements and the historical abnormal state characteristics, define the specific substrate process abnormal state type and the corresponding abnormal trigger condition for each target substrate process node.

[0086] Step S2015: According to the real-time process fluctuation data, adjust the trigger condition of the substrate process abnormal state, ensure that the abnormal state definition is adapted to the current process environment, and avoid false positives or false negatives caused by environmental changes.

[0087] Therefore, step S101 screens out the core node with the greatest impact on the quality of the carrier plate based on the process complexity, the abnormal state rate and the critical path analysis; defines the abnormal state with a strong correlation with the actual abnormal state in combination with the process specification and the historical abnormal state data; and adjusts the abnormal triggering condition through real-time process fluctuation to ensure the pertinence and adaptability of the monitoring.

[0088] In an embodiment of the present application, based on step S106, a possible embodiment will be given below to non-restrictively illustrate the specific implementation thereof. Step S106 further includes the following steps: S6021: determining a target backup process node in the target carrier plate process node; The target backup process node is determined by at least one of process control device configuration identification, a monitoring command or a log of the circuit board process, and historical record analysis, and the target backup process node has a uniquely identified block identifier, which is used to locate the target backup process node in the process control device.

[0089] S6022: reading the data stored in the target backup process node through a preset target interface to obtain initial carrier plate process monitoring information; The target interface is a physical or logical interface in the circuit board process control device that communicates with the target backup process node, and the initial carrier plate process monitoring information is the original process data of the target carrier plate process node before the carrier plate process abnormal state is set.

[0090] S6023: modifying the data stored in the target backup process node, and introducing the carrier plate process abnormal state into the target backup process node; the modification method includes adjusting the process parameters, processing result identifiers or associated metadata stored in the target backup process node, so that the backup data in the modified target backup process node meets the preset abnormal characteristics.

[0091] S6024: determining the modified backup data in the target backup process node as the target carrier plate process information, and extracting the carrier plate process monitoring information from the target carrier plate process information; the carrier plate process monitoring information includes at least one of a process parameter deviation value corresponding to the abnormal characteristics, a data integrity mark or a processing timeliness index.

[0092] S6025: when the carrier plate process abnormal state includes an abnormality of the target backup process node, storing the modified data in the target backup process node into other backup process nodes except the target backup process node; the other backup process nodes are redundant storage units associated with the target backup process node in the circuit board process control device.

[0093] S6026: reading other substrate process monitoring information stored in the other backup process nodes through the target interface, comparing the initial substrate process monitoring information with the other substrate process monitoring information to obtain a first comparison result; determining whether the abnormal response capability of the target substrate process control flow of the target substrate process node is normal based on the first comparison result; if the first comparison result indicates that the two pieces of information are the same, it is determined that the abnormal response capability is normal; if they are different, it is determined that the abnormal response capability is abnormal.

[0094] The embodiment determines a target backup process node with a unique identifier in the target substrate process node, reads original data thereof as initial monitoring information; introduces an abnormal state by modifying the node data, takes the modified data as target process information and extracts monitoring information containing abnormal characteristics; when the target backup node is abnormal, stores the modified data to other backup nodes, reads the information thereof and compares it with the initial information to determine whether the abnormal response capability of the target node is normal.

[0095] The unique identifier is used to accurately locate the backup node, ensuring the accuracy of data reading; the original data is compared with the abnormal data to effectively detect the abnormal response capability; the abnormal state based method is close to the actual fault scene, improving the authenticity of monitoring; the cooperative operation of multiple backup nodes enhances the data reliability, ensuring the accuracy of the abnormal judgment result.

[0096] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0097] The following is an embodiment of a circuit board manufacturing process monitoring system provided by the embodiment of the present disclosure. The system and the circuit board manufacturing process monitoring method of each embodiment described above belong to the same inventive concept. Details not described in detail in the embodiment of the circuit board manufacturing process monitoring system can be referred to the embodiment of the circuit board manufacturing process monitoring method described above.

[0098] As shown in Figure 2 The system includes: A node locking module 201 is configured to select at least one as a target substrate process node in each key process node of the IC substrate manufacturing process; for each target substrate process node, its corresponding substrate process abnormal state is defined in advance according to the process specification or historical abnormal state data; An original data acquisition module 202 is configured to acquire target substrate process information stored in the target substrate process node after the target substrate process node completes the current substrate process processing process; The abnormal feature extraction module 203 is configured to extract the substrate process monitoring information directly related to the abnormal state of the substrate process from the target substrate process information. The threshold comparison triggering module 204 is configured to compare the substrate process monitoring information with the determination threshold of the abnormal state of the substrate process of the target substrate process node, and if the monitoring information exceeds the determination threshold, trigger the substrate process to start the substrate process abnormality processing flow for the target substrate process node. The process monitoring collection module 205 is configured to collect the monitoring data of the processing process in real time during the execution of the substrate process abnormality processing flow, and obtain the final processing effect data after the processing is completed. The response evaluation feedback module 206 is configured to compare and verify the processing effect data with the process specification requirement of the target substrate process node, evaluate the response capability of the target substrate process processing process to the abnormal state of the substrate process in combination with the substrate process monitoring information and the processing process monitoring data, and perform feedback.

[0099] As shown in Figure 3 The present application also provides a terminal, which comprises a display module 103, a memory 102, a processor 101, and a computer program stored in the memory and executable on the processor 101, and the processor 101 implements the steps of the circuit board manufacturing process monitoring method when executing the program.

[0100] In the embodiments of the present application, the terminal includes but is not limited to a laptop computer, a desktop computer, a workstation, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The terminal can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the embodiments of the present application described herein and / or claimed.

[0101] In the embodiments of the present application, the processor 101 can be implemented by using at least one of a specific-purpose integrated circuit, a programmable logic device, a field programmable gate array, a processor, a controller, a microcontroller, a microprocessor, an electronic unit designed to perform the functions described herein, and in some cases, such implementation can be implemented in a controller. For software implementation, the implementation of the processes or functions can be implemented with separate software modules that allow at least one function or operation to be performed. The software code can be implemented by a software application (or program) written in any appropriate programming language, which can be stored in the memory and executed by the controller.

[0102] The display module 103 is configured to display information input by a user or information provided to the user. The display module 103 can include a display panel, which can be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.

[0103] The memory 102 can be used to store software programs as well as various data. The memory 102 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device.

[0104] The present application also provides a storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of the circuit board manufacturing process monitoring method.

[0105] The storage medium can employ any combination of one or more of readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0106] In the storage medium, the readable signal medium can include a data signal carried in a baseband or as part of a carrier wave, in which readable program code is carried. Such a propagated data signal can take on many forms, including but not limited to electro-magnetic, optical, or any suitable combination thereof. The readable signal medium can also be any readable medium that is not a readable storage medium and that can be used to carry or store program code for use by or in connection with an instruction execution system, apparatus, or device.

[0107] The above description of disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit board manufacturing process monitoring method, characterized in that: Methods include: S101: Selecting at least one target substrate process node from among key process nodes of an IC substrate manufacturing process; For each target substrate process node, define the corresponding substrate process abnormal state type and trigger conditions in advance based on process specification files or historical abnormal state data; S102: After the target substrate process node completes the current substrate process, the target substrate process information stored in the node is obtained; S103: extracting carrier board process monitoring information directly associated with the abnormal carrier board process state from the target carrier board process information; S104: Comparing the substrate process monitoring information with a substrate process abnormality determination threshold preset for the target substrate process node. If the monitoring information exceeds the determination threshold, triggering the circuit board process to initiate a substrate process abnormality handling process for the target substrate process node. S105: During the execution of the substrate process abnormality handling process, monitoring data of the handling process is collected in real time, and final handling effect data is obtained after the handling is completed; S106: Compare and verify the processing effect data with the process specification requirements of the target substrate process node, combine the substrate process monitoring information and the processing process monitoring data, evaluate the response capability of the target substrate process to the abnormal state of the substrate process, and provide feedback.

2. The circuit board manufacturing process monitoring method according to claim 1, characterized in that: Step S101 also includes the following steps: Determine a set of candidate substrate process nodes for IC substrate manufacturing processes; Conduct process relevance analysis on the initial screening target nodes to assess their dependencies with upstream and downstream processes. Combined with their critical path status in the overall process flow, further select core nodes with a weight of ≥30% impact on the final substrate quality from the initial screening target nodes as the final target substrate process nodes. For each final target substrate process node, extract the key quality characteristics from its process specification file, collect historical abnormal status data of the node within a preset time period, and establish a mapping relationship between process specification requirements and historical abnormal status characteristics; Based on the mapping relationship between process specification requirements and historical abnormal state characteristics, a specific substrate process abnormal state type and corresponding abnormal trigger condition are defined for each target substrate process node; Adjust the trigger conditions for abnormal substrate process conditions based on real-time process fluctuation data to ensure that the abnormal state definition is compatible with the current process environment.

3. The circuit board manufacturing process monitoring method according to claim 1, characterized in that: Step S101 also includes the following steps: In the IC substrate manufacturing process, a node identity token is set for each key process node, and the node type, equipment number and process sequence code are solidified in the token; Collect all abnormal status records and parameter drift records of the node in the historical operation cycle, and write the abnormal status type, occurrence frequency, and parameter limit value into the node-specific abnormal status register as the first data source for defining the abnormal status of the substrate process; Establishing an association field between the node identity token and the exception status register, the association field allows the exception status register content to be read or updated only after the node identity token is successfully verified; Generate an abnormal status description file for each node based on the abnormal status register content. The abnormal status description file is indexed by the node identity token and migrates synchronously with the node movement. When a node enters the target substrate process node candidate pool, it is verified through identity token verification and consistency check of the exception status description file. Only when the two are completely matched will the node be allowed to be selected as the target substrate process node, thus completing node locking.

4. The circuit board manufacturing process monitoring method according to claim 1, characterized in that: Step S104 specifically includes the following steps: Classify the substrate process abnormality status of the target substrate process node and configure the abnormality type; Assign corresponding substrate process monitoring information indicators to each abnormality type; Obtain historical process data for the target substrate process node and calculate the corresponding judgment threshold for each anomaly type; Compare each indicator in the substrate process monitoring information with the corresponding abnormality type judgment threshold, and record the abnormal indicators that exceed the threshold and the degree of deviation; Based on the degree of deviation of the abnormal indicators and the impact level of the abnormal type, a comprehensive judgment is made as to whether the substrate process abnormality handling process should be triggered.

5. The circuit board manufacturing process monitoring method according to claim 1, characterized in that: Step S106 also includes the following steps: Determining a target backup process node in a target carrier board process node; Read the data stored in the target backup process node through a preset target interface to obtain initial carrier board process monitoring information; Modifying the data stored in the target backup process node, and introducing the abnormal state of the carrier process into the target backup process node; Determining the data backed up in the modified target backup process node as target substrate process information, and extracting substrate process monitoring information from the target substrate process information; the substrate process monitoring information includes at least one of a process parameter deviation value, a data integrity flag, or a processing timeliness index corresponding to the abnormal feature; When the abnormal state of the carrier process includes an abnormality in the target backup process node, storing the modified data backed up in the target backup process node in other backup process nodes except the target backup process node; reading other carrier process monitoring information stored in the other backup process nodes through the target interface, and comparing the initial carrier process monitoring information with the other carrier process monitoring information to obtain a first comparison result; Based on the first comparison result, determine whether the abnormal response capability of the target carrier process control flow of the target carrier process node is normal; wherein, if the first comparison result indicates that the two pieces of information are the same, it is determined that the abnormal response capability is normal; if they are different, it is determined that the abnormal response capability is abnormal.

6. The circuit board manufacturing process monitoring method according to claim 1, characterized in that: Step S106 also includes the following steps: Define the evaluation index system, including the success rate of abnormality handling, the rate of timely handling compliance, and the qualified rate of post-treatment process parameters; Adjust the weight of each evaluation indicator according to the anomaly type; Synchronize the evaluation results to the process control device of the circuit board process to generate monitoring feedback including optimization suggestions; The current assessment results are associated with historical assessment data and stored to form a historical database of exception handling effects; the historical database is used as a reference for optimizing assessment indicator weights or adjusting judgment thresholds during monitoring; When the evaluation results of the same type of anomaly continue to be lower than the preset standard, the process optimization process of the circuit board process is triggered.

7. The circuit board manufacturing process monitoring method according to claim 1, characterized in that: Step S106 also includes the following steps: For the target substrate process node, multiple evaluation information is divided according to its process specification requirements; Match the processing effect data, substrate process monitoring information, and processing process monitoring data to each evaluation information, and calculate the actual value of each evaluation information; Set weight values ​​for each evaluation information; The actual value of each evaluation information is multiplied by the corresponding weight value and then added up to obtain a comprehensive score of the target substrate process's response capability to substrate process abnormalities. Feedback information is generated based on the range of the comprehensive score. Feedback for scores above the first score threshold includes process parameter maintenance suggestions, feedback for scores between the first score threshold and the second score threshold includes parameter fine-tuning solutions, and feedback for scores below the second score threshold includes exception handling process optimization instructions. The feedback information is synchronized to the process control device and the corresponding target substrate process node.

8. A circuit board manufacturing process monitoring system, characterized in that: The system is used to implement the circuit board manufacturing process monitoring method according to any one of claims 1 to 7; The system includes: A node locking module is used to select at least one target substrate process node from each key process node of the IC substrate manufacturing process; for each target substrate process node, the corresponding substrate process abnormality state is pre-defined based on the process specification or historical abnormality state data; The original data acquisition module is used to obtain the target substrate process information stored in the node after the target substrate process node completes the current substrate process processing process; An abnormal feature extraction module is used to extract carrier board process monitoring information directly associated with the abnormal state of the carrier board process from the target carrier board process information; A threshold comparison trigger module is used to compare the substrate process monitoring information with the substrate process abnormality judgment threshold pre-set for the target substrate process node. If the monitoring information exceeds the judgment threshold range, the circuit board process is triggered to start the substrate process abnormality handling process for the target substrate process node; The process monitoring and acquisition module is used to collect monitoring data of the processing process in real time during the execution of the substrate process abnormality processing flow, and obtain the final processing effect data after the processing is completed; The response evaluation feedback module is used to compare and verify the processing effect data with the process specification requirements of the target substrate process node, combine the substrate process monitoring information and the processing process monitoring data, evaluate the response capability of the target substrate process to the abnormal status of the substrate process, and provide feedback.

9. A terminal comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the circuit board manufacturing process monitoring method according to any one of claims 1 to 7 are implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the circuit board manufacturing process monitoring method according to any one of claims 1 to 7 are implemented.

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