A circuit board manufacturing process monitoring method, system, terminal and storage medium

Abstract

The application provides a circuit board manufacturing process monitoring method, system, terminal and storage medium, belongs to the circuit board manufacturing technical field, and through selecting a key process node as a target carrier board process node, an abnormal state is defined in advance based on process specifications or historical data; after the node is completed, process information is acquired and associated monitoring information is extracted; the monitoring information is compared with a preset threshold value, and if it exceeds, an abnormal processing flow is triggered; processing data is collected in real time, processing effect is acquired, the response capability of the processing process is evaluated in combination with the monitoring information, and finally optimization is fed back. Through adjusting the abnormal state, defining the abnormality, comparing the multi-level threshold value and closed-loop feedback, the accuracy and timeliness of the monitoring are improved, and the hysteresis of the traditional static monitoring is avoided; in combination with the evaluation index and historical data tracing, quantitative evaluation and continuous optimization of the abnormal processing capability are realized, and the stability and reliability of the IC carrier board manufacturing process are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit board manufacturing, and particularly relates to a circuit board manufacturing process monitoring method and system, a terminal and a storage medium. BACKGROUND

[0002] IC carrier boards, as a key component of chip packaging, play an extremely important role in the semiconductor industry. Its main function is to provide electrical connection, mechanical support and heat dissipation channel for chips, and it is a bridge for efficient interconnection and intercommunication between chips and external circuits, directly affecting the performance and reliability of electronic products.

[0003] In terms of process, IC carrier board manufacturing process is complex and requires high standards, similar to PCB process. Common processes include subtractive process and additive process. The subtractive process forms a circuit on the substrate through full plating, pattern plating or hybrid plating; the additive process is divided into full additive, semi-additive and partial additive, among which semi-additive process (SAP) and modified semi-additive process (mSAP) are widely used.

[0004] In the current processing technology, the plating node and the drilling node are identified by equipment number record, which is easy to be tampered with or the old equipment is eliminated, and the historical data of the old equipment is still used to identify the new equipment, resulting in that the abnormal data of the copper thickness of the new equipment is incorrectly associated with the historical defect record of the old equipment, and finally misjudges the new equipment "insufficient copper thickness" to trigger unnecessary downtime maintenance and delay production.

[0005] In some processes, the threshold of abnormal state is usually set based on the initial process specification, without considering factors such as equipment aging and environmental changes, which may increase processing errors and affect product quality. After the execution of some abnormal processing procedures, only whether the final parameters meet the standards is verified, and the adjustment time and process switching times of the processing process are not analyzed, resulting in repeated occurrence of similar abnormalities and reduced production line efficiency. Moreover, the association between abnormal state and monitoring indicators is fixed, and the trigger condition is not adjusted according to the influence level of abnormal type. SUMMARY

[0006] The application provides a circuit board manufacturing process monitoring method, which clearly defines abnormality determination criteria to improve monitoring specificity, and timely acquires and extracts key information to improve abnormality recognition efficiency and accuracy.

[0007] The method comprises the following steps:

[0008] Step S101: In each key process node of the IC carrier board manufacturing process, at least one is selected as a target carrier board process node; for each target carrier board process node, its corresponding carrier board process abnormal state is defined in advance according to the process specification or historical abnormal state data;

[0009] Step S102: After the target carrier board process node completes the current carrier board process treatment process, target carrier board process information stored in the node is acquired;

[0010] Step S103: Carrier board process monitoring information directly associated with the abnormal state of the carrier board process is extracted from the target carrier board process information;

[0011] Step S104: The carrier board process monitoring information is compared with the determination threshold of the abnormal state of the carrier board process set in advance for the target carrier board process node, and if the monitoring information exceeds the determination threshold range, the carrier board process abnormal treatment process for the target carrier board process node is triggered;

[0012] Step S105: During the execution of the carrier board process abnormal treatment process, monitoring data of the treatment process is collected in real time, and final treatment effect data is acquired after the treatment is completed;

[0013] Step S106: The treatment effect data is compared with the process specification requirement of the target carrier board process node, the response capability of the target carrier board process treatment process to the abnormal state of the carrier board process is evaluated in combination with the carrier board process monitoring information and the treatment process monitoring data, and feedback is performed.

[0014] Preferably, step S101 further comprises the following steps:

[0015] A candidate carrier board process node set of the IC carrier board manufacturing process is determined;

[0016] The process correlation analysis is performed on the preliminary screening target node to evaluate the dependency relationship with the upstream and downstream processes, and the core node with an impact weight ≥ 30% on the final carrier board quality is further selected from the preliminary screening target node as the final target carrier board process node in combination with the key path position in the overall process flow;

[0017] For each final target carrier board process node, the key quality characteristics in the process specification file are extracted, and the historical abnormal state data of the node in a preset time period is collected to establish a mapping relationship between the process specification requirement and the historical abnormal state characteristics;

[0018] Based on the mapping relationship between the process specification requirement and the historical abnormal state characteristics, the specific carrier board process abnormal state type and the corresponding abnormal triggering condition are defined for each target carrier board process node;

[0019] According to the real-time process fluctuation data, the triggering condition of the carrier board process abnormal state is adjusted to ensure that the abnormal state definition is adapted to the current process environment.

[0020] Preferably, step S101 further comprises the following steps:

[0021] In the IC carrier board manufacturing process, a node identity token is set for each key process node, and the token is fixed with node type, equipment number and process sequence code;

[0022] The acquisition node collects all abnormal state records and parameter drift records in the historical operation period, writes the abnormal state type, occurrence frequency and parameter limit value into the node-specific abnormal state register as the first data source for defining the carrier board process abnormal state;

[0023] An association field is established between the node identity token and the abnormal state register, and the content of the abnormal state register can only be read or updated after the node identity token is verified successfully;

[0024] According to the content of the abnormal state register, an abnormal state description file is generated for each node, and the abnormal state description file is indexed by the node identity token and is synchronized with the node migration;

[0025] When the node enters the target carrier board process node candidate pool, consistency verification is performed through identity token verification and abnormal state description file, and only when the two are completely matched can the node be selected as the target carrier board process node, thereby completing the node locking.

[0026] Preferably, step S104 specifically comprises the following steps:

[0027] Classify the carrier board process abnormal state of the target carrier board process node, and configure the abnormal type;

[0028] Assign corresponding carrier board process monitoring information indicators to each abnormal type;

[0029] Obtain the historical process data of the target carrier board process node, and calculate the determination threshold value corresponding to each abnormal type;

[0030] Compare each indicator in the carrier board process monitoring information with the determination threshold value of the corresponding abnormal type, and record the abnormal indicators and their deviation degrees that exceed the threshold value;

[0031] According to the deviation degree of the abnormal indicator and the influence level of the abnormal type, it is comprehensively judged whether to trigger the carrier board process abnormal handling process.

[0032] Preferably, step S106 further comprises the following steps:

[0033] Determine the target backup process node in the target carrier board process node;

[0034] Read the data stored in the target backup process node through a preset target interface to obtain the initial carrier board process monitoring information;

[0035] modify the data stored in the target backup process node, and introduce the carrier plate process abnormal state in the target backup process node;

[0036] determine the modified data backed up in the target backup process node as target carrier plate process information, and extract carrier plate process monitoring information from the target carrier plate process information; the carrier plate process monitoring information includes at least one of a process parameter deviation value corresponding to the abnormal feature, a data integrity mark, or a processing timeliness index;

[0037] When the carrier plate process abnormal state includes an abnormality of the target backup process node, store the modified data backed up in the target backup process node in other backup process nodes except the target backup process node;

[0038] read other carrier plate process monitoring information stored in the other backup process nodes through a target interface, compare the initial carrier plate process monitoring information with the other carrier plate process monitoring information to obtain a first comparison result, and determine whether the abnormal response capability of the target carrier plate process control flow of the target carrier plate process node is normal based on the first comparison result; if the first comparison result indicates that the two information are the same, it is determined that the abnormal response capability is normal; if they are different, it is determined that the abnormal response capability is abnormal.

[0039] Preferably, step S106 further comprises the following steps:

[0040] Define an evaluation index system including an abnormality handling success rate, a processing timeliness compliance rate, and a process parameter eligibility rate after processing;

[0041] Adjust the weight of each evaluation index according to the abnormal type;

[0042] Synchronize the evaluation result to a process control device of the circuit board process to generate a monitoring feedback containing optimization suggestions;

[0043] Store the current evaluation result in association with historical evaluation data to form a historical database of abnormality handling effects; the historical database is used as a reference basis for optimizing evaluation index weight or adjusting determination threshold in monitoring;

[0044] When the evaluation result of the same type of abnormality continuously falls below a preset standard, trigger a process optimization flow of the circuit board process.

[0045] Preferably, step S106 further comprises the following steps:

[0046] For the target carrier plate process node, divide a plurality of evaluation information according to its process specification requirements;

[0047] The processing effect data, the carrier plate process monitoring information, and the processing process monitoring data are respectively corresponded to each evaluation information, and actual values of each evaluation information are calculated;

[0048] A weight value is set for each evaluation information;

[0049] The actual values of each evaluation information are multiplied by the corresponding weight values and then accumulated to obtain a comprehensive score of the response capability of the target carrier plate process to the carrier plate process abnormal state;

[0050] According to the interval in which the comprehensive score is located, feedback information is generated, the feedback containing process parameter maintenance suggestions when the score is higher than a first score threshold, the feedback containing parameter fine-tuning schemes when the score is between the first score threshold and a second score threshold, and the feedback containing abnormal processing flow optimization instructions when the score is lower than the second score threshold, and the feedback information is synchronized to the process control device and the corresponding target carrier plate process node.

[0051] The application also provides a circuit board manufacturing process monitoring system, which comprises:

[0052] A node locking module is configured to select at least one as a target carrier plate process node in each key process node of the IC carrier plate manufacturing process, and to define the corresponding carrier plate process abnormal state of each target carrier plate process node according to the process specification or historical abnormal state data in advance;

[0053] An original data acquisition module is configured to acquire the target carrier plate process information stored in the node after the target carrier plate process node completes the current carrier plate process;

[0054] An abnormal feature extraction module is configured to extract carrier plate process monitoring information directly associated with the carrier plate process abnormal state from the target carrier plate process information;

[0055] A threshold comparison triggering module is configured to compare the carrier plate process monitoring information with the judgment threshold of the carrier plate process abnormal state set in advance for the target carrier plate process node, and to trigger the circuit board process to start the carrier plate process abnormal processing flow for the target carrier plate process node if the monitoring information exceeds the judgment threshold range;

[0056] A process monitoring acquisition module is configured to acquire monitoring data of the processing process in real time during the execution of the carrier plate process abnormal processing flow, and to acquire the final processing effect data after the processing is completed;

[0057] A response evaluation feedback module is configured to compare and verify the processing effect data with the process specification requirements of the target carrier plate process node, to evaluate the response capability of the target carrier plate process to the carrier plate process abnormal state in combination with the carrier plate process monitoring information and the processing process monitoring data, and to perform feedback.

[0058] According to another embodiment of the present application, a terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the circuit board manufacturing process monitoring method when executing the program.

[0059] According to still another embodiment of the present application, a storage medium is also provided, having a computer program stored thereon, wherein the computer program is executable by a processor to implement the steps of the circuit board manufacturing process monitoring method.

[0060] From the above technical solutions, the present application has the following advantages:

[0061] The circuit board manufacturing process monitoring method provided by the present application ensures the uniqueness of the target carrier board process node and the data tamper resistance by using a node identity token, and solidifying the association field design of node type, equipment number, process sequence code, and abnormal state register, thereby avoiding the monitoring failure problem caused by node identity confusion or data tamper in the traditional process. The determination threshold generated based on the historical defect record replaces the fixed threshold, and adapts to the process fluctuations caused by equipment aging and environmental temperature and humidity changes. Through abnormal type classification and monitoring index matching, combined with the trigger judgment of the influence level, redundant processing is avoided, and the abnormal response time is shortened. Through comparison and verification of the processing effect data and the process specification, feedback containing optimization suggestions and parameter correction values is generated, thereby improving the process stability.

[0062] The present application simulates an abnormality by a backup node, without triggering an abnormality in actual production nodes, thereby ensuring the continuity of the IC carrier board manufacturing process. The processing effect of the process control flow on abnormal data is verified by comparing the preset abnormality characteristics and the redundant node data. The design of the redundant backup node ensures the security of data storage, and avoids the interruption of monitoring caused by single node failure. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0064] Figure 1 A flowchart of the circuit board manufacturing process monitoring method;

[0065] Figure 2 A schematic diagram of the circuit board manufacturing process monitoring system;

[0066] Figure 3 A schematic diagram of the terminal. DETAILED DESCRIPTION

[0067] The IC carrier board manufacturing process involved in the circuit board manufacturing process monitoring method provided by the present application covers more than ten procedures such as material preparation, circuit processing, lamination, drilling, electroplating, and surface treatment.

[0068] A process node is set as a monitoring point of process data at each procedure of the IC carrier board manufacturing process. The monitoring point is provided with a terminal, which is a device capable of automatically performing numerical calculation and / or information processing according to a pre-set or stored instruction, and the hardware thereof includes but is not limited to a microprocessor, an application specific integrated circuit, a programmable gate array, a digital processor, an embedded device, etc.

[0069] Specifically, the data mainly monitored by the substrate and core plate processing node are as follows: material parameters: CTE (usually 10-18 ppm / ℃ in Z-axis direction), Dk (dielectric constant, such as PTFE carrier board Dk≈2.1), Df (loss factor, ≤0.001), Tg (glass transition temperature, ≥180℃), copper foil type (rolled copper RCF or electrolytic copper EDC). Size data: core plate thickness (such as 0.1 mm, 0.2 mm), dimensional tolerance (±0.1 mm).

[0070] The data monitored by the inner layer circuit manufacturing node are as follows: circuit parameters: line width (L) / line spacing (S) (such as 5 / 5 μm, 3 / 3 μm), line thickness (copper thickness, such as 12 μm), annular ring (such as not less than 8 μm). Abnormal state data: number of short circuit / short circuit detected by AOI, notch / spur size (such as notch length >20 μm is judged as defective).

[0071] The data monitored by the drilling node are as follows: hole parameters: hole diameter (such as 80 μm, 50 μm), hole site accuracy (deviation from design coordinate ≤±15 μm), hole depth (blind hole depth tolerance ±20 μm), hole wall roughness (Ra≤0.5 μm). Drilling quality: number of holes (such as 50-200 holes per square centimeter), uniformity of hole density distribution.

[0072] The data monitored by the electroplating node are as follows: plating thickness: chemical copper plating layer thickness (5-10 μm), full-plate electroplated copper thickness (20-35 μm), electroplated nickel layer thickness (3-6 μm), electroplated gold layer thickness (0.05-3 μm). Electroplating uniformity: copper thickness deviation of the same panel (≤±5%), hole copper coverage (≥95%).

[0073] The data monitored by the outer layer circuit processing node are as follows: circuit accuracy: outer layer L / S (such as 3 / 3 μm), circuit edge roughness (LER≤10 μm). Pattern alignment accuracy: outer layer and inner layer circuit alignment deviation (≤±20 μm).

[0074] The data monitored by the surface treatment processing node is: plating thickness: thick gold Ni (3-6 μm), thick Au (0.05-0.15 μm); thick electric gold Ni (3-6 μm), thick Au (0.5-3 μm). Surface performance: weldability (wetting time ≤ 3 s), bonding force (no peeling in grid test).

[0075] The data monitored by the forming and testing node is: forming size: carrier plate length and width (e.g., 10 mm x 10 mm), thickness (e.g., 0.2 mm), shape tolerance (± 20 μm). Electrical parameter: on-resistance (≤ 50 mΩ), insulation resistance (≥ 100 MΩ). Reliability data: crack rate after temperature cycle test (≤ 0.1%), plating layer peeling area after thermal shock (≤ 0.01%).

[0076] The line board manufacturing process monitoring method related to the present application will be described in detail below. For the purpose of illustration but not for the purpose of limitation, specific details such as specific system structures, techniques, and the like are presented in order to provide a thorough understanding of the embodiments of the present application. However, it should be apparent to those skilled in the art that the present application can be implemented in other embodiments without these specific details.

[0077] It should be understood that when used in the specification, the term "comprises" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The terms "comprise", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0078] The phrase "one embodiment" or "some embodiments" appearing in the present application means that the specific feature, structure or characteristic described in the embodiment is included in one or more embodiments of the present application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in yet some embodiments" appearing in different places in the present application do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized.

[0079] Computer program code for carrying out operations of the present disclosure can be written in any one or more programming languages or combinations of languages including object oriented programming languages such as Java, Smalltalk, C++ or conventional procedural programming languages such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0080] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0081] Referring to Figure 1 As shown in FIG. 1, which is a flowchart of a circuit board manufacturing process monitoring method in an embodiment, the method comprises the following steps:

[0082] Step S101: In each key process node of the IC carrier board manufacturing process, at least one target carrier board process node is selected; for each target carrier board process node, its corresponding carrier board process abnormal state is defined in advance according to the process specification or historical abnormal state data.

[0083] In some embodiments, the key monitoring nodes are selected from the key processes of the IC carrier board manufacturing, and the abnormal state judgment basis is set for the key monitoring nodes.

[0084] Specifically, the key processes in the whole process, such as substrate processing, drilling, electroplating, etc., are sorted out, and the target nodes are selected in combination with the influence degree of each node on product quality, historical failure frequency and other factors; then the specific performance of each abnormal state is determined according to the parameter standard in the process specification and the historical abnormal state data, for example, the drilling hole diameter exceeding the design value ± 5 μm is defined as the abnormal state of the drilling node.

[0085] The step S101 provided in the present application further relates to the following specific steps, specifically comprising:

[0086] Step S1011: In the IC carrier board manufacturing process, a node identity token is set for each key process node, the token has the node type, equipment number and process sequence code fixed therein, so that the node has a unique and tamper-proof identity in the network;

[0087] Step S1012: Collect all abnormal state records and parameter drift records of the node in the historical operation period, write the abnormal state type, occurrence frequency and parameter limit value into the node-specific abnormal state register as the first data source for defining the carrier board process abnormal state;

[0088] Step S1013: An association field is established between the node identity token and the abnormal state register, the association field allows the content of the abnormal state register to be read or updated only after the node identity token is verified successfully, preventing unauthorized external writing;

[0089] Step S1014: According to the content of the abnormal state register, a replaceable abnormal state description file is generated for each node, the abnormal state description file is indexed by the node identity token and is synchronously migrated with the node;

[0090] Step S1015: When the node enters the target carrier board process node candidate pool, consistency verification is performed through the identity token and the abnormal state description file, and only when the two are completely matched, the node is allowed to be selected as the target carrier board process node, thereby completing the node locking.

[0091] The step S101 of the embodiment realizes strong binding of node identity and abnormal state history by giving each key process node an uncopyable identity token and internalizing the abnormal state register in the node; before the node is selected as the target carrier board process node, bidirectional consistency verification of the identity token and the abnormal state description file must be completed to ensure that the abnormal state is real and has not been tampered with; this method can complete node screening and abnormal definition on site without a central database, reducing data coupling and improving on-site adaptability.

[0092] Step S102: After the target carrier board process node completes the current carrier board process, the target carrier board process information stored by the node is obtained.

[0093] In some embodiments, after the target node completes the current process, the process information generated by the target node is collected. Specifically, when the target node completes processing of a batch of products, through the data storage module built in the node or the database connected with the node, each data in the processing of the batch is obtained, including the processing time, the concentration of the chemical reagent used, the equipment operation parameter, etc.

[0094] Step S103: Extract the carrier board process monitoring information directly related to the carrier board process abnormal state from the target carrier board process information.

[0095] In some embodiments, data directly related to preset abnormal states is filtered out from the target process information, focusing on key monitoring indicators. Specifically, according to the carrier process abnormal states defined in step S101, corresponding parameters are extracted from the target carrier process information, for example, if the abnormal state includes weak plating adhesion, adhesion test data is extracted; if the abnormal state involves dimensional deviation, feature size measurement values are extracted, etc.

[0096] Step S104: Compare the carrier process monitoring information with the carrier process abnormal state determination threshold set in advance for the target carrier process node. If the monitoring information exceeds the determination threshold range, trigger the carrier process abnormal handling process for the target carrier process node.

[0097] In some embodiments, by comparing the monitoring information with the determination threshold, it is determined whether there is an abnormality, and then the corresponding processing process is triggered to realize timely response to the abnormality. Specifically, the carrier process monitoring information extracted in step S103 is compared with the determination threshold set in step S101. If the monitoring information exceeds the threshold range, the abnormal handling process for the target node is started, such as adjusting the drilling equipment parameters or suspending production for maintenance. By comparing the explicit threshold, rapid identification of abnormality and timely triggering of processing process are realized, avoiding the expansion of abnormality to cause more product abnormal states, and improving process stability.

[0098] Step S105: During the execution of the carrier process abnormal handling process, monitoring data of the handling process is collected in real time, and final handling effect data is obtained after the handling is completed.

[0099] In some embodiments, relevant data is collected during the abnormal handling process and after the handling to provide a basis for evaluating the handling effect. Specifically, during the execution of the carrier process abnormal handling process, monitoring data such as parameter adjustment during the handling process and equipment running state changes are recorded in real time; after the handling is completed, secondary detection data of the product, handling time consumption and other effect data are obtained.

[0100] Step S106: Compare and verify the handling effect data with the process specification requirements of the target carrier process node, evaluate the response capability of the target carrier process handling process to the carrier process abnormal state in combination with the carrier process monitoring information and the handling process monitoring data, and feedback.

[0101] In some embodiments, by comparing the handling effect with the process specification, the response capability of the process to the abnormality is evaluated in combination with the relevant data, and the result is fed back to realize continuous optimization.

[0102] Specifically, the processing effect data is compared with the process specification requirements of the target node, combined with the carrier board process monitoring information and the processing process monitoring data, the rationality of parameter adjustment in the processing process, whether the processing time is within a reasonable range, etc. are analyzed, the response capability is evaluated, and a feedback report is formed, such as suggesting to adjust the parameter adjustment amplitude in the abnormal processing flow. Through evaluation and feedback, the process processing process and abnormal response mechanism are continuously optimized, the process processing capability for abnormality is improved, the continuous improvement of the IC carrier board manufacturing process is realized, and the product quality and production efficiency are improved.

[0103] In some specific embodiments, step S106 specifically comprises the following steps:

[0104] S1061. Define an evaluation index system, including abnormal processing success rate, processing timeliness compliance rate, and post-processing process parameter compliance rate.

[0105] Among them, the abnormal processing success rate is calculated based on the ratio of the number of nodes that actually eliminate the abnormality to the number of nodes that trigger the abnormal processing flow, the processing timeliness compliance rate is calculated based on the ratio of the actual processing time to the preset standard time, and the post-processing process parameter compliance rate is calculated based on the compliance of the post-processing parameter with the process specification allowed range.

[0106] S1062. Adjust the weight of each evaluation index according to the type of abnormality; for example, for parameter deviation type abnormality, increase the weight of post-processing process parameter compliance rate; for timeliness sensitive abnormality, increase the weight of processing timeliness compliance rate; the weight adjustment is based on the correlation analysis result of different abnormal types and evaluation indexes in historical abnormal data.

[0107] S1063. Synchronize the evaluation result to the process control device of the circuit board process to generate a monitoring feedback containing optimization suggestions; the optimization suggestions include at least one of adjusting the process parameter threshold of the target carrier board process node, modifying the trigger condition of the abnormal processing flow, or updating the monitoring rule of the process control device.

[0108] S1064. Store the evaluation result of this time in association with historical evaluation data to form a historical database of abnormal processing effect; the historical database is used as a reference basis for optimizing evaluation index weight or adjusting threshold in monitoring.

[0109] S1065. When the evaluation result of the same type of abnormality continuously falls below the preset standard, trigger the process optimization flow of the circuit board process; the process optimization flow includes at least one of adjusting the equipment parameter of the target carrier board process node, redefining the carrier board process abnormal state, or adding redundant verification steps in the abnormal processing flow.

[0110] The abnormality processing capability of the carrier plate process is evaluated and optimized in step S106 of the embodiment, multi-dimensional evaluation indexes including success rate, time limit compliance rate and parameter qualification rate are defined, and the weights of each index are adjusted according to the abnormality type; the evaluation result is synchronized to the process control device to generate optimization suggestions and stored in the historical database; when the evaluation result is continuously substandard, the process optimization process is triggered to adjust the equipment parameters or abnormality processing rules. Through evaluation and feedback, the subjectivity of evaluation is avoided, and the continuous optimization of the abnormality processing capability is realized.

[0111] In an embodiment of the present application, based on step S104, a possible embodiment will be given below to illustrate the specific implementation thereof. Step S104 specifically includes the following steps:

[0112] Step S1041: Classify the abnormality state of the carrier plate process of the target carrier plate process node, and configure the abnormality type.

[0113] Optionally, the abnormality type involves specific abnormality types such as line short circuit, hole wall roughness exceeding the standard, copper thickness deficiency, weak plating layer bonding force or size deviation exceeding the limit. According to the common problems of the IC carrier plate manufacturing process, the abnormality state of the carrier plate process is divided into specific identifiable abnormality types, and the representation form of each abnormality is determined.

[0114] Step S1042: Assign corresponding carrier plate process monitoring information indexes to each abnormality type.

[0115] Optionally, the carrier plate process monitoring information indexes include but are not limited to: line short circuit corresponding line width / line spacing deviation value, hole wall roughness exceeding the standard corresponding roughness measurement value, copper thickness deficiency corresponding copper thickness detection value, weak plating layer bonding force corresponding bonding force test value, and size deviation exceeding the limit corresponding feature size deviation amount.

[0116] For each abnormality type, the monitoring information index that best reflects the severity thereof is screened out, such as the Ra value corresponding to the hole wall roughness exceeding the standard and the copper thickness measurement value corresponding to the copper thickness deficiency, so as to ensure that the monitoring index corresponds to the abnormality type one by one.

[0117] Step S1043: Obtain the historical process data of the target carrier plate process node, and calculate the determination threshold value corresponding to each abnormality type.

[0118] The setting method of the determination threshold value can be based on the mean value ± 3 times the standard deviation of the historical normal data, or a fixed threshold range set according to the process specification.

[0119] Step S1044: Compare each index in the carrier plate process monitoring information with the dynamic determination threshold value of the corresponding abnormality type, and record the abnormality index and its deviation degree exceeding the threshold value.

[0120] The deviation degree includes: the line width deviation value is +8 μm, the upper threshold value is +5 μm, and the deviation degree is +3 μm; the Ra roughness measurement value is 0.6 μm, the upper threshold value is 0.5 μm, and the deviation degree is +0.1 μm.

[0121] Step S1045: According to the deviation degree of the abnormal index and the influence level of the abnormal type, it is comprehensively judged whether to trigger the carrier plate process abnormality processing flow.

[0122] It should be noted that the carrier plate process abnormality processing flow involves triggering immediately when the deviation degree of the key abnormal index exceeds 50% of the threshold range, and triggering when the deviation degree of the secondary abnormal index exceeds 100% of the threshold range.

[0123] Exemplarily, according to the influence level of the abnormal type, the line width abnormality affects the product yield by 15%, which belongs to the key abnormality; the Ra abnormality affects the yield by 5%, which belongs to the secondary abnormality, and the line width deviation exceeds the threshold value of 50%, that is, +2.5 μm, and the Ra deviation exceeds the threshold value of 100%, that is, +0.1 μm, and it is comprehensively judged whether to trigger the abnormality processing flow.

[0124] Step S104 of the embodiment adjusts the threshold value by using historical data, comprehensively evaluates the multi-dimensional monitoring index according to the influence level of the abnormal type, and ensures that the processing flow is triggered only when the abnormality that truly affects the process quality occurs, thereby avoiding invalid intervention.

[0125] In an embodiment of the present application, based on step S106, a possible embodiment will be given below to non-limitingly illustrate the specific implementation scheme. Step S106 further includes the following steps:

[0126] S2061: For the target carrier plate process node, according to the process specification requirements, a plurality of evaluation information is divided, including the parameter compliance rate after abnormality processing, the deviation rate of the processing process time and the standard time length, and the change rate of the product abnormal state quantity before and after processing.

[0127] S2062: The processing effect data, the carrier plate process monitoring information, and the processing process monitoring data are respectively corresponded to each evaluation information, and the actual value of each evaluation information is calculated, wherein the parameter compliance rate is the proportion of the number of compliant parameter items to the total number of parameter items, the deviation rate is the ratio of (actual time consumption-standard time length) to the standard time length, and the change rate is the ratio of (the number of abnormal states before processing-the number of abnormal states after processing) to the number of abnormal states before processing.

[0128] S2063: A weight value is set for each evaluation information, and the weight value is determined according to the influence degree of the dimension on the process stability, such as setting the parameter compliance rate weight to 40%, setting the deviation rate weight to 30%, and setting the change rate weight to 30%, and the sum of the weight values of each dimension is 100%.

[0129] S2064: The actual value of each evaluation information is multiplied by the corresponding weight value and accumulated to obtain a comprehensive score of the response capability of the target carrier plate process to the abnormal state of the carrier plate process.

[0130] Optionally, the calculation method of the comprehensive score is parameter compliance rate x 40% + (1-|deviation rate|) x 30% + change rate x 30%, wherein the absolute value of the deviation rate is taken to avoid positive and negative offset, 1-|deviation rate| ensures that the time consumption is closer to the standard score, and multi-dimensional evaluation information is realized by weighted integration.

[0131] S2065: According to the interval in which the comprehensive score is located, generate feedback information, the feedback containing process parameter maintenance suggestion when the score is higher than the first score threshold, the feedback containing parameter fine-tuning scheme when the score is between the first score threshold and the second score threshold, and the feedback containing abnormal processing flow optimization instruction when the score is lower than the second score threshold, and synchronize the feedback information to the process control device and the corresponding target carrier plate process node.

[0132] It should be noted that the comprehensive score is compared with the preset threshold, such as the first score threshold of 80 points and the second score threshold of 60 points, different intervals correspond to different feedback strategies, the high score interval indicates that the current processing flow is effective, the low score interval corresponds to parameter fine-tuning or flow reconstruction, and the feedback information is written through the interface of the process control device to directly guide subsequent process adjustment.

[0133] The embodiment evaluates the response effect of the target carrier plate process to the abnormal state, combines the importance of each dimension to obtain evaluation information, generates targeted feedback information, and realizes continuous optimization of the process.

[0134] In an embodiment of the present application, based on step S101, a possible embodiment will be given below to non-limitingly illustrate the specific implementation scheme. Step S101 further includes the following steps:

[0135] Step S2011: Determine a candidate carrier plate process node set of the IC carrier plate manufacturing process, the candidate node set contains all key process nodes, and through process complexity evaluation and historical abnormal state rate statistics, nodes with high process complexity and historical abnormal state rate ≥ 5% are selected as the initial screening target nodes.

[0136] The embodiment lists all key process nodes, excludes nodes with simple process and low abnormal state rate through process complexity evaluation and historical abnormal state rate statistics, and retains initial screening nodes with complex process and high abnormal state rate.

[0137] Optionally, the key process nodes can be substrate and core plate processing, drilling, electroplating, outer layer circuit processing, surface treatment, forming and testing, etc. The process complexity is the number of process steps, equipment precision requirement, operation difficulty.

[0138] Step S2012: Process correlation analysis is performed on the screening target nodes, the dependency relationship with upstream and downstream processes is evaluated, the core nodes with an impact weight on the final carrier plate quality greater than or equal to 30% are further selected from the screening target nodes according to the key path position in the overall process flow, and the final target carrier plate process nodes are obtained.

[0139] Step S2013: For each final target carrier plate process node, the key quality characteristics in the process specification file are extracted, and the historical abnormal state data of the node in a preset time period are collected to establish a mapping relationship between the process specification requirements and the historical abnormal state characteristics.

[0140] It should be noted that the key quality characteristics refer to the CTE value range of substrate and core plate processing, the hole diameter tolerance of drilling, and the copper thickness target value of electroplating. The historical abnormal state data includes the abnormal state type, the occurrence frequency, and the severity.

[0141] For each node, the key quality characteristics in the process specification are extracted, and the historical abnormal state data are collected to establish a mapping relationship between the abnormality and the yield loss.

[0142] Step S2014: Based on the mapping relationship between the process specification requirements and the historical abnormal state characteristics, the specific carrier plate process abnormal state type and the corresponding abnormal trigger condition are defined for each target carrier plate process node.

[0143] Step S2015: According to the real-time process fluctuation data, the trigger condition of the carrier plate process abnormal state is adjusted to ensure that the abnormal state definition is adapted to the current process environment, and false positives or false negatives caused by environmental changes are avoided.

[0144] Therefore, step S101 screens the core nodes with the greatest impact on the carrier plate quality based on the process complexity, the abnormal state rate and the key path analysis; defines the abnormal state with strong correlation with the actual abnormal state by combining the process specification and the historical abnormal state data; and adjusts the abnormal trigger condition in real time to ensure the pertinence and adaptability of the monitoring.

[0145] In an embodiment of the present application, based on step S106, a possible embodiment will be given below to non-restrictively describe the specific implementation scheme. Step S106 further includes the following steps:

[0146] S6021: Determine the target backup process node in the target carrier plate process node;

[0147] The target backup process node is determined by at least one of process control device configuration recognition, a monitoring command or a log of a circuit board process, and historical record analysis, and has a unique block identifier for locating the target backup process node in the process control device.

[0148] S6022: Read the data stored in the target backup process node through a preset target interface to obtain initial circuit board process monitoring information.

[0149] The target interface is a physical or logical interface in the circuit board process control device that communicates with the target backup process node, and the initial circuit board process monitoring information is original process data of the target circuit board process node before the abnormal state of the circuit board process is set.

[0150] S6023: Modify the data stored in the target backup process node to introduce the abnormal state of the circuit board process into the target backup process node. The modification method includes adjusting the process parameters, processing result identifiers, or associated metadata stored in the target backup process node, so that the modified data stored in the target backup process node meets the preset abnormal characteristics.

[0151] S6024: Determine the modified data stored in the target backup process node as the target circuit board process information, and extract circuit board process monitoring information from the target circuit board process information. The circuit board process monitoring information includes at least one of process parameter deviation values, data integrity markers, or processing timeliness indicators corresponding to the abnormal characteristics.

[0152] S6025: When the abnormal state of the circuit board process includes an abnormality of the target backup process node, store the modified data stored in the target backup process node in other backup process nodes other than the target backup process node. The other backup process nodes are redundant storage units associated with the target backup process node in the circuit board process control device.

[0153] S6026: Read other circuit board process monitoring information stored in the other backup process nodes through the target interface, compare the initial circuit board process monitoring information with the other circuit board process monitoring information, and obtain a first comparison result. Determine whether the abnormal response capability of the target circuit board process control flow of the target circuit board process node is normal based on the first comparison result. If the first comparison result indicates that the two information are the same, it is determined that the abnormal response capability is normal. If they are different, it is determined that the abnormal response capability is abnormal.

[0154] The embodiment determines a target backup process node with a unique identifier in a target process node, reads original data thereof as initial monitoring information, introduces an abnormal state by modifying the node data, uses the modified data as target process information, and extracts monitoring information containing abnormal characteristics; when the target backup node is abnormal, the modified data is stored in other backup nodes, and the information thereof is read and compared with the initial information to determine whether the abnormal response capability of the target node is normal.

[0155] The backup node is accurately positioned by the unique identifier to ensure the accuracy of data reading; the abnormal response capability is effectively detected by comparing the original data with the abnormal data; the abnormal state-based mode is close to the actual fault scene to improve the authenticity of monitoring; and the data reliability is enhanced by the collaborative operation of multiple backup nodes to ensure the accuracy of the abnormal judgment result.

[0156] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0157] The following is an embodiment of a circuit board manufacturing process monitoring system provided by the embodiment of the present disclosure. The system and the circuit board manufacturing process monitoring method of each embodiment described above belong to the same inventive concept. Details not described in the embodiment of the circuit board manufacturing process monitoring system can be referred to the embodiment of the circuit board manufacturing process monitoring method.

[0158] As shown in Figure 2 , the system comprises:

[0159] The node locking module 201 is configured to select at least one as a target process node in each key process node of the IC substrate manufacturing process; and for each target process node, the corresponding process abnormal state of the target process node is defined in advance according to the process specification or historical abnormal state data.

[0160] The original data acquisition module 202 is configured to acquire the target process information stored in the target process node after the target process node completes the current process of the substrate.

[0161] The abnormal characteristic extraction module 203 is configured to extract the substrate process monitoring information directly associated with the substrate process abnormal state from the target process information.

[0162] The threshold comparison triggering module 204 is configured to compare the substrate process monitoring information with the judgment threshold of the substrate process abnormal state of the target process node set in advance, and if the monitoring information exceeds the judgment threshold range, trigger the circuit board process to start the substrate process abnormal processing flow for the target process node.

[0163] The process monitoring collection module 205 is configured to collect monitoring data of the process in real time during execution of the carrier plate process exception handling flow, and obtain final processing effect data after the process is completed.

[0164] The response evaluation feedback module 206 is configured to compare and verify the processing effect data with process specification requirements of a target carrier plate process node, combine carrier plate process monitoring information and process monitoring data, evaluate response capability of the target carrier plate process to the carrier plate process exception state, and perform feedback.

[0165] As shown in the method for monitoring a circuit board manufacturing process, the method comprises the following steps of: Figure 3 The application further provides a terminal, comprising a display module 103, a memory 102, a processor 101, and a computer program stored in the memory and executable on the processor 101, wherein the processor 101 implements the steps of the method for monitoring a circuit board manufacturing process when executing the program.

[0166] In the embodiments of the application, the terminal includes, but is not limited to, a laptop computer, a desktop computer, a workstation, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The terminal can also represent various forms of mobile devices, such as a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are merely examples, and are not intended to limit the implementation of the embodiments of the application described herein and / or claimed.

[0167] In the embodiments of the application, the processor 101 can be implemented by using at least one of a special-purpose integrated circuit, a programmable logic device, a field programmable gate array, a processor, a controller, a microcontroller, a microprocessor, an electronic unit designed to perform the functions described herein, and in some cases, such implementation can be implemented in a controller. For software implementation, the implementation of the processes or functions can be implemented with separate software modules that allow at least one function or operation to be performed. The software code can be implemented by a software application (or program) written in any appropriate programming language, which can be stored in the memory and executed by the controller.

[0168] The display module 103 is configured to display information input by a user or information provided to the user. The display module 103 can include a display panel, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, etc.

[0169] The memory 102 can be used to store software programs and various data. The memory 102 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device.

[0170] The application also provides a storage medium, which stores a computer program, and the computer program is executed by a processor to implement steps of the circuit board manufacturing process monitoring method.

[0171] The storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples (non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0172] In the storage medium, the readable signal medium can include a data signal borne in a baseband or as part of a carrier wave, in which readable program codes are borne. Such a propagated data signal can adopt various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination thereof. The readable signal medium can also be any readable medium other than the readable storage medium, which can send, propagate or transmit programs for use by or in connection with an instruction execution system, device or apparatus.

[0173] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of monitoring a process for manufacturing a circuit board, characterized by, The method comprises: S101: In each key process node of the IC carrier board manufacturing process, at least one target carrier board process node is screened; For each target carrier board process node, its corresponding carrier board process abnormal state type and trigger condition are defined in advance according to a process specification file or historical abnormal state data; S102: After the target carrier board process node completes the current carrier board process treatment process, target carrier board process information stored in the node is acquired; S103: Carrier board process monitoring information directly related to the carrier board process abnormal state is extracted from the target carrier board process information; S104: The carrier board process monitoring information is compared with the determination threshold of the carrier board process abnormal state set in advance for the target carrier board process node, and if the monitoring information exceeds the determination threshold range, the carrier board process abnormal treatment process for the target carrier board process node is triggered; S105: During the execution of the carrier board process abnormal treatment process, monitoring data of the treatment process is collected in real time, and final treatment effect data is acquired after the treatment is completed; S106: The treatment effect data is compared and verified with the process specification requirement of the target carrier board process node, the response capability of the target carrier board process treatment process to the carrier board process abnormal state is evaluated in combination with the carrier board process monitoring information and the treatment process monitoring data, and feedback is performed; A target backup process node in the target carrier board process node is determined; Data stored in the target backup process node is read through a preset target interface to obtain initial carrier board process monitoring information; The data stored in the target backup process node is modified, and the carrier board process abnormal state is introduced into the target backup process node; The modified data backed up in the target backup process node is determined as target carrier board process information, and carrier board process monitoring information is extracted from the target carrier board process information; the carrier board process monitoring information comprises at least one of a process parameter deviation value corresponding to an abnormal feature, a data integrity mark, or a processing timeliness index; When the carrier board process abnormal state includes an abnormality of the target backup process node, the modified data backed up in the target backup process node is stored in other backup process nodes except the target backup process node; Other carrier board process monitoring information stored in the other backup process nodes is read through the target interface, the initial carrier board process monitoring information is compared with the other carrier board process monitoring information, and a first comparison result is obtained; Based on the first comparison result, it is determined whether the abnormal response capability of the target carrier board process control process of the target carrier board process node is normal; if the first comparison result indicates that the two information are the same, it is determined that the abnormal response capability is normal; if they are different, it is determined that the abnormal response capability is abnormal.

2. The circuit board manufacturing process monitoring method according to claim 1, wherein Step S101 further comprises the following steps: A candidate carrier board process node set of the IC carrier board manufacturing process is determined; A process correlation analysis is performed on the screening target nodes to evaluate their dependency relationship with upstream and downstream processes, and a core node with an impact weight of greater than or equal to 30% on the final carrier plate quality is further selected from the screening target nodes as a final target carrier plate process node according to the key path position of the core node in the overall process flow; For each final target carrier plate process node, key quality characteristics in the process specification file thereof are extracted, and historical abnormal state data of the node within a preset time period are collected to establish a mapping relationship between the process specification requirements and the historical abnormal state characteristics; Based on the mapping relationship between the process specification requirements and the historical abnormal state characteristics, a specific carrier plate process abnormal state type and a corresponding abnormal trigger condition are defined for each target carrier plate process node; According to real-time process fluctuation data, the trigger condition of the carrier plate process abnormal state is adjusted to ensure that the abnormal state definition is adapted to the current process environment.

3. The circuit board manufacturing process monitoring method according to claim 1, wherein step S101 further comprises the following steps: In the IC carrier plate manufacturing process, a node identity token is set for each key process node, and the token is fixed with the node type, equipment number and process sequence code; All abnormal state records and parameter drift records of the node within a historical running period are collected, and the abnormal state type, occurrence frequency and parameter limit value are written into the node-specific abnormal state register as the first data source for defining the carrier plate process abnormal state; An association field is established between the node identity token and the abnormal state register, and the content of the abnormal state register is only allowed to be read or updated after the node identity token is verified successfully; According to the content of the abnormal state register, an abnormal state description file is generated for each node, and the abnormal state description file is indexed by the node identity token and is synchronized with the node migration; When the node enters the target carrier plate process node candidate pool, consistency verification is performed through the identity token and the abnormal state description file, and only when the two are completely matched, the node is allowed to be selected as the target carrier plate process node, thereby completing the node locking.

4. The circuit board manufacturing process monitoring method according to claim 1, wherein step S104 specifically comprises the following steps: Classify the carrier plate process abnormal state of the target carrier plate process node and configure the abnormal type; Assign corresponding carrier plate process monitoring information indicators to each abnormal type; Obtain the historical process data of the target carrier plate process node, and calculate the determination threshold value corresponding to each abnormal type; Compare each indicator in the carrier plate process monitoring information with the determination threshold value of the corresponding abnormal type, and record the abnormal indicators and their deviation degrees that exceed the threshold value; According to the deviation degree of the abnormal indicator and the influence level of the abnormal type, it is comprehensively judged whether to trigger the carrier plate process abnormal handling process.

5. The circuit board manufacturing process monitoring method according to claim 1, wherein step S106 further comprises the following steps: Define an evaluation index system including the abnormal handling success rate, the processing time efficiency compliance rate and the process parameter qualification rate after processing; Adjust the weight of each evaluation index according to the abnormal type; ​ ​ ​ The evaluation result is synchronized to a process control device of the circuit board process to generate monitoring feedback containing optimization suggestions; The evaluation result is stored in association with historical evaluation data to form a historical database of abnormality processing effects; the historical database is used as a reference basis for optimizing evaluation index weights or adjusting decision thresholds in monitoring; When the evaluation result of the same type of abnormality continuously falls below a preset standard, a process optimization process of the circuit board process is triggered.

6. The circuit board manufacturing process monitoring method of claim 1, wherein, Step S106 further comprises the following steps: According to the process specification requirements of the target substrate process node, a plurality of evaluation information is divided; The processing effect data, substrate process monitoring information, and processing process monitoring data are respectively corresponded to each evaluation information, and the actual value of each evaluation information is calculated; A weight value is set for each evaluation information; The actual values of the evaluation information are multiplied by the corresponding weight values and then accumulated to obtain a comprehensive score of the response capability of the target substrate process to the abnormal state of the substrate process; According to the interval in which the comprehensive score is located, feedback information is generated; feedback containing process parameter maintenance suggestions is included when the score is higher than a first score threshold, feedback containing parameter fine-tuning schemes is included when the score is between the first score threshold and a second score threshold, and feedback containing abnormality processing process optimization instructions is included when the score is lower than the second score threshold; and the feedback information is synchronized to the process control device and the corresponding target substrate process node.

7. A circuit board manufacturing process monitoring system, characterized in that, The system is used to implement the circuit board manufacturing process monitoring method of any one of claims 1 to 6; The system comprises: A node locking module is used to select at least one as a target substrate process node in each key process node of the IC substrate manufacturing process; for each target substrate process node, its corresponding substrate process abnormal state is defined in advance according to the process specification or historical abnormal state data; An original data acquisition module is used to acquire the target substrate process information stored in the node after the target substrate process node completes the current substrate process processing process; An abnormality feature extraction module is used to extract substrate process monitoring information directly related to the substrate process abnormal state from the target substrate process information; A threshold comparison triggering module is used to compare the substrate process monitoring information with the decision threshold of the substrate process abnormal state of the target substrate process node set in advance; if the monitoring information exceeds the decision threshold range, the circuit board process starts the substrate process abnormality processing process for the target substrate process node; A process monitoring and collection module is used to collect monitoring data of the processing process in real time during the execution of the substrate process abnormality processing process, and to acquire the final processing effect data after the processing is completed; A response evaluation and feedback module is used to compare and verify the processing effect data with the process specification requirements of the target substrate process node, combine the substrate process monitoring information and the processing process monitoring data, evaluate the response capability of the target substrate process to the abnormal state of the substrate process, and provide feedback.

8. A terminal comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the steps of the circuit board manufacturing process monitoring method of any one of claims 1 to 6 when executing the program.

9. A storage medium having stored thereon a computer program, characterized in that The computer program, when executed by a processor, implements the steps of the circuit board manufacturing process monitoring method according to any one of claims 1 to 6.

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