Clock synchronization instruction synchronization method and system for cooperative work of multiple single-chip microcomputers

Abstract

The invention discloses a clock synchronization instruction synchronization method and system for cooperative work of multiple single-chip microcomputers, and relates to the field of single-chip microcomputers, and the system comprises a generation module which is used for selecting a physical phenomenon with a constant periodic characteristic in an environment, converting the physical phenomenon into a unique pulse string with a fixed time interval through a special conversion assembly, and transmitting the pulse string to a clock synchronization module; the signal source serves as a unified time reference signal source of the whole system and is output; the receiving module is used for continuously receiving the reference pulse string and comparing the cumulative difference between the local clock and the reference pulse in real time so as to adjust the oscillation frequency of the single chip microcomputer to eliminate the difference value; according to the invention, a constant period physical phenomenon in an environment is taken as a unified time reference, stable pulses are formed through accurate conversion, local clocks of the single-chip microcomputers can be calibrated in real time, clock skew is greatly reduced, and time synchronization precision of the whole system in a multi-single-chip microcomputer working scene is guaranteed.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of single-chip microcomputers, in particular to a clock synchronization instruction synchronization method and system for multiple single-chip microcomputers working in cooperation. BACKGROUND

[0002] In the cooperation of multiple single-chip microcomputers, clock synchronization is the key. Through hardware synchronization or software protocol, the clock deviation of each single-chip microcomputer is controlled within microseconds. The synchronization instruction ensures the consistency of task execution timing, avoids data conflicts, and improves the cooperation efficiency of the system.

[0003] The application number 202111252171.X discloses a web3D multi-virtual single-chip microcomputer system cooperation system, which comprises: multiple virtual single-chip microcomputer systems in communication connection with each other; a virtual computer connected with the multiple virtual single-chip microcomputer systems, the virtual computer is used to configure sequential codes for each virtual single-chip microcomputer system and control the running of the cooperation system, and each sequential code corresponds to a specific virtual single-chip microcomputer system; a code input editing box provided on the virtual computer and used for writing C language control codes for the virtual single-chip microcomputer system; a virtual burning adapter provided between the virtual computer and the virtual single-chip microcomputer system; the virtual burning adapter identifies and connects the virtual single-chip microcomputer system corresponding to the sequential code instruction output by the virtual computer and writes the C language control code into the virtual single-chip microcomputer system; a virtual power supply connected with the virtual single-chip microcomputer system; a virtual voltage converter provided between the virtual power supply and the virtual single-chip microcomputer system; the virtual voltage converter is used to convert different analog voltages to supply power to the virtual single-chip microcomputer system. The system aims to solve the problems that the traditional virtual single-chip microcomputer cannot execute logic codes and cannot meet the scene requirements of multi-machine cooperation, and the connection relationship between the virtual single-chip microcomputer systems cannot be correctly configured and lacks a correct signal transmission mechanism, resulting in chaotic signal response between the systems.

[0004] However, for the multi-single-chip microcomputer cooperation scene, the synchronization of instruction distribution and execution is an important prerequisite for accurate execution of the specified instructions. Therefore, a clock synchronization instruction synchronization method and system for multiple single-chip microcomputers working in cooperation are proposed. SUMMARY

[0005] In view of the above shortcomings of the prior art, the application provides a clock synchronization instruction synchronization method and system for multiple single-chip microcomputers working in cooperation, which can effectively solve the problems of the prior art.

[0006] To achieve the above purpose, the following technical solutions are used. The application discloses a clock synchronization instruction synchronization system for multiple single-chip microcomputers working in cooperation, which comprises: The generation module is used to select physical phenomena with constant periodic characteristics in the environment, and convert them into a unique pulse train with a fixed time interval through a dedicated conversion component, which is used as a unified time reference signal source for the entire system and output; the receiving module is used to continuously receive the reference pulse train, and compare the cumulative difference between the local clock and the reference pulse in real time to adjust the oscillation frequency of the microcontroller to eliminate the difference; the distribution module is used to collect the instructions issued by each microcontroller, sort them according to the preset execution window period of the instruction-associated task, and distribute them to the target microcontroller in a targeted manner; the feedback module is used to collect the status information of each microcontroller after executing the instruction, encapsulate the collected status information of each microcontroller after executing the instruction, and feed it back to the microcontroller that initiated the instruction; the mediation module is used to monitor and identify instruction execution conflicts or timing conflicts in real time, and mediate and eliminate conflicts according to preset rules to ensure the priority of the core functions of the system; the monitoring module is used to track the operating parameters of the system modules and microcontrollers in real time. When the parameters exceed the preset threshold, an abnormal signal is triggered and the preset backup coordination mechanism is activated.

[0007] Furthermore, the physical phenomena with constant periodic characteristics in the environment selected in the generation module include but are not limited to: the carrier migration period of semiconductor materials under constant voltage; the round-trip period of ion directional movement in an electrolyte solution of preset concentration; the stimulated vibration period of a certain type of crystal under laser irradiation of preset frequency; the collision period of thermal motion of fixed mass gas molecules in a closed cavity; the deflection vibration period of magnetic particles in a magnetic field of preset strength; The dedicated conversion component in the generation module is integrated by a signal acquisition unit, a period purification unit, a pulse shaping unit and a feedback verification unit.

[0008] Furthermore, during the operation phase of the dedicated conversion component, the signal acquisition unit selects a periodic , which is converted into the initial electrical signal through the corresponding conversion element: , periodic purification unit pair Noise is filtered out and the cycle is locked by a closed-loop cycle locking circuit, so that the output cycle is stable. The purified signal , the pulse shaping unit will Compared with the preset threshold, when When the output width is greater than or equal to the preset threshold High-level pulses form a pulse train , the feedback verification unit monitors the pulse interval in real time, and the real-time deviation exceeds That is, the periodic purification unit is triggered to make corrections and finally output a unique pulse train with a fixed time interval; Where: is the signal amplitude; a time variable starting from the time when the signal acquisition unit captures the periodic variation moment of the preset physical phenomenon; an initial phase; wherein the conversion element comprises a carrier concentration sensor, an ion mobility detector, a vibration sensor, a molecular collision counter, a particle deflection detector, noise filtering is performed using a filter adapted to the physical phenomenon, .

[0009] Further, the receiving module operating stage adjusts the single-chip oscillator frequency in compliance with: calculating the cumulative number difference ; the adjusted single-chip oscillator frequency: ; wherein: is the initial frequency of the local clock of the clock calibration receiving module; is the time interval between two consecutive reference pulses; is the frequency of the reference pulse; is the linear fine-tuning coefficient; wherein, represents the actual cumulative pulse number of the local clock within the time, represents the theoretical cumulative number of reference pulses within the time.

[0010] Further, the distribution module operating flow includes: instruction collection link: the distribution module receives instruction data packets sent by each single-chip in real time through a preset signal interface, the instruction data packet contains instruction content, initiator identification, target identification, task association code, and is stored in a temporary buffer area; sorting link: extract the preset execution window period parameters corresponding to the task association code in each instruction data packet, i.e. the earliest start time stamp and the latest completion time stamp, and sort the buffer area instructions according to the logic that the higher the priority, the earlier the latest completion time stamp, if the time stamps are the same, then secondary sorting or parallel sorting according to the importance level of the function module to which the initiator belongs; directional distribution link: according to the sorting result, the instruction data packet is sent to the target single-chip through the corresponding data transmission channel in turn, and the distribution time and the instruction state are recorded synchronously, and the instruction data with the instruction state of completed distribution in the temporary buffer area is cleared.

[0011] Further, the state information of each single-chip executing instruction in the feedback module includes: execution progress, result code, and abnormal reason; The state information of each single-chip microcomputer after executing the instruction is packaged in the feedback module, and the packaging format of the state information of each single-chip microcomputer after executing the instruction is consistent, and the packaging content is the execution progress, the result code, and the abnormal reason.

[0012] Further, when the mediation module monitors and identifies instruction execution conflicts or timing conflicts, it continuously scans the instruction execution requests sent by each single-chip microcomputer, records the resources involved in each request, including specific interfaces, operation units, and planned execution time periods, and determines that there is an instruction execution conflict when two or more instruction requests point to the same resource and the planned execution time periods overlap; and determines that there is a timing conflict when there is a dependency relationship between instructions. After the mediation module identifies the conflicts, the number of single-chip microcomputers associated with each conflict instruction is obtained, and the conflict instruction associated with the largest number of single-chip microcomputers is determined as the priority execution object and is given the resource usage right. The remaining conflict instructions enter a preset dynamic waiting pool, and the instructions in the pool are sorted in real time according to the number of associated single-chip microcomputers. When the priority execution conflict instruction ends or an execution gap occurs, the conflict instruction associated with the largest number of single-chip microcomputers in the dynamic waiting pool is automatically promoted and obtains the resource usage right.

[0013] Further, the system module tracked by the monitoring module includes a generation module, a receiving module, a distribution module, a feedback module, and a mediation module. The operating parameters include module response time, single-chip microcomputer load rate, pulse interval deviation of the generation module, synchronization error of the receiving module, instruction retention number of the distribution module, feedback delay of the feedback module, and conflict processing time of the mediation module. The synchronization error of the receiving module is the time difference between the adjusted local clock and the reference clock. The exception signal triggered by the monitoring module is a digital signal composed of the module name and the single-chip microcomputer number of the operating parameter source exceeding the preset threshold. During the exception signal triggering stage, the exception signal is synchronously transmitted to the mediation module and the distribution module, and a preset backup cooperation mechanism is activated. The backup cooperation mechanism is defined by the system end user.

[0014] Further, the generation module is connected to the receiving module and the distribution module through a wireless network, the distribution module is connected to the feedback module through a wireless network, the feedback module is connected to the mediation module through a wireless network, and the mediation module is connected to the monitoring module through a wireless network.

[0015] On the other hand, a clock synchronization instruction synchronization method for multiple single-chip microcomputer cooperative work includes the following steps: Capture the physical phenomenon with constant periodic characteristics in the environment, convert the physical phenomenon into a pulse train with fixed time interval and uniqueness by using a special conversion component, generate and output a unified time reference for the entire system; continuously receive the reference pulse train, compare the cumulative number difference between the local clock and the reference pulse in real time, eliminate the difference by linearly fine-tuning the self-oscillation frequency, and make the local clock and the reference clock achieve zero-difference synchronization; gather the instructions issued by each single-chip, sort the sorted instructions according to the preset execution window period of the task associated with the instructions, and distribute the sorted instructions to the corresponding target single-chip; collect the state information of each single-chip after executing the instructions, the state information including execution progress, result code and abnormal reason, and feed back the state information to the single-chip initiating the instruction after encapsulating the state information in a unified format; real-time monitor and identify the conflict in the instruction execution process, the conflict including simultaneous calling of the same resource and contradictory instruction execution sequence, and mediate the conflict according to the preset rule of guaranteeing the priority of the core function of the system to eliminate the conflict; real-time track the running parameters of each part and single-chip, the running parameters including module response time and single-chip load rate, and trigger an abnormal signal and activate a preset backup cooperation mechanism when the running parameters exceed the preset threshold; Wherein, the preset execution window period contains the earliest start time and the latest completion time.

[0016] Compared with the known prior art, the technical scheme provided by the present application has the following beneficial effects: The clock synchronization instruction synchronization method and system for multiple single-chip cooperation provided by the present application use a constant periodic physical phenomenon in the environment as a unified time reference, form stable pulses through accurate conversion, can real-time calibrate the local clock of each single-chip, greatly reduce the clock deviation, guarantee the time synchronization accuracy of the whole system, at the same time, orderly schedule instructions according to the task preset execution window, combined with the function importance hierarchical sorting, improve the instruction distribution efficiency. It can dynamically identify and handle instruction execution and timing conflict, preferentially guarantee the task associated with more devices, reduce resource contention, uniformly encapsulate the execution state feedback, facilitate the instruction initiating party to real-time track the progress and result, in addition, real-time monitor the system running parameters, trigger the backup mechanism when the threshold is exceeded, enhance the system stability and fault tolerance ability, and overall improve the reliability and efficiency of multiple single-chip cooperation. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creating any inventive labor.

[0018] Figure 1 A schematic diagram of the structure of a clock synchronization and instruction synchronization system for multiple single-chip microcomputers to work together; Figure 2 The present invention is a flowchart of a clock synchronization instruction synchronization method for multiple single-chip microcomputers working in coordination. DETAILED DESCRIPTION

[0019] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0020] The present invention will be further described below with reference to the embodiments. Example 1:

[0021] This embodiment is a clock synchronization instruction synchronization system for multiple single-chip computers working in coordination, such as Figure 1 Shown, including: The generation module is used to select physical phenomena with constant periodic characteristics in the environment and convert them into a unique pulse train with a fixed time interval through a dedicated conversion component. This pulse train is then output as a unified time reference signal source for the entire system. It should be stated that: The sources of the physical phenomena involved in the generation module are all dedicated physical generation devices independently set up outside the system, including: Semiconductor carrier generation device: It consists of a constant temperature chamber independent of the single-chip microcomputer, a dedicated semiconductor chip and a regulated power supply, and is specifically used to generate stable carrier migration phenomena; Electrolyte ion movement device: It includes a sealed container, a preset concentration electrolyte solution and a DC power supply module. It has no circuit connection with the single-chip computer system and only serves as the source of ion movement. Crystal stimulated vibration device: It consists of a laser emitter, a crystal holder and a shock-proof base. Its vibration signal is output through a photoelectric converter and is not related to the core processing unit of the microcontroller. Gas molecule motion device: It is a sealed metal cavity with a fixed mass of inert gas built in. It maintains a constant environment through a temperature control system and is independent of the power supply system of the microcontroller; Magnetic particle vibration device: It consists of an electromagnet, a particle suspension cavity and a magnetic field intensity controller. Its working power supply is completely isolated from the microcontroller power supply system. The above devices all exist as independent physical units of the system and are connected to the single-chip microcomputer only through signal transmission lines (not power supply or control lines). The physical phenomena they produce are not affected by the operating status of the single-chip microcomputer. Physical phenomena with constant periodic characteristics in the environment selected in the generation module include, but are not limited to: the carrier migration period of semiconductor materials under constant voltage; the round-trip period of ion directional movement in an electrolyte solution of preset concentration; the stimulated vibration period of a certain type of crystal under laser irradiation of preset frequency; the collision period of thermal motion of fixed mass gas molecules in a closed cavity; the deflection vibration period of magnetic particles in a magnetic field of preset strength; The dedicated conversion component in the generation module is integrated by the signal acquisition unit, the period purification unit, the pulse shaping unit and the feedback verification unit; During the operation phase of the dedicated conversion component, the signal acquisition unit selects a period from the preset physical phenomenon , which is converted into the initial electrical signal through the corresponding conversion element: , periodic purification unit pair Noise is filtered out and the cycle is locked by a closed-loop cycle locking circuit, so that the output cycle is stable. The purified signal , the pulse shaping unit will Compared with the preset threshold, when When the output width is greater than or equal to the preset threshold High-level pulses form a pulse train , the feedback verification unit monitors the pulse interval in real time, and the real-time deviation exceeds That is, the periodic purification unit is triggered to make corrections and finally output a unique pulse train with a fixed time interval; Where: is the signal amplitude; It is a time variable calculated from the moment when the signal acquisition unit starts to capture the periodic change of the preset physical phenomenon; is the initial phase; The closed-loop period locking circuit is composed of a period comparator, an error signal generator, a proportional-integral regulator, and a controllable period oscillator connected in cascade sequence. Its working process is as follows: The period comparator receives the purified signal and the reference signal output by the controllable period oscillator in real time. The rising-edge-triggered counter records the period values ​​of the two signals and calculates the period difference (the period difference is equal to the period of the purified signal minus the period of the reference signal). The measurement error of the two period values ​​does not exceed one billionth of the natural period. The error signal generator receives the period difference and linearly converts it into a voltage type error signal, when the period difference is 0, the error signal is 0 volt, when the period difference is positive, the error signal outputs a positive voltage not exceeding 5 volts, and when the period difference is negative, the error signal outputs a negative voltage not lower than -5 volts; The proportional-integral regulator processes the error signal by combining proportional regulation and integral regulation, and outputs a control voltage, the proportional regulation quickly reduces the instantaneous error, and the integral regulation eliminates the steady-state error, so that the control voltage linearly responds to the period difference; The voltage-controlled oscillation unit of the controllable period oscillator dynamically adjusts the oscillation frequency according to the control voltage, when the control voltage is 0 volt, the period of the reference signal is equal to the inherent period, when the control voltage is a positive voltage, the oscillation frequency decreases to make the period of the reference signal increase, and the increase amount is proportional to the control voltage value, and when the control voltage is a negative voltage, the oscillation frequency increases to make the period of the reference signal decrease, and the decrease amount is proportional to the absolute value of the control voltage; The deviation of the period of the adjusted reference signal from the inherent period is not more than 8 parts per billion of the inherent period, through the above-mentioned closed-loop feedback, when the period of the purified signal fluctuates due to interference, the circuit can correct the period difference to an absolute value not more than 8 parts per billion of the inherent period within 10 periods, and ensure that the period of the reference signal is stably locked to the inherent period; The conversion element includes a carrier concentration sensor, an ion migration detector, a vibration sensor, a molecular collision counter, and a particle deflection detector, When noise filtering is performed, a filter suitable for the physical phenomenon is used for noise filtering, ; The receiving module is used for continuously receiving the reference pulse train, and comparing the cumulative number difference between the local clock and the reference pulse in real time to adjust the oscillation frequency of the single-chip microcomputer to eliminate the difference; During the operation stage of the receiving module, the oscillation frequency of the single-chip microcomputer is adjusted as follows: Calculate the cumulative number difference ; The adjusted oscillation frequency of the single-chip microcomputer is: ; In the formula: is the initial frequency of the local clock of the clock calibration receiving module; is the time interval between two consecutive reference pulses; is the frequency of the reference pulse; is the linear fine-tuning coefficient; In the formula, represents the actual cumulative pulse number of the local clock within the time, represents the theoretical cumulative number of the reference pulse within the time; It should be noted that the linear fine-tuning coefficient Initial calibration stage: when the local clock and the cumulative number difference of reference pulses When the difference is larger (such as ), a larger k value (such as 0.6

[0022] Fine-tuning calibration stage: when the cumulative number difference is smaller (such as 1

[0023] Steady-state maintenance stage: when the cumulative number difference tends to 0 (such as ΔN|=0 or 1), a smaller k value (such as 0.1 In addition, the maximum value of k needs to be limited to within 0.8 to prevent the local clock frequency from suddenly changing due to a large adjustment amplitude in a single adjustment, which would disrupt the continuity of system operation; the minimum value should not be less than 0.1 to ensure that small deviations can still be effectively corrected under environmental interference.

[0024] The distribution module is used to collect instructions sent by each single-chip microcomputer, sort them according to the preset execution window period of the task associated with the instructions, and then distribute them to the target single-chip microcomputer; The running process of the distribution module includes: Instruction collection link: the distribution module receives instruction data packets sent by each single-chip microcomputer in real time through a preset signal interface. The instruction data packet contains instruction content, initiator identification, target identification, and task association code, and is stored in a temporary buffer area; Sorting link: extract the preset execution window period parameters corresponding to the task association code in each instruction data packet, i.e., the earliest start timestamp and the latest completion timestamp, and sort the buffer area instructions according to the logic that the higher the priority, the earlier the latest completion timestamp. If the timestamps are the same, a secondary sorting or parallel sorting is performed according to the importance level of the function module to which the initiator belongs; Targeted distribution link: according to the sorting result, the instruction data packet is sent to the target single-chip microcomputer through the corresponding data transmission channel one by one, and the distribution time and instruction state are recorded synchronously, and the instructions in the temporary buffer area whose instruction state is completed are cleared; The feedback module is used to collect the state information of each single-chip microcomputer after executing the instructions, encapsulate the collected state information of each single-chip microcomputer after executing the instructions, and feedback to the single-chip microcomputer that initiated the instructions; The state information of each single-chip microcomputer after executing the instructions in the feedback module includes: execution progress, result code, and abnormal reason; Further explanation of the execution progress, result code, and abnormal reason: Execution progress: Quantify the percentage of the current completed steps based on the total operation steps contained in the instruction. For example, a certain instruction needs to complete "data collection - operation processing - result output" for 3 steps, and the execution progress is 66.66% when the first 2 steps are completed. Record the actual time consumption of each step and compare it with the preset standard time consumption to generate a progress deviation value (such as 5% ahead or 3% behind) to assist in judging the execution efficiency. Result code: Use 4-digit code, the first 2 digits represent the instruction type (such as "01" for data transmission type, "02" for control type); the last 2 digits represent the execution result, for example, "00" means completely in line with the expected completion; "01" means the core function is completed but the additional function is not implemented; "10" means the execution is interrupted and cannot be recovered; "11" means the execution result conflicts with the expectation. Abnormal reason: Hardware related: including "specified interface has no signal input", "execution component vibration exceeds stable threshold", "power supply voltage fluctuation amplitude exceeds 3%", and other quantifiable physical abnormalities. Logical correlation: including "instruction parameters conflict with local preset range", "predecessor dependent instruction not executed", "simultaneously received instructions have inadmissible overlap in timing", and other program running abnormalities. All abnormal reasons are associated with specific occurrence time (accurate to 1 / 10 of the reference pulse period) for easy tracing and troubleshooting; When the state information of each single-chip execution instruction is packaged in the feedback module, the packaging format of the state information of each single-chip execution instruction is consistent, and the packaging content is the execution progress, result code, and abnormal reason; Mediation module, for real-time monitoring and identifying instruction execution conflict or timing conflict, mediation according to the preset rule of ensuring system core function priority, eliminating conflict; When the mediation module runs to monitor and identify instruction execution conflict or timing conflict, it continuously scans the instruction execution requests sent by each single-chip, records the resources involved in each request, including: specific interface, operation unit, and planned execution period. When two or more instruction requests point to the same resource and there is overlap in the planned execution period, it is determined as instruction execution conflict; when there is a dependency relationship between instructions, it is determined as timing conflict; Examples of the above dependency relationship: For example, B instruction needs to be executed after A instruction is completed, but it is monitored that B instruction starts before A instruction; The specific interface and the operation unit are independent of the single-chip microcomputers and are shared and cooperative components, the specific interface, the operation unit and all the single-chip microcomputers are connected through a dedicated signal interaction path, and can be called by any single-chip microcomputer to complete instruction execution; The specific interface is, for example, an instruction transmission interface, a state feedback interface, a pulse signal interface and a resource calling interface. After the mediation module identifies the conflicts, the number of single-chip microcomputers associated with each conflict instruction is obtained, and the conflict instruction associated with a large number of single-chip microcomputers is determined as a priority execution object and is given a resource use right. The rest of the conflict instructions enter a preset dynamic waiting pool, the instructions in the pool are sorted in real time according to the number of associated single-chip microcomputers, when the priority execution conflict instruction ends or an execution gap occurs, the conflict instruction associated with the largest number of single-chip microcomputers in the dynamic waiting pool is automatically promoted and obtains the resource use right. The monitoring module is used to track the running parameters of the system modules and the single-chip microcomputers in real time, when the parameters exceed the preset threshold, an abnormal signal is triggered and a preset backup cooperation mechanism is activated. The preset backup cooperation mechanism includes but is not limited to: The preset backup cooperation mechanism one: after the system triggers an abnormal signal, the material resonance sensor equipped with each single-chip microcomputer is started, the resonance frequency change of a specific solid material affected by environmental pressure is captured, and the resonance frequency change is converted into a temporary cooperation signal; at the same time, according to the execution stage of the task undertaken by the abnormal module, the task is disassembled into multiple continuous operation units, the operation units are dynamically allocated according to the real-time load of the unaffected single-chip microcomputer, the execution order of each operation unit is coordinated through the temporary cooperation signal, the uninterrupted system core function is ensured, and after the abnormality is eliminated, the task flow is reorganized to restore the original cooperation mode. The preset backup cooperation mechanism two: when the system triggers an abnormal signal, the environmental field strength sensing component of each single-chip microcomputer is activated, the fluctuation data of a certain stable field strength in the surrounding space is collected, and a temporary synchronization reference is generated; then according to the importance of the function of the abnormal module, the tasks undertaken by the abnormal module are sorted by priority, the high-priority tasks are preferentially allocated to the unaffected single-chip microcomputers with corresponding function interfaces, the task execution time points of each single-chip microcomputer are calibrated through the temporary synchronization reference, the on-time completion of the key tasks is ensured, and after the abnormality is eliminated, the tasks are gradually returned and the original cooperation architecture is restored. The preset backup cooperation mechanism three: after the system triggers an abnormal signal, the energy fluctuation capture device built-in each single-chip microcomputer is enabled, the periodic fluctuation information of a certain energy form in the environment is obtained, and the periodic fluctuation information is converted into a temporary cooperation instruction; at the same time, the task undertaken by the abnormal module is functionally disassembled, the core function module is extracted, the core function module is adapted to the corresponding single-chip microcomputer according to the functional compatibility of the unaffected single-chip microcomputer, the running of each core function module is coordinated through the temporary cooperation instruction, the most basic function output of the system is maintained, and after the abnormality is eliminated, the function modules are re-integrated to restore the original cooperation state. The monitoring module tracks the system module of the running parameter, including the generating module, the receiving module, the distribution module, the feedback module and the mediation module, and the running parameter includes the module response time, the single-chip microcomputer load rate, the pulse interval deviation of the generating module, the synchronization error of the receiving module, the instruction retention number of the distribution module, the feedback delay of the feedback module and the conflict processing time of the mediation module; The synchronization error of the receiving module is the time difference between the local clock and the reference clock after adjustment. The abnormal signal triggered by the monitoring module is a digital signal composed of the module name and the single-chip microcomputer number of the running parameter source exceeding the preset threshold. In the abnormal signal triggering stage, the abnormal signal is synchronously transmitted to the mediation module and the distribution module, and the preset backup collaborative mechanism is activated. The backup collaborative mechanism is customized by the system end user. The generating module is connected with the receiving module and the distribution module through wireless network interaction, the distribution module is connected with the feedback module through wireless network interaction, the feedback module is connected with the mediation module through wireless network interaction, and the mediation module is connected with the monitoring module through wireless network interaction.

[0025] In the embodiment, the generating module selects a physical phenomenon with constant period characteristics in the environment, converts it into a pulse train with fixed and unique time interval through a special conversion component, and outputs it as a unified time reference signal source of the whole system. The receiving module receives the reference pulse train continuously, compares the cumulative number difference between the local clock and the reference pulse in real time, adjusts the single-chip microcomputer oscillation frequency to eliminate the difference, collects the instructions sent by each single-chip microcomputer, sorts them according to the preset execution window period of the instruction associated task, and then distributes them to the target single-chip microcomputer. The feedback module further collects the state information of each single-chip microcomputer after executing the instruction, encapsulates the collected state information, and feeds back to the single-chip microcomputer that initiated the instruction. The mediation module monitors and identifies the instruction execution conflict or timing conflict in real time, mediates according to the preset rule of prioritizing the core function of the system, eliminates the conflict, and finally the monitoring module tracks the running parameters of the system module and the single-chip microcomputer in real time. When the parameter exceeds the preset threshold, an abnormal signal is triggered and the preset backup collaborative mechanism is activated.

[0026] In the above embodiment, the system can provide a unified time reference based on the constant period physical phenomenon in the environment, synchronize the clocks of each single-chip microcomputer, distribute the instructions in order according to the task window period, ensure the order of execution, feedback the execution status in time, mediate the instruction and timing conflict, prioritize the core function, monitor the running parameters in real time, activate the backup mechanism in case of abnormality, improve the collaborative efficiency and stability of multiple single-chip microcomputers, reduce conflicts, and enhance the fault tolerance of the system. Embodiment 2:

[0027] In a specific implementation level, on the basis of embodiment 1, the present embodiment refers to Figure 2 A clock synchronization instruction synchronization system for multiple single-chip computers to work cooperatively is further described in detail: A clock synchronization instruction synchronization method for multiple single-chip computers to work cooperatively includes the following steps: A physical phenomenon with constant periodic characteristics in the environment is captured, and a special conversion component is used to convert the physical phenomenon into a pulse train with fixed and unique time intervals, to generate and output a unified time reference for the entire system; The reference pulse train is continuously received, and the cumulative number difference between the local clock and the reference pulse is compared in real time, and the difference is eliminated by linearly fine-tuning the self-oscillation frequency, so that the local clock and the reference clock achieve zero-difference synchronization; The instructions issued by each single-chip computer are aggregated, sorted according to the preset execution window period of the task associated with the instruction, and the sorted instructions are distributed to the corresponding target single-chip computer; The state information after each single-chip computer executes the instruction is collected, including execution progress, result code and abnormal reason, and the state information is packaged in a unified format and fed back to the single-chip computer that initiates the instruction; Real-time monitoring and identification of conflicts in the instruction execution process, including simultaneous invocation of the same resource and contradictory instruction execution sequence, and mediation of the conflict according to the preset rule of prioritizing the core function of the system to eliminate the conflict; Real-time tracking of the running parameters of each part and single-chip computer, including module response time and single-chip computer load rate, and when the running parameters exceed the preset threshold, an abnormal signal is triggered and the preset standby cooperation mechanism is activated; The preset execution window period includes the earliest start time and the latest completion time.

[0028] In summary, in the above-mentioned embodiments, the system uses a constant periodic physical phenomenon in the environment as a unified time reference, forms a stable pulse through accurate conversion, can real-time calibrate the local clock of each single-chip computer, greatly reduces the clock deviation, and guarantees the time synchronization accuracy of the whole system. At the same time, the instructions are scheduled in order according to the task preset execution window, and the instruction distribution efficiency is improved by combining with the function importance grading. It can dynamically identify and handle instruction execution and timing conflicts, prioritize tasks associated with more devices, reduce resource contention, and uniformly package execution state feedback to facilitate the instruction initiator to track progress and results in real time. In addition, real-time monitoring of system running parameters triggers the standby mechanism when the threshold is exceeded, enhancing the stability and fault tolerance of the system, and overall improving the reliability and efficiency of multiple single-chip computers working cooperatively.

[0029] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination, characterized in that: include: The generation module is used to select physical phenomena with constant periodic characteristics in the environment and convert them into a unique pulse train with a fixed time interval through a dedicated conversion component. This pulse train is then output as a unified time reference signal source for the entire system. The receiving module is used to continuously receive the reference pulse train and compare the accumulated difference between the local clock and the reference pulse in real time to adjust the oscillation frequency of the microcontroller to eliminate the difference; The distribution module is used to collect the instructions issued by each MCU, sort them according to the preset execution window period of the task associated with the instruction, and distribute them to the target MCU in a targeted manner; The feedback module is used to collect the status information of each microcontroller after executing the instruction, encapsulate the collected status information of each microcontroller after executing the instruction, and feed it back to the microcontroller that initiated the instruction; The mediation module is used to monitor and identify instruction execution conflicts or timing conflicts in real time, and mediate and resolve conflicts based on preset rules that prioritize the core functions of the system; The monitoring module is used to track the operating parameters of the system modules and the single-chip microcomputer in real time. When the parameters exceed the preset threshold, an abnormal signal is triggered and the preset backup coordination mechanism is activated.

2. A clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: The physical phenomena with constant periodic characteristics in the environment selected in the generation module include, but are not limited to: the carrier migration period of semiconductor materials under constant voltage; the round-trip period of ion directional movement in an electrolyte solution of preset concentration; the stimulated vibration period of a certain type of crystal under laser irradiation of preset frequency; the collision period of thermal motion of fixed mass gas molecules in a closed cavity; and the deflection vibration period of magnetic particles in a magnetic field of preset strength. The dedicated conversion component in the generation module is integrated by a signal acquisition unit, a period purification unit, a pulse shaping unit and a feedback verification unit.

3. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 2, characterized in that: During the operation phase of the dedicated conversion component, the signal acquisition unit selects a periodic , which is converted into the initial electrical signal through the corresponding conversion element: , periodic purification unit pair Noise is filtered out and the cycle is locked by a closed-loop cycle locking circuit, so that the output cycle is stable. The purified signal , the pulse shaping unit will Compared with the preset threshold, when When the output width is greater than or equal to the preset threshold High-level pulses form a pulse train , the feedback verification unit monitors the pulse interval in real time, and the real-time deviation exceeds That is, the periodic purification unit is triggered to make corrections and finally output a unique pulse train with a fixed time interval; Where: is the signal amplitude; It is a time variable calculated from the moment when the signal acquisition unit starts to capture the periodic change of the preset physical phenomenon; is the initial phase; Among them, the conversion elements include carrier concentration sensors, ion migration detectors, vibration sensors, molecular collision counters, and particle deflection detectors. When performing noise filtering, a filter adapted to the physical phenomenon is used to filter out noise. .

4. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: During the operation phase of the receiving module, the oscillation frequency of the microcontroller is adjusted to comply with the following: Calculate the cumulative difference ; The oscillation frequency of the microcontroller after adjustment: ; Where: Calibrate the initial local clock frequency of the receiving module for clock calibration; is the time interval between two consecutive reference pulses; is the frequency of the reference pulse; is the linear fine-tuning coefficient; in, express The actual accumulated pulse number of the local clock within the time, express The theoretical cumulative number of reference pulses within a time period.

5. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: The distribution module operation process includes: Instruction collection link: The distribution module receives the instruction data packets sent by each microcontroller in real time through the preset signal interface. The instruction data packets contain the instruction content, initiator identification, target identification, and task association code, and are stored in a temporary buffer area; Sorting: Extract the preset execution window parameters corresponding to the task association code in each instruction data packet, namely the earliest start timestamp and the latest completion timestamp. Sort the instructions in the cache by the logic that the earlier the latest completion timestamp, the higher the priority. If the timestamps are the same, they are sorted again according to the importance level of the functional module to which the initiator belongs, or sorted in parallel. Directed distribution link: According to the sorting results, the instruction data packets are sent to the target microcontroller through the corresponding data transmission channel in sequence, and the distribution time and instruction status are recorded synchronously. At the same time, the instruction data in the temporary cache area with the instruction status of completed distribution is cleared.

6. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: The status information after each single chip microcomputer executes the instruction in the feedback module includes: execution progress, result code, and abnormal reason; When the feedback module encapsulates the status information after each single-chip microcomputer executes the instruction, the encapsulation format of the status information after each single-chip microcomputer executes the instruction is consistent, and the encapsulation content is the execution progress, result code, and exception reason.

7. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: When the mediation module runs to monitor and identify instruction execution conflicts or timing conflicts, it continuously scans the instruction execution requests issued by each single-chip microcomputer and records the resources involved in each request, including: specific interfaces, computing units, and planned execution time periods. When two or more instruction requests simultaneously point to the same resource and the planned execution time periods overlap, it is determined to be an instruction execution conflict; when there is a dependency relationship between instructions, it is determined to be a timing conflict. After the mediation module identifies the conflict, it obtains the number of microcontrollers associated with each conflicting instruction, determines the conflicting instruction with the largest number of associated microcontrollers as the priority execution object and grants resource usage rights; The remaining conflicting instructions enter the preset dynamic waiting pool. The instructions in the pool are sorted in real time according to the number of associated MCUs. When the conflicting instruction with priority is executed or an execution gap occurs, the conflicting instruction with the largest number of associated MCUs in the dynamic waiting pool automatically takes over and obtains resource usage rights.

8. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: The system modules for tracking operating parameters of the monitoring module include a generation module, a receiving module, a distribution module, a feedback module and a mediation module. The operating parameters include module response time, microcontroller load rate, pulse interval deviation of the generation module, synchronization error of the receiving module, instruction retention number of the distribution module, feedback delay of the feedback module, and conflict processing time of the mediation module; The synchronization error of the receiving module is the time difference between the local clock and the reference clock after adjustment; The abnormal signal triggered by the monitoring module is a digital signal composed of the module name and the MCU number of the operating parameter source that exceeds the preset threshold. During the abnormal signal triggering phase, the abnormal signal is synchronously transmitted to the mediation module and the distribution module, and then the preset backup coordination mechanism is activated: Among them, the backup coordination mechanism is customized by the system end user.

9. The clock synchronization instruction synchronization system for multiple single-chip microcomputers working in coordination according to claim 1, characterized in that: The generation module is interactively connected to the receiving module and the distribution module via a wireless network. The distribution module is interactively connected to the feedback module via a wireless network. The feedback module is interactively connected to the mediation module via a wireless network. The mediation module is interactively connected to the monitoring module via a wireless network.

10. A method for synchronizing clock synchronization instructions for collaborative operation of multiple single-chip microcomputers, the method being an implementation method of a system for synchronizing clock synchronization instructions for collaborative operation of multiple single-chip microcomputers as claimed in any one of claims 1 to 9, characterized in that: The following steps are involved: Capturing physical phenomena with constant periodic characteristics in the environment, using dedicated conversion components to convert the physical phenomena into unique pulse trains with fixed time intervals, and generating and outputting a unified time base for the entire system; Continuously receiving the reference pulse train, comparing the cumulative number difference between the local clock and the reference pulse in real time, and linearly adjusting its own oscillation frequency to eliminate the difference, so that the local clock and the reference clock achieve zero-difference synchronization; Gather the instructions issued by each MCU, sort them according to the preset execution window of the task associated with the instruction, and distribute the sorted instructions to the corresponding target MCU; Collect the status information of each MCU after executing the instruction, including the execution progress, result code and exception reason, encapsulate the status information in a unified format, and feed it back to the MCU that initiated the instruction; Real-time monitoring and identification of conflicts during instruction execution, including simultaneous resource calls and inconsistent instruction execution order, and mediation to resolve conflicts based on pre-set rules prioritizing core system functions. Real-time tracking of operating parameters of each component and the MCU, including module response time and MCU load rate. When these operating parameters exceed preset thresholds, an abnormal signal is triggered and a preset backup coordination mechanism is activated. The preset execution window includes the earliest start time and the latest completion time.

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