A method, apparatus and terminal equipment for dynamic voltage frequency adjustment

Abstract

This invention belongs to the field of high-integration SOC chip technology and discloses a dynamic voltage and frequency adjustment method, device, and terminal equipment. The method includes: obtaining a mapping table; determining the voltage level and frequency level to be adjusted of the subsystem based on the load strength of the subsystem; sending the voltage level and frequency level to be adjusted of multiple subsystems to the DVFS driver; determining, in the mapping table, the target voltage register value corresponding to the maximum voltage value among the multiple voltage values ​​corresponding to the multiple voltage levels to be adjusted, and the target frequency register value corresponding to the maximum frequency value among the multiple frequency values ​​corresponding to the multiple frequency levels to be adjusted; writing the target voltage register value into the register of the power chip and the target frequency register value into the register of the frequency chip; and adjusting the voltage of multiple subsystems to the target voltage value and the frequency to the target frequency value through the DVFS driver. This invention completes the DVFS process without delay.

Description

Technical Field

[0001] This invention belongs to the field of high-integration SOC chip technology, and specifically relates to a dynamic voltage and frequency adjustment method, device and terminal equipment. Background Technology

[0002] Highly integrated System-on-Chip (SoC) chips are the brains of various types of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars; SoC chips are ubiquitous. In practical applications, the SoC chip of a terminal device (such as a mobile phone, tablet, POS machine, or adult watch) comprises multiple subsystems. For example, an application processor, a communication processor, or a system processor can all be considered a subsystem. To achieve low power consumption, the frequencies and operating frequencies of multiple subsystems need to be dynamically adjusted.

[0003] In existing technologies, when multiple subsystems need to perform DVFS (Dynamic Voltage and Frequency Scaling), a driver needs to be written for each subsystem, resulting in high development costs, long execution paths, long DVFS execution time, and low efficiency. Summary of the Invention

[0004] The purpose of this invention is to allow multiple subsystems to share a single DVFS driver, rather than writing a separate driver for each subsystem. This reduces development costs, decreases DVFS execution time, and improves efficiency. Furthermore, the pre-established mapping table records voltage and frequency register values, allowing direct configuration of voltage and frequency register values ​​into the power supply chip's registers and vice versa. This eliminates the need for upper-layer software to temporarily calculate and write the actual voltage or frequency values ​​into registers when calling the DVFS driver, significantly reducing DVFS driver execution time and latency. Terminal devices can reduce voltage and frequency under low load to save power, and increase voltage and frequency under increased load to provide higher performance, thus balancing power consumption and performance.

[0005] In a first aspect, embodiments of the present invention provide a dynamic voltage frequency adjustment method, applied to a terminal device comprising multiple subsystems configured to share the same DVFS driver, the method comprising:

[0006] Obtain a pre-established mapping table, which includes the mapping relationship between the voltage level, voltage value and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value and frequency register value of each subsystem.

[0007] The load intensity of the multiple subsystems is obtained through the load module, and for each subsystem, the voltage level and frequency level to be adjusted for the subsystem are determined based on the load intensity of the subsystem.

[0008] Send the voltage and frequency ranges to be adjusted of the multiple subsystems to the DVFS driver. Based on the multiple voltage and frequency ranges to be adjusted, the DVFS driver determines the target voltage register value corresponding to the maximum voltage value among the multiple voltage values ​​corresponding to the multiple voltage ranges to be adjusted, and the target frequency register value corresponding to the maximum frequency value among the multiple frequency values ​​corresponding to the multiple frequency ranges to be adjusted, in the mapping table.

[0009] Write the target voltage register value into the register of the power chip, and write the target frequency register value into the register of the frequency chip;

[0010] The voltages of the multiple subsystems are adjusted to target voltage values ​​using the DVFS driver, and the frequencies of the multiple subsystems are adjusted to target frequency values ​​using the DVFS driver; the target voltage value is the voltage value corresponding to the target voltage register value in the mapping table, and the target frequency value is the frequency value corresponding to the target frequency register value in the mapping table.

[0011] Optionally, the process of establishing the mapping table includes:

[0012] Obtain the voltage threshold and frequency threshold for each subsystem;

[0013] For each subsystem, multiple voltage levels and the voltage value corresponding to each voltage level are extracted from the voltage domain, and the voltage register value corresponding to each voltage value is calculated to obtain the first mapping relationship between the voltage level, voltage value and voltage register value.

[0014] For each subsystem, multiple frequency levels and the corresponding frequency value are extracted from the frequency domain, and the frequency register value corresponding to each frequency level is calculated respectively to obtain the second mapping relationship between the frequency level, the frequency value and the frequency register value.

[0015] A mapping table is established based on the first mapping relationship and the second mapping relationship.

[0016] Optionally, the step of determining, through the DVFS driver, the target voltage register value corresponding to the maximum voltage value among the multiple voltage values ​​corresponding to multiple voltage levels to be adjusted, and the target frequency register value corresponding to the maximum frequency value among the multiple frequency values ​​corresponding to multiple frequency levels to be adjusted, in the mapping table, includes:

[0017] The DVFS driver searches the mapping table for the voltage values ​​to be adjusted for each voltage level and the frequency values ​​to be adjusted for each frequency level.

[0018] The largest of the multiple voltage values ​​to be adjusted is determined as the target voltage value, and the largest of the multiple frequency values ​​to be adjusted is determined as the target frequency value;

[0019] The target voltage register value corresponding to the target voltage value and the target frequency register value corresponding to the target frequency value are found in the mapping table.

[0020] Optionally, the mapping table may also include the mapping relationship between voltage stabilization time and voltage level, voltage value and voltage register value, as well as the mapping relationship between frequency stabilization time and frequency level, frequency value and frequency register value.

[0021] Optionally, after writing the target voltage register value to the power supply chip and the target frequency register value to the frequency chip, the method further includes:

[0022] Find the target voltage stabilization duration corresponding to the target voltage register value and the target frequency stabilization duration corresponding to the target frequency register value in the mapping table;

[0023] Configure the timer duration based on the target voltage stability duration and the target frequency stability duration;

[0024] Upon receiving a timer duration interrupt, respond to the timer duration interrupt by executing the steps of adjusting the voltage of the multiple subsystems to the target voltage value and adjusting the frequency of the multiple subsystems to the target frequency value via the DVFS driver.

[0025] Optionally, the method further includes:

[0026] Before receiving the timer duration interrupt, other system services are executed based on system service requirements until the timer duration interrupt is received. Then, the steps of adjusting the voltage of the multiple subsystems to the target voltage value and adjusting the frequency of the multiple subsystems to the target frequency value through the DVFS driver are executed.

[0027] After adjusting the voltage and frequency of the multiple subsystems, other system services will continue to be executed.

[0028] Secondly, embodiments of the present invention provide a dynamic voltage frequency adjustment device applied to a terminal device comprising multiple subsystems configured to share the same DVFS driver. The device is specifically used to perform the following steps:

[0029] Obtain a pre-established mapping table, which includes the mapping relationship between the voltage level, voltage value and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value and frequency register value of each subsystem.

[0030] The load intensity of the multiple subsystems is obtained through the load module, and for each subsystem, the voltage level and frequency level to be adjusted for the subsystem are determined based on the load intensity of the subsystem.

[0031] The DVFS driver sends the voltage and frequency levels to be adjusted of the multiple subsystems. Based on the multiple voltage and frequency levels to be adjusted, the DVFS driver determines the target voltage register value to be written to the power supply chip and the target frequency register value to be written to the frequency chip in the mapping table.

[0032] Write the target voltage register value into the register of the power chip, and write the target frequency register value into the register of the frequency chip;

[0033] The voltages of the multiple subsystems are adjusted to target voltage values ​​using the DVFS driver, and the frequencies of the multiple subsystems are adjusted to target frequency values ​​using the DVFS driver; the target voltage value is the voltage value corresponding to the target voltage register value in the mapping table, and the target frequency value is the frequency value corresponding to the target frequency register value in the mapping table.

[0034] Thirdly, embodiments of the present invention provide a terminal device, the terminal device comprising multiple subsystems configured to share the same DVFS driver, and further comprising:

[0035] At least one processor;

[0036] Memory for storing the at least one processor-executable instruction;

[0037] The at least one processor is configured to execute the instructions to implement the method as described in the first aspect.

[0038] Fourthly, embodiments of the present invention provide a computer-readable storage medium that, when instructions in the computer-readable storage medium are executed by a processor of a terminal device, enables the terminal device to perform the method described in the first aspect.

[0039] Fifthly, embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0040] The technical solution provided in this invention pre-establishes a mapping table, which includes the mapping relationship between the voltage level, voltage value, and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value, and frequency register value of each subsystem. When multiple load modules send the voltage level and frequency level to be adjusted of multiple subsystems to the DVFS driver, the target voltage register value to be written to the power supply chip and the target frequency register value to be written to the frequency chip can be quickly determined from the mapping table based on the mapping relationship between the voltage level, voltage value, and voltage register value, and the mapping relationship between the frequency level, frequency value, and frequency register value. By writing the target voltage register value into the register of the power supply chip and the target frequency register value into the register of the frequency chip, the DVFS driver adjusts the voltage of multiple subsystems to the target voltage value and the frequency of multiple subsystems to the target frequency value.

[0041] As can be seen, this invention allows multiple subsystems to share a single DVFS driver, instead of writing a separate driver for each subsystem. This reduces development costs, DVFS execution time, and improves efficiency. Furthermore, the pre-established mapping table already records voltage and frequency register values. Voltage and frequency register values ​​can be directly configured into the power supply chip's registers, and vice versa. This eliminates the need for upper-layer software to temporarily calculate and write the actual voltage or frequency values ​​into registers when calling the DVFS driver, significantly reducing DVFS driver execution time and latency. The terminal device can reduce voltage and frequency under low load to save power, and increase voltage and frequency under increased load to provide higher performance, thus balancing power consumption and performance. Attached Figure Description

[0042] Figure 1 A flowchart of a dynamic voltage frequency adjustment method provided in an embodiment of the present invention;

[0043] Figure 2 A flowchart illustrating the process of establishing a mapping relationship table according to an embodiment of the present invention;

[0044] Figure 3 for Figure 1 A flowchart illustrating the specific implementation method of step S130;

[0045] Figure 4 A flowchart of another dynamic voltage frequency adjustment method provided in an embodiment of the present invention;

[0046] Figure 5 A flowchart illustrating a specific example provided in this embodiment of the invention. Detailed Implementation

[0047] The present invention will be described in detail below through embodiments.

[0048] Highly integrated System-on-Chip (SoC) chips are the brains of various types of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars; SoC chips are ubiquitous. In practical applications, the SoC chip of a terminal device (such as a mobile phone, tablet, POS machine, or adult watch) comprises multiple subsystems. For example, an application processor, a communication processor, or a system processor can all be considered a subsystem. To achieve low power consumption, the frequencies and operating frequencies of multiple subsystems need to be dynamically adjusted.

[0049] In existing technologies, when multiple subsystems require DVFS (Dynamic Voltage and Frequency Scaling), a separate driver needs to be written for each subsystem, resulting in high development costs, long execution paths, long DVFS execution times, and low efficiency. Dynamic Voltage and Frequency Scaling (DVFS), on the other hand, is a highly efficient low-power technology that reduces power consumption by dynamically adjusting the operating voltage and clock frequency. DVFS allows for a trade-off between power consumption and performance. By reducing voltage and frequency, end devices can reduce power consumption, thereby extending battery life or reducing data center electricity costs. DVFS is dynamic, adjusting voltage and frequency in real time based on the processor's workload. End devices can reduce voltage and frequency under low load to save power, and increase voltage and frequency under increased load to provide higher performance. DVFS can also be used for thermal management. By reducing voltage and frequency, end devices can reduce heat generation, prevent overheating, and reduce cooling requirements.

[0050] Furthermore, when adjusting the voltage and frequency, it is necessary to wait for the voltage and frequency to stabilize before connecting to multiple subsystems. This results in a significant delay, requiring the CPU to wait, which blocks the CPU and prevents it from performing other tasks, thus affecting the performance of the software system.

[0051] To address the aforementioned technical problems in the prior art, this invention provides a dynamic voltage frequency adjustment method with no delay and no blocking. The following is a brief summary of the three inventive points of this invention:

[0052] 1. This invention organizes and logically processes the voltage parameters, frequency parameters, delay parameters, arbitration actions, and voltage and frequency configuration actions of multiple subsystems in the DVFS service, modularizing and objectifying them all. Thus, when performing DVFS (Dynamic Voltage and Frequency Adjustment) on any subsystem, no changes to the logic code are required; only the configuration parameter table needs modification. This configuration parameter table (also known as a mapping table) can include the mapping relationships between multiple voltage levels, voltage values, voltage register values, and voltage stabilization duration parameters (also known as delay parameters) for each subsystem; and can also include the mapping relationships between multiple frequency levels, frequency values, frequency register values, and frequency stabilization duration parameters for each subsystem.

[0053] 2. The mapping table above has recorded the voltage register value and the frequency register value. The voltage register value can be directly configured into the register of the power chip, and the frequency register value can be directly configured into the register of the frequency chip. There is no need to temporarily calculate the voltage or frequency value and write the actual value into the register when the upper-layer software calls the DVFS driver, which greatly reduces the execution time of the DVFS driver and reduces latency.

[0054] 3. The embodiments of the present invention innovate the action of "busy waiting for voltage and frequency to stabilize". By using the timer interrupt method, the CPU does not need to busy wait for voltage and frequency to stabilize. Instead, after setting a timer, the CPU continues to do other business. When the stabilization period is up, the timer interrupt is generated, and the CPU immediately responds to the interrupt, returns to the DVFS process to configure the registers, and completes DVFS, which completes the adjustment of voltage and frequency of multiple subsystems.

[0055] After introducing the above three inventive points of the embodiments of the present invention, the following will provide a detailed description of a dynamic voltage frequency adjustment method provided by the embodiments of the present invention.

[0056] like Figure 1 As shown, this embodiment of the invention provides a dynamic voltage and frequency adjustment method applied to a terminal device comprising multiple subsystems, wherein the multiple subsystems are configured to share the same DVFS driver. Specifically, the terminal device includes a SOC chip, and the SOC chip of the terminal device (such as a mobile phone, tablet, POS machine, or adult watch) includes multiple subsystems, such as an application processor, a communication processor, or a system processor, which can all be referred to as a subsystem. In the prior art, when performing dynamic voltage and frequency adjustment on multiple subsystems, a separate DVFS driver needs to be written for each subsystem. This embodiment of the invention allows multiple subsystems to share a single DVFS driver, which can reduce development costs, reduce DVFS time consumption, and achieve higher efficiency.

[0057] The dynamic voltage frequency adjustment method may include the following steps:

[0058] S110, obtain the pre-established mapping table.

[0059] The mapping table includes the mapping relationship between the voltage level, voltage value and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value and frequency register value of each subsystem.

[0060] As one implementation of the present invention, such as Figure 2 As shown, the process of establishing a mapping table may include the following steps:

[0061] S210, obtain the voltage threshold and frequency threshold for each subsystem.

[0062] S220: For each subsystem, extract multiple voltage levels from the voltage domain and the voltage value corresponding to each voltage level, and calculate the voltage register value corresponding to each voltage value to obtain the first mapping relationship between the voltage level, voltage value and voltage register value.

[0063] S230: For each subsystem, extract multiple frequency levels from the frequency domain and the frequency value corresponding to each frequency level, and calculate the frequency register value corresponding to each frequency value to obtain the second mapping relationship between the frequency level, the frequency value and the frequency register value.

[0064] S240, Establish a mapping table based on the first mapping relationship and the second mapping relationship.

[0065] Specifically, each subsystem corresponds to a voltage domain, which can include multiple voltage levels, each corresponding to a voltage value. For example, there are four voltage levels: the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level. The voltage value corresponding to the first voltage level is 0.7V, the second voltage level is 0.8V, the third voltage level is 0.9V, and the fourth voltage level is 1V. After obtaining the voltage values ​​corresponding to these four voltage levels, the voltage register values ​​corresponding to these four voltage values ​​can be calculated respectively. This yields the mapping relationship between the voltage level, the voltage value, and the voltage register value. For clarity, this mapping relationship can be referred to as the first mapping relationship. Those skilled in the art should understand how to convert voltage values ​​to voltage register values; each voltage value corresponds to one voltage register value, which will not be elaborated further here.

[0066] Similarly, each subsystem corresponds to a frequency domain, which can include multiple frequency levels, each corresponding to a frequency value. For example, there are four frequency levels: the first, second, third, and fourth frequency levels. The first frequency level corresponds to a frequency value of 0.7Hz, the second to 0.8Hz, the third to 0.9Hz, and the fourth to 1Hz. After obtaining the frequency values ​​corresponding to these four frequency levels, the corresponding frequency register values ​​can be calculated. This yields the mapping relationship between the frequency level, the frequency value, and the frequency register value. For clarity, this mapping relationship can be referred to as the second mapping relationship. Those skilled in the art should understand how to convert frequency values ​​to frequency register values; each frequency value corresponds to one frequency register value, which will not be elaborated upon here.

[0067] After obtaining the first and second mapping relationships mentioned above, a mapping relationship table can be established, which includes the first and second mapping relationships. The format of the mapping relationship table is not specifically limited.

[0068] S120 obtains the load strength of multiple subsystems through the load module, and for each subsystem, determines the voltage level and frequency level to be adjusted for that subsystem based on the load strength of that subsystem.

[0069] Specifically, each subsystem corresponds to a load module. For each subsystem, the corresponding load module monitors the load intensity in real time. If the load intensity of a subsystem is high, its voltage and frequency need to be increased; if the load intensity is low, its voltage and frequency need to be decreased. Furthermore, the load module can determine the required voltage and frequency adjustment levels for the subsystem based on its load intensity. The voltage adjustment level refers to the specific voltage setting, and the frequency adjustment level refers to the specific frequency setting.

[0070] S130: Send the voltage and frequency ranges to be adjusted of multiple subsystems to the DVFS driver. Based on the multiple voltage and frequency ranges to be adjusted, the DVFS driver determines the target voltage register value corresponding to the maximum voltage value among the multiple voltage values ​​corresponding to the multiple voltage ranges to be adjusted, and the target frequency register value corresponding to the maximum frequency value among the multiple frequency values ​​corresponding to the multiple frequency ranges to be adjusted, in the mapping table.

[0071] Specifically, multiple load modules determine the voltage and frequency levels to be adjusted for their respective subsystems. These levels are then sent to the DVFS driver. The DVFS driver searches the mapping table for the voltage values ​​corresponding to each voltage level and arbitrates these values. The highest voltage value among the multiple values ​​is determined as the target voltage value for each subsystem, and the corresponding voltage register value is set as the target voltage register value to be written to the power supply chip. Similarly, the DVFS driver searches the mapping table for the frequency values ​​corresponding to each frequency level and arbitrates these values. The highest frequency value among the multiple frequency values ​​is determined as the target frequency value for each subsystem, and the corresponding frequency register value is set as the target frequency register value to be written to the frequency chip.

[0072] As one implementation of this invention, in step S130, based on multiple voltage levels and multiple frequency levels to be adjusted, the DVFS driver determines, through the mapping table, the target voltage register value corresponding to the maximum voltage value among the multiple voltage values ​​corresponding to the multiple voltage levels to be adjusted, and the target frequency register value corresponding to the maximum frequency value among the multiple frequency values ​​corresponding to the multiple voltage levels to be adjusted, such as... Figure 3 As shown, it may include the following steps:

[0073] S131 uses the DVFS driver to look up the adjustable voltage values ​​corresponding to multiple adjustable voltage levels and the adjustable frequency values ​​corresponding to multiple adjustable frequency levels in the mapping table.

[0074] S132, determine the largest voltage value among multiple voltage values ​​to be adjusted as the target voltage value, and determine the largest frequency value among multiple frequency values ​​to be adjusted as the target frequency value.

[0075] S133, look up the target voltage register value corresponding to the target voltage value and the target frequency register value corresponding to the target frequency value in the mapping table.

[0076] Specifically, suppose there are two subsystems that need to adjust voltage and frequency. The first subsystem has a voltage setting of 2, which corresponds to 0.8V in the mapping table. The second subsystem has a voltage setting of 3, which corresponds to 0.9V in the mapping table. By comparing 0.8V and 0.9V, 0.9V is larger. Therefore, the target voltage value is 0.9V. The voltage register value corresponding to 0.9V is then found in the mapping table and used as the target voltage register value to be written to the power supply chip.

[0077] Similarly, suppose there are two subsystems that need to adjust voltage and frequency. The first subsystem has a frequency setting of 2, which corresponds to a frequency of 0.8Hz in the mapping table. The second subsystem has a frequency setting of 3, which corresponds to a frequency of 0.9Hz in the mapping table. By comparing 0.8Hz and 0.9Hz, 0.9Hz is larger. Therefore, the target frequency value is 0.9Hz. The corresponding frequency register value for 0.9Hz is found in the mapping table and used as the target frequency register value to be written to the frequency chip.

[0078] As can be seen, this implementation method can quickly and accurately find the target voltage register value of the power supply chip to be written and the target frequency register value of the frequency chip to be written in the mapping table, without having to calculate the value of the write register temporarily, which greatly reduces the execution time of the DVFS driver and reduces latency.

[0079] S140: Write the target voltage register value into the power supply chip's register, and write the target frequency register value into the frequency chip's register.

[0080] Specifically, after calculating the target voltage register value to be written to the power chip register, the target voltage register value can be directly written into the power chip register, and the target frequency register value can be directly written into the frequency chip register.

[0081] The S150 adjusts the voltage of multiple subsystems to the target voltage value and adjusts the frequency of multiple subsystems to the target frequency value through the DVFS driver.

[0082] The target voltage value is the voltage value corresponding to the target voltage register value in the mapping table, and the target frequency value is the frequency value corresponding to the target frequency register value in the mapping table.

[0083] Specifically, after writing the target voltage register value into the register of the power supply chip and the target frequency register value into the register of the frequency chip, and waiting for the voltage and frequency to stabilize, the voltage of multiple subsystems can be adjusted to the target voltage value and the frequency of multiple subsystems can be adjusted to the target frequency value through the DVFS driver. At this point, the adjustment of the voltage and frequency of multiple subsystems is completed.

[0084] Furthermore, in the actual process of adjusting voltage and frequency, if it is necessary to reduce frequency and voltage, then the frequency must be reduced first and then the voltage must be reduced; if it is necessary to increase frequency and voltage, then the voltage must be increased first and then the frequency must be increased, in order to meet the performance requirements of multiple subsystems.

[0085] The technical solution provided in this invention pre-establishes a mapping table, which includes the mapping relationship between the voltage level, voltage value, and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value, and frequency register value of each subsystem. When multiple load modules send the voltage level and frequency level to be adjusted of multiple subsystems to the DVFS driver, the target voltage register value to be written to the power supply chip and the target frequency register value to be written to the frequency chip can be quickly determined from the mapping table based on the mapping relationship between the voltage level, voltage value, and voltage register value, and the mapping relationship between the frequency level, frequency value, and frequency register value. By writing the target voltage register value into the register of the power supply chip and the target frequency register value into the register of the frequency chip, the DVFS driver adjusts the voltage of multiple subsystems to the target voltage value and the frequency of multiple subsystems to the target frequency value.

[0086] As can be seen, this invention allows multiple subsystems to share a single DVFS driver, instead of writing a separate driver for each subsystem. This reduces development costs, DVFS execution time, and improves efficiency. Furthermore, the pre-established mapping table already records voltage and frequency register values. Voltage and frequency register values ​​can be directly configured into the power supply chip's registers, and vice versa. This eliminates the need for upper-layer software to temporarily calculate and write the actual voltage or frequency values ​​into registers when calling the DVFS driver, significantly reducing DVFS driver execution time and latency. The terminal device can reduce voltage and frequency under low load to save power, and increase voltage and frequency under increased load to provide higher performance, thus balancing power consumption and performance.

[0087] Based on the above embodiments, as an implementation of the present invention, the mapping relationship table also includes the mapping relationship between voltage stabilization time and voltage level, voltage value and voltage register value, as well as the mapping relationship between frequency stabilization time and frequency level, frequency value and frequency register value.

[0088] Because after writing the target voltage register value into the power chip's register and the target frequency register value into the frequency chip's register, the voltage and frequency need to stabilize before the voltage and frequency of multiple subsystems can be adjusted. To prevent the CPU from busy-waiting for voltage and frequency stabilization during this stabilization period, the mapping table also records the mapping relationship between voltage stabilization time and voltage level, voltage value, and voltage register value, as well as the mapping relationship between frequency stabilization time and frequency level, frequency value, and frequency register value. In other words, for each voltage value, the mapping table records how long it takes for the voltage to stabilize when adjusted to that voltage value, and for each frequency value, the mapping table records how long it takes for the frequency to stabilize when adjusted to that frequency value.

[0089] At this point, as one implementation of the present invention, after writing the target voltage register value to the power supply chip and the target frequency register value to the frequency chip, as follows: Figure 4 As shown, the method may also include the following steps:

[0090] S150a: Look up the target voltage stabilization time corresponding to the target voltage register value and the target frequency stabilization time corresponding to the target frequency register value in the mapping table.

[0091] S150b configures the timer duration based on the target voltage stabilization time and the target frequency stabilization time.

[0092] When S150c receives a timer duration interrupt, it responds to the timer duration interrupt and executes the steps of adjusting the voltage of multiple subsystems to the target voltage value and adjusting the frequency of multiple subsystems to the target frequency value through the DVFS driver.

[0093] Specifically, this implementation innovates the "busy waiting for voltage and frequency to stabilize" action by using a timer interrupt. Instead of busy waiting for voltage and frequency to stabilize, the CPU sets a timer; for example, it can choose the larger of the target voltage stabilization time and the target frequency stabilization time as the timer duration. This way, after the timer duration is interrupted, both voltage and frequency have stabilized. The CPU continues performing other tasks. When the stabilization time expires, the timer duration interrupt occurs, and the CPU immediately responds to the interrupt, returning to the DVFS process to adjust the voltage and frequency of multiple subsystems, thus completing the adjustment of the voltage and frequency of multiple subsystems.

[0094] exist Figure 4 Based on the illustrated embodiment, as one implementation of the present invention, the method may further include the following steps:

[0095] Before receiving the timer duration interrupt, other system services are executed based on system business requirements until the timer duration interrupt is received. Then, the steps of adjusting the voltage of multiple subsystems to the target voltage value and adjusting the frequency of multiple subsystems to the target frequency value are performed through the DVFS driver.

[0096] After adjusting the voltage and frequency of multiple subsystems, other system services can continue to be executed.

[0097] In this implementation, the CPU can execute other system services before receiving a timer duration interrupt. Once the timer duration interrupt is received, the CPU will adjust the voltage of multiple subsystems to the target voltage value and adjust the frequency of multiple subsystems to the target frequency value through the DVFS driver. After completing the voltage and frequency adjustment of multiple subsystems, the CPU will continue to execute other system services.

[0098] As can be seen, the CPU does not need to busy-wait for the voltage and frequency to stabilize. Instead, it sets a timer and then continues to perform other tasks. Once the stabilization period is over, the timer interrupt is generated. In this way, during the period when the voltage and frequency stabilize, CPU resources are released, thus achieving the goal of non-blocking CPU operation.

[0099] To clarify the description, the technical solution of this invention will be explained in detail below with reference to a specific example. Suppose a subsystem needs to adjust voltage and frequency, such as... Figure 5 As shown, it may include the following steps:

[0100] Step 1: The upper layer (i.e., the load module in the above embodiment) sends a message to the dvfs driver indicating which voltage and frequency level needs to be adjusted. Let's assume that the voltage and frequency level needs to be adjusted to the 5th level.

[0101] Step 2: The DVFS driver finds the voltage register value corresponding to the voltage value of the 5th level and the frequency register value corresponding to the frequency value of the 5th level in the mapping table.

[0102] Step 3: Configure the voltage register value and frequency register value to the power supply chip and frequency chip.

[0103] Step 4: After configuring the CPU timer (voltage and frequency stabilization duration), immediately proceed with other tasks.

[0104] Step 5: Monitor if the timer is interrupted. If the CPU receives a timer interrupt, proceed to step 6. This avoids blocking the CPU. If the CPU does not receive a timer interrupt, continue executing other tasks.

[0105] Step 6: The DVFS driver configures the "voltage of 1V and frequency of 1GHz for level 5" to the subsystem, thus completing the entire DVFS process.

[0106] As can be seen, this invention allows multiple subsystems to share a single DVFS driver, instead of writing a separate driver for each subsystem. This reduces development costs, DVFS execution time, and improves efficiency. Furthermore, the pre-established mapping table records voltage and frequency register values. Voltage and frequency register values ​​can be directly configured into the power supply chip's registers, and vice versa. This eliminates the need for upper-layer software to temporarily calculate and write the actual voltage or frequency values ​​into registers when calling the DVFS driver, significantly reducing DVFS driver execution time and latency. The terminal device can reduce voltage and frequency under low load to save power, and increase voltage and frequency under increased load to provide higher performance, thus balancing power consumption and performance.

[0107] This invention also provides a dynamic voltage frequency adjustment device applied to a terminal device comprising multiple subsystems configured to share the same DVFS driver. The device is specifically used to perform the following steps:

[0108] Obtain a pre-established mapping table, which includes the mapping relationship between the voltage level, voltage value and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value and frequency register value of each subsystem.

[0109] The load intensity of the multiple subsystems is obtained through the load module, and for each subsystem, the voltage level and frequency level to be adjusted for the subsystem are determined based on the load intensity of the subsystem.

[0110] The DVFS driver sends the voltage and frequency levels to be adjusted of the multiple subsystems. Based on the multiple voltage and frequency levels to be adjusted, the DVFS driver determines the target voltage register value to be written to the power supply chip and the target frequency register value to be written to the frequency chip in the mapping table.

[0111] Write the target voltage register value into the register of the power chip, and write the target frequency register value into the register of the frequency chip;

[0112] The voltages of the multiple subsystems are adjusted to target voltage values ​​using the DVFS driver, and the frequencies of the multiple subsystems are adjusted to target frequency values ​​using the DVFS driver; the target voltage value is the voltage value corresponding to the target voltage register value in the mapping table, and the target frequency value is the frequency value corresponding to the target frequency register value in the mapping table.

[0113] This invention also provides a terminal device, which includes multiple subsystems configured to share the same DVFS driver, and further includes:

[0114] At least one processor;

[0115] Memory for storing the at least one processor-executable instruction;

[0116] The at least one processor is configured to execute the instructions to implement the method as described in the first aspect.

[0117] This invention also provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by the processor of a terminal device, enables the terminal device to perform the method described in the first aspect.

[0118] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0119] The technical solution provided in this invention pre-establishes a mapping table, which includes the mapping relationship between the voltage level, voltage value, and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value, and frequency register value of each subsystem. When multiple load modules send the voltage level and frequency level to be adjusted of multiple subsystems to the DVFS driver, the target voltage register value to be written to the power supply chip and the target frequency register value to be written to the frequency chip can be quickly determined from the mapping table based on the mapping relationship between the voltage level, voltage value, and voltage register value, and the mapping relationship between the frequency level, frequency value, and frequency register value. By writing the target voltage register value into the register of the power supply chip and the target frequency register value into the register of the frequency chip, the DVFS driver adjusts the voltage of multiple subsystems to the target voltage value and the frequency of multiple subsystems to the target frequency value.

[0120] As can be seen, this invention allows multiple subsystems to share a single DVFS driver, instead of writing a separate driver for each subsystem. This reduces development costs, DVFS execution time, and improves efficiency. Furthermore, the pre-established mapping table already records voltage and frequency register values. Voltage and frequency register values ​​can be directly configured into the power supply chip's registers, and vice versa. This eliminates the need for upper-layer software to temporarily calculate and write the actual voltage or frequency values ​​into registers when calling the DVFS driver, significantly reducing DVFS driver execution time and latency. The terminal device can reduce voltage and frequency under low load to save power, and increase voltage and frequency under increased load to provide higher performance, thus balancing power consumption and performance.

[0121] Although embodiments of the present invention have been shown and described above, these embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A dynamic voltage frequency adjustment method, characterized in that, Applied to a terminal device comprising multiple subsystems configured to share the same DVFS driver, the method includes: Obtain a pre-established mapping table, which includes the mapping relationship between the voltage level, voltage value and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value and frequency register value of each subsystem. The load intensity of the multiple subsystems is obtained through the load module, and for each subsystem, the voltage level and frequency level to be adjusted for the subsystem are determined based on the load intensity of the subsystem. Send the voltage and frequency ranges to be adjusted of the multiple subsystems to the DVFS driver. Based on the multiple voltage and frequency ranges to be adjusted, the DVFS driver determines the target voltage register value corresponding to the maximum voltage value among the multiple voltage values ​​corresponding to the multiple voltage ranges to be adjusted, and the target frequency register value corresponding to the maximum frequency value among the multiple frequency values ​​corresponding to the multiple frequency ranges to be adjusted, in the mapping table. Write the target voltage register value into the register of the power chip, and write the target frequency register value into the register of the frequency chip; The voltages of the multiple subsystems are adjusted to target voltage values ​​using the DVFS driver, and the frequencies of the multiple subsystems are adjusted to target frequency values ​​using the DVFS driver; the target voltage value is the voltage value corresponding to the target voltage register value in the mapping table, and the target frequency value is the frequency value corresponding to the target frequency register value in the mapping table.

2. The method according to claim 1, characterized in that, The process of establishing the mapping table includes: Obtain the voltage threshold and frequency threshold for each subsystem; For each subsystem, multiple voltage levels and the voltage value corresponding to each voltage level are extracted from the voltage domain, and the voltage register value corresponding to each voltage value is calculated to obtain the first mapping relationship between the voltage level, voltage value and voltage register value. For each subsystem, multiple frequency levels and the corresponding frequency value are extracted from the frequency domain, and the frequency register value corresponding to each frequency level is calculated respectively to obtain the second mapping relationship between the frequency level, the frequency value and the frequency register value. A mapping table is established based on the first mapping relationship and the second mapping relationship.

3. The method according to claim 1, characterized in that, The step of determining the target voltage register value corresponding to the maximum voltage value among multiple voltage values ​​corresponding to multiple voltage levels to be adjusted, and the target frequency register value corresponding to the maximum frequency value among multiple frequency values ​​corresponding to multiple frequency levels to be adjusted, through the DVFS driver in the mapping table, includes: The DVFS driver searches the mapping table for the voltage values ​​to be adjusted for each voltage level and the frequency values ​​to be adjusted for each frequency level. The largest of the multiple voltage values ​​to be adjusted is determined as the target voltage value, and the largest of the multiple frequency values ​​to be adjusted is determined as the target frequency value; The target voltage register value corresponding to the target voltage value and the target frequency register value corresponding to the target frequency value are found in the mapping table.

4. The method according to any one of claims 1 to 3, characterized in that, The mapping table also includes the mapping relationship between voltage stabilization time and voltage level, voltage value and voltage register value, as well as the mapping relationship between frequency stabilization time and frequency level, frequency value and frequency register value.

5. The method according to claim 4, characterized in that, After writing the target voltage register value to the power supply chip and the target frequency register value to the frequency chip, the method further includes: Find the target voltage stabilization duration corresponding to the target voltage register value and the target frequency stabilization duration corresponding to the target frequency register value in the mapping table; Configure the timer duration based on the target voltage stability duration and the target frequency stability duration; Upon receiving a timer duration interrupt, respond to the timer duration interrupt by executing the steps of adjusting the voltage of the multiple subsystems to the target voltage value and adjusting the frequency of the multiple subsystems to the target frequency value via the DVFS driver.

6. The method according to claim 5, characterized in that, The method further includes: Before receiving the timer duration interrupt, other system services are executed based on system service requirements until the timer duration interrupt is received. Then, the steps of adjusting the voltage of the multiple subsystems to the target voltage value and adjusting the frequency of the multiple subsystems to the target frequency value through the DVFS driver are executed. After adjusting the voltage and frequency of the multiple subsystems, other system services will continue to be executed.

7. A dynamic voltage frequency adjustment device, characterized in that, Applied to a terminal device comprising multiple subsystems configured to share the same DVFS driver, the device is specifically used to perform the following steps: Obtain a pre-established mapping table, which includes the mapping relationship between the voltage level, voltage value and voltage register value of each subsystem, as well as the mapping relationship between the frequency level, frequency value and frequency register value of each subsystem. The load intensity of the multiple subsystems is obtained through the load module, and for each subsystem, the voltage level and frequency level to be adjusted for the subsystem are determined based on the load intensity of the subsystem. The DVFS driver sends the voltage and frequency levels to be adjusted of the multiple subsystems. Based on the multiple voltage and frequency levels to be adjusted, the DVFS driver determines the target voltage register value to be written to the power supply chip and the target frequency register value to be written to the frequency chip in the mapping table. Write the target voltage register value into the register of the power chip, and write the target frequency register value into the register of the frequency chip; The voltage of the multiple subsystems is adjusted to the target voltage value by using the DVFS driver, and the frequency of the multiple subsystems is adjusted to the target frequency value by using the DVFS driver. The target voltage value is the voltage value corresponding to the target voltage register value in the mapping table, and the target frequency value is the frequency value corresponding to the target frequency register value in the mapping table.

8. A terminal device, characterized in that, The terminal device includes multiple subsystems configured to share the same DVFS driver, and further includes: At least one processor; Memory for storing the at least one processor-executable instruction; The at least one processor is configured to execute the instructions to implement the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the terminal device, the terminal device is enabled to perform the method as described in any one of claims 1-6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-6.

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