Manufacturing process for ultra-narrow frame of capacitive touch screen

Abstract

The invention relates to the technical field of capacitive touch screens, in particular to a capacitive touch screen ultra-narrow frame manufacturing process which comprises the following steps: S1, substrate selection; s2, preparing a touch layer; s3, slotting the base material; s4, wiring is carried out; s5, integrating the touch control chip; s6, packaging is carried out; and S7, testing. Through the combination of the asymmetric double-step groove and the fractal geometric wiring, the limitation of a traditional symmetric structure is broken through; the problems of stress concentration, signal attenuation, sealing reliability and the like in the narrow frame manufacturing process are solved through the technologies of femtosecond laser and ultrasonic vibration composite processing, metal-semiconductor composite wire preparation, shape memory alloy-silica gel composite packaging and the like, and compared with the prior art, the performance is remarkably improved; during testing, through on-line detection of terahertz time-domain spectroscopy and establishment of a touch-stress collaborative testing platform, full-dimension and dynamic reliability evaluation of an ultra-narrow frame is realized, and the technical blank of existing static testing is filled.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of capacitive touch screens, in particular to a capacitive touch screen ultra-narrow frame manufacturing process. BACKGROUND

[0002] The technical background of the capacitive touch screen ultra-narrow frame manufacturing process is the problem of excessively wide frame caused by structural limitations of traditional capacitive screens. Early capacitive screens adopt a four-layer composite glass structure, electrodes are arranged at the four corners, and the components are fixed through the edge bonding process, resulting in a frame width generally exceeding 3mm. With the development of display devices towards full screens, the industry's demand for narrow frames is increasingly urgent, and there is an urgent need for touch screens with narrower frames, so the existing technology needs to be improved. SUMMARY

[0003] The purpose of the present application is to provide a capacitive touch screen ultra-narrow frame manufacturing process to solve the problems raised in the background.

[0004] To achieve the above purpose, the present application provides the following technical solution: a capacitive touch screen ultra-narrow frame manufacturing process, comprising the following steps:

[0005] S1: substrate selection, selecting appropriate material as substrate and performing surface pretreatment on the substrate;

[0006] S2: touch layer preparation, adopting a "graphene-silver nanowire" double-layer structure, first preparing a single-layer graphene on the substrate by CVD method, then depositing a silver nanowire network by slot coating technology; using laser direct writing technology to directly engrave electrode patterns on the composite touch layer;

[0007] S3: substrate slotting, slotting processing is performed on the edge of the substrate, and the slotting adopts femtosecond laser and ultrasonic vibration composite processing;

[0008] S4: wiring, first performing metalization pretreatment on the slot, depositing a 50nm thick Al2O3 insulating layer on the slot wall using atomic layer deposition (ALD) technology, the deposition temperature is 150℃, the cycle number is 200 times, the insulating layer breakdown voltage is >100V, ensuring the insulation reliability between electrodes; using electroplating process to prepare 2μm copper wire (purity 99.99%) in the slot, then treating the wire through magnetron sputtering, and then designing electrode traces using three Koch curve fractal structures;

[0009] S5: touch chip integration, connecting the chip, flexible circuit board and wire;

[0010] S6: packaging, first performing shape memory alloy micro-spring presetting; then filling and packaging with low-viscosity silicone; and then performing plasma-induced interface polymerization;

[0011] S7: test, test the packaged product.

[0012] Preferably, the substrate is selected from 0.4mm thick high alumina silicate reinforced glass or 125μm flexible PI film, the glass substrate needs to meet the bending strength ≥800MPa, and the PI film needs to have a thermal shrinkage rate of ≤1.5%. Compared with traditional sodium calcium glass, the bending strength of high alumina glass is increased by 30%, providing structural strength basis for narrow frame.

[0013] Preferably, the surface pretreatment adopts oxygen plasma treatment combined with 5% hydrofluoric acid etching (etching rate 5nm / s), so that the glass surface roughness Ra is less than 0.2μm, the PI film surface introduces hydroxyl groups, and the contact angle is reduced from 85° to below 30°, enhancing the adhesion of the subsequent coating.

[0014] Preferably, the substrate slot is also processed into an asymmetric stepped slot with the upper width being wider than the lower width, the upper step width is 0.3mm, the depth is 60μm, the lower step width is 0.15mm, the depth is 40μm, and the slot bottom has a round corner radius of 5μm. Through ANSYS simulation verification, this structure reduces the edge stress concentration coefficient from 3.2 to 1.8, effectively reducing the risk of glass breakage.

[0015] Preferably, the slot is processed using 532nm femtosecond laser (pulse energy 50nJ, repetition frequency 100kHz) and 20kHz ultrasonic vibration superimposed processing, vibration amplitude 3μm, processing speed 10mm / s. This process realizes a slot wall roughness Ra of less than 0.5μm, and the efficiency is increased by 40% compared with single laser processing, and there is no thermal damage layer.

[0016] Preferably, the wiring adopts an optimization algorithm to minimize the wiring width, thereby further reducing the frame width. A three-dimensional optimization model is constructed with the minimum wiring width, the lowest signal attenuation rate, and the maximum manufacturing feasibility as the goal. Genetic algorithm (GA) + finite element method (FEM) coupling solution is adopted, and the objective function expression is:

[0017] min f(w, a, m) = w·l1 + a·l2 + (1-m)·l3 where w is the wiring width, a is the signal attenuation rate, and m is the manufacturing feasibility coefficient. The three weight coefficients l1, l2 and l3 are 0.5, 0.3 and 0.2 respectively.

[0018] Preferably, the test includes:

[0019] Terahertz time domain spectroscopy online detection, using a 0.3THz terahertz light source to scan the grooved substrate, analyzing the reflection spectrum characteristics of 0.1-1.0THz frequency band, and through the established mathematical model (R 2Real-time calculation of groove depth and groove width size, detection speed 100mm / s, 100% online full detection, instead of traditional sampling detection;

[0020] Three-dimensional capacitance scanning test, using a multi-frequency excitation capacitance test system (excitation frequency 10-100kHz) and a 3D scanning probe (needle tip curvature radius 5um) to detect the three-dimensional distribution of the touch capacitance in the 0.15mm area of the frame, with a resolution of 0.1pF, ensuring that the uniformity deviation of the touch sensitivity in the narrow frame area is less than 5%;

[0021] Touch-stress collaborative test, on the test platform integrating capacitance scanning and micro-stress loading, the sample is subjected to an edge pressure of 10-100mN while the touch test is being conducted, the pressure-capacitance change curve is analyzed by an LSTM machine learning model to identify edge touch failure at the level of 0.1mm, the test time is 30s per sample, ensuring the reliability of the narrow frame under stress;

[0022] Environmental reliability test, the sample is subjected to high-low temperature cycle test (-40℃-85℃, 1000 cycles, 30min dwell time), damp heat test (85℃ / 85%RH, 1000h) and drop test (1.8m drop to steel ground, 3 times on each of the 6 sides), after the test, the touch response time is required to be less than 5ms, the resistance change rate ΔR / R is not greater than 5%, and there is no problem such as package cracking, touch failure, etc.

[0023] Compared with the prior art, the beneficial effects of the present application are:

[0024] The manufacturing process of the ultra-narrow frame of the capacitive touch screen provided by the present application breaks through the limitation of the traditional symmetrical structure by combining the asymmetric double-step groove with the fractal geometric wiring, realizes the reduction of the frame width from 0.3mm to 0.15mm through cross-domain technology integration, and improves the screen-to-body ratio to 98.7%; and through femtosecond laser + ultrasonic vibration composite processing, metal-semiconductor composite wire preparation, shape memory alloy-silicone composite packaging and other processes, the problems such as stress concentration, signal attenuation and sealing reliability in the narrow frame manufacturing are solved, the performance is significantly improved compared with the prior art; through the establishment of the terahertz time domain spectrum online detection and the touch-stress collaborative test platform during the test, the full-dimensional and dynamic reliability evaluation of the ultra-narrow frame is realized, filling the technical gap of the existing static test. Under the premise of ensuring the touch performance, the present application realizes the reliable manufacturing of the ultra-narrow frame of the capacitive touch screen, is suitable for the demand of extreme screen-to-body ratio of high-end electronic equipment, and has significant technical progress and industrialization prospect. BRIEF DESCRIPTION OF DRAWINGS

[0025] Fig. 1 It is a schematic diagram of the groove structure of the substrate of the present application.

[0026] Fig. 2 Figure 2 is a schematic diagram of a substrate slotting structure according to another embodiment of the present application.

[0027] Fig. 3 Figure 3 is a schematic diagram of a wiring structure according to the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0029] Referring to Figs. 1 to 3 The present application provides a technical solution: a manufacturing process of a capacitive touch screen with an ultra-narrow frame, comprising the following steps:

[0030] S1: substrate selection, selecting a suitable material as a substrate and performing surface pretreatment on the substrate;

[0031] S2: touch layer preparation, adopting a "graphene-silver nanowire" double-layer structure, first preparing a single-layer graphene (sheet resistance < 30, light transmittance > 97%) on a substrate by a CVD method, then depositing a silver nanowire network (sheet resistance < 10) with a diameter of 50 nm by a slot coating technology, the composite structure improves the conductivity of the traditional ITO touch layer by 40%, and has better flexibility; using a laser direct writing technology (wavelength 355 nm, pulse width 50 ns) to directly engrave an electrode pattern on the composite touch layer, the line width is controlled within 8 μm, the electrode spacing is 15 μm, and the "honeycomb electrode array" design is innovatively adopted, which reduces the electrode material usage by 25% while ensuring the touch sensitivity;

[0032] S3: substrate slotting, performing slotting treatment on the edge of the substrate, and the slotting adopts femtosecond laser and ultrasonic vibration composite machining;

[0033] S4: wiring, first, pre-treat the groove with metalization, deposit a 50 nm thick Al2O3 insulating layer on the groove wall using atomic layer deposition (ALD) technology, deposition temperature 150°C, cycle number 200 times, insulating layer breakdown voltage > 100 V, ensure the reliability of the electrode insulation; use electroplating process to prepare a 2 μm copper wire (purity 99.99%) in the groove, then process the wire by magnetron sputtering to grow a 100 nm diameter ITO nanocolumn array on the copper surface, sputtering power 100 W, argon flow rate 20 sccm, form a "copper-ITO" composite conductive structure, conductivity up to 5.8 x 10 S / m, 12% higher than pure copper wire; then design the electrode trace with a three-time Koch curve fractal structure, realize an equivalent wire length of 18 mm in a 0.25 mm wide groove, 3 times higher than traditional straight-line wiring. Optimize the branch angle (60° ± 5°) through HFSS simulation to reduce the signal attenuation rate from 15% to 5%, ensure the touch signal transmission under narrow frame;

[0034] S5: touch chip integration, connect the chip, flexible circuit board and wire, select a 0.3 mm x 0.3 mm ultra-low power touch chip (working current < 1 mA), use flip-chip technology to directly solder on the copper wire in the groove, use indium solder balls (diameter 20 μm) as interconnection medium, reflow temperature 200°C, holding time 30 s, realize reliable electrical connection between the chip and the wire; use a 0.3 mm wide extremely narrow FPC (line width / line spacing 50 μm / 50 μm), press the groove electrode through anisotropic conductive adhesive (ACF), press bonding temperature 180°C, pressure 10 MPa, holding time 60 s, connection resistance < 50 mΩ, ensure stable signal transmission;

[0035] S6: packaging, first, preset the shape memory alloy micro spring, prepare a 50 μm x 50 μm NiTi shape memory alloy micro spring array at the bottom of the groove using micro-electro-mechanical systems (MEMS) technology, spring free height 80 μm, phase transition temperature 60°C, the micro spring is in a compressed state at room temperature, and generates a 0.1 MPa compressive stress after heating; then fill and package with low viscosity silicone, use liquid silicone with a viscosity of 8 cP (hardness 20 Shore A), fill the groove through capillary siphon effect in a -0.1 MPa vacuum environment, filling speed 5 mm / s, after filling, heat to 60°C for 10 min, trigger the NiTi alloy phase transition, make the silicone closely adhere to the groove wall, sealing reliability up to 99.9%; then perform plasma-induced interface polymerization, treat the edge of the package with oxygen plasma (power 100 W, treatment time 30 s), then coat UV curing glue (thickness 50 μm), irradiate with 365 nm ultraviolet light (energy 100 mJ / cm 2) solidification, forming a 500nm thick chemical covalent bond transition layer at the interface between the adhesive layer and the glass, and the water absorption rate after the hygrothermal test (85℃ / 85%RH, 1000h) is only 1 / 10 of that of traditional packaging;

[0036] S7: testing, testing the packaged product.

[0037] The substrate is selected from 0.4mm thick high alumina silicate reinforced glass or 125μm flexible PI film. The glass substrate needs to meet the bending strength ≥800MPa, and the PI film needs to have a thermal shrinkage rate of ≤1.5%. Compared with traditional sodium-calcium glass, the bending strength of high alumina glass is increased by 30%, providing structural strength basis for narrow frame.

[0038] The surface pretreatment adopts oxygen plasma treatment combined with 5% hydrofluoric acid etching (etching rate 5nm / s), so that the glass surface roughness Ra<0.2μm, the PI film surface introduces hydroxyl groups, and the contact angle is reduced from 85° to below 30°, enhancing the adhesion of the subsequent coating.

[0039] The substrate slot is also processed into an asymmetric stepped slot with the upper width and the lower width, the upper step width is 0.3mm, the depth is 60μm, the lower step width is 0.15mm, the depth is 40μm, and the slot bottom radius is 5μm. Through ANSYS simulation verification, the edge stress concentration coefficient is reduced from 3.2 to 1.8, effectively reducing the risk of glass breakage.

[0040] The slot is processed using 532nm femtosecond laser (pulse energy 50nJ, repetition frequency 100kHz) and 20kHz ultrasonic vibration superimposed processing, vibration amplitude 3μm, processing speed 10mm / s. This process realizes the slot wall roughness Ra<0.5μm, the efficiency is increased by 40% compared with single laser processing, and there is no thermal damage layer.

[0041] The wiring adopts an optimization algorithm to minimize the wiring width, thereby further reducing the frame width. A three-dimensional optimization model is constructed with the minimum wiring width, the lowest signal attenuation rate, and the maximum manufacturing feasibility as the target. Genetic algorithm (GA) + finite element method (FEM) coupling solution is adopted, and the objective function expression is:

[0042] min f(w, a, m) = w·l1 + a·l2 + (1-m)·l3

[0043] Wherein, w is the wiring width, a is the signal attenuation rate, m is the manufacturing feasibility coefficient, and the three weight coefficients l1, l2, l3 are 0.5, 0.3 and 0.2 respectively.

[0044] The algorithm iteration process is: 1. Parameter initialization: set the wiring space boundary (0.25mmx0.1mm slot section), minimum line width constraint (3μm), wire spacing constraint (≥5μm); 2. Population generation: randomly generate 100 groups of fractal / spiral / tree topological structures as the initial population; 3. Fitness calculation: calculate the resistance, parasitic capacitance and stress distribution of each group of structures by FEM simulation; 4. Selection-crossover-variation: retain the top 20% optimal solutions, generate a new population through arithmetic crossover and Gaussian mutation; 5. Iteration termination: terminate when the target function optimization amplitude is less than 1% for 50 consecutive generations, and output the optimal topology.

[0045] Wiring structure innovation based on algorithm: using fractal-tree hybrid topology, a mixed topology of three Koch curves and binary tree structure is obtained through algorithm optimization, which realizes an equivalent wire length of 22mm in a 0.2mm wide slot, which is 22% higher than the original fractal structure. Key parameters: main branch angle: 58.3° (algorithm optimization optimal solution), secondary branch fractal dimension: 1.65, end wire curvature radius: 2μm.

[0046] Variable width wire design: the algorithm outputs a variable width wire scheme, which uses an 8μm wide wire at the signal input end (to reduce the input impedance), gradually changes to a 3μm wide wire in the middle section (to compress the bezel), and returns to a 5μm wide wire at the output end (to match the chip interface). HFSS simulation shows that this design reduces the resistance by 18% compared to the equal-width wire scheme, while meeting the 0.15mm bezel width requirement.

[0047] Nanoimprint lithography (NIL) wiring: using a SiC mold (line width accuracy ±1μm) to imprint a wire groove in the slot, and filling a 3μm wide copper wire using ALD+electroplating composite process. Compared with the original laser direct writing process, the line width accuracy is improved by 50%, and the edge roughness Ra is less than 0.3μm; a three-layer stereoscopic wiring network is constructed within a 0.1mm depth range: bottom layer: 3μm wide copper wire (signal main line), middle layer: 2μm wide silver nanowire network (shielding layer), top layer: 1μm thick PI insulating layer (dielectric constant 3.2); through algorithm optimization of the interlayer spacing to 8μm, the crosstalk suppression is greater than 40dB, saving 35% horizontal space compared with the planar wiring.

[0048] The test includes:

[0049] Terahertz time-domain spectroscopy online detection: using a 0.3THz terahertz light source to scan the grooved substrate, analyzing the reflection spectrum characteristics in the 0.1-1.0THz frequency band, and calculating the groove depth and groove width size in real time through the established mathematical model (R 2 =0.992) with a detection speed of 100mm / s, achieving 100% online full detection, replacing traditional sampling detection;

[0050] Three-dimensional capacitance scanning test, using a multi-frequency excitation capacitance test system (excitation frequency 10-100 kHz), combined with a 3D scanning probe (needle tip curvature radius 5 μm), to detect the three-dimensional distribution of touch capacitance in the 0.15 mm area of the frame, with a resolution of 0.1 pF, to ensure that the uniformity deviation of the touch sensitivity in the narrow frame area is less than 5%;

[0051] Touch-stress collaborative test, on a test platform integrating capacitance scanning and micro-stress loading, to apply an edge pressure of 10-100 mN to the sample while conducting touch tests, to analyze the pressure-capacitance change curve through an LSTM machine learning model, to identify edge touch failures at the 0.1 mm level, with a test time of 30 s per sample, to ensure the reliability of the narrow frame under stress;

[0052] Environmental reliability test, to conduct high-low temperature cycle tests (-40℃-85℃, 1000 cycles, 30 min dwell time), damp heat tests (85℃ / 85%RH, 1000 h), and drop tests (1.8 m drop to steel ground, 3 times on each of the 6 sides) on the sample, to require a touch response time of less than 5 ms, a resistance change rate ΔR / R of no more than 5%, and no problems such as package cracking, touch failure, etc.

[0053] Although embodiments of the present application have been shown and described, it is to be understood that various modifications, substitutions, replacements and changes can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A process for manufacturing an ultra-narrow border of a capacitive touch screen, characterized by: The following steps are included: S1: Substrate selection: select a suitable material as the substrate and perform surface pretreatment on the substrate; S2: Touch layer fabrication, using a graphene-silver nanowire double-layer structure. A single layer of graphene is first deposited on a substrate using CVD, followed by a slit-coating technique to deposit a silver nanowire network. Laser direct writing technology is then used to directly engrave the electrode pattern on the composite touch layer. S3: substrate grooving, which is done on the edge of the substrate using a combination of femtosecond laser and ultrasonic vibration processing; S4: Wiring: First, metallization pretreatment is performed inside the groove. Atomic layer deposition (ALD) technology is used to deposit a 50nm thick Al2O3 insulation layer on the groove wall. The deposition temperature is 150°C, the number of cycles is 200, and the insulation layer breakdown voltage is greater than 100V to ensure the insulation reliability between electrodes. Copper wires are prepared in the groove using a plating process, and then the wires are processed by magnetron sputtering. The electrode routing is designed using a cubic Koch curve fractal structure. S5: Touch chip integration, connecting the chip, flexible circuit board and wires; S6: Encapsulation: first pre-set the shape memory alloy microspring; then fill and encapsulate with low-viscosity silicone; and then perform plasma-induced interfacial polymerization; S7: Testing, testing the packaged products.

2. The process for manufacturing an ultra-narrow border of a capacitive touch screen according to claim 1, characterized in that: The substrate is made of 0.4mm thick high-aluminum silicate tempered glass or 125μm flexible PI film. The glass substrate must meet the bending strength of ≥800MPa, and the PI film must have a thermal shrinkage rate of ≤1.5%. Compared with traditional soda-lime glass, the flexural strength of high-aluminum glass is increased by 30%, providing a structural strength foundation for the narrow frame.

3. The process for manufacturing an ultra-narrow border of a capacitive touch screen according to claim 1, characterized in that: The surface pretreatment uses oxygen plasma treatment combined with 5% hydrofluoric acid etching to make the glass surface roughness Ra less than 0.2 μm, introduce hydroxyl groups on the PI film surface, reduce the contact angle from 85° to below 30°, and enhance the adhesion of subsequent coatings.

4. The process for manufacturing an ultra-narrow border of a capacitive touch screen according to claim 1, characterized in that: The substrate grooves are also processed into asymmetric stepped grooves that are wide at the top and narrow at the bottom. The upper step width is 0.3mm and the depth is 60μm, the lower step width is 0.15mm and the depth is 40μm, and the groove bottom fillet radius is 5μm. ANSYS simulation verification shows that this structure reduces the edge stress concentration coefficient from 3.2 to 1.8, effectively reducing the risk of glass shattering.

5. The process for manufacturing an ultra-narrow border of a capacitive touch screen according to claim 1, characterized in that: The grooving is done by superimposing a 532nm femtosecond laser and 20kHz ultrasonic vibration, with a vibration amplitude of 3μm and a processing speed of 10mm / s. This process achieves a groove wall roughness Ra < 0.5μm, which is 40% more efficient than single laser processing and has no thermal damage layer.

6. The process for manufacturing an ultra-narrow border of a capacitive touch screen according to claim 1, characterized in that: The wiring adopts an optimization algorithm to minimize the wiring width, thereby further reducing the border width. A three-dimensional optimization model is constructed with the goals of minimizing the wiring width, minimizing the signal attenuation rate, and maximizing the manufacturing feasibility. The genetic algorithm + finite element method is coupled to solve the problem. The objective function expression is: minf(w,α,m)=w·λ1+α·λ2+(1-m)·λ3 Among them, w is the wiring width, α is the signal attenuation rate, m is the manufacturing feasibility coefficient, and the three weight coefficients λ1, λ2, and λ3 are 0.5, 0.3, and 0.2 respectively.

7. The process for manufacturing an ultra-narrow border of a capacitive touch screen according to claim 1, characterized in that: The tests include: Terahertz time-domain spectroscopy online detection uses a 0.3THz terahertz light source to scan the grooved substrate, analyze the reflection spectrum characteristics in the 0.1-1.0THz frequency band, and calculate the groove depth and width in real time through an established mathematical model. The detection speed is 100mm / s, achieving 100% online full inspection, replacing traditional sampling inspection; The three-dimensional capacitance scanning test uses a multi-frequency excitation capacitance test system with a 3D scanning probe to perform three-dimensional distribution detection of touch capacitance within a 0.15mm area of ​​the border with a resolution of 0.1pF, ensuring that the touch sensitivity uniformity deviation in the narrow border area is less than 5%; Touch-stress collaborative testing: On a test platform integrating capacitance scanning and micro-stress loading, 10-100mN edge pressure is applied to the sample while performing touch testing. An LSTM machine learning model analyzes the pressure-capacitance curve and identifies edge touch failures as low as 0.1mm. The test takes 30 seconds per sample to ensure the reliability of narrow bezels under stress. Environmental reliability testing involves subjecting samples to high and low temperature cycle testing, humidity and heat testing, and drop testing. After the test, the touch response time is required to be less than 5ms, the resistance change rate is no more than 5%, and there is no package cracking or touch failure.

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