Pipeline architecture based on RISC-V instruction set, processor, electronic device and equipment

Abstract

The invention provides a pipeline architecture based on an RISC-V instruction set, a processor, an electronic device and equipment, and the pipeline architecture comprises a branch prediction circuit which is connected with a PC pointer generation circuit and is used for obtaining a PC value with the latest generation time from the PC pointer generation circuit, and generating an instruction branch result through the PC value with the latest generation time; the PC pointer generation circuit is used for generating a PC value of a next instruction to be executed according to the instruction branch result; the address translation circuit is used for acquiring a PC value from the PC pointer generation circuit and converting the acquired PC value into a corresponding physical address; the instruction acquisition circuit is connected with the address translation circuit and is used for acquiring the physical address from the address translation circuit and acquiring an instruction from the acquired physical address; and the instruction execution circuit is connected with the instruction acquisition circuit and is used for acquiring the instruction from the instruction acquisition circuit and executing operation corresponding to the instruction. Therefore, the instruction execution time can be shortened, and the instruction throughput rate is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor design, in particular to a pipeline architecture based on a RISC-V instruction set, a processor, an electronic device and equipment. BACKGROUND

[0002] RISC-V (Reduced Instruction Set Computer V) is an open-source instruction set architecture. It adopts the principle of reduced instruction set computing, is designed to be simple, efficient and modular, and supports multiple data widths (such as 32 bits, 64 bits, and 128 bits).

[0003] Although there are various processors based on the RISC-V instruction set at home and abroad, such as common five-stage pipelines and six-stage pipelines, most processors usually classify the instruction fetching stage as one stage, which not only leads to tight timing, but also makes the time period consumed by the instruction fetching stage very large, affecting the instruction throughput and execution efficiency of the processor. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a pipeline architecture based on a RISC-V instruction set, a processor, an electronic device and equipment, to solve the problem that the pipeline architecture of the RISC-V processor is not detailed enough in the instruction fetching stage, thereby affecting the instruction throughput and execution efficiency of the processor.

[0005] In a first aspect, the embodiments of the present application provide a pipeline architecture based on a RISC-V instruction set, comprising: a branch prediction circuit, connected with a PC pointer generation circuit, the branch prediction circuit being configured to obtain a PC value generated at the latest time from the PC pointer generation circuit, generate an instruction branch result by using the PC value generated at the latest time, and feed back the instruction branch result to the PC pointer generation circuit, the instruction branch result representing whether to perform branch jump or not; the PC pointer generation circuit, configured to generate a PC value of a next instruction to be executed according to the instruction branch result; an address translation circuit, connected with the PC pointer generation circuit, configured to obtain PC values from the PC pointer generation circuit in the generation order of the PC pointer generation circuit, and convert the obtained PC values into corresponding physical addresses; an instruction obtaining circuit, connected with the address translation circuit, configured to obtain physical addresses from the address translation circuit in the conversion order of the address translation circuit, and obtain instructions from the obtained physical addresses; The instruction execution circuit is connected with the instruction obtaining circuit, and is configured to obtain the instruction from the instruction obtaining circuit according to the obtaining sequence of the instruction in the instruction obtaining circuit, execute an operation corresponding to the instruction, obtain an operation result, and write the operation result back to the preset general register.

[0006] In the implementation process, the instruction fetch stage is subdivided into a branch prediction circuit, a PC pointer generation circuit, an address translation circuit, an instruction obtaining circuit and other circuit modules. In this way, the instruction fetch stage is subdivided, so that each stage can be processed in parallel. Therefore, each circuit module can process different execution stages of different instructions at the same time. As a result, each circuit module can process different stages of different instructions in parallel, thereby shortening the instruction execution time and improving the instruction throughput.

[0007] Further, in the case that the instruction branch result represents an execution branch jump, the instruction branch result includes a predicted jump address. Correspondingly, the PC pointer generation circuit is specifically configured to take the predicted jump address as the PC value of the next to-be-executed instruction.

[0008] In the implementation process, by splitting the branch prediction stage in the instruction execution process, a branch prediction circuit is obtained. In this way, even if other circuits except the branch prediction circuit are in the running process, the branch prediction circuit can also predict the instruction branch result. In the case that the instruction branch result represents an execution branch jump, the instruction branch result can also include a predicted jump address, that is, the PC value of the next to-be-executed instruction. In this way, the PC pointer generation circuit can take the predicted jump address in the instruction branch result as the PC value of the next to-be-executed instruction, thereby realizing the advance generation of the PC value of the next to-be-executed instruction. In this way, in the case that the next to-be-executed instruction needs to be executed, the PC value of the next to-be-executed instruction can be directly obtained from the PC pointer generation circuit for subsequent operation, without waiting for the generation of the PC value of the next to-be-executed instruction, thereby achieving the effect of shortening the instruction execution time and improving the instruction throughput.

[0009] Further, in the case that the instruction branch result represents no execution branch jump, the PC pointer generation circuit is specifically configured to increment the latest PC value at the generation moment by a preset increment to obtain the PC value of the next to-be-executed instruction.

[0010] In the implementation process, the branch prediction stage in the instruction execution process is split to obtain a branch prediction circuit. Thus, even if other circuits except the branch prediction circuit are in operation, the branch prediction circuit can still predict the instruction branch result. In the case that the instruction branch result represents that the branch jump is not performed, the PC pointer generation circuit can determine that the instruction is sequentially executed. Therefore, the PC value at the latest generation time can be directly incremented by a preset increment, thereby skipping the length of the PC value at the latest generation time to point to the next to-be-executed instruction, and the PC value of the next to-be-executed instruction is generated in advance. In this way, in the case that the next to-be-executed instruction needs to be executed, the PC value of the next to-be-executed instruction can be directly obtained from the PC pointer generation circuit for subsequent operation, without waiting for the generation of the PC value of the next to-be-executed instruction, thereby shortening the instruction execution time and improving the instruction throughput.

[0011] Further, the instruction execution circuit comprises: a decoding circuit, connected with the instruction acquisition circuit, configured to sequentially acquire instructions from the instruction acquisition circuit according to the acquisition order of the instructions in the instruction acquisition circuit, and decode the acquired instructions to obtain instruction operation codes corresponding to the instructions; an operation execution circuit, connected with the decoding circuit, configured to sequentially acquire instruction operation codes from the decoding circuit according to the acquisition order of the instruction operation codes in the decoding circuit, and execute operations corresponding to the instruction operation codes to obtain operation results, the operation results comprising memory access addresses; a memory access circuit, connected with the operation execution circuit, configured to sequentially acquire memory access addresses from the operation execution circuit according to the acquisition order of the memory access addresses in the operation execution circuit, and access a data memory according to the acquired memory access addresses to obtain access results; a write-back circuit, connected with the memory access circuit, the operation execution circuit and the decoding circuit, the write-back circuit configured to acquire operation results from the operation execution circuit and access results from the memory access circuit, and write the operation results and the access results back to general registers in the decoding circuit.

[0012] In the implementation process, the instruction execution circuit is divided into the decoding circuit, the operation execution circuit, the memory access circuit and the write-back circuit, thereby further subdividing the instruction execution process. Since each circuit in the instruction execution circuit can operate in parallel, each circuit in the instruction execution circuit can process different execution stages of different instructions at the same time. Thus, each circuit in the instruction execution circuit can process different stages of different instructions in parallel, thereby further shortening the instruction execution time and improving the instruction throughput.

[0013] Further, the operation execution circuit is connected with the PC pointer generation circuit, and the operation result further comprises an actual jump address; Correspondingly, the PC pointer generation circuit is specifically configured to update the target PC value with the actual jump address in a case that the instruction branch result represents that no branch jump is performed, or in a case that the instruction branch result represents that branch jump is performed, but the target PC value in the PC pointer generation circuit is different from the actual jump address; The target PC value is a PC value of a next to-be-executed instruction of the operation execution circuit.

[0014] In the implementation process, in a case that the operation result of the operation execution circuit comprises the actual jump address, if the instruction branch result represents that no branch jump is performed, it can be determined that the branch prediction circuit predicts incorrectly whether the branch jump is performed. Or, in a case that the instruction branch result represents that branch jump is performed, but the target PC value in the PC pointer generation circuit is different from the actual jump address, it can also be determined that the branch prediction circuit predicts incorrectly the predicted jump address. In the above two cases, it can be determined that the PC value of the next to-be-executed instruction generated by the PC pointer generation circuit according to the instruction branch result is also incorrect. Therefore, by updating the PC value of the next to-be-executed instruction generated by the PC pointer generation circuit according to the instruction branch result with the actual jump address, the PC value of the next to-be-executed instruction can be corrected.

[0015] Further, based on the pipeline architecture of the RISC-V instruction set, the pipeline architecture further comprises: a controller connected with the PC pointer generation circuit, the address translation circuit, the instruction acquisition circuit, the decoding circuit and the operation execution circuit; The controller is configured to acquire the instruction branch result from the operation execution circuit, and acquire the target PC value from the PC pointer generation circuit; In a case that the instruction branch result represents that no branch jump is performed, or in a case that the instruction branch result represents that branch jump is performed, but the target PC value is different from the actual jump address, the controller is further configured to generate a flush instruction to flush the pipeline of the PC pointer generation circuit, the address translation circuit, the instruction acquisition circuit, the decoding circuit and the operation execution circuit.

[0016] In the implementation process, in a case where the operation result of the operation execution circuit includes an actual branch address, if the instruction branch result indicates that no branch jump is performed, it can be determined that the branch prediction circuit makes a prediction error for whether to perform the branch jump. Alternatively, in a case where the instruction branch result indicates that the branch jump is performed, but the target PC value in the PC pointer generation circuit is different from the actual branch address, it can also be determined that the branch prediction circuit makes a prediction error for the predicted branch address. In the above two cases, it can be determined that the PC value of the next to-be-executed instruction generated by the PC pointer generation circuit according to the instruction branch result is also incorrect. Therefore, the flush instruction is generated by the controller to flush the pipeline of the PC pointer generation circuit, the address translation circuit, the instruction acquisition circuit, the decoding circuit and the operation execution circuit, so that the incorrect PC value stored in the PC pointer generation circuit can be cleared, and the results performed by the address translation circuit, the instruction acquisition circuit, the decoding circuit and the operation execution circuit according to the incorrect PC value can also be cleared, so that all circuits in the instruction execution process can continue according to the correct PC value.

[0017] Further, the controller is further configured to generate an interrupt jump address. Correspondingly, in a case where the controller generates the interrupt jump address, the PC pointer generation circuit is configured to acquire the interrupt jump address from the controller, and use the interrupt jump address as the PC value of the next to-be-executed instruction. Alternatively, In a case where the controller does not generate the interrupt jump address, the PC pointer generation circuit is configured to generate the PC value of the next to-be-executed instruction according to the instruction branch result.

[0018] In the implementation process, the interrupt jump address refers to a target address to which a jump is needed in a case where an interrupt or an exception occurs in the instruction execution process. In addition, the interrupt jump address can enable the instruction to normally resume running in a case where an interrupt or an exception occurs in the instruction execution process. Therefore, in a case where the controller generates the interrupt jump address, it can be determined that an exception occurs in the running of the pipeline architecture. Therefore, in the case where the controller generates the interrupt jump address, the interrupt jump address can be directly used as the PC value of the next to-be-executed instruction, without generating the PC value of the next to-be-executed instruction according to the instruction branch result. Thus, the pipeline architecture can resume normal running.

[0019] In a second aspect, the embodiments of the present application further provide a processor including the pipeline architecture based on the RISC-V instruction set in the first aspect.

[0020] In a third aspect, the embodiments of the present application further provide an electronic device including the processor in the second aspect.

[0021] In a fourth aspect, the embodiments of the present application further provide an electronic device comprising the processor of the second aspect or the electronic device of the third aspect. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0023] Figure 1 A structural schematic diagram of a pipeline architecture based on a RISC-V instruction set provided by the embodiments of the present application; Figure 2 A structural schematic diagram of an instruction execution circuit provided by the embodiments of the present application; Figure 3 Another structural schematic diagram of a pipeline architecture based on a RISC-V instruction set provided by the embodiments of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described below in combination with the drawings in the embodiments of the present application.

[0025] Embodiment one: In order to solve the problem that the related art does not divide the value phase of the pipeline architecture of the RISC-V processor in detail, thereby affecting the instruction throughput rate and execution efficiency of the processor, the embodiments of the present application provide a pipeline architecture based on a RISC-V instruction set, which combines Figures 1 to 3 As shown in the figure, the pipeline architecture based on the RISC-V instruction set comprises a branch prediction circuit 100, a PC pointer generation circuit 200, an address translation circuit 300, an instruction acquisition circuit 400, an instruction execution circuit 500 and a controller 600.

[0026] The controller 600 is connected with the branch prediction circuit 100, the PC pointer generation circuit 200, the address translation circuit 300, the instruction acquisition circuit 400 and the instruction execution circuit 500.

[0027] The branch prediction circuit 100 is connected with the PC pointer generation circuit 200. The PC pointer generation circuit 200 is connected with the address translation circuit 300. The address translation circuit 300 is connected with the instruction acquisition circuit 400. The instruction acquisition circuit 400 is connected with the instruction execution circuit 500.

[0028] In combination with Figure 2As shown, the instruction execution circuit 500 includes a decode circuit, an operation execution circuit, a memory access circuit and a write back circuit. The instruction fetch circuit 400 is connected with the decode circuit. The decode circuit is connected with the operation execution circuit, the operation execution circuit is connected with the memory access circuit, the memory access circuit is connected with the write back circuit and the address translation circuit 300. The write back circuit is connected with the decode circuit. By dividing the instruction execution circuit into the decode circuit, the operation execution circuit, the memory access circuit and the write back circuit, further subdivision of the instruction execution process is achieved. Also, since each of the circuits in the instruction execution circuit can run in parallel, each of the circuits in the instruction execution circuit can process different execution stages of different instructions at the same time. Thus, each of the circuits in the instruction execution circuit can process different stages of different instructions in parallel, so that the instruction execution time can be further shortened and the instruction throughput rate can be improved.

[0029] The controller 600 is connected with the decode circuit, the operation execution circuit, the memory access circuit and the write back circuit.

[0030] The branch prediction circuit 100 is configured to obtain the latest generated PC value from the PC pointer generation circuit 200, generate an instruction branch result using the latest generated PC value, and feed back the instruction branch result to the PC pointer generation circuit 200, where the instruction branch result represents whether to perform branch jump or not.

[0031] In an optional implementation of the embodiment of the present application, the branch prediction circuit 100 can include a branch target buffer, a pattern history table and a branch history register table.

[0032] The pattern history table is configured to record the value of the two-bit saturating counter corresponding to the PC value of the executed instruction. The branch history register table is configured to record the jump result of the branch instruction. The branch target buffer is configured to buffer the jump address of the branch instruction.

[0033] The branch prediction circuit 100 can perform a matching operation on the pattern history table using the latest generated PC value to obtain the value of the two-bit saturating counter corresponding to the latest generated PC value. Then, the branch prediction circuit 100 performs a matching operation on the branch history register table using the value of the two-bit saturating counter corresponding to the latest generated PC value to obtain the jump result corresponding to the latest generated PC value, where the jump result represents whether to perform jump or not. The branch prediction circuit 100 can also perform a matching operation on the branch target buffer using the latest generated PC value to obtain the predicted jump address corresponding to the latest generated PC value. Thus, the instruction branch result corresponding to the latest generated PC value is composed of the predicted jump address corresponding to the latest generated PC value and the jump result corresponding to the latest generated PC value.

[0034] In another optional implementation of the embodiment of the present application, the branch prediction circuit 100 can be replaced by a global history register instead of the branch history register table, so as to reduce the area. The global history register is used to record the jump result of the executed branch instruction, and the result 1 indicates the jump, and the result 0 indicates the non-jump. The result of the bit splicing or exclusive-OR operation of the global history register value and the PC value is used to address the mode history table, so as to reduce the conflict of different branch instructions occupying the same saturation counter. After obtaining the two-bit saturation counter value, the result of the branch prediction can be known, and the branch jump or non-jump is predicted.

[0035] The PC pointer generation circuit 200 is configured to generate the PC value of the next to-be-executed instruction according to the instruction branch result.

[0036] The PC pointer generation circuit 200 includes a multiplexer, a PC pointer generation unit and a PC value register.

[0037] The multiplexer is connected with the branch prediction circuit 100, the PC pointer generation unit, the controller 600 and the operation execution circuit. The controller 600 can generate an interrupt jump address in the case that the pipeline architecture has an exception. The exception of the pipeline architecture can be that the execution time of a single instruction by each circuit exceeds a preset time threshold. The interrupt jump address represents a target address to be jumped in the case that an interrupt or an exception occurs in the instruction execution process, so as to realize that the pipeline architecture can resume normal operation.

[0038] Since the interrupt jump address is a target address to be jumped in the case that an interrupt or an exception is sent in the instruction execution process, it can be determined that the pipeline architecture has an exception in the case that the controller generates the interrupt jump address. Since the interrupt jump address enables the pipeline architecture to resume normal operation, the interrupt jump address can be directly used as the PC value of the next to-be-executed instruction in the case that the controller generates the interrupt jump address, and it is not necessary to generate the PC value of the next to-be-executed instruction according to the instruction branch result. Thus, the pipeline architecture can resume normal operation.

[0039] The multiplexer can obtain the instruction branch result from the branch prediction circuit 100, obtain the interrupt jump address from the controller 600, and obtain the actual jump address from the operation execution circuit.

[0040] In an optional implementation of the embodiment of the present application, in the case that the multiplexer obtains the interrupt jump address from the controller 600, whether the multiplexer obtains the instruction branch result and the actual jump address. The multiplexer transmits the interrupt jump address to the PC pointer generation unit, and the PC pointer generation unit, in the case that the interrupt jump address is obtained, takes the interrupt jump address as the PC value of the next to be executed instruction, and stores the interrupt jump address into the PC value register. In this way, in the case that the controller generates the interrupt jump address, the interrupt jump address can be directly taken as the PC value of the next to be executed instruction, thereby making the pipeline architecture resume normal operation.

[0041] In an optional implementation of the embodiment of the present application, in the case that the multiplexer does not obtain the interrupt jump address from the controller 600, does not obtain the actual jump address from the operation execution unit, but obtains the instruction branch result from the branch prediction circuit 100, if the instruction branch result represents that the branch jump is executed, the multiplexer transmits the predicted jump address in the instruction branch result to the PC pointer generation unit, and the PC pointer generation unit, in the case that the predicted jump address is obtained, takes the predicted jump address as the PC value of the next to be executed instruction, and stores the predicted jump address into the PC value register. Or, in the case that the instruction branch result represents that the branch jump is not executed, the multiplexer can send a notification signal of not executing the branch jump to the PC pointer generation unit, and the PC pointer generation unit, in the case that the notification signal of not executing the branch jump is received, obtains the PC value of the latest generation time from the PC value register, and increments the PC value of the latest generation time by a preset increment to obtain the PC value of the next to be executed instruction. And stores the PC value of the next to be executed instruction into the PC value register. In some embodiments, the preset increment can be 4.

[0042] In an optional implementation of the embodiment of the present application, in the case that the multiplexer does not obtain the interrupt jump address from the controller 600, but obtains the actual jump address from the operation execution circuit, and obtains the instruction branch result from the branch prediction circuit 100, if the actual jump address and the instruction branch result belong to the same cycle, that is, the PC value of the next to be executed instruction predicted by the instruction branch result corresponds to the actual jump address. In the case that the instruction branch result represents that the branch jump is not executed, since the actual jump address is obtained from the operation execution unit, it is indicated that the branch jump actually needs to be executed, so it can be determined that the branch prediction circuit 100 predicts the branch jump execution error. The multiplexer can transmit the actual jump address to the PC pointer generation unit. The PC pointer generation unit, in the case that the actual jump address is obtained, takes the actual jump address as the PC value of the next to be executed instruction, and stores the actual jump address into the PC value register.

[0043] Alternatively, in the case that the instruction branch result represents a branch jump, but the predicted jump address in the instruction branch result is not the same as the actual jump address, it indicates that the branch prediction circuit 100 makes a mistake in predicting the address of the branch jump. Similarly, the multiplexer can transmit the actual jump address to the PC pointer generation unit. The PC pointer generation unit, in the case that the actual jump address is obtained, takes the actual jump address as the PC value of the next instruction to be executed, and stores the actual jump address into the PC value register, thereby correcting the instruction branch result.

[0044] In an optional implementation of the embodiment of the present application, in the case that the multiplexer does not obtain the interrupt jump address from the controller 600, but obtains the actual jump address from the operation execution circuit, and obtains the instruction branch result from the branch prediction circuit 100, if the actual jump address and the instruction branch result belong to different cycles, the multiplexer can transmit the actual jump address to the PC pointer generation unit. The PC pointer generation unit, in the case that the actual jump address is obtained, can update the target PC value stored in the PC value register by using the actual jump address. The target PC value is the PC value of the next instruction to be executed by the operation execution circuit. In other words, the target PC value is the PC value in the PC value register which belongs to the same cycle as the actual jump address.

[0045] The PC value register is used to store the PC value generated by the PC pointer generation unit. The PC values in the PC value register can be sorted according to the generation order of the PC values in the PC pointer generation unit. In this way, the generation order of the PC values in the PC pointer generation unit can be determined by the sorting of the PC values in the PC value register. The PC value register can also store the generation time of each PC value in the PC pointer generation unit. In this way, the generation order of the PC values can also be determined by the generation time of the PC values.

[0046] The address translation circuit 300 is used to obtain the PC values from the PC pointer generation circuit 200 in turn according to the generation order of the PC values in the PC pointer generation circuit 200, and convert the obtained PC values into corresponding physical addresses.

[0047] The address translation circuit 300 is connected with the PC value register. The address translation circuit 300 can obtain the PC values from the PC value register, and in the case that the address translation circuit 300 obtains the PC values from the PC value register, the address translation circuit 300 can obtain the physical address corresponding to the obtained PC value from the preset corresponding relationship between the PC values and the physical addresses, thereby converting the obtained PC values into corresponding physical addresses.

[0048] Exemplarily, the preset correspondence between the PC value and the physical address can be in the form of one of virtual memory paging modes of Sv39, Sv48, and Sv57, the size of a page table entry (PTE) can be 256T, 512G, 1G, 2M, or 4K, and the address translation circuit 300 includes a translation lookaside buffer (TLB) cache, a page table walk (PTW) page table traversal, and physical memory protection (PMP).

[0049] The TLB cache is used to cache the correspondence between the virtual address and the physical address. In the embodiment of the present application, the virtual address can be a PC value or a memory access address. Therefore, the address translation circuit 300 can perform a matching operation on the TLB cache by using the obtained PC value, so as to obtain the corresponding physical address. The TLB cache is a cache with a direct mapping structure. When the TLB is missing, in other words, when the corresponding physical address of the PC value is not obtained in the TLB cache, the PTW can be used to perform a matching operation on the external memory by using the PC value, so as to obtain the corresponding virtual address of the PC value. Then, the PTW can perform address translation on the corresponding virtual address of the PC value, so as to obtain a translation result, that is, the corresponding physical address of the PC value, and then store the translation result in the TLB cache.

[0050] In addition, the PTW sends the physical address to the permission management module after obtaining the physical address. The permission management module performs permission checking on the physical address when receiving the physical address. The permission can include at least one of the following permissions: cacheable permission, cacheable permission, readable permission, writable permission, and executable permission.

[0051] Optionally, the permission management module can perform permission checking on the obtained physical address according to the attribute setting of each physical address, including instruction address permission checking and data address permission checking. When the permission in the corresponding operation of the physical address and the attribute setting of the physical address is inconsistent, the permission management module can send a permission error exception message to the controller.

[0052] Exemplarily, if the attribute setting of the physical address is set as a read-only permission, and the instruction in the physical address obtained by the permission management module is a write operation, the permission management module can send a permission error exception message to the controller.

[0053] The instruction obtaining circuit 400 and the address translation circuit 300 are connected through a physical address register. The physical address register is used to store the physical address obtained by the address translation circuit 300. The instruction obtaining circuit 400 can obtain the physical addresses from the physical address register in the order of the conversion of the address translation circuit 300, and obtain the instructions from the obtained physical addresses.

[0054] The instruction obtaining circuit 400 can obtain the physical addresses from the physical address register, and the instruction obtaining circuit 400 can obtain the compressed instructions from the obtained physical addresses, and then decompress the compressed instructions to obtain the instructions.

[0055] In an optional implementation of the embodiment of the present application, the instruction obtaining circuit 400 can include an instruction cache and a compressed instruction unit, and the instruction cache includes the compressed instructions corresponding to the physical addresses. In some embodiments, the instruction obtaining circuit 400 can obtain the compressed instructions from the instruction cache by using the obtained physical addresses. If the instruction obtaining circuit 400 obtains the compressed instructions from the instruction cache, the obtained compressed instructions can be transmitted to the compressed instruction unit, and the compressed instruction unit is used to translate the compressed instructions to obtain the decompressed instructions. Alternatively, in the case that the instruction obtaining circuit 400 cannot obtain the compressed instructions from the instruction cache by using the physical addresses, the instruction obtaining circuit 400 can obtain the compressed instructions from the external memory by using the obtained physical addresses. Similarly, in the case that the instruction obtaining circuit 400 obtains the compressed instructions from the external memory, the instruction obtaining circuit 400 can transmit the obtained compressed instructions to the compressed instruction unit, and the compressed instruction unit is used to translate the compressed instructions to obtain the decompressed instructions.

[0056] The compressed instructions in the instruction cache are part of the compressed instructions in the external memory, so the compressed instructions in the instruction cache cannot be obtained according to the physical addresses. However, since the instruction cache exists in the instruction obtaining circuit, compared with the method of obtaining the compressed instructions from the external memory, the speed of obtaining the compressed instructions can be accelerated.

[0057] In an optional implementation of the embodiment of the present application, the instruction obtaining circuit 400 can include the instruction cache but not the compressed instruction unit. The instruction cache can include the compressed instructions corresponding to the physical addresses. Similarly, the instruction obtaining circuit 400 can obtain the compressed instructions from the instruction cache or the external memory according to the obtained physical addresses, but does not translate the compressed instructions.

[0058] The decoding circuit is used to obtain the instructions from the instruction obtaining circuit 400 in the order of the obtaining of the instruction obtaining circuit 400, and decode the obtained instructions to obtain the instruction operation codes corresponding to the instructions.

[0059] For example, the decoding circuit can sequentially perform the following operations on each instruction in the order of the instructions fetched by the instruction fetch circuit 400: the decoding circuit fetches an instruction from the instruction fetch circuit 400, decodes the instruction to obtain an instruction opcode, or the decoding circuit fetches a compressed instruction from the instruction fetch circuit 400, decodes the compressed instruction to obtain an instruction, and then decodes the instruction to obtain an instruction opcode.

[0060] The pipeline architecture based on the RISC-V instruction set can include GPRs (General Purpose Registers) and CSRs (Control and Status Registers). The GPRs and CSRs can be in the decoding circuit.

[0061] The GPRs are used to temporarily store data and addresses. For example, the GPRs can be used to temporarily store operation results in the operation execution circuit.

[0062] The operation execution circuit is configured to sequentially fetch instruction opcodes from the decoding circuit in the order of the instruction opcodes fetched by the decoding circuit, and perform operations corresponding to the instruction opcodes to obtain operation results, the operation results including memory access addresses.

[0063] For example, the operation execution circuit can include ALUs (Arithmetic Logic Units), MUL-DIVs (Multiply-Divide), NLCs (Non-Linear Computing Units), FPUs (Floating Point Units), and BJUs (Branch Jump Units).

[0064] The ALUs are configured to perform arithmetic operations and logical operations. The arithmetic operations can include adding, subtracting, multiplying, and dividing two operands, or incrementing or decrementing an operand, or comparing two operands to generate a flag.

[0065] The logical operations can include performing logical AND, OR, NOT, or XOR operations on each bit of two operands, or shifting the bits of an operand.

[0066] The BJUs are configured to calculate actual jump addresses.

[0067] The memory access circuit is connected with the operation execution circuit, and is configured to sequentially obtain the memory access addresses from the operation execution circuit according to the obtaining sequence of the memory access addresses in the operation execution circuit, and perform memory access on the data memory according to the obtained memory access addresses to obtain a memory access result.

[0068] In an optional implementation of the embodiment of the application, the memory access address can be a virtual address. The memory access circuit can be connected with an address translation circuit. Before the memory access circuit performs memory access on the data memory according to the obtained memory access address, the access circuit can send the memory access address to the address translation circuit 300, and the address translation circuit 300 translates the memory access address into a corresponding physical address, and returns the physical address corresponding to the memory access address to the memory access circuit, so that the memory access circuit can perform memory access on the data memory according to the physical address corresponding to the memory access address, thereby obtaining the memory access result.

[0069] For example, the data memory can include a data buffer and an external memory. The data buffer can exist in the memory access circuit. The external memory exists independently of the memory access circuit. Correspondingly, the memory access circuit can perform memory access on the data buffer according to the physical address corresponding to the memory access address. In the case that the data buffer includes the physical address corresponding to the memory access address, the memory access circuit can perform memory access on the data buffer according to the physical address corresponding to the memory access address to obtain the memory access result. Alternatively, in the case that the data buffer does not include the physical address corresponding to the memory access address, the memory access circuit can perform memory access on the external memory according to the physical address corresponding to the memory access address to obtain the memory access result, and store the memory access result in the data buffer.

[0070] The write-back circuit is connected with the memory access circuit, the operation execution circuit and the decoding circuit, and is configured to obtain the operation result from the operation execution circuit and the memory access result from the memory access circuit, and write the operation result and the memory access result back to the general register in the decoding circuit.

[0071] For example, the write-back circuit can write the operation result back to the general register in the decoding circuit in the case that the operation result is obtained from the operation execution circuit. And / or, the write-back circuit can write the memory access result back to the general register in the decoding circuit in the case that the memory access result is obtained from the memory access circuit.

[0072] Optionally, the memory access circuit can be connected with the write back circuit through a multiplexer. In the case that the memory access circuit implements the memory access to the external memory according to the physical address corresponding to the memory access address, obtains the memory access result, and the attribute of the physical address corresponding to the memory access address includes the cacheable permission, the multiplexer turns on the write back circuit and the data cache so that the write back circuit can obtain the memory access result from the data cache and write the memory access result back to the general register in the decoding circuit.

[0073] In the case that the memory access circuit implements the memory access to the external memory according to the physical address corresponding to the memory access address, obtains the memory access result, and the attribute of the physical address corresponding to the memory access address does not include the cacheable permission, the multiplexer turns on the memory access circuit and the write back circuit so that the write back circuit can directly obtain the memory access result from the memory access circuit and write the memory access result back to the general register in the decoding circuit.

[0074] The controller 600 can be configured to obtain the instruction branch result from the operation execution circuit and the target PC value from the PC pointer generation circuit 200. In the case that the instruction branch result represents that the branch jump is not performed, or in the case that the instruction branch result represents that the branch jump is performed but the target PC value is not the same as the actual jump address, the controller 600 is further configured to generate a flush instruction to flush the PC pointer generation circuit 200, the address translation circuit 300, the instruction fetch circuit 400, the decoding circuit and the operation execution circuit.

[0075] In the case that the operation result of the operation execution circuit includes the actual jump address, if the instruction branch result represents that the branch jump is not performed, it can be determined that the branch prediction circuit 100 makes a prediction error for whether the branch jump is performed. Or, in the case that the instruction branch result represents that the branch jump is performed but the target PC value in the PC pointer generation circuit 200 is not the same as the actual jump address, it can also be determined that the branch prediction circuit 100 makes a prediction error for the predicted jump address. In the above two cases, it can be determined that the PC value of the next to be executed instruction generated by the PC pointer generation circuit 200 according to the instruction branch result is also wrong. That is, the target PC value is wrong, therefore, the flush instruction is generated by the controller 600 to flush the PC pointer generation circuit 200, the address translation circuit 300, the instruction fetch circuit 400, the decoding circuit and the operation execution circuit. The wrong PC value stored in the PC pointer generation circuit 200 can be cleared, and the results executed by the address translation circuit 300, the instruction fetch circuit 400, the decoding circuit and the operation execution circuit according to the wrong PC value can also be cleared, so that all the circuits in the instruction execution process can continue to operate according to the correct PC value.

[0076] The controller 600 can also be configured to generate a no-operation instruction. Illustratively, in a case where an operation performed by the operation execution circuit depends on another operand but the other operand has not been obtained, the controller 600 can generate and send the no-operation instruction to the operation execution circuit, so that the operation execution circuit performs a no-operation and waits for the other operand to be obtained.

[0077] The embodiment of the present application provides the pipeline architecture based on the RISC-V instruction set, and the fetch stage is split into a branch prediction circuit, a PC pointer generation circuit, an address translation circuit, an instruction acquisition circuit and the like. Thus, the fetch stage is subdivided, so that each stage can be processed in parallel. Therefore, each circuit can process different execution stages of different instructions at the same time. Thus, each stage can process different stages of different instructions in parallel, so that the instruction execution time is shortened and the instruction throughput is improved.

[0078] Embodiment two: Based on the same inventive concept, the embodiment provides a processor comprising the pipeline architecture based on the RISC-V instruction set of the above-embodiment one.

[0079] Optionally, the processor can comprise a register and a memory. The processor can further comprise a timer, a UART (Universal Asynchronous Receiver / Transmitter, universal asynchronous receiver / transmitter) serial port and a bus system. The timer is configured to generate a timing interrupt to realize task scheduling and processing, and functions such as a watchdog. The UART serial port is configured to print information and can also be used for booting. The bus system is mainly used to realize communication transmission between the processor and the register, the memory.

[0080] The processor can further comprise a debugging module. The debugging module is configured to perform instruction set emulation verification, coremark performance emulation test, MMU memory management function emulation verification, FreeRTOS emulation verification and interruption exception emulation verification.

[0081] Illustratively, the verification step comprises the following steps: First, parameters of a required hardware configuration are selected, including supported instruction sets, Cache specifications and the like, an execution script is generated to generate RTL (Register-Transfer Level, register transfer level) hardware code of a corresponding kernel version, and a corresponding circuit model is constructed; Second, a corresponding version of a test instruction set is generated by using a GCC compilation tool, such as RV32IM, RV32IMC and the like.

[0082] Third, use GCC (GNU Compiler Collection) to compile the test cases of coremark, FreeRTOS, MMU, etc. to generate bin files.

[0083] Finally, run the bin files of the test cases of the instruction set, coremark, FreeRTOS, MMU, etc. to realize the simulation verification of the instruction set, the performance simulation test of coremark, the simulation verification of the MMU memory management function, the simulation verification of FreeRTOS, and the simulation verification of interrupt exceptions.

[0084] Embodiment Three This embodiment further illustrates the application based on the above-mentioned embodiments.

[0085] To verify the correctness and rationality of the above-mentioned pipeline architecture based on the RISC-V instruction set, after the RISC-V core is constructed by using the pipeline architecture, the following operation steps can be performed: First step: select the parameters of the required hardware configuration, and execute the preset automatic script to generate the RTL of the corresponding core version.

[0086] Second step: use the GCC compilation tool to generate the test instruction sets of the corresponding version, such as RV32IM, RV32IMC, etc.

[0087] Third step: use the GCC compilation tool to generate the bin files of the test cases of coremark, FreeRTOS, MMU, etc.

[0088] Fourth step: use the automatic script to automatically run the simulation verification according to the hardware parameter configuration and the TB environment, save the printed output results, and simulate the test cases of all instructions in the instruction set, i.e. compatibility test, coremark, i.e. performance test, MMU and FreeRTOS, i.e. system case test.

[0089] Fifth step: after completing the above-mentioned simulation verification, the comprehensive evaluation script can be run to complete the netlist synthesis with the comprehensive tool, and the SDC (Synopsys Design Constraints, timing constraints) file template is provided.

[0090] Sixth step: according to the synthesis result of the fifth step, perform timing analysis and run formality formal verification with the script and the tool to verify the logical consistency of the RTL code and the gate-level netlist, confirm the rationality and correctness of the core design. Then, the performance, area, power consumption, etc. can be analyzed in combination with the synthesis result and the simulation result, and finally the PPA (Performance, Power, Area) evaluation is completed.

[0091] Based on the same inventive concept, the embodiment further provides an electronic device comprising the processor in the second embodiment.

[0092] The electronic device is a basic unit of an electronic equipment, and the electronic device in the embodiment can be combined with other electronic devices to form an electronic equipment. The existing forms of the electronic device include but are not limited to a communication module, an integrated circuit, a board card and a display card.

[0093] Based on the same inventive concept, the embodiment further provides an electronic equipment comprising the processor or the electronic device.

[0094] The electronic equipment can be a device that can be directly used by a user, such as a computer, a mobile phone, a tablet computer or a wearable device.

[0095] In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are only schematic. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection can be indirect coupling or communication connection through some communication interfaces, and can be electrical, mechanical or other forms.

[0096] In addition, the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the embodiment.

[0097] Furthermore, each functional circuit in each embodiment of the present application can be integrated together to form an independent part, or each circuit can exist independently, or two or more circuits can be integrated to form an independent part.

[0098] In this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0099] In this document, plural refers to two or more.

[0100] The above merely provides an example of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A pipeline architecture based on the RISC-V instruction set, characterized in that: include: a branch prediction circuit connected to the PC pointer generation circuit, the branch prediction circuit being configured to obtain a latest PC value from the PC pointer generation circuit, generate an instruction branch result using the latest PC value, and feed the instruction branch result back to the PC pointer generation circuit, the instruction branch result indicating whether a branch jump is executed or not; The PC pointer generating circuit is used to generate a PC value of the next instruction to be executed according to the instruction branch result; an address translation circuit connected to the PC pointer generation circuit, configured to sequentially obtain PC values ​​from the PC pointer generation circuit in the order in which the PC values ​​are generated by the PC pointer generation circuit, and convert the obtained PC values ​​into corresponding physical addresses; an instruction acquisition circuit connected to the address translation circuit, configured to sequentially acquire physical addresses from the address translation circuit according to the conversion order of the physical addresses in the address translation circuit, and acquire instructions from the acquired physical addresses; An instruction execution circuit is connected to the instruction acquisition circuit and is used to acquire instructions from the instruction acquisition circuit in the order in which the instructions are acquired in the instruction acquisition circuit, perform operations corresponding to the instructions, obtain operation results, and write the operation results back to a preset general register.

2. The pipeline architecture according to claim 1, wherein: In the case where the instruction branch result represents an execution branch jump, the instruction branch result includes a predicted jump address; Correspondingly, the PC pointer generation circuit is specifically configured to use the predicted jump address as the PC value of the next instruction to be executed.

3. The pipeline architecture according to claim 1, wherein: When the instruction branch result indicates that the branch jump is not executed, the PC pointer generation circuit is specifically used to increment the latest PC value generated according to a preset increment to obtain the PC value of the next instruction to be executed.

4. The pipeline architecture according to claim 1, wherein: The instruction execution circuit includes: a decoding circuit connected to the instruction acquisition circuit, configured to sequentially acquire instructions from the instruction acquisition circuit in the order in which the instructions are acquired by the instruction acquisition circuit, and decode the acquired instructions to obtain instruction operation codes corresponding to the instructions; an operation execution circuit connected to the decoding circuit, configured to sequentially obtain instruction operation codes from the decoding circuit in the order in which the instruction operation codes are obtained in the decoding circuit, and to perform operations corresponding to the instruction operation codes to obtain operation results, wherein the operation results include a memory access address; a memory access circuit connected to the operation execution circuit, configured to sequentially obtain memory access addresses from the operation execution circuit in the order in which the memory access addresses are obtained in the operation execution circuit, and access the data memory according to the obtained memory access addresses to obtain memory access results; A write-back circuit is connected to the memory access circuit, the operation execution circuit and the decoding circuit. The write-back circuit is used to obtain the operation result from the operation execution circuit and the memory access result from the memory access circuit, and write the operation result and the memory access result back to the general register in the decoding circuit.

5. The pipeline architecture according to claim 4, wherein: The operation execution circuit is connected to the PC pointer generation circuit, and the operation result also includes an actual jump address; Correspondingly, the PC pointer generation circuit is specifically configured to update the target PC value with the actual jump address when the instruction branch result indicates that the branch jump is not executed, or when the instruction branch result indicates that the branch jump is executed but the target PC value in the PC pointer generation circuit is different from the actual jump address; The target PC value is a PC value of an instruction to be executed next to the instruction currently executed by the operation execution circuit.

6. The pipeline architecture according to claim 5, wherein: Also includes: a controller connected to the PC pointer generation circuit, the address translation circuit, the instruction acquisition circuit, the decoding circuit, and the operation execution circuit; The controller is used to obtain the instruction branch result from the operation execution circuit and obtain the target PC value from the PC pointer generation circuit; When the instruction branch result indicates that a branch jump is not executed, or when the instruction branch result indicates that a branch jump is executed but the target PC value is different from the actual jump address, the controller is further used to generate a flush instruction to perform pipeline flushing on the PC pointer generation circuit, the address translation circuit, the instruction acquisition circuit, the decoding circuit and the operation execution circuit.

7. The pipeline architecture according to claim 6, wherein: The controller is also used to generate an interrupt jump address; Correspondingly, in the case where the controller generates an interrupt jump address, the PC pointer generation circuit is used to obtain the interrupt jump address from the controller and use the interrupt jump address as the PC value of the next instruction to be executed; or, In the case that the controller does not generate an interrupt jump address, the PC pointer generation circuit is used to generate a PC value of the next instruction to be executed according to the instruction branch result.

8. A processor, characterized in that: A pipeline architecture based on the RISC-V instruction set comprising any one of claims 1 to 7.

9. An electronic device, characterized in that: comprising the processor of claim 8.

10. An electronic device, characterized in that: comprising the processor according to claim 8 or the electronic device according to claim 9.

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