Dual-path prediction method and device capable of reducing memory access delay of processor
Through the dual-path prediction method, L2 and LLC miss predictors are used to concurrently access the main memory or cache, which solves the problem of increased memory access latency in the existing technology, achieves no increase in latency when prediction errors occur, and improves the processor's memory access efficiency and performance.
Patent Information
- Application Number
- CN202510834759.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2025-10-17
AI Technical Summary
In the prior art, when a processor core generates an L2 or LLC miss, memory access latency increases. Existing prefetchers, cache level prediction, and off-chip prediction methods each have defects and cannot effectively reduce memory access latency.
A dual-path prediction method is adopted to simultaneously predict L2 and LLC misses of memory access requests through the L2 miss predictor and LLC miss predictor. If the prediction is a miss, the LLC or main memory is accessed concurrently. If a hit is found, the on-chip cache data is returned. If a miss is found, the main memory or LLC data is returned. The perception and predictor are combined with the CNN-LSTM predictor for training to improve the prediction accuracy.
When the prediction is correct, the latency of memory access requests to the on-chip cache is hidden, improving processor performance; when the prediction is wrong, the memory access latency is not increased, invalid data replacement is avoided, and memory access efficiency is improved.
Smart Images
Figure CN120803531A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to microprocessors, and in particular to a dual-path prediction method and apparatus for reducing memory access latency of a processor. BACKGROUND
[0002] With the growth of scientific computing and graphics processing workloads, memory access patterns become more complex, resulting in frequent L2 (level 2 cache) or LLC (last level cache) misses of memory requests generated by a processor core. Such misses can significantly increase memory access latency of memory requests, limiting the improvement of processor performance. Therefore, reducing memory access latency when L2 or LLC misses is crucial to improving processor performance. In order to reduce the damage of L2 or LLC misses to processor performance, computer architects have proposed prefetchers, cache level prediction, and off-chip prediction methods in recent years. By prefetching data from LLC (or main memory) to L2 (or LLC), prefetchers can effectively reduce the number of L2 (or LLC) misses, thereby reducing memory access latency of memory requests. Prefetchers have a significant drawback: when prefetchers prefetch useless data, useful data in L2 (or LLC) is discarded, which can increase the number of L2 (or LLC) misses, thereby increasing memory access latency of memory requests. The cache level prediction method predicts which cache level a memory request will hit. By making the memory request directly access the predicted cache level, this method can effectively reduce memory access latency of memory requests. The cache level prediction method has a significant drawback: when it predicts a cache level higher than the actual hit cache level, memory access latency of memory requests will increase. The off-chip prediction method predicts which memory requests will have LLC misses. By making these memory requests access the main memory and the cache concurrently, this method can effectively reduce memory access latency of memory requests. The off-chip prediction method has a significant drawback: it cannot reduce memory access latency of memory requests when they have LLC hits. SUMMARY
[0003] The technical problem solved by the present application: In view of the above problems of the prior art, the present application provides a dual-path prediction method and apparatus for reducing memory access latency of a processor. The present application aims to hide memory access latency of on-chip caches (L1D and L2) when memory requests have L2 misses (or LLC misses), thereby improving memory efficiency and performance of the processor.
[0004] To solve the above technical problems, the technical scheme adopted by the present application is: The application discloses a double-path prediction method for reducing processor access delay, which comprises the following steps: activating an L2 miss predictor and an LLC miss predictor simultaneously when a processor core generates an access request; the L2 miss predictor is used to predict whether the access request will cause L2 miss according to the request characteristics of a plurality of recent access requests, the L2 miss refers to the L2 cache miss in the on-chip cache of the processor core, and the access request is sent to the LLC cache when the prediction result is that the L2 miss occurs; the LLC miss predictor is used to predict whether the access request will cause LLC miss according to the request characteristics of a plurality of recent access requests, and the access request is sent to the main memory controller when the prediction result is that the LLC miss occurs, so that the access request accesses the LLC cache or the main memory concurrently when accessing the on-chip cache of the processor core, if the on-chip cache hits, the data of the L1 cache or the L2 cache in the on-chip cache is returned to the processor core, and the data returned by accessing the LLC cache or the main memory is discarded, if the on-chip cache misses, the data returned by the LLC cache or the main memory is returned to the processor core.
[0005] Optionally, when the L2 miss predictor predicts whether the access request will cause L2 miss according to the request characteristics of a plurality of recent access requests, the request characteristics include part or all of the program count value PC, the virtual page number, the cache line offset and the cache byte offset of the plurality of recent access requests.
[0006] Optionally, when the LLC miss predictor predicts whether the access request will cause LLC miss according to the request characteristics of the access request, the request characteristics include part or all of the program count value PC, the virtual page number, the cache line offset and the cache byte offset of a plurality of recent access requests.
[0007] Optionally, at least one of the L2 miss predictor and the LLC miss predictor is a combined predictor composed of at least one of the awareness and prediction predictor and the CNN-LSTM predictor, and for the L2 miss predictor, if at least one of the prediction results of the awareness and prediction predictor and the CNN-LSTM predictor is L2 miss, it is determined that the final prediction result of the combined predictor is L2 miss; and for the LLC miss predictor, if at least one of the prediction results of the awareness and prediction predictor and the CNN-LSTM predictor is LLC miss, it is determined that the final prediction result of the combined predictor is LLC miss; the awareness and prediction predictor predicts whether a memory request will cause L2 miss or LLC miss according to request features of the plurality of recent memory requests, and includes three stages: stage 1, for each of the plurality of recent memory requests, adding a program counter value PC to a virtual page number, a cache line offset and a cache byte offset, and averaging the low 64 bits of the addition result into multiple equal parts and performing XOR operation on two of the equal parts; stage 2, querying a preset weight table with each XOR operation result to obtain a weight corresponding to the XOR operation result, thereby generating three weights for each memory request; and stage 3, summing the three weights of each of the plurality of recent memory requests to obtain a probability of causing L2 miss or LLC miss, and if the probability of causing L2 miss or LLC miss is greater than or equal to a threshold, it is predicted that the memory request will cause L2 miss or LLC miss; otherwise, it is predicted that the memory request will not cause L2 miss or LLC miss; the CNN-LSTM predictor predicts whether a memory request will cause L2 miss or LLC miss according to request features of the plurality of recent memory requests, and includes five stages: stage 1, encoding each request feature of the plurality of recent memory requests into a 16-dimensional dense vector through linear mapping to form a uniform-dimensional feature representation, and then splicing the 16-dimensional dense vectors of the request features to form a 16-dimensional feature sequence with a length of 16; stage 2, performing a sliding window operation on the 16-dimensional feature sequence with a length of 16 using 16 convolution kernels with a size of 2x16 through a one-dimensional CNN layer, and the sliding step is 1, thereby extracting a spatial feature map reflecting address locality from the 16-dimensional feature sequence with a length of 16; stage 3, sequentially performing layer normalization, nonlinear activation ReLU, maximum pooling and random dropout operations on the spatial feature map to obtain a processed spatial feature map; stage 4, extracting a time feature of address access behavior from the processed spatial feature map using an LSTM layer; and stage 5, processing the time feature of address access behavior through two fully connected layers to obtain a probability of causing L2 miss or LLC miss, and if the probability of causing L2 miss or LLC miss is greater than or equal to a threshold, it is predicted that the memory request will cause L2 miss or LLC miss; otherwise, it is predicted that the memory request will not cause L2 miss or LLC miss.
[0008] Optionally, at least one of the L2 miss predictor and the LLC miss predictor is a perception and prediction predictor; the perception and prediction predictor predicts whether a memory access request will cause an L2 miss or an LLC miss according to request features of a plurality of recent memory access requests, including three stages: stage 1, for each of the plurality of recent memory access requests, adding a program counter value PC to a virtual page number, a cache line offset, and a cache byte offset, respectively, averaging the lower 64 bits of the addition results into a plurality of equal parts, and performing XOR operation on two of the equal parts; stage 2, querying a preset weight table with each of the XOR operation results to obtain a weight corresponding to the XOR operation result, thereby generating three weights for each of the memory access requests; and stage 3, summing the three weights of each of the plurality of recent memory access requests to obtain a probability of causing an L2 miss or an LLC miss, and if the probability of causing an L2 miss or an LLC miss is greater than or equal to a threshold value, predicting that the memory access request will cause an L2 miss or an LLC miss; otherwise, predicting that the memory access request will not cause an L2 miss or an LLC miss.
[0009] Optionally, at least one of the L2 miss predictor and the LLC miss predictor is a CNN-LSTM predictor; the CNN-LSTM predictor predicts whether a memory access request will cause an L2 miss or an LLC miss according to request features of a plurality of recent memory access requests, including five stages: stage 1, encoding each of the request features of the plurality of recent memory access requests into a 16-dimensional dense vector through linear mapping to form a uniform-dimensional feature representation, and then splicing the 16-dimensional dense vectors of the request features to form a 16-dimensional feature sequence with a length of 16; stage 2, performing a sliding window operation on the 16-dimensional feature sequence with a length of 16 using 16 convolution kernels with a size of 2x16 through a one-dimensional CNN layer, and a sliding step of 1, thereby extracting a spatial feature map reflecting address locality from the 16-dimensional feature sequence with a length of 16; stage 3, sequentially performing layer normalization, nonlinear activation ReLU, maximum pooling, and random dropout operations on the spatial feature map to obtain a processed spatial feature map; stage 4, extracting a time feature of address access behavior from the processed spatial feature map using an LSTM layer; and stage 5, processing the time feature of address access behavior through two fully connected layers to obtain a probability of causing an L2 miss or an LLC miss, and if the probability of causing an L2 miss or an LLC miss is greater than or equal to a threshold value, predicting that the memory access request will cause an L2 miss or an LLC miss; otherwise, predicting that the memory access request will not cause an L2 miss or an LLC miss.
[0010] Optionally, the returning the data of the L1 cache or L2 cache hit in the on-chip cache to the processor core, and the returning the data returned by the LLC cache or the main memory to the processor core further comprises using the results of whether the L2 miss and the LLC miss occur as tags, in combination with the request features of the memory access request, to train the L2 miss predictor and the LLC miss predictor.
[0011] In addition, the application further provides a dual-path prediction device capable of reducing processor memory access delay, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay.
[0012] In addition, the application further provides a computer readable storage medium, wherein a computer program or instructions are stored in the computer readable storage medium, and the computer program or instructions are programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay by using a processor.
[0013] In addition, the application further provides a computer program product, comprising a computer program or instructions, which are programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay by using a processor.
[0014] Compared with the prior art, the application mainly has the following beneficial effects: 1. Compared with the prior prefetcher, the application does not increase the number of L2 (or LLC) misses in the case of prediction error. 2. Compared with the prior cache level prediction method, the application does not increase the memory access delay of the memory access request in the case of prediction error. 3. Compared with the prior off-chip prediction method, the application can reduce the memory access delay of the memory access request when the memory access request occurs LLC hit. In summary, the application can hide the memory access delay of the memory access request accessing the on-chip cache (the first cache L1D and the second cache L2) in the case of correct prediction, improve the memory access efficiency and performance of the processor, and does not increase the memory access delay of the memory access request in the case of prediction error. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 The figure is a structural schematic diagram of an embodiment of the application.
[0016] Figure 2 The figure is a flow schematic diagram of an embodiment of the application.
[0017] Figure 3 The figure is a structure schematic diagram of a perception and predictor of an embodiment of the application.
[0018] Figure 4 The figure is a flow schematic diagram of a perception and predictor of an embodiment of the application.
[0019] Figure 5A structure schematic diagram of the CNN-LSTM predictor of the embodiment of the present application.
[0020] Figure 6 A flow schematic diagram of the CNN-LSTM predictor of the embodiment of the present application. DETAILED DESCRIPTION
[0021] In order to make the personnel in the technical field better understand the technical solutions of the present application, the technical solutions of the present application will be further described in detail below in combination with the drawings in the embodiments of the present application.
[0022] As shown in Figure 1 and Figure 2 The dual-path prediction method for reducing the memory access delay of the processor of the present embodiment includes the following steps: activating the L2 miss predictor and the LLC miss predictor simultaneously whenever the processor core generates a memory access request; the L2 miss predictor is used to predict whether the memory access request will cause an L2 miss according to the request characteristics of the recent multiple memory access requests, the L2 miss refers to the L2 cache miss in the on-chip cache of the processor core, and the memory access request is sent to the LLC cache when the prediction result is that the L2 miss occurs; the LLC miss predictor is used to predict whether the memory access request will cause an LLC miss according to the request characteristics of the recent multiple memory access requests, and the memory access request is sent to the main memory controller when the prediction result is that the LLC miss occurs, so that the memory access request accesses the LLC cache or the main memory concurrently when accessing the on-chip cache of the processor core, if the on-chip cache hits, the data of the L1 cache or the L2 cache in the on-chip cache that hits is returned to the processor core, and the data returned by accessing the LLC cache or the main memory is discarded, if the on-chip cache misses, the data returned by the LLC cache or the main memory is returned to the processor core. Wherein, the number of the recent multiple memory access requests can be selected according to actual needs, as an optional implementation, the recent multiple memory access requests in the present embodiment refer to the last four memory access requests.
[0023] As shown in Figure 2As shown, this embodiment returns the data of the L1 cache or L2 cache hit in the on-chip cache to the processor core, and returns the data returned by the LLC cache or main memory to the processor core, and also includes using the result of whether the memory access request has an L2 miss and an LLC miss as a label, and combining the request characteristics of the memory access request to train and activate the L2 miss predictor and the LLC miss predictor. First, the error between the actual hit label of the memory access request (the label is 1 for miss, and the label is 0 for hit) and the output probability is calculated, and then the network parameters in the L2 miss predictor or the LLC miss predictor are trained through the back propagation algorithm and the Adam optimizer. If a memory access request is predicted to miss in the L2 (or LLC), the request is directed to the LLC (or main memory) and on-chip cache concurrently. If the prediction is correct, the request to the on-chip cache misses in the L2 (or LLC) and waits for the data from the LLC (or main memory). This behavior hides the access latency of the on-chip cache (L1D and L2), thereby improving processor performance. If the prediction is incorrect, the request to the on-chip cache hits in the L1D or L2 (or on-chip cache), and the request to the LLC (or main memory) is discarded. This behavior ensures that even in the case of an incorrect prediction, the memory access latency of the memory request is not increased. When a memory access request delivers data to the processor core and is about to release the corresponding memory queue entry, the predictor training mechanism is activated. The perception and predictor and CNN-LSTM predictor are trained based on the actual memory access results of the memory request to improve their prediction accuracy.
[0024] like Figure 1 As shown, in this embodiment, the L2 miss predictor predicts whether a memory access request will cause an L2 miss based on the request characteristics of multiple recent memory access requests, where the request characteristics include the program counter value PC, virtual page number, cache line offset, and cache byte offset (or part thereof) of the multiple recent memory access requests.
[0025] like Figure 1 As shown, in this embodiment, the LLC miss predictor is used to predict whether an LLC miss will occur in a memory access request based on the request characteristics of the memory access request, and the request characteristics include the program counter value PC, virtual page number, cache line offset and cache byte offset (or part of them) of the most recent multiple memory access requests.
[0026] In this embodiment, both the L2 miss predictor and the LLC miss predictor are combined predictors composed of a combination of the perception and prediction predictor and the CNN-LSTM predictor. For the L2 miss predictor, if at least one of the prediction results of the perception and prediction predictor and the CNN-LSTM predictor is L2 miss, it is determined that the final prediction result of the combined predictor is L2 miss. For the LLC miss predictor, if at least one of the prediction results of the perception and prediction predictor and the CNN-LSTM predictor is LLC miss, it is determined that the final prediction result of the combined predictor is LLC miss. In addition, as an optional implementation, the probabilities of L2 miss or LLC miss predicted by the perception and prediction predictor and the CNN-LSTM predictor can be weighted and summed, and then it is determined whether the weighted sum result is greater than or equal to a threshold value. If the weighted sum result is greater than or equal to the threshold value, it is predicted that the memory request will occur L2 miss or LLC miss; otherwise, it is predicted that the memory request will not occur L2 miss or LLC miss. In addition, as an optional implementation, the L2 miss predictor and the LLC miss predictor can also select a single perception and prediction predictor, a CNN-LSTM prediction model, etc. according to needs.
[0027] As Figure 3 and Figure 4As shown, the prediction of whether a memory access request will cause an L2 miss or an LLC miss according to the request characteristics of the recent multiple memory access requests in the embodiment comprises three stages: stage 1, for each of the recent multiple memory access requests, add the program counter value PC to the virtual page number, the cache line offset and the cache byte offset respectively, average the low 64 bits of the addition results into multiple equal parts and perform XOR operation on two parts, for example, for the first memory access request, add the program counter value PC (PC1) to the virtual page number 1, the cache line offset 1 and the cache byte offset 1 respectively, average the low 64 bits of the addition results into 8 equal parts, and then perform XOR operation on two parts, the equal parts between which the XOR operation is performed can be specified as needed, for example, as an optional implementation, the first and second equal parts are used to perform XOR operation, the third and fourth equal parts are used to perform XOR operation, the fifth and sixth equal parts are used to perform XOR operation, and the seventh and eighth equal parts are used to perform XOR operation; stage 2, query a preset weight table with each XOR operation result to obtain the weight corresponding to the XOR operation result, thereby generating three weights for each memory access request, the embodiment contains 12 weight tables, and the address of each weight table is 8 bits; stage 3, sum the three weights of each of the recent multiple memory access requests to obtain the probability of causing an L2 miss or an LLC miss, if the probability of causing an L2 miss or an LLC miss is greater than or equal to a threshold value, it is predicted that the memory access request will cause an L2 miss or an LLC miss; otherwise, it is predicted that the memory access request will not cause an L2 miss or an LLC miss.
[0028] As Figure 5 and Figure 6As shown, the CNN-LSTM predictor in the embodiment predicts whether a memory access request will incur L2 miss or LLC miss according to the request features of the recent multiple memory access requests, which includes five stages: stage 1 is to encode each request feature of the recent multiple memory access requests into a 16-dimensional dense vector through linear mapping to form a uniform-dimensional feature representation, and then splice the 16-dimensional dense vectors of each request feature to form a 16-dimensional feature sequence with a length of 16; stage 2 is to perform a sliding window operation on the 16-dimensional feature sequence with a length of 16 through a one-dimensional CNN layer using 16 convolution kernels with a size of 2x16, and the sliding step is 1, thereby extracting a spatial feature map reflecting address locality from the 16-dimensional feature sequence with a length of 16; stage 3 is to sequentially perform layer normalization, nonlinear activation ReLU, maximum pooling (pooling window size is 2x1, and step is 2) and random dropout operation on the spatial feature map to obtain a processed spatial feature map, so as to standardize the output distribution, improve the nonlinear expression, reduce the feature dimension and suppress overfitting; stage 4 is to extract the time features of address access behavior from the processed spatial feature map using an LSTM layer, wherein the LSTM layer has 64 hidden units; and stage 5 is to obtain the probability of incurring L2 miss or LLC miss through two fully connected layers processing the time features of address access behavior, if the probability of incurring L2 miss or LLC miss is greater than or equal to a threshold, it is predicted that the memory access request will incur L2 miss or LLC miss; otherwise, it is predicted that the memory access request will not incur L2 miss or LLC miss. As an optional implementation, in the two fully connected layers of stage 5 of the embodiment, the input dimension and the output dimension of the first fully connected layer are 64 and 32 respectively, and the ReLU activation function is used; the input dimension and the output dimension of the second fully connected layer are 32 and 1 respectively, and the Sigmoid activation function is used. The output of the Sigmoid function is the probability of the memory access request incurring L2 (or LLC) miss. When the probability is greater than or equal to the threshold, the CNN-LSTM predicts that the memory access request will incur L2 (or LLC) miss; otherwise, the CNN-LSTM predicts that the memory access request will not incur L2 (or LLC) miss.
[0029] In summary, the method of the embodiment includes obtaining request features of a memory access request, predicting whether the memory access request will miss in L2 (or LLC) according to the request features of the memory access request, if it is predicted that L2 (or LLC) misses, making the memory access request access LLC (or main memory) and on-chip cache concurrently, if the prediction is correct, the memory access request accessing on-chip cache misses in L2 (or LLC), and waiting for the memory access request accessing LLC (or main memory) to return data. Through the above behavior, the device can hide the memory access delay of the memory access request accessing on-chip cache (L1D and L2), thereby improving the performance of the processor. The L2 miss predictor and the LLC miss predictor are trained when the memory access request delivers data, so as to improve the prediction performance thereof. The method of the embodiment can hide the memory access delay of on-chip cache (L1D and L2) when the memory access request misses in L2 (or LLC), thereby improving the memory efficiency and performance of the processor.
[0030] In addition, the embodiment also provides a dual-path prediction device capable of reducing processor memory access delay, which comprises a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay. Whenever a processor core generates a memory access request, the prediction mechanism of the L2 miss predictor and the LLC miss predictor of the device is activated. The device obtains the relevant features of the memory access request. These features include the PC, virtual page number, cache byte offset and cache line offset of the last four memory access requests. The L2 miss predictor of the device predicts whether the memory access request will miss in L2, and the LLC miss predictor predicts whether the memory access request will miss in LLC. The L2 miss predictor and the LLC miss predictor are both combination predictors of the same structure. The combination predictor comprises two sub-predictors, namely a perception and prediction predictor and a CNN-LSTM predictor. As long as any one of the sub-predictors predicts that the memory access request will miss in L2 (or LLC), the combination predictor predicts that the memory access request will miss in L2 (or LLC).
[0031] In addition, the embodiment also provides a computer readable storage medium, which stores a computer program or instructions programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay by a processor.
[0032] In addition, the embodiment also provides a computer program product comprising a computer program or instructions programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay by a processor.
[0033] The above merely describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-described embodiments. Any technical solution falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.
Claims
1. A dual-path prediction method for reducing processor memory access latency, characterized in that: The invention comprises the following steps: whenever a processor core generates a memory access request, an L2 miss predictor and an LLC miss predictor are simultaneously activated; the L2 miss predictor is used to predict whether an L2 miss will occur in the memory access request based on the request characteristics of multiple recent memory access requests, wherein the L2 miss refers to a miss in the secondary cache in the on-chip cache of the processor core, and when the prediction result is that an L2 miss occurs, a memory access request is sent to the LLC cache; the LLC miss predictor is used to predict whether an LLC miss will occur in the memory access request based on the request characteristics of multiple recent memory access requests, and when the prediction result is that an LLC miss occurs, a memory access request is sent to the main memory controller, so that the memory access request concurrently accesses the LLC cache or the main memory when accessing the on-chip cache of the processor core; if the on-chip cache hits, the data hit in the L1 cache or L2 cache in the on-chip cache is returned to the processor core, and the data returned by accessing the LLC cache or the main memory is discarded; if the on-chip cache does not hit, the data returned by the LLC cache or the main memory is returned to the processor core.
2. The dual-path prediction method for reducing processor memory access latency according to claim 1, wherein: The L2 miss predictor predicts whether an L2 miss will occur for a memory access request based on request characteristics of multiple recent memory access requests, where the request characteristics include part or all of the program counter values PC, virtual page numbers, cache line offsets, and cache byte offsets of the multiple recent memory access requests.
3. The dual-path prediction method for reducing processor memory access latency according to claim 1, wherein: The LLC miss predictor is used to predict whether an LLC miss will occur in a memory access request based on the request characteristics of the memory access request, where the request characteristics include part or all of the program counter values PC, virtual page numbers, cache line offsets, and cache byte offsets of multiple recent memory access requests.
4. The dual-path prediction method for reducing processor memory access latency according to claim 1, wherein: At least one of the L2 missing predictor and the LLC missing predictor is a combined predictor composed of the perception and predictor and the CNN-LSTM predictor. For the L2 missing predictor, at least one of the perception and predictor and the CNN-LSTM predictor must predict L2 missing, and then the final prediction result of the combined predictor is determined to be L2 missing; for the LLC missing predictor, at least one of the perception and predictor and the CNN-LSTM predictor must predict LLC missing, and then the final prediction result of the combined predictor is determined to be LLC missing. The perception and predictor predicts whether an L2 miss or LLC miss will occur in a memory access request based on the request characteristics of multiple recent memory access requests, including three stages from stage 1 to stage 3: stage 1 is to add the program counter value PC to the virtual page number, cache line offset, and cache byte offset for each of the multiple recent memory access requests, and the lower 64 bits of the addition result are evenly divided into multiple equal parts and XOR operations are performed on each of them; stage 2 is to query the preset weight table for each XOR operation result to obtain the weight corresponding to the XOR operation result, thereby generating three weights for each memory access request; Stage 3 is to sum the three weights of each memory access request in the most recent multiple memory access requests to obtain the probability of L2 loss or LLC loss. If the probability of L2 loss or LLC loss is greater than or equal to the threshold, it is predicted that the memory access request will have L2 loss or LLC loss; otherwise, it is predicted that the memory access request will not have L2 loss or LLC loss. The CNN-LSTM predictor predicts whether the memory access request will have L2 loss or LLC loss based on the request features of the most recent multiple memory access requests. It includes five stages from stage 1 to stage 5: stage 1 is to encode each request feature of the most recent multiple memory access requests into a 16-dimensional dense vector through linear mapping to form a feature representation of unified dimension, and then concatenate the 16-dimensional dense vectors of each request feature to form a 16-dimensional feature sequence with a length of 16; stage 2 is to use 1 through a one-dimensional CNN layer Six convolution kernels of size 2×16 perform a sliding window operation on a 16-dimensional feature sequence of length 16 with a sliding step of 1, thereby extracting a spatial feature map reflecting address locality from the 16-dimensional feature sequence of length 16; stage 3 is to perform layer normalization, nonlinear activation ReLU, maximum pooling and random dropout operations on the spatial feature map in sequence to obtain the processed spatial feature map; stage 4 is to use the LSTM layer to extract the temporal characteristics of address access behavior from the processed spatial feature map; stage 5 is to process the temporal characteristics of address access behavior through two fully connected layers to obtain the probability of L2 miss or LLC miss. If the probability of L2 miss or LLC miss is greater than or equal to the threshold, it is predicted that the memory access request will have L2 miss or LLC miss; otherwise, it is predicted that the memory access request will not have L2 miss or LLC miss.
5. The dual-path prediction method capable of reducing processor memory access latency according to claim 1, wherein: At least one of the L2 miss predictor and the LLC miss predictor is a sensing and predictor; the sensing and predictor predicts whether a memory access request will cause an L2 miss or an LLC miss based on the request characteristics of multiple recent memory access requests, including three stages from stage 1 to stage 3: stage 1 is for each of the multiple recent memory access requests, adding the program counter value PC to the virtual page number, cache line offset, and cache byte offset respectively, and dividing the lower 64 bits of the addition result into multiple equal parts and performing XOR operations on them in pairs; stage 2 is to query a preset weight table for each XOR operation result to obtain the weight corresponding to the XOR operation result, thereby generating three weights for each memory access request; Stage 3 is to sum the three weights of each of the most recent memory access requests to obtain the probability of an L2 miss or LLC miss. If the probability of an L2 miss or LLC miss is greater than or equal to a threshold, it is predicted that an L2 miss or LLC miss will occur for the memory access request; otherwise, it is predicted that an L2 miss or LLC miss will not occur for the memory access request.
6. The dual-path prediction method capable of reducing processor memory access latency according to claim 1, wherein: At least one of the L2 miss predictor and the LLC miss predictor is a CNN-LSTM predictor; the CNN-LSTM predictor predicts whether a memory access request will have an L2 miss or an LLC miss based on the request features of the most recent memory access requests, and includes five stages from stage 1 to stage 5: stage 1 is to encode each request feature of the most recent memory access requests into a 16-dimensional dense vector through linear mapping to form a feature representation of a unified dimension, and then concatenate the 16-dimensional dense vectors of each request feature to form a 16-dimensional feature sequence of length 16; stage 2 is to perform a sliding window operation on the 16-dimensional feature sequence of length 16 using 16 convolution kernels of size 2×16 through a one-dimensional CNN layer, and the sliding step size is 1, thereby extracting a spatial feature map reflecting address locality from a 16-dimensional feature sequence of length 16; stage 3 is to perform layer normalization, nonlinear activation ReLU, maximum pooling and random drop operations on the spatial feature map in sequence to obtain a processed spatial feature map; stage 4 is to use the LSTM layer to extract the temporal characteristics of the address access behavior from the processed spatial feature map; stage 5 is to process the temporal characteristics of the address access behavior through two fully connected layers to obtain the probability of L2 loss or LLC loss. If the probability of L2 loss or LLC loss is greater than or equal to the threshold, it is predicted that the memory access request will have an L2 loss or LLC loss; otherwise, it is predicted that the memory access request will not have an L2 loss or LLC loss.
7. The dual-path prediction method capable of reducing processor memory access latency according to claim 1, wherein: When returning the data hit by the L1 cache or L2 cache in the on-chip cache to the processor core, and returning the data returned by the LLC cache or main memory to the processor core, it also includes using the results of whether the memory access request has an L2 miss and an LLC miss as a label, and combining the request characteristics of the memory access request to train and activate the L2 miss predictor and the LLC miss predictor.
8. A dual-path prediction device capable of reducing processor memory access latency, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the dual-path prediction method capable of reducing processor memory access delay as claimed in any one of claims 1 to 7.
9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute, through a processor, the dual-path prediction method for reducing processor memory access latency as recited in any one of claims 1 to 7.
10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute, through a processor, the dual-path prediction method for reducing processor memory access latency as recited in any one of claims 1 to 7.