Queue circuit, processor, computer device, chip product and method

Abstract

The application discloses a queue circuit, a processor, a computer device, a chip product and a method, and relates to the technical field of electronics. The queue circuit comprises a signal receiving unit, an index queue and a storage unit. The index queue stores indexes of N requests, and the storage unit stores information carried by the N requests. The signal receiving unit is used for receiving a queue updating signal, and the queue updating signal carries a first index. The storage unit is used for outputting information carried by a first request in the N requests under the condition that the first request meets an output condition. The output condition comprises that the first request is a first index request among M first index requests included in the N requests, and information carried by the first index request is written into the storage unit first. The first index request refers to a request with the first index. The above scheme guarantees that information carried by each request for the same object is returned to an upstream (a receiving party of an output of the queue circuit) in a writing order.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a queue circuit, processor, computer device, chip product, and method. Background Technology

[0002] In some chip products (such as processor chips), after the request initiator (hereinafter referred to as upstream) initiates a request to the request responder (hereinafter referred to as downstream), the upstream will temporarily store the data carried by the request in the chip's queue circuit. The request is only marked as completed when the data carried by a request in the queue circuit is returned to the upstream.

[0003] Therefore, the order in which the queue circuit returns data will affect the upstream processing logic, and further research is needed on how to design the queue circuit reasonably. Summary of the Invention

[0004] This application provides a queue circuit, a processor, a computer device, a chip product, and a method. The technical solutions provided by this application are as follows:

[0005] According to one aspect of the embodiments of this application, a queue circuit is provided, the queue circuit including a signal receiving unit, an index queue and a storage unit, wherein the index queue stores indexes of N requests, the indexes of the requests are used to indicate the objects targeted by the requests, and the storage unit stores information carried by the N requests respectively, where N is a positive integer;

[0006] The signal receiving unit is used to receive a queue update signal, which carries a first index, and the first index belongs to the index of the processed request.

[0007] The storage unit is used to output the information carried by the first request when the first request among the N requests meets the output conditions; wherein, the output conditions include: the first request is the first index request whose information is written to the storage unit first among the M first index requests included in the N requests, the first index request refers to the request with the first index, and M is a positive integer less than or equal to N.

[0008] According to one aspect of the embodiments of this application, a processor is provided, the processor including the queue circuit described above.

[0009] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor, the processor including the above-described queue circuit.

[0010] According to one aspect of the embodiments of this application, a chip product is provided, the chip product including the above-described queue circuit.

[0011] According to one aspect of the embodiments of this application, an information processing method based on a queue circuit is provided. The queue circuit includes a signal receiving unit, an index queue, and a storage unit. The index queue stores indices of N requests, each index indicating an object targeted by the request. The storage unit stores information carried by each of the N requests, where N is a positive integer. The method includes:

[0012] The signal receiving unit receives a queue update signal, which carries a first index, and the first index belongs to the index of processed requests.

[0013] When the first request among the N requests meets the output conditions, the storage unit outputs the information carried by the first request; wherein, the output conditions include: the first request is the first index request whose information is written to the storage unit first among the M first index requests included in the N requests, and the first index request refers to the request with the first index, where M is a positive integer less than or equal to N.

[0014] The technical solutions provided in this application have at least the following beneficial effects:

[0015] For a queue circuit storing indices of N requests (stored in the index queue of the queue circuit) and the information carried by each of the N requests (stored in the storage units of the queue circuit), the signal receiving unit of the queue circuit is designed such that, upon receiving the first index (which belongs to the index of a processed request), the storage unit outputs the information carried by the first request (the request with the first index among the N requests whose information was written to the storage unit first). This ensures that the data carried by requests with the same index stored in the queue circuit are output in order (according to their writing order). Since the index of the request indicates the object to which the request targets, the above scheme ensures that for requests targeting the same object, the information carried by them is returned to the upstream (the receiver of the queue circuit's output) in the writing order, thereby ensuring the correctness of the upstream processing logic. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a circuit structure including upstream and downstream structures provided in one embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the structure of a queue circuit provided in one embodiment of this application;

[0018] Figure 3 This is a schematic diagram illustrating the generation process of a first preparation signal according to an embodiment of this application;

[0019] Figure 4 This is a schematic diagram illustrating the generation process of the second preparation signal according to an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the shifting process of pointers stored in a pointer queue according to an embodiment of this application;

[0021] Figure 6 This is a flowchart of an information processing method based on a queue circuit provided in one embodiment of this application;

[0022] Figure 7 This is a flowchart of an information processing method based on a queue circuit provided in another embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0024] In some chips with upstream and downstream structures (i.e., request initiators and request responders), a queue circuit is typically included. This queue circuit serves to record the information carried in the request during the request execution process. When the downstream completes the processing of a request and returns a response to the upstream, the queue circuit also needs to return the information carried in the request to the upstream to indicate that the request processing is complete and the next action can be performed.

[0025] Please refer to Figure 1 This illustration shows a schematic diagram of a circuit structure including upstream and downstream structures according to an embodiment of this application. The circuit structure includes an upstream structure 10, a downstream structure 20, and a queue circuit 30.

[0026] Upstream structure 10 may include any device with request sending functionality, such as different logic units in a chip. Downstream structure 20 may include any device for processing requests, such as logic units in a chip, memory (e.g., cache), etc. Both upstream structure 10 and downstream structure 20 may include one or more devices; this application does not limit this.

[0027] In some embodiments, the upstream structure 10 sends a request to the downstream structure 20. If a logic unit in the downstream structure 20 receives the request, the request may be a request for the logic unit to perform a certain logical action. Correspondingly, the response returned by the downstream structure 20 to the request may include the data generated by the logical action. If a memory in the downstream structure 20 receives the request, the request may be a read / write request. Correspondingly, the response returned by the downstream structure 20 to the request may include read data / a successful write response, etc. In some embodiments, the data in the response returned by the downstream structure 20 is stored in the SRAM (Static Random-Access Memory) of the upstream structure. In some embodiments, when the upstream structure 10 sends a request to the downstream structure 20, it synchronously records the index of the request (used to indicate the object targeted by the request) and the information carried by the request in the queue circuit 30. When the downstream structure 20 processes the request and returns a response, it provides the index of the request to the queue circuit 30, which then returns the information carried by the request to the upstream structure 10 based on the index.

[0028] In related technologies, the queue circuit 30 has two implementation methods. One method determines the output order of the queue circuit 30 based on the order in which the downstream structure 20 returns. When the downstream structure 20 returns out of order, the queue circuit 30 first outputs the information carried by the request corresponding to the first index returned by the downstream structure 20. In this way, the output order of the queue circuit 30 is equivalent to the return order of the downstream structure 20. When an index returned by the downstream structure 20 corresponds to multiple requests (the information carried by these multiple requests is recorded in the queue circuit 30), a round-robin method is usually chosen to select the output of the queue circuit 30.

[0029] Another implementation outputs all requests in order. That is, when the downstream structure 20 returns an index, the queue circuit 30 must wait for the information carried by each earlier written request (the information carried by these requests was written earlier than the information carried by the request with the index) before it can output the information carried by the request with the index.

[0030] In the first implementation described above, the completely out-of-order queue circuit 30 cannot achieve sequential output of the same index, which fails to meet design requirements in many scenarios. For example, program execution in a processor may depend on the order of memory access. In this case, if the queue circuit 30 returns the information carried by the requests out of order for multiple requests with the same index (for the same object), it may cause program execution errors.

[0031] In the second implementation described above, the fully ordered queue circuit 30 sorts all requests together. Even when a later index meets the output condition, it still needs to wait for the output of the previously sent index (the information carried by the corresponding request). In this case, the efficiency of queue utilization is reduced, and the probability of the queue becoming full and putting back pressure on the upstream is increased, thus failing to achieve optimal performance.

[0032] To address the aforementioned issues, this application provides a novel queue circuit 30 that returns the information carried by requests in the same order for requests with the same index, thereby achieving higher performance and greater utilization efficiency of the queue circuit 30.

[0033] Please refer to Figure 2 The diagram illustrates a schematic of a queue circuit according to an embodiment of this application. The queue circuit 30 includes a signal receiving unit 31, an index queue 32, and a storage unit 33.

[0034] Index queue 32 stores the indices of N requests, which indicate the object to which the request is directed. For example, in the case of a read request, the request index indicates the device accessed by the read request, or the storage location of the data to be read. As another example, in the case of a request to trigger a device to perform a logical operation, the request index indicates that device.

[0035] In some embodiments, the index queue 32 consists of registers.

[0036] In some embodiments, index queue 32 includes at least two registers.

[0037] In some embodiments, the index queue 32 includes Q entries, where Q is an integer greater than N. One of the Q entries is used to store a requested index. When an index is stored in one of the Q entries, that entry is occupied. When no index is stored in that entry, that entry is said to be in an idle state.

[0038] Storage unit 33 stores information carried by N requests, where N is a positive integer. Those skilled in the art should understand that the information carried by requests with different functions is different. For example, a read request needs to carry information such as the address and length of the data to be read, a write request needs to carry the data to be written, and a request used to perform logical operations needs to carry the data involved in the operation, an indication of the operation type, etc. Therefore, this application does not limit the specific content of the information carried by the requests.

[0039] In some embodiments, storage unit 33 includes RAM (Random Access Memory).

[0040] The signal receiving unit 31 is used to receive the queue update signal, which carries a first index, and the first index belongs to the index of the processed request.

[0041] The queue update signal is used to indicate the update of the contents stored in the queue circuit 30.

[0042] A processed request refers to a request that has been processed. That is, when the downstream structure 20 finishes processing a request, it will send a queue update signal carrying the index of the processed request to the queue circuit 30.

[0043] Storage unit 33 is used to output the information carried by the first request when the first request among N requests meets the output conditions.

[0044] The output conditions include: the first request is the first index request whose information is written to storage unit 33 first among the M first index requests included in the N requests. The first index request refers to the request with the first index, and M is a positive integer less than or equal to N.

[0045] In some embodiments, M first index requests are all the first index requests contained in N requests.

[0046] For example, storage unit 33 stores information carried by request a, information carried by request b, and information carried by request c. Request a has an index of 1, while requests b and c both have indices of 2. Request a is written to storage unit 33 earlier than request b, and request b is written to storage unit 33 earlier than request c. Therefore, if the queue update signal received by signal receiving unit 31 carries index 2, storage unit 33 will output the information carried by request b.

[0047] The technical solution provided in this application provides a queue circuit that stores an index of N requests (stored in the index queue of the queue circuit) and the information carried by each of the N requests (stored in the storage unit of the queue circuit). By designing the signal receiving unit in the queue circuit (which belongs to the index of processed requests), and then, if the first request belongs to the N requests and its information was first written into the storage unit, the storage unit outputs the information carried by the first request (the first index request). This ensures that the data carried by requests with the same index stored in the queue circuit are output in order (according to their writing order). Since the index of a request indicates the object targeted by that request, the above solution ensures that for requests targeting the same object, the information carried by them is returned to the upstream (the receiver of the queue circuit's output) in the writing order, thereby ensuring the correctness of the upstream processing logic.

[0048] In some embodiments, please refer to Figure 2 The queue circuit 30 also includes a pointer queue 34, which stores pointers corresponding to N requests. The pointers corresponding to the requests are used to indicate the storage location of the information carried by the requests in the storage unit 33.

[0049] In some embodiments, pointer queue 34 consists of registers. In some embodiments, pointer queue 34 includes at least two registers.

[0050] In some embodiments, the storage space of storage unit 33 is divided into R entries, each entry being used to store information carried in a request, where R is an integer greater than or equal to N. When one of the R entries stores the requested information, that entry is occupied; when that entry does not store the requested information, it is said to be in an idle state.

[0051] For example, when the depth of storage cell 33 (i.e., the value of R) is 128, the pointer corresponding to the request can be a 7-bit number, which can indicate any one of the 128 entries.

[0052] The pointer queue 34 is used to provide the pointer corresponding to the first request to the storage unit 33 when the pointer corresponding to the first index request is written to the pointer queue 34 firstly among M first index requests. The order in which the information carried by the N requests is written to the storage unit 33 is consistent with the order in which the pointers corresponding to the N requests are written to the pointer queue 34.

[0053] Storage unit 33 is used to output the information carried by the first request according to the pointer corresponding to the first request.

[0054] For example, M first index requests include request b and request c. The pointer corresponding to request b is 2 and the pointer corresponding to request c is 3. If pointer 2 is written to pointer queue 34 before pointer 3, pointer queue 34 provides pointer 2 to storage unit 33. Storage unit 33 can then find the entry containing the information carried by request b according to pointer 2, and then output the information carried by request b stored in that entry.

[0055] In some embodiments, the pointer corresponding to the request is also used to indicate the storage location of the requested index in the index queue 32. In some embodiments, R=Q.

[0056] In the above embodiment, pointers corresponding to N requests are recorded in pointer queue 34 of queue circuit 30. Since the order in which the information carried by the N requests is written into storage unit 33 is the same as the order in which the pointers corresponding to the N requests are written into pointer queue 34, in the above scheme, queue circuit 30 only needs to provide the correct pointer to storage unit 33 according to the order of its stored pointers. By providing pointers to storage unit 33 in this simple way, it can ensure that storage unit 33 outputs the information carried by the requests with the same index in order.

[0057] In some embodiments, the pointer queue 34 includes P entries, where P is an integer greater than or equal to N.

[0058] When the pointer corresponding to the first request is the i-th pointer written to pointer queue 34 among the pointers corresponding to N requests, the pointer corresponding to the first request is stored in the i-th entry among P entries, where i is a positive integer less than or equal to N.

[0059] For example, if pointer queue 34 includes 10 entries, and the N requests are request a, request b, and request c, with pointer 1 corresponding to request a, pointer 2 corresponding to request b, and pointer 3 corresponding to request c, then if pointer 1 is stored in the first entry of the 10 entries, pointer 2 in the second entry of the 10 entries, and pointer 3 in the third entry of the 10 entries, then pointer 1 for request a is written to pointer queue 34 first, pointer 2 for request b is written to pointer queue 34 second, and pointer 3 for request c is written to pointer queue 34 third.

[0060] In the above embodiment, the order in which the pointers corresponding to the N requests are located in the pointer queue 34 reflects their writing order. There is no need to deploy additional storage resources to record the writing order, which saves chip area and reduces implementation cost.

[0061] In some embodiments, please refer to Figure 2 The queue circuit 30 also includes a write management unit 35.

[0062] The write management unit 35 is used to determine the pointer corresponding to the second request upon receiving the index of the second request and the information carried by the second request.

[0063] In some embodiments, the write management unit is connected to the index queue 32, the storage unit 33 and the pointer queue 34 respectively.

[0064] In some embodiments, the write management unit 35 is used to receive the index of the second request and the information carried by the second request. In some embodiments, the index of the second request and the information carried by the second request are contained in the same information or signal.

[0065] In some embodiments, the pointer corresponding to the second request is used to indicate the storage location of the index of the second request in the index queue 32, and to indicate the storage location of the information carried by the second request in the storage unit 33. That is to say, the pointer corresponding to the second request is both a write pointer for writing the index of the second request into the index queue 32, a write pointer for writing the information carried by the second request into the storage unit 33, and a read pointer for reading the information carried by the second request from the storage unit 33.

[0066] Therefore, the write management unit 35 can determine the pointer corresponding to the second request using either of the following two methods.

[0067] Method 1: The write management unit 35, upon receiving the index of the second request and the information carried by the second request, searches for an idle entry from the Q entries of the index queue 32 (for example, starting from the first entry in the Q entries and searching downwards), and determines the pointer indicating that entry as the pointer corresponding to the second request.

[0068] Method 2: The write management unit 35, upon receiving the index of the second request and the information carried by the second request, searches for an entry in an idle state from the R entries of the storage unit 33 (for example, starting from the first entry in the R entries and searching downwards), and determines the pointer indicating that entry as the pointer corresponding to the second request.

[0069] For each request, the information it carries and its corresponding index are always synchronously stored in storage unit 33 and index queue 32. After the information carried by the request is read, the information and its corresponding index are synchronously deleted. Therefore, it can be guaranteed that the positions of idle entries in index queue 32 and idle entries in storage unit 33 are the same. Thus, based on the pointer determined by method 1 or method 2, the storage location of the information in storage unit 33 and the storage location of the index in index queue 32 can be indicated simultaneously.

[0070] The write management unit 35 is also used to write the pointer corresponding to the second request into the pointer queue 34, and, according to the pointer corresponding to the second request, write the index of the second request into the index queue 32, and write the information carried by the second request into the storage unit 33.

[0071] In some embodiments, the second request is a request other than the aforementioned N requests. The write management unit 35 is used to write the pointer corresponding to the second request into the (N+1)th entry of the P entries in the pointer queue 34 when P is greater than N.

[0072] In the above embodiment, the write management unit 35 synchronously records the pointers used when writing the index of the second request and the information carried by the second request. On the one hand, this ensures that the writing order of the pointers corresponding to the N requests in the pointer queue 34 reflects the order in which the information carried by the N requests is written to the storage unit 33 (and the order in which the indexes of the N requests are written to the index queue 32). On the other hand, the write pointers used when writing the index of the request and the information carried by the request are cleverly used as the read pointers used when the storage unit 33 outputs information. This makes the pointers in this solution highly reused, and the queue circuit 30 only needs to record a small amount of additional data to achieve the ordered output of the same index request.

[0073] In some embodiments, the order in which the pointers corresponding to the N requests are stored in the pointer queue 34 is consistent with the order in which the pointers corresponding to the N requests are written into the pointer queue.

[0074] For example, if the pointer corresponding to the first request is the i-th pointer to the write pointer queue 34 among the pointers corresponding to N requests, the pointer corresponding to the first request is stored in the i-th entry among P entries.

[0075] In some embodiments, the signal receiving unit 31 is also connected to the index queue 32.

[0076] The signal receiving unit 31 is also used to compare the first index with the index stored in the index queue 32 to generate a first preparation signal corresponding to each of the M first index requests. The first preparation signal corresponding to the first index request is used to mark the storage position of the index of the first index request in the index queue 32.

[0077] In some embodiments, the first preparation signal corresponding to the first index request is used to mark the entry in the Q entries of the index queue 32 where the index of the first index request is located.

[0078] Furthermore, as can be seen from the above embodiments, the pointer corresponding to the request can indicate both the storage location of the requested index in the index queue 32 and the storage location of the information carried in the request in the storage unit 33. Similarly, the first preparation signal corresponding to the first index request can be used not only to mark the storage location of the index of the first index request in the index queue 32, but also to mark the storage location of the information carried in the first index request in the index queue 32.

[0079] In some embodiments, the first preparation signal corresponding to the first index request is used to mark the entry in the R entries of the storage unit 33 where the information carried by the first index request is located.

[0080] In some embodiments, please refer to Figure 2The queue circuit 30 also includes a preparation signal recording unit 36, one end of which is connected to the signal receiving unit 31, and the other end of which is connected to the pointer queue 34. The preparation signal recording unit 36 ​​is used to record the first preparation signals corresponding to M first index requests.

[0081] In some embodiments, the signal recording preparation unit 36 ​​consists of registers. In some embodiments, the signal recording preparation unit includes at least two registers.

[0082] In some embodiments, the signal receiving unit 31 is further configured to write the first preparation signals corresponding to the M first index requests into the preparation signal recording unit 36.

[0083] In some embodiments, please refer to Figure 3 The preparation signal recording unit 36 ​​includes T entries 361, where T is an integer greater than N. One entry 361 in the preparation signal recording unit 36 ​​is used to mark whether the corresponding entry in the index queue 32 stores the index of the first index request. For example, when an entry in the preparation signal recording unit 36 ​​is set to 1, it indicates that the corresponding entry in the index queue 32 stores the index of the first index request (in this case, 1 in the entry can be considered as the first preparation signal corresponding to the first index request). When an entry in the preparation signal recording unit 36 ​​is set to 0, it can be considered as indicating that the corresponding entry in the index queue 32 does not store the index of the first index request. That is to say, the pointer corresponding to the first index request can also be used to indicate the entry where the first preparation signal corresponding to the first index request is located from the T entries 361 included in the preparation signal recording unit 36. In some embodiments, R=Q=T.

[0084] For example, please refer to Figure 3 The signal receiving unit 31 compares the received first index 2 with the index recorded in the index queue 32, and then knows that the third and fourth entries in the index queue 32 store the index 2 corresponding to the first index request. Accordingly, the signal receiving unit 31 sets the values ​​of the third and fourth entries in the preparation signal recording unit 36 ​​to 1, which marks the third and fourth entries in the index queue 32 (the value 1 in the third and fourth entries in the preparation signal recording unit 36 ​​can be regarded as the first preparation signal).

[0085] In some embodiments, the pointer queue 34 is further configured to read the first preparation signals corresponding to the M first index requests from the signal receiving unit 31.

[0086] In the above embodiment, a preparation signal recording unit 36 ​​is provided between the signal receiving unit 31 and the pointer queue 34, thereby providing corresponding storage space to support the signal receiving unit 31 in real time recording the first preparation signal, and to support the pointer queue 34 in completing the conversion from the first preparation signal to the second preparation signal.

[0087] The pointer queue 34 is used to convert the first preparation signals corresponding to M first index requests into second preparation signals corresponding to M first index requests respectively. The second preparation signal corresponding to the first index request is used to mark the storage location of the pointer corresponding to the first index request in the pointer queue 34.

[0088] In some embodiments, the pointer queue 34 is also used to write back the second ready signals corresponding to the M first index requests to the ready signal recording unit 36.

[0089] In some embodiments, for any one of the M first index requests, the pointer queue 34 is used to determine the pointer corresponding to the first index request from the pointers corresponding to the N requests stored therein, which indicates the storage location marked by the first preparation signal corresponding to the first index request (see above, the storage location can be either the storage location of the index of the first index request in the index queue 32 or the storage location of the information carried by the first index request in the storage unit 33), and generate a signal for marking the storage location of the pointer in the pointer queue 34 as the second preparation signal corresponding to the first index request.

[0090] In some embodiments, referring to the above, the pointer corresponding to the first index request can also be used to indicate the entry where the first preparation signal corresponding to the first index request is located from the T entries 361 included in the preparation signal recording unit 36. Therefore, for any one of the M first index requests, the pointer queue 34 can also be used to determine the pointer that indicates the entry where the first preparation signal (in the preparation signal recording unit 36) corresponding to the first index request is located from the pointers corresponding to the N requests stored in itself, and generate a signal to mark the storage position of the pointer in the pointer queue 34 as the second preparation signal corresponding to the first index request.

[0091] For example, please refer to Figure 4The third and fourth entries in the index queue 32 store index 2 corresponding to the first index request. Accordingly, the signal receiving unit 31 sets the values ​​of the third and fourth entries in the preparation signal recording unit 36 ​​to 1, and sets the remaining entries to 0. In this case, the pointer 2 stored in the second entry in the pointer queue 34 can indicate the third entry in the index queue 32 (or the preparation signal recording unit 36), and the pointer 3 stored in the third entry in the pointer queue 34 can indicate the fourth entry in the index queue 32 (or the preparation signal recording unit 36). Therefore, the pointer queue 34 sets the second and third entries in the preparation signal recording unit 36 ​​to 1 (which can be regarded as the second preparation signal), and sets the remaining entries to 0, thereby converting the first preparation signals corresponding to the M first index requests into the second preparation signals corresponding to the M first index requests, and thus marking the second and third entries in the pointer queue 34.

[0092] In some embodiments, the pointer queue 34 includes a storage subunit and a logic subunit ( Figure 2 (Not shown in the diagram). The storage subunit is used to store pointers corresponding to N requests respectively, and the logic subunit is used to convert the first preparation signals corresponding to M first index requests respectively into second preparation signals corresponding to M first index requests respectively, and to implement other logical functions executed by the pointer queue 34.

[0093] The pointer queue 34 is also used to provide the pointer corresponding to the first request to the storage unit 33 when the pointer corresponding to the first request is located in the first storage location among the M storage locations, wherein the M storage locations are marked by the second preparation signals corresponding to the M first index requests respectively, and M is a positive integer less than or equal to N.

[0094] For example, please refer to Figure 4 The second and third entries in pointer queue 34 are marked by the second preparation signal. Therefore, the M storage locations are the second and third entries in pointer queue 34. Since the second entry in pointer queue 34 is before the third entry, pointer queue 34 can directly provide pointer 2 stored in the second entry to storage unit 33.

[0095] In the above embodiment, firstly, the first preparation signal corresponding to the first index request is converted into a second preparation signal. This can correctly mark the storage position of the pointer corresponding to the first index request in the pointer queue 34 when the pointer queue 34 needs to maintain the pointer writing order (ensuring that the storage order of the pointers corresponding to the N requests in the pointer queue 34 is consistent with the order in which the pointers corresponding to the N requests are written into the pointer queue), thus facilitating the retrieval of the corresponding pointer. Secondly, the above scheme only marks the position of the index / pointer of the first index request, without considering the writing order of the indexes / carried information of the other requests among the N requests. Therefore, request return can be achieved with lower latency and less power consumption. Thirdly, in the above scheme, the pointer queue 34 directly provides the pointer with the earlier storage position among the pointers corresponding to the M first index requests, without needing to record the corresponding storage time, resulting in lower implementation complexity.

[0096] In some embodiments, the pointer queue 34 is used to delete the pointer stored in the i-th entry (i.e., the pointer corresponding to the first request) after providing the pointer corresponding to the first request to the storage unit 33, and, if i is less than N, to move the pointers stored in the pointer queue from the (i+1)-th entry to the N-th entry forward by one entry in sequence. That is, to move the pointer stored in the (i+1)-th entry to the i-th entry, to move the pointer storing the amount in the (i+2)-th entry to the (i+1)-th entry, ..., and to move the pointer stored in the N-th entry to the (N-1)-th entry.

[0097] For example, please refer to Figure 5 In cycle 0, pointer queue 34 has four occupied entries, corresponding to four write operations of queue circuit 30, that is, four requests in sequence. The pointer corresponding to the first request is pointer 0, index = 0; the pointer corresponding to the second request is pointer 1, index = 0; the pointer corresponding to the third request is pointer 2, index = 1; and the pointer corresponding to the fourth request is pointer 3, index = 0. Simultaneously, in cycle 0, the position of pointer 2 in pointer queue 34 is marked by the second ready signal in ready signal recording unit 36. Pointer queue 34 then outputs pointer 2 as a pointer provided to storage unit 33. In the next cycle (cycle 1), pointer queue 34 will shift pointer 3 from its original entry (the entry after pointer 2) to the entry where pointer 2 was deleted.

[0098] In the above embodiment, after the pointer queue 34 provides the pointer corresponding to the first request to the storage unit 33, the pointer corresponding to the first request will not only be removed by the pointer queue 34, but the pointers located after it will also be moved forward accordingly, thereby ensuring that there will be no free entries (i.e., entries that do not store pointers) between any two occupied entries (i.e., entries that store pointers) in the pointer queue 34, thereby ensuring that when new pointers are written later, the arrangement order of pointers in the pointer queue 34 can always accurately reflect their writing order.

[0099] In some embodiments, the storage unit 33 is further configured to delete the information carried in the first request after outputting the information carried in the first request.

[0100] In some embodiments, the index queue 32 is further configured to delete the index of the first request after the pointer queue 34 provides the pointer corresponding to the first request to the storage unit 33.

[0101] The following are embodiments of the method of this application. For details not described in the embodiments of the method of this application, please refer to the above embodiments regarding queue circuits.

[0102] Please refer to Figure 6 The diagram illustrates a flowchart of an information processing method based on a queue circuit according to an embodiment of this application. The queue circuit includes a signal receiving unit, an index queue, and a storage unit. The index queue stores indices of N requests, where each request index indicates the object targeted by the request. The storage unit stores information carried by each of the N requests, where N is a positive integer. The method includes at least one of the following steps 610-620.

[0103] Step 610: The signal receiving unit receives the queue update signal, which carries a first index, and the first index belongs to the index of the processed request.

[0104] Step 620: If the first request among the N requests meets the output conditions, the storage unit outputs the information carried by the first request.

[0105] The output conditions include: the first request is the first index request whose information is written to the storage unit first among the M first index requests included in the N requests. The first index request refers to the request with the first index, and M is a positive integer less than or equal to N.

[0106] In some embodiments, the queue circuit further includes a pointer queue, which stores pointers corresponding to N requests. The pointers corresponding to the requests are used to indicate the storage location of the information carried by the requests in the storage unit.

[0107] The above method further includes: when the pointer queue is the first index request in M ​​first index requests, the pointer corresponding to the first request is provided to the storage unit, wherein the order in which the information carried by the N requests is written to the storage unit is consistent with the order in which the pointers corresponding to the N requests are written to the pointer queue.

[0108] Step 620 above includes: the storage unit outputs the information carried by the first request according to the pointer corresponding to the first request.

[0109] The technical solution provided in this application embodiment addresses a queue circuit that stores an index of N requests (stored in the index queue of the queue circuit) and the information carried by each of the N requests (stored in the storage unit of the queue circuit). By designing the signal receiving unit in the queue circuit (which belongs to the index of a processed request), and then, in the case where the first request among the N requests is the first index request whose information is written to the storage unit first (a first index request refers to a request with the first index), the storage unit outputs the information carried by the first request. This ensures that the data carried by requests with the same index stored in the queue circuit are output in order (according to their writing order). Since the index of a request indicates the object targeted by that request, the above solution ensures that for requests targeting the same object, the information carried by them is returned to the upstream (the receiver of the queue circuit's output) in the writing order, thereby ensuring the correctness of the upstream processing logic.

[0110] In some embodiments, the order in which the pointers corresponding to the N requests are stored in the pointer queue is consistent with the order in which the pointers corresponding to the N requests are written into the pointer queue. In this case, please refer to... Figure 7 The diagram illustrates a flowchart of an information processing method based on a queue circuit according to another embodiment of this application. The method includes at least one of the following steps 710-750.

[0111] Step 710: The signal receiving unit receives a queue update signal, which carries a first index that belongs to the index of the processed request.

[0112] Step 720: The signal receiving unit compares the first index with the indexes stored in the index queue to generate a first preparation signal corresponding to each of the M first index requests.

[0113] The first ready signal corresponding to the first index request is used to mark the storage location of the index of the first index request in the index queue.

[0114] Step 730: The pointer queue converts the first ready signals corresponding to the M first index requests into the second ready signals corresponding to the M first index requests.

[0115] The second preparation signal corresponding to the first index request is used to mark the storage location of the pointer corresponding to the first index request in the pointer queue.

[0116] Step 740: If the pointer corresponding to the first request is located in the first storage location among the M storage locations, the pointer queue provides the storage unit with the pointer corresponding to the first request.

[0117] Among them, the M storage locations are marked by the second preparation signals corresponding to the M first index requests, where M is a positive integer less than or equal to N.

[0118] Step 750: The storage unit outputs the information carried by the first request according to the pointer corresponding to the first request.

[0119] In some embodiments, the queue circuit further includes a preparation signal recording unit, one end of which is connected to a signal receiving unit and the other end of which is connected to a pointer queue; the preparation signal recording unit is used to record the first preparation signals corresponding to M first index requests respectively.

[0120] In some embodiments, the pointer queue includes P entries, where P is an integer greater than or equal to N; when the pointer corresponding to the first request is the i-th pointer among the pointers corresponding to the N requests respectively written into the pointer queue, the pointer corresponding to the first request is stored in the i-th entry among the P entries, where i is a positive integer less than or equal to N.

[0121] In some embodiments, please refer to Figure 7 The above method also includes step 760.

[0122] Step 760: After providing the pointer corresponding to the first request to the storage unit, the pointer queue deletes the pointer stored in the i-th entry, and if i is less than N, the pointers stored in the pointer queue from the (i+1)-th entry to the N-th entry are shifted forward one entry in sequence.

[0123] In some embodiments, the queue circuit further includes a write management unit; the method further includes:

[0124] 1. Upon receiving the index of the second request and the information carried by the second request, the write management unit determines the pointer corresponding to the second request.

[0125] 2. The write management unit writes the pointer corresponding to the second request into the pointer queue, and writes the index of the second request into the index queue according to the pointer corresponding to the second request, and writes the information carried by the second request into the storage unit.

[0126] For ease of understanding, an application example based on the above embodiments is given below.

[0127] The upstream structure sends request a, request b, and request c (equivalent to the second request mentioned above) to the downstream structure in sequence. The indexes of requests a and b are both index 1, and the index of request c is index 2.

[0128] Assuming that when write management unit 35 receives request a (receiving the index of request a and the information carried by request a), the first, second, and third free positions in index queue 32 and storage unit 33 are all the second, third, and fourth entries, then write management unit 35 can determine the pointers corresponding to each request based on the free entries in index queue 32 (or storage unit 33). Request a corresponds to pointer 1, pointing to the second entry in index queue 32 and storage unit 33; request b corresponds to pointer 2, pointing to the third entry in index queue 32 and storage unit 33; and request c corresponds to pointer 3, pointing to the fourth entry in index queue 32 and storage unit 33. Pointers 1, 2, and 3 are sequentially stored in pointer queue 34. For simplicity, it is assumed that pointer queue 34 is empty, so pointers 1, 2, and 3 are stored sequentially in the first, second, and third entries of pointer queue 34.

[0129] Based on the positions indicated by pointers 1, 2, and 3, the second, third, and fourth entries of index queue 32 sequentially store index 1, index 2, and index 3. The second, third, and fourth entries of storage unit 33 sequentially store the information carried by request a, request b, and request c.

[0130] The signal receiving unit 31 receives queue update information from the downstream structure. Assuming that the index of the processed request carried by the queue update information is index 1 (i.e. the first index mentioned above), the signal receiving unit 31 compares the first index with the index stored in the index queue 32 to obtain the first preparation signal 01100..., that is, the second and third entries containing index 1 are marked as 1, and the others are marked as 0.

[0131] Next, the pointers pointing to the second and third entries in the index queue 32, namely pointer 1 and pointer 2, are found in the pointer queue 34. The first preparation signal is converted into the second preparation signal 1100... that is, the first and second entries where pointer 1 and pointer 2 are located are marked as 1, and the others are marked as 0.

[0132] Based on the storage location indicated by the second preparation signal, it can be determined that the writing order of pointer 1 is earlier than that of pointer 2. Therefore, based on the storage location indicated by pointer 1, the information carried by request a is read from storage unit 33 and output to the upstream structure.

[0133] Delete pointer 1, the information carried by request 'a', and the index corresponding to 'a' (i.e., index 1 stored in the second entry). The storage locations of pointers 2 and 3 are changed to the first and second entries in pointer queue 34.

[0134] An exemplary embodiment of this application also provides a processor, the processor including the queue circuit described in the above embodiments.

[0135] The aforementioned processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and coprocessors. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, the processor may also include an AI processor, which is used to handle computational operations related to machine learning.

[0136] An exemplary embodiment of this application also provides a computer device, the computer device including a processor, the processor including the queue circuit described in the above embodiments.

[0137] Optionally, the computer device may be a server, or a terminal device such as a mobile phone, tablet computer, vehicle terminal, wearable device, smart home device, or any device that uses a processor, such as a robot or base station. This application does not limit the scope of the application.

[0138] An exemplary embodiment of this application also provides a chip product, the chip product including the queue circuit described in the above embodiments.

[0139] One embodiment of this application also provides a GPU, which includes the queue circuit described in the above embodiments.

[0140] One embodiment of this application also provides a graphics card, the graphics card including a processor, the processor including the queue circuit described above.

[0141] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0142] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A queue circuit, characterized in that, The queue circuit includes a signal receiving unit, an index queue, and a storage unit. The index queue stores the indices of N requests, and the indexes of the requests are used to indicate the objects targeted by the requests. The storage unit stores the information carried by the N requests, where N is a positive integer. The signal receiving unit is used to receive a queue update signal, which carries a first index. The first index belongs to the index of the processed request. The queue update signal is sent by the processor of the processed request when the processed request is completed. The storage unit is used to output the information carried by the first request when the first request among the N requests meets the output conditions; wherein, the output conditions include: the first request is the first index request whose information is written to the storage unit first among the M first index requests included in the N requests, the first index request refers to the request with the first index, and M is a positive integer less than or equal to N.

2. The queue circuit according to claim 1, characterized in that, The queue circuit also includes a pointer queue, which stores pointers corresponding to the N requests respectively. The pointers corresponding to the requests are used to indicate the storage location of the information carried by the requests in the storage unit. The pointer queue is used to provide the storage unit with the pointer corresponding to the first request when the pointer corresponding to the first request is written to the pointer queue first among the M first index requests. The order in which the information carried by the N requests is written to the storage unit is consistent with the order in which the pointers corresponding to the N requests are written to the pointer queue. The storage unit is used to output the information carried by the first request according to the pointer corresponding to the first request.

3. The queue circuit according to claim 2, characterized in that, The order in which the pointers corresponding to the N requests are stored in the pointer queue is consistent with the order in which the pointers corresponding to the N requests are written into the pointer queue. The signal receiving unit is further configured to compare the first index with the index stored in the index queue to generate a first preparation signal corresponding to each of the M first index requests. The first preparation signal corresponding to the first index request is used to mark the storage position of the index of the first index request in the index queue. The pointer queue is used to convert the first preparation signals corresponding to the M first index requests into second preparation signals corresponding to the M first index requests, wherein the second preparation signal corresponding to the first index request is used to mark the storage position of the pointer corresponding to the first index request in the pointer queue. The pointer queue is further configured to provide the storage unit with the pointer corresponding to the first request when the pointer corresponding to the first request is located in the first storage location among the M storage locations, wherein the M storage locations are marked by the second preparation signals corresponding to the M first index requests respectively, and M is a positive integer less than or equal to N.

4. The queue circuit according to claim 3, characterized in that, The queue circuit also includes a preparation signal recording unit, one end of which is connected to the signal receiving unit, and the other end of which is connected to the pointer queue. The preparation signal recording unit is used to record the first preparation signals corresponding to the M first index requests respectively.

5. The queue circuit according to any one of claims 2 to 4, characterized in that, The pointer queue includes P entries, where P is an integer greater than or equal to N; when the pointer corresponding to the first request is the i-th pointer among the pointers corresponding to the N requests respectively written into the pointer queue, the pointer corresponding to the first request is stored in the i-th entry among the P entries, where i is a positive integer less than or equal to N.

6. The queue circuit according to claim 5, characterized in that, The pointer queue is also used to delete the pointer stored in the i-th entry after providing the pointer corresponding to the first request to the storage unit, and, if i is less than N, to sequentially move the pointers stored in the (i+1)-th to N-th entries of the pointer queue forward by one entry.

7. The queue circuit according to any one of claims 2 to 4, characterized in that, The queue circuit also includes a write management unit; The write management unit is used to determine the pointer corresponding to the second request upon receiving the index of the second request and the information carried by the second request; The write management unit is further configured to write the pointer corresponding to the second request into the pointer queue, and, according to the pointer corresponding to the second request, write the index of the second request into the index queue, and write the information carried by the second request into the storage unit.

8. A processor, characterized in that, The processor includes the queue circuit as described in any one of claims 1 to 7.

9. A computer device, characterized in that, The computer device includes a processor, the processor including a queue circuit as described in any one of claims 1 to 7.

10. A chip product, characterized in that, The chip product includes the queue circuit as described in any one of claims 1 to 7.

11. An information processing method based on queue circuits, characterized in that, The queue circuit includes a signal receiving unit, an index queue, and a storage unit. The index queue stores indices of N requests, each index indicating the object targeted by the request. The storage unit stores information carried by each of the N requests, where N is a positive integer. The method includes: The signal receiving unit receives a queue update signal, which carries a first index. The first index belongs to the index of the processed request. The queue update signal is sent by the processor of the processed request when the processed request is completed. When the first request among the N requests meets the output conditions, the storage unit outputs the information carried by the first request; wherein, the output conditions include: the first request is the first index request whose information is written to the storage unit first among the M first index requests included in the N requests, and the first index request refers to the request with the first index, where M is a positive integer less than or equal to N.

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