Request processing method, secondary merging device, and request processing system

Abstract

The embodiments of the present disclosure disclose a request processing method, a secondary merging device and a request processing system, wherein the request processing method comprises: performing primary merging on a plurality of original requests of to-be-processed instructions to obtain a plurality of primary merging requests; performing secondary merging on the plurality of primary merging requests to obtain a plurality of secondary merging requests, and issuing the secondary merging requests to a downstream module, so that the downstream module performs operations corresponding to the plurality of secondary merging requests; the granularity of the secondary merging is greater than the granularity of the primary merging; when a disturbance request is received in the process of the secondary merging, it is determined whether to interpose the disturbance request into the secondary merging requests based on the fullness of the secondary merging area corresponding to the original request, and then issue the secondary merging requests to the downstream module, so that the downstream module performs operations corresponding to the disturbance request; the secondary merging area is used to cache the primary merging requests to a cache layer in a determined order of the primary merging requests.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of computer, and particularly relates to a request processing method, a two-stage merging device, and a request processing system. BACKGROUND

[0002] In modern processor design, multiple address length smaller requests are merged into an address longer request to reduce the number of requests accessing downstream modules (such as cache). However, this request merging scheme is only applicable to single source request merging, and the scope of application is narrow. SUMMARY

[0003] Therefore, the embodiments of the present disclosure provide at least a request processing method, a two-stage merging device, and a request processing system.

[0004] The technical scheme of the embodiments of the present disclosure is implemented as follows:

[0005] In one aspect, the embodiments of the present disclosure provide a request processing method, comprising:

[0006] performing one-stage merging on multiple original requests of a to-be-processed instruction to obtain multiple one-stage merging requests;

[0007] performing two-stage merging on the multiple one-stage merging requests to obtain multiple two-stage merging requests, and issuing the two-stage merging requests to a downstream module, so that the downstream module performs operations corresponding to the multiple two-stage merging requests; the granularity of the two-stage merging is greater than the granularity of the one-stage merging;

[0008] when a disturbance request is received in the process of the two-stage merging, determining whether to interpose the disturbance request into the two-stage merging requests based on the fullness of a two-stage merging area corresponding to the original request, and issuing the disturbance request to the downstream module, so that the downstream module performs an operation corresponding to the disturbance request; the two-stage merging area is used to cache the multiple one-stage merging requests to a cache layer in a determined order of the one-stage merging requests.

[0009] In another aspect, the embodiments of the present disclosure provide a two-stage merging device, comprising:

[0010] a two-stage merging area, configured to cache multiple one-stage merging requests to a cache layer in a determined order of the one-stage merging requests, to implement two-stage merging on the multiple one-stage merging requests to obtain multiple two-stage merging requests; the multiple one-stage merging requests are obtained by performing one-stage merging on multiple original requests of a to-be-processed instruction, and the granularity of the two-stage merging is greater than the granularity of the one-stage merging;

[0011] an additional cache area, configured to cache other requests except read requests and write requests;

[0012] an order storage area, configured to record an order of requests arriving at the two-stage merging device.

[0013] The secondary merging device is configured to issue the plurality of secondary merging requests to a downstream module, so that the downstream module performs operations corresponding to the plurality of secondary merging requests.

[0014] When a disturbance request is received in the process of secondary merging, the secondary merging device is further configured to determine whether to interpose the disturbance request into the secondary merging requests based on whether the secondary merging area corresponding to the original request is empty or full, and then issue the secondary merging requests to the downstream module, so that the downstream module performs operations corresponding to the disturbance request.

[0015] In another aspect, the embodiments of the present disclosure provide a request processing system, comprising:

[0016] The primary merging device is configured to perform primary merging on a plurality of original requests of to-be-processed instructions, to obtain a plurality of primary merging requests.

[0017] The secondary merging device is configured to perform secondary merging on the plurality of primary merging requests, to obtain a plurality of secondary merging requests; when a disturbance request is received in the process of secondary merging, the secondary merging device is further configured to determine whether to interpose the disturbance request into the secondary merging requests based on whether the secondary merging area corresponding to the original request is empty or full, and then issue the secondary merging requests to the downstream module; the granularity of secondary merging is greater than the granularity of primary merging; and the secondary merging area is configured to cache the plurality of primary merging requests to a cache layer in a determined order of the primary merging requests.

[0018] The downstream module is configured to perform operations corresponding to the plurality of secondary merging requests, to implement processing of the to-be-processed instructions; and perform operations corresponding to the disturbance request.

[0019] In another aspect, the embodiments of the present disclosure provide a computer device, comprising a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0020] In another aspect, the embodiments of the present disclosure provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps of the above method.

[0021] In another aspect, the embodiments of the present disclosure provide a computer program, which comprises computer readable code, and when the computer readable code runs in a computer device, a processor in the computer device executes part or all of the steps of the above method.

[0022] In another aspect, the embodiments of the present disclosure provide a computer program product, which comprises a non-transitory computer readable storage medium storing a computer program, and the computer program is read and executed by a computer to implement part or all of the steps of the above method.

[0023] In the embodiments of the present disclosure, when a disturbance request is received in the process of secondary merging, it is determined whether to interpose the disturbance request into the secondary merging request based on the fullness of the secondary merging area corresponding to the original request, and the following is sent to the downstream module. In this way, in the case of a disturbance request and a main branch request, the disturbance request can be sent to the downstream module in different ways based on the fullness of the secondary merging area corresponding to the original request, while ensuring that the requests of the main branch are in order, the requests of the disturbance branch are in order with the requests of the main branch, and the secondary merging device can achieve better performance in any mode.

[0024] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0026] Figure 1 A schematic diagram of the composition structure of a request processing system provided by an embodiment of the present disclosure Figure 1 ;

[0027] Figure 2 A schematic diagram of the composition structure of a request processing system provided by an embodiment of the present disclosure Figure 2 ;

[0028] Figure 3(a) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 1 ;

[0029] Figure 3(b) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 2 ;

[0030] Figure 4 A schematic diagram of the implementation process of a request processing method provided by an embodiment of the present disclosure Figure 1 ;

[0031] Figure 5 A schematic diagram of the implementation process of a request processing method provided by an embodiment of the present disclosure Figure 2 ;

[0032] Figure 6(a) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure

[0033] Figure 6(b) is a schematic diagram of the inlet and outlet of a secondary merging device in a request processing system provided by an embodiment of the present disclosure Figure 4 ;

[0034] Figure 6(c) is a schematic diagram of the entrance and exit of a secondary merging device in a request processing system provided in an embodiment of this disclosure. Figure 5 ;

[0035] Figure 7 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0038] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0040] This disclosure provides a request processing system, the request processing system comprising:

[0041] A first-level merging device is used to merge multiple original requests for the instruction to be processed into multiple first-level merged requests.

[0042] A secondary merging device is used to perform secondary merging on multiple primary merging requests to obtain multiple secondary merging requests; when a disturbance request is received during the secondary merging process, based on the empty / full status of the secondary merging area corresponding to the original request, it determines whether to interpolate the disturbance request into the secondary merging request and send it to the downstream module; the granularity of the secondary merging is larger than the granularity of the primary merging; the secondary merging area is used to cache multiple primary merging requests to the cache layer according to the determination order of the primary merging requests;

[0043] A downstream module is configured to perform operations corresponding to the plurality of secondary merging requests to implement processing of the to-be-processed instruction; and perform operations corresponding to the disturbance request.

[0044] The request processing system can be deployed in a computer device, which can be a device containing a graphics processing unit (GPU) or a device containing an artificial intelligence (AI) cluster, etc. In some embodiments, the request processing system can also be replaced by other names, such as a request merging system, a request issuing system, a request response system, etc.

[0045] The request processing system is configured to merge original requests with small address length into requests with long length, or merge requests with repeated addresses into one request, thereby reducing the number of requests accessed by a downstream module. The request merging module can be set as one module or multiple levels for progressive merging according to design requirements.

[0046] The embodiments of the present disclosure select a multi-level merging module design. As shown in Figure 1 The first-level merging device (first-level merging module) is also referred to as a front-level merging module, and is configured to merge original requests with length less than or equal to R Byte into requests with R Byte granularity. The second-level merging device (second-level merging module) is also referred to as a rear-level merging module, and is configured to merge the requests with R Byte granularity into requests with R*N Byte granularity; N is a positive integer greater than 1.

[0047] The first-level merging device generally performs parallel address comparison and request merging on a plurality of original requests (one beat can receive and process a plurality of original requests). The input of the second-level merging device is generally the output of one first-level merging device, that is, one beat can only receive and process one request of the front-level merging module. The second-level merging device needs to receive requests of the first-level merging device at most N times, and then outputs one request with length of R*N Byte.

[0048] The downstream module is configured to perform operations corresponding to the secondary merging requests to implement processing of the to-be-processed instruction. For example, the downstream module can be a cache, a memory, etc.

[0049] The disturbance module is configured to receive requests other than read requests and write requests. In addition to read requests and write requests, there are generally some requests for maintaining the consistency of system memory, such as fence / flush / invalidate / barrier requests, which can be collectively referred to as coherent requests. Due to the consistency requirements of these requests, the requests between the first merging device and the second merging device and between the second merging device and the downstream module need to be in order.

[0050] Figure 1 In some embodiments, as shown in FIG. 1, the branch from the first merging device to the second merging device and from the second merging device to the downstream module is a main branch, and the branch from the disturbance module to the second merging device and from the second merging module to the downstream module is a disturbance branch. The request sent by the disturbance module is a disturbance request.

[0051] The read and write requests of the main branch have a high frequency of occurrence, while the disturbance requests of the disturbance branch have a low frequency of occurrence, such as load requests. Disturbance requests generally have no merging requirements, and have no order-keeping requirements with the read and write requests of the main branch, but have order-keeping requirements with the coherent requests of the main branch.

[0052] In some embodiments, as shown in FIG. 1, the second merging device includes: Figure 2

[0053] a second merging area, configured to cache a plurality of first merging requests to a cache layer in a determined order of the first merging requests, to implement second merging of the plurality of first merging requests, and to obtain a plurality of second merging requests; the plurality of first merging requests are obtained by first merging a plurality of original requests of to-be-processed instructions, and the granularity of the second merging is greater than the granularity of the first merging;

[0054] an additional cache area, configured to cache other requests in addition to the read requests and the write requests;

[0055] an order storage area, configured to record the order of requests arriving at the second merging device;

[0056] the second merging device, configured to issue the plurality of second merging requests to a downstream module, to enable the downstream module to perform operations corresponding to the plurality of second merging requests;

[0057] When a disturbance request is received in the process of the second merging, the second merging device is further configured to determine whether to interpose the disturbance request into the second merging requests based on the fullness of the second merging area corresponding to the original request, and then issue the disturbance request to the downstream module, to enable the downstream module to perform an operation corresponding to the disturbance request.

[0058] ​The reason that the secondary coalescing device is divided into a secondary coalescing area, an additional cache area, and an order storage area is that: through the secondary coalescing area, the read-write requests after the first coalescing can be coalesced at the secondary level; through the additional cache area, other requests (noise requests) other than read requests and write requests can be cached; in this way, the secondary coalescing of read-write requests and the caching of noise requests are separated, which can prevent noise requests from interfering with secondary coalescing, so that noise requests can be interleaved into secondary coalescing requests for delivery without interfering with secondary coalescing. In addition, the order storage area stores the order of each request (including first coalescing requests and noise requests) to the secondary coalescing device, so that the order storage area can achieve the ordered delivery of requests.

[0059] Interleaving noise requests into secondary coalescing requests means that, in the process of secondary coalescing, noise requests are inserted into the secondary coalescing requests that have been coalesced and then delivered, and the unfinished secondary coalescing is continued to be processed.

[0060] The coalescing granularity of the secondary coalescing area can be R*N Byte, that is, N read-type first coalescing requests from the first coalescing device can be coalesced into one secondary coalescing request.

[0061] The additional cache area (other cmd coalesce buffer) is used to cache coherent requests and noise requests.

[0062] The order storage area (order table) is used to record the order of the secondary coalescing device entry request.

[0063] In some embodiments, when the type of the original request is a read type, the secondary coalescing area is a read request coalescing area; when the type of the original request is a write type, the secondary coalescing is a write request coalescing area; the read request coalescing area is used to coalesce the read-type first coalescing requests at the secondary level; the write request coalescing area is used to coalesce the write-type first coalescing requests at the secondary level; the depth of the cache layer of the read request coalescing area, the write request coalescing area, and the additional cache area is determined based on the number of first coalescing requests that the secondary coalescing device can receive at one time and the number threshold; the depth of the order storage area is the sum of the depths of the read request coalescing area, the write request coalescing area, and the additional cache area.

[0064] The coalescing granularity of the read request coalescing area (Read cmd coalesce buffer) is R*N Byte, that is, N read-type first coalescing requests from the first coalescing device can be coalesced into one read-type secondary coalescing request.

[0065] The coalescing granularity of the write request coalesce buffer (Write cmd coalesce buffer) is R*N Byte, that is, N write type primary coalescing requests sent by the primary coalescing device can be coalesced into one write type secondary coalescing request.

[0066] The write request coalesce buffer (Write cmd coalesce buffer) is responsible for secondary coalescing of write requests, coalescing R byte length write requests into N*R byte length write requests. The read request coalesce buffer (Read cmd coalesce buffer) is responsible for secondary coalescing of read requests, coalescing R byte length read requests into N*R byte length read requests. Since it is secondary coalescing, the coalescing function can be simplified to only coalesce consecutive received requests, and once a newly received 1 request does not belong to the same N*R range as the previous buffer request, the cache layer stops request coalescing.

[0067] The number of primary coalescing requests that can be received by the secondary coalescing device at one time is N. The number threshold can be set to 1.

[0068] The depth of the write request coalesce buffer (write cmd coalesce buffer) is set to N+1. Depth N corresponds to the coalescing granularity R*N Byte of the secondary coalescing device; +1 is to prevent the primary coalescing device from being blocked in the scenario of receiving consecutive write requests sent by the primary coalescing device.

[0069] The depth of the read request coalesce buffer (Read cmd coalesce buffer) is set to N+1. Depth N corresponds to the coalescing granularity R*N Byte of the secondary coalescing device; +1 is to prevent the primary coalescing device from being blocked in the scenario of receiving consecutive read requests sent by the primary coalescing device.

[0070] The depth of the additional cache area (other cmd coalesce buffer) is set to N+1. In this scenario: N write requests, at least N coherent or noise requests, N write requests, if the request output by the secondary coalescing device is to be guaranteed not to be interrupted, the depth of the other cmd coalesce buffer needs to be set to at least N+1.

[0071] As shown in FIG. 3(a) to 3(b), write1beat0, write1beat1, write1beat2, write1beat3 are 4 beat (tap) write requests belonging to the same N * R length, which can be combined into 1 N * R length write1. Similarly, write2beat0, write2beat1, write2beat2, write2beat3 are 4 beat (tap) write requests belonging to the same N * R length, which can be combined into 1 N * R length write2. The difference between the write request beat 0 / 1 / 2 / 3 of the secondary coalesce device entrance and the secondary coalesce device exit is that the entrance is 4 requests, and the length of 1 request is R; the exit is 1 request with length = N * R, and 4 taps are transmitted on the interface.

[0072] As shown in FIG. 3(a), assuming N = 4, the depth of the additional cache area (other cmd coalesce buffer) is set to 5, and the above scenario is encountered, which can ensure that the secondary coalesce device exit is continuously flowing. As shown in FIG. 3(b), if the depth of the additional cache area (other cmd coalesce buffer) is set to 2, then under the above scenario, the secondary coalesce device entrance will be full due to the cmd coalesce buffer, which will block the secondary coalesce device entrance (entrance back pressure) for 3 taps, and thus the secondary coalesce device exit request will also have 3 null taps (null in FIG. 3(b)).

[0073] The depth of the order storage area (order table) is 3N + 3. The request type received by the secondary coalesce device entrance can be divided into write request, read request, coherent request, and noise request. The internal storage of each layer of the order table is 2-bit request type, which is used to mark the four types of request. For example: write request, read request, coherent request, noise request are marked as 2’b00, 2’b01, 2’b10, 2’b11 respectively.

[0074] In some embodiments, each cache layer of the write request coalesce buffer and the read request coalesce buffer is provided with a 1-bit coalesce flag (collect_finish_flag) for identifying whether the request of the layer has completed coalesce, and the initial value is 0. If the collect_finish_flag = 0, it indicates that the coalesce has not ended and the subsequent request needs to be waited for coalesce; if the collect_finish_flag = 1, it indicates that the coalesce has ended.

[0075] In some embodiments, in addition to carrying the request address, the request information sent by the first-level coalesce device to the second-level coalesce device can also carry an end identifier. The end identifier (end_of_instruction) is used to identify whether the second-level coalesce device ends the coalesce of the request; when the second-level coalesce device receives the end_of_instruction == 1 of 1 request (assuming 1 as the end identifier), it will stop coalesce even if some requests may not be coalesced to N * R length.

[0076] One instruction can correspond to multiple read requests or write requests, but the type of multiple requests corresponding to one instruction is the same. One coherent request is one instruction, which corresponds to 1 cycle on the interface; the last request of one instruction carries an end identifier (end_of_instruction == 1). The request received by the second-level coalesce device from the first-level coalesce device is in order, that is, after encountering the end_of_instruction == 1 of one instruction, the type of request can be switched. The noise request sent by the disturbance module can be inserted into any position of the entry request of the second-level coalesce device, and one noise request corresponds to one cycle (1 cycle). The noise request inserted will not affect the coalesce of the write / read request; at the same time, at the outlet of the second-level coalesce device, the noise request is not inserted into the middle of multiple beats of one write request.

[0077] If the newly received request does not belong to the same N * R range as the request in the previous buffer, the request in the previous buffer stops coalescing, and the collect_finish_flag corresponding to the previous request is set to 1. If the newly received request in the buffer belongs to the same N * R range as the request in the previous buffer, the collect_finish_flag is maintained as 0; if the end_of_instruction of the newly received request in the buffer is 1, it indicates that the instruction ends, and coalescing is stopped, at which time the collect_finish_flag of the request and the previous request in the buffer is set to 1.

[0078] After the secondary merging device entrance receives a request, if it is a write request, it is pushed into the write request merging area (write cmd coalesce buffer) and recorded in the order table; if the write request merging area (write cmd coalesce buffer) is full, the secondary merging device entrance is blocked. If it is a read request, it is pushed into the read request merging area (Read cmd coalesce buffer) and recorded in the order table; if the read request merging area (Read cmd coalesce buffer) is full, the secondary merging device entrance is blocked. If it is a coherent request, it is pushed into the other cmd coalesce buffer and recorded in the order table; if the other cmd buffer is full, the secondary merging device entrance is blocked.

[0079] If it is a noise request, it needs to be sent to the downstream module based on the empty / full condition of the secondary merging area corresponding to the original request (for a specific description of the request merging method below).

[0080] Specifically, if it is a noise request, the collect_finish_flag of all requests in the corresponding write request merging area (write cmd coalesce buffer) / read request merging area (Read cmd coalesce buffer) is checked.

[0081] 1. If there is a request with collect_finish_flag == 0 in these requests, then this noise request is likely to be inserted into the write / read request of the same N * R length multi-beat. Since the noise request and the coherent request of the main branch have the order requirement, at this time, the other cmd buffer and the order table are checked,

[0082] a) If the other cmd buffer is not empty, block the secondary merging device entrance, wait for the other cmd buffer to be empty, and the request corresponding to collect_finish_flag == 1 in the order table has been popped (removed from the secondary merging device to the downstream module), then bypass the noise request to the secondary merging device exit, at the same time, release the secondary merging device entrance to allow receiving new requests. This noise request is not recorded in the order table.

[0083] b) If the other cmd buffer is empty, but the request corresponding to collect_finish_flag == 1 in the order table has not been popped completely, block the secondary merging device entrance, wait for the request corresponding to collect_finish_flag == 1 in the order table to be popped completely, then bypass the noise request to the secondary merging device exit. In this scenario, the noise request is not recorded in the order table.

[0084] c) If the other cmd buffer is empty and the request corresponding to collect_finish_flag == 1 in the order table has been popped, then bypass the noise request to the secondary merging device exit. In this scenario, the noise request is not recorded in the order table.

[0085] 2. If all the collect_finish_flag of the requests in the write cmd coalesce buffer and the read cmd coalesce buffer are 1, the noise request enters the other cmd buffer, and is recorded in the order table. If the other cmd buffer is full, the secondary coalescing device entrance is blocked.

[0086] The embodiment of the present disclosure provides a request processing method, which can be applied to a request processing system. As shown in the figure, the method comprises the following steps 401 to 403: Figure 4

[0087] Step 401: One-level coalescing is performed on a plurality of original requests of a to-be-processed instruction to obtain a plurality of one-level coalesced requests.

[0088] The to-be-processed instruction refers to the instruction that needs to be processed at present. One instruction can correspond to a plurality of original requests. The original request can be a read request or a write request. The one-level coalesced request refers to the request after one-level coalescing. One-level coalescing is used to coalesce the request smaller than R (byte) Byte into the request of R Byte granularity; wherein the request smaller than R byte is the original request, and the request of R Byte granularity is the first coalesced request.

[0089] In some embodiments, the specific implementation of step 401 can be: one-level coalescing is performed on a plurality of original requests of a to-be-processed instruction based on a first coalescing granularity to obtain a plurality of one-level coalesced requests. Specifically, the one-level coalescing device can be used to perform one-level coalescing on a plurality of original requests of a to-be-processed instruction based on a first coalescing granularity. The first coalescing granularity can reflect the address length of the one-level coalesced request, for example: the first coalescing granularity can be R Byte.

[0090] In a feasible implementation, the one-level coalescing device can be used to coalesce the original requests with addresses in the same cache line to obtain a plurality of one-level coalesced requests. The size of the cache line is equal to the granularity of one-level coalescing.

[0091] In another feasible implementation, the one-level coalescing device can be used to cache the original requests with smaller address length in order according to the arrival order to the cache line (the size of the cache line is R Byte) of the one-level coalescing device. In this way, one cache line corresponds to one one-level coalesced request of R Byte. Here, the arrival order refers to the order of the original request arriving at the one-level coalescing device. ​

[0092] Step 402, performing secondary merging on the plurality of the primary merging requests to obtain a plurality of secondary merging requests, and issuing the secondary merging requests to a downstream module to enable the downstream module to perform operations corresponding to the plurality of the secondary merging requests; the granularity of the secondary merging is greater than the granularity of the primary merging.

[0093] The secondary merging request refers to a request after secondary merging. The secondary merging is used to merge R Byte granularity requests into R*N Byte (N>1) granularity requests.

[0094] In some embodiments, a specific implementation of step 402 can be: performing secondary merging on the primary merging requests based on a second merging granularity to obtain a plurality of secondary merging requests. Specifically, the secondary merging can be performed on the primary merging requests based on the second merging granularity by a secondary merging device. The second merging granularity can reflect the address length of the secondary merging request, for example: the second merging granularity can be R*N Byte.

[0095] In a feasible implementation, the secondary merging device can perform secondary merging on the primary merging requests based on the second merging granularity according to the arrival order of the primary merging requests. Here, the arrival order refers to the order of the primary merging requests arriving at the secondary merging device.

[0096] For example, the primary merging requests are sequentially cached to the cache line (here, the size of the cache line is R*N Byte) of the secondary merging device according to the determined order of the primary merging requests, so that one cache line corresponds to one R*N Byte secondary merging request.

[0097] Step 403, when a disturbance request is received during the secondary merging, determining whether to interpose the disturbance request into the secondary merging requests based on the fullness of the secondary merging area corresponding to the original request, and issuing the disturbance request to the downstream module to enable the downstream module to perform operations corresponding to the disturbance request; the secondary merging area is used to cache a plurality of the primary merging requests to the cache layer according to the determined order of the primary merging requests.

[0098] The secondary merging area corresponding to the original request is determined based on the type of the original request. If the original request is a read request, the fullness of the secondary merging area corresponding to the original request refers to the fullness of the read request merging area; if the original request is a write request, the fullness of the secondary merging area corresponding to the original request refers to the fullness of the write request merging area. The fullness refers to whether the cache layer of the merging area is full of data.

[0099] In some embodiments, the specific implementation of step 403 can be: in the case that there is a cache layer in the secondary merging area corresponding to the original request that has not completed request merging, interpose the disturbance request into the secondary merging request and send it to the downstream module; in the case that all cache layers in the secondary merging area corresponding to the original request have completed request merging, send the disturbance request to the downstream module through an additional cache area.

[0100] In the embodiments of the present disclosure, when a disturbance request is received in the process of secondary merging, it is determined whether to interpose the disturbance request into the secondary merging request and send it to the downstream module based on the fullness of the secondary merging area corresponding to the original request. In this way, in the case of a disturbance request and a main branch request, the disturbance request can be sent to the downstream module in different ways based on the fullness of the secondary merging area corresponding to the original request, while ensuring that the requests of the main branch are in order and the requests of the disturbance branch are in order with the requests of the main branch, thereby ensuring that the secondary merging device can achieve better performance in any mode.

[0101] The embodiments of the present disclosure provide a request processing method, which can be applied to a request processing system. As shown in Figure 5 The method comprises the following steps 501 to 505:

[0102] Step 501: primary merging is performed on a plurality of original requests of to-be-processed instructions to obtain a plurality of primary merging requests.

[0103] Here, the above step 501 corresponds to the aforementioned step 401, and in implementation, the specific implementation of the aforementioned step 401 can be referred to.

[0104] Step 502: secondary merging is performed on the plurality of primary merging requests to obtain a plurality of secondary merging requests, and the secondary merging requests are sent to a downstream module to enable the downstream module to perform operations corresponding to the plurality of secondary merging requests; the granularity of the secondary merging is greater than the granularity of the primary merging.

[0105] Here, the above step 502 corresponds to the aforementioned step 402, and in implementation, the specific implementation of the aforementioned step 402 can be referred to.

[0106] Step 503: when a disturbance request is received in the process of secondary merging, a secondary merging area corresponding to the original request is determined; the secondary merging area is used to cache a plurality of primary merging requests to a cache layer in the determined order of the primary merging requests.

[0107] The secondary merging area refers to a merging area used for secondary merging of original requests.

[0108] In some embodiments, the specific implementation of step 503 can be: determining the secondary merge area corresponding to the original request based on the type of the original request.

[0109] In some embodiments, the specific implementation of step 503 can be: in the case that the type of the original request is a read type, taking the read request merge area as the secondary merge area; in the case that the type of the original request is a write type, taking the write request merge area as the secondary merge area.

[0110] Step 504: in the case that the secondary merge area has a cache layer with uncompleted request merging, interposing the disturbance request into the secondary merge request based on whether the additional cache area is empty and the issue of the target secondary merge request corresponding to the cache layer with completed request merging in the secondary merge area, and then issuing the disturbance request to the downstream module; the additional cache area is used to cache requests other than read requests and write requests.

[0111] In some embodiments, since each cache layer of the secondary merge area corresponds to a merge identifier (collect_finish_flag), the presence of a cache layer with uncompleted request merging in the secondary merge area can be determined according to the identifier value of the merge identifier of the secondary merge area. Specifically, if the identifier value of the merge identifier of the secondary merge area is a first identifier value (such as 0), it is determined that the secondary merge area has a cache layer with uncompleted request merging; if the identifier value of the merge identifier of the secondary merge area is a second identifier value (such as 1), it is determined that the secondary merge area does not have a cache layer with uncompleted request merging.

[0112] Case one, the specific implementation of step 504 can be: in the case that the additional cache area is not empty, suspending the operation of the secondary merge; in the case that the requests in the additional cache area and the target secondary merge request are all issued to the downstream module, issuing the disturbance request to the downstream module and continuing the operation of the secondary merge.

[0113] Suspending the operation of the secondary merge means blocking the entrance of the secondary merge device, i.e. no longer receiving the primary merge request. The requests in the additional cache area and the target secondary merge request being all issued to the downstream module means that the other cmdbuffer is empty and the requests corresponding to collect_finish_flag == 1 in the order table have all been popped.

[0114] Specifically, if the coalesce buffer corresponding to the original request exists a cache line with collect_finish_flag == 0, and the other cmd buffer is not empty, the entrance of the secondary coalescing device is blocked, and after the other cmd buffer is empty and the requests corresponding to collect_finish_flag == 1 in the order table are all popped, the noise request is bypassed to the exit of the secondary coalescing device, and at the same time, the entrance of the secondary coalescing device is released to allow receiving new requests. In this way, the noise request is interleaved between the secondary coalescing requests, and then sent to the downstream module, and the order of the main branch requests is ensured.

[0115] In case two, the specific implementation of step 504 can be: in the case that the additional cache area is empty, but the target secondary coalescing requests are not all sent to the downstream module, suspending the operation of the secondary coalescing; in the case that the target secondary coalescing requests are all sent to the downstream module, sending the noise request to the downstream module and continuing the operation of the secondary coalescing.

[0116] Specifically, if the coalesce buffer corresponding to the original request exists a cache line with collect_finish_flag == 0, and the other cmd buffer is empty, but the requests corresponding to collect_finish_flag == 1 in the order table are not all popped, the entrance of the secondary coalescing device is blocked, and after the requests corresponding to collect_finish_flag == 1 in the order table are all popped, the noise request is bypassed to the exit of the secondary coalescing device. At the same time, the entrance of the secondary coalescing device is released to allow receiving new requests. In this way, the noise request is interleaved between the secondary coalescing requests, and then sent to the downstream module, and the order of the main branch requests is ensured.

[0117] As shown in FIG. 6(a), if the noise request is not sent to the downstream module through the bypass path in the above case one, the request pattern of the secondary coalescing device exit is that the noise request is interleaved between the multiple beats of 1 read or write request, and the secondary coalescing device exit is back-pressured for 3 beats. As shown in FIG. 6(b), if the noise request is not sent to the downstream module through the bypass path in the above case two, the secondary coalescing device entrance is back-pressured.

[0118] The reason why the first and second cases send the noise request to the downstream module through the bypass path instead of pushing it into the other cmd buffer is that the order table must be popped in order, and there are already some requests in the order table that have not been completed coalesced. At this time, if the noise request is pushed into the other cmd buffer (the implicit step is to record in the order table), it will cause the request pattern at the exit of the secondary merging device to be noise requests inserted into the multi-beat of 1 read or write request, which is not allowed. If the inserted noise request exceeds 5, it will also cause a deadlock problem: the noise request will fill the other cmd buffer, blocking the entrance of the secondary merging device, and the previous incomplete coalesced request will always wait for the subsequent request, and the order table will always be released, resulting in a deadlock.

[0119] The third case, the specific implementation of step 504 can be: in the case that the additional cache area is empty, and the target secondary merging request is all issued to the downstream module, the disturbance request is issued to the downstream module, and the operation of the secondary merging is continued.

[0120] Specifically, if the original request corresponds to a coalesce buffer with collect_finish_flag == 0 cache line, and the other cmd buffer is empty, and the collect_finish_flag == 1 corresponding request in the order table has been popped, the noise request is bypassed to the exit of the secondary merging device.

[0121] As shown in FIG. 6(c), if the third case does not send the noise request to the downstream module through the bypass path, the secondary merging device exit appears empty.

[0122] It should be noted that case one, case two and case three are bypassing the noise request to the exit of the secondary coalescing device directly in the case that the additional cache area is empty and the target secondary coalescing request is all issued to the downstream module, so as to ensure that the noise request inserted will not affect the request coalescing and order preserving of the main branch, and at the same time ensure that the noise request will not be inserted into the middle of the multi-beat of 1 write request. In addition, the noise request processed in case one, case two and case three is not recorded in the order table.

[0123] In step 505, in the case that the cache layer of the secondary coalescing area has completed request coalescing, but there is free space in the additional cache area, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to issue the disturbance request to the downstream module based on the arrival order of the disturbance request.

[0124] The cache layer of the secondary coalescing area has completed request coalescing, which means that the disturbance request cannot be inserted into the secondary coalescing request for issuance, and therefore the issuance of the disturbance request is performed through the additional cache area. Since the additional cache area is also used to cache coherent requests, and the coherent request has order preserving requirement, the arrival order of the disturbance request needs to be recorded in the order storage area, so as to issue the disturbance request to the downstream module according to the arrival order of the disturbance request.

[0125] It should be noted that, as shown in FIG. 6(c), in the case that the cache layer of the secondary coalescing area has completed request coalescing, but there is free space in the additional cache area (case four), the bypass path can be continued by waiting for the additional cache area (othercmdcoalesce buffer) to be empty, as in case one and case two, but this will cause back pressure at the entrance of the secondary coalescing device, resulting in performance degradation. Issuing the disturbance request through the additional cache area will not affect the processing of the main branch request, so as to achieve the issuance of the disturbance request.

[0126] In step 506, in the case that the cache layer of the secondary coalescing area has completed request coalescing, and there is no free space in the additional cache area, the operation of the secondary coalescing is suspended.

[0127] In step 507, in the case that the requests in the secondary coalescing area and the additional cache area are all issued to the downstream module, the disturbance request is issued to the downstream module, and the operation of the secondary coalescing is continued.

[0128] Based on the foregoing embodiments, the request processing method provided by the embodiments of the present disclosure further includes the following steps 508 to 510:

[0129] Step 508: In the case that the new acquired first-level merge request and the request of the second-level merge area corresponding to the original request belong to the same granularity of the second-level merge, the merge identifier of the cache layer of the second-level merge area is kept as a first identifier value; the first identifier value represents that the request merging of the corresponding cache layer is not completed.

[0130] Step 509: In the case that the new acquired first-level merge request and the request of the second-level merge area do not belong to the same granularity of the second-level merge, the merge identifier of the cache layer of the second-level merge area is set as a second identifier value; the second identifier value represents that the request merging of the corresponding cache layer is completed.

[0131] Step 510: In the case that a first-level merge request carrying an end identifier is received, the merge identifier of the cache layer of the second-level merge area is set as a second identifier value; the second identifier value represents that the request merging of the corresponding cache layer is completed; the end identifier is used to represent the end of the request merging of the to-be-processed instruction.

[0132] In the embodiments of the present disclosure, when a disturbance request is received in the process of the second-level merge, based on the empty or full condition of the second-level merge area corresponding to the original request, it is determined whether to interpose the disturbance request into the second-level merge request and then send it to the downstream module. In this way, in the case that there is a disturbance request and a main branch request, based on the empty or full condition of the second-level merge area corresponding to the original request, the disturbance request can be sent to the downstream module in different ways, while ensuring that the requests of the main branch are in order and the requests of the disturbance branch are in order with the requests of the main branch, thereby ensuring that the second-level merge device can achieve better performance in any mode, and in such a scenario, N write requests, at least N coherent or noise requests, and N write requests also ensure that the second-level merge device output request does not appear to be interrupted.

[0133] The application of the request processing method provided by the embodiments of the present disclosure in an actual scenario is described below.

[0134] In the request information sent by the first-level merge module (corresponding to the above-mentioned first-level merge device) to the second-level merge module (corresponding to the above-mentioned second-level merge device), in addition to the request address, there is an end identifier (end_of_instruction), which is used to identify whether the second-level merge module ends the request merging of the current instruction or switches the request type. When the second-level merge module receives 1 request end_of_instruction==1, even if some requests may not be merged into N*R length, it will stop merging.

[0135] One instruction can correspond to multiple A to B read or write requests, and the request type corresponding to one instruction is the same. A coherent request is one instruction, which corresponds to 1 cycle on the interface; the last request of one instruction carries end_of_instruction == 1. The request received by the secondary coalescing module from the primary coalescing module is in order, that is, it is necessary to encounter end_of_instruction == 1 of one instruction before the request type can be switched. The noise request sent by the disturbance module can be inserted into any position of the secondary coalescing module entrance request, and one noise request corresponds to 1 cycle (1 cycle). The noise request inserted will not affect the coalesce of the write / read request. At the same time, it is expected that at the outlet of the secondary coalescing module, the noise request will not be inserted into the middle of multiple beats of one write request.

[0136] In the secondary coalescing module, a write request coalescing area (Write cmd coalesce buffer) is set, and the depth is set to N+1. The depth N corresponds to the coalescing granularity R*N Byte of the secondary coalescing module, that is, N write requests from the primary coalescing module can be coalesced into one write request; +1 is to receive the continuous write request scenario sent by the primary coalescing module, so as not to back pressure the primary coalescing module.

[0137] In the secondary coalescing module, a read request coalescing area (Read cmd coalesce buffer) is set, and the depth is set to N+1. The depth N corresponds to the coalescing granularity R*N Byte of the secondary coalescing module, that is, N read requests from the primary coalescing module can be coalesced into one read request; +1 is to receive the continuous read request scenario sent by the primary coalescing module, so as not to back pressure the primary coalescing module.

[0138] Each layer of the write request coalescing area (Write cmd coalesce buffer) and the read request coalescing area (Read cmd coalesce buffer) corresponds to a coalescing identifier (collect_finish_flag) of 1 bit, which is used to identify whether the request of the layer has completed coalescing, and the initial value is 0 (assuming that 0 indicates that coalescing has not ended and needs to wait for subsequent requests to coalesce together).

[0139] The write request coalescing area (Write cmd coalesce buffer) and the read request coalescing area (Read cmd coalesce buffer) are respectively responsible for second-level coalescing of write requests and read requests, and coalescing of R byte length requests into N * R bytes; since it is second-level coalescing, the coalescing function is simplified to only coalesce the continuously received requests, and once a newly received request does not belong to the same N * R range as the request in the previous buffer, the coalescing of the request in the previous buffer stops, and the collect_finish_flag corresponding to the previous request is set to 1. If the newly received request in the buffer belongs to the same N * R range as the request in the previous buffer, the collect_finish_flag is kept as 0; if the newly received request in the buffer has end_of_instruction == 1, it indicates that the instruction ends and coalescing stops, at this time the collect_finish_flag of the request and the request in the buffer is set to 1.

[0140] In the second-level coalescing module, an additional buffer area (other cmd coalesce buffer) is set for buffering coherent requests and noise requests, and the depth is set to N + 1. In this scenario: N write requests, at least N coherent or noise requests, N write requests, if the exit request of the second-level coalescing module is to be ensured not to appear broken, the depth of the additional buffer area (other cmd coalesce buffer) must be set to at least N + 1.

[0141] As shown in FIG. 3(a), assuming N = 4, if the depth of the additional cache area (other cmd coalesce buffer) is set to 5, the above-mentioned scenario can be encountered, and it can be ensured that the exit of the secondary coalescing module is continuous; as shown in FIG. 3(b), if the depth of the additional cache area (other cmd coalesce buffer) is set to 2, the secondary coalescing module entrance will be blocked (back pressure of the entrance) for 3 beats due to fullness of the cmd coalesce buffer in the above-mentioned scenario, and thus the secondary coalescing module exit request will also have 3 beats of null (as shown in the figure). Among them, the write request beats 0 / 1 / 2 / 3 are 4 beats of write request belonging to the same N * R length, which can form one piece of N * R length request.

[0142] In the secondary coalescing module, an order storage area (order table) is set to record the order (arrival order) of the secondary coalescing module entrance request, and the depth is 3N + 3. The types of the requests received by the secondary coalescing module entrance include write request, read request, coherent request, and noise request. The internal storage of each layer of the order storage area (order table) is 2-bit request type, which is used to mark the four types of request.

[0143] After the secondary coalescing module entrance receives one piece of request, if it is a write request, it is pushed into the write cmd coalesce buffer and recorded in the order storage area (order table); if the write cmd coalesce buffer is full, the secondary coalescing module entrance is blocked. If it is a read request, it is pushed into the read request coalescing area (Read cmd coalesce buffer) and recorded in the order storage area (order table); if the order storage area is full, the secondary coalescing module entrance is blocked. If it is a coherent request, it is pushed into the additional cache area (other cmd coalesce buffer) and recorded in the order storage area (order table); if the additional cache area (other cmd coalesce buffer) is full, the secondary coalescing module entrance is blocked.

[0144] If it is a noise request, special processing is required. First, check the collect_finish_flag of all requests in the write request coalescing area (Write cmd coalesce buffer) and the read request coalescing area (Read cmd coalesce buffer):

[0145] 1. If it is found that there is a coalescing identifier collect_finish_flag == 0 among these requests, then this noise is very likely to be inserted between the write / read requests belonging to the same N * R length multi-beat. Since the noise request and the coherent request of the main branch have the order preserving requirement, at this time, the other cmd buffer and the order table are checked.

[0146] a) (case one) If the additional buffer (other cmd coalesce buffer) is not empty, block the secondary coalescing module entrance, wait for the additional buffer (other cmd coalesce buffer) to be empty, and the coalescing identifier collect_finish_flag == 1 corresponding request in the order storage area (order table) has been popped, then bypass the noise request to the secondary coalescing module exit, at the same time, release the secondary coalescing module entrance, allow to receive new requests. This noise request is not recorded in the order table.

[0147] b) (case two) If the additional buffer (other cmd coalesce buffer) is empty but the coalescing identifier collect_finish_flag == 1 corresponding request in the order storage area (order table) has not been popped completely, block the secondary coalescing module entrance, wait for the coalescing identifier collect_finish_flag == 1 corresponding request in the order storage area (order table) to be popped completely, then bypass the noise request to the secondary coalescing module exit. This noise request is not recorded in the order table.

[0148] c) If the other cmd coalesce buffer is empty and all requests in the order table corresponding to collect_finish_flag == 1 have been popped, then bypass the current noise request to the exit of the second level coalesce module. The current noise request is not recorded in the order table.

[0149] 2) If all requests in the write cmd coalesce buffer and the read cmd coalesce buffer have collect_finish_flag == 1, then the current noise request enters the other cmd coalesce buffer and is recorded in the order table. If the other cmd coalesce buffer is full, then the entrance of the second level coalesce module is blocked.

[0150] The bypass of the noise request to the downstream in steps 1.a and 1.b is because the order table must be popped in order and there are some requests in the order table that have not been coalesced. If the noise request is pushed into the other cmd coalesce buffer (which implies recording in the order table), then the request pattern at the exit of the second level coalesce module will be noise requests interleaved in the multi-beat of one read or write request, which is not allowed. If the number of interleaved noise requests exceeds 5, then a deadlock problem will occur: the noise request will fill the other cmd coalesce buffer, the entrance of the second level coalesce module will be blocked, the preceding requests that have not been coalesced will wait for the following requests, the order table will not be released, and a deadlock will occur.

[0151] The step 2 above can also wait for the other cmd coalesce buffer to be empty as in 1.a / 1.b, and continue to walk the bypass path, but this will cause back pressure to the secondary coalesce module entry, causing some performance degradation.

[0152] The protection points of the embodiments of the present disclosure include at least:

[0153] 1. In the secondary coalesce module, a write request coalesce buffer (Write cmd coalesce buffer) is set, and the depth is set to N+1.

[0154] 2. In the secondary coalesce module, a read request coalesce buffer (Read cmd coalesce buffer) is set, and the depth is set to N+1.

[0155] 3. The write request coalesce buffer (Write cmd coalesce buffer) and the read request coalesce buffer (Read cmd coalesce buffer) each correspond to 1 bit of collect_finish_flag, which is used to identify whether the request of the layer has completed the coalesce.

[0156] 4. The write request coalesce buffer (Write cmd coalesce buffer) and the read request coalesce buffer (Read cmd coalesce buffer) are responsible for the secondary coalesce of the write / read request, and the R byte length request is coalesced to N*R byte. Since it is the secondary coalesce, the coalesce can be simplified to only coalesce the continuously received request. Once the newly received request does not belong to the same N*R range as the request in the buffer, the request in the buffer stops coalesce, and the coalesce identifier collect_finish_flag corresponding to the previous request in the buffer is set to 1. If the newly received request in the buffer belongs to the same N*R range as the request in the buffer, the collect_finish_flag is maintained as 0. If the end identifier end_of_instruction of the newly received request in the buffer is 1, it indicates that the instruction ends, and the coalesce is stopped. At this time, the collect_finish_flag of the request and the previous request in the buffer is set to 1.

[0157] 5. In the second level coalesce module, an additional buffer (other cmd coalesce buffer) is set up to buffer coherent request and noise request, and its depth is set to N + 1.

[0158] 6. In the second level coalesce module, an order table is set up to record the order of the requests received by the second level coalesce module, and its depth is 3N + 3. The types of the requests received by the second level coalesce module include write request, read request, coherent request and noise request. The internal storage of each layer of the order table is 2-bit request type, which is used to mark the four types of requests.

[0159] 7. After the second level coalesce module receives a request, if it is write request, it is pushed into the write request coalesce buffer and recorded in the order table. If the write request coalesce buffer is full, the second level coalesce module is blocked. If it is read request, it is pushed into the read request coalesce buffer and recorded in the order table. If the read request coalesce buffer is full, the second level coalesce module is blocked. If it is coherent request, it is pushed into the other cmd coalesce buffer and recorded in the order table. If the other cmd coalesce buffer is full, the second level coalesce module is blocked.

[0160] 8、After the 2nd coalesce module entry receives a request, if it is a noise request, special handling is needed. First, check the coalesce flags (collect_finish_flag) of all requests in the write request coalesce buffer and the read request coalesce buffer. If a request with collect_finish_flag == 0 is found, it is very likely that the noise request is interleaved in the middle of a multi-beat write / read request with N * R length. Since the noise request and the coherent request of the main branch have sequential requirements, check the other cmd buffer and the order table at this time.

[0161] a) If the additional buffer (other cmd coalesce buffer) is not empty, block the 2nd coalesce module entry, wait until the additional buffer (other cmd coalesce buffer) is empty and the requests corresponding to collect_finish_flag == 1 in the order storage area (order table) have all been popped, then bypass the noise request to the 2nd coalesce module exit, and at the same time, release the 2nd coalesce module entry to allow the reception of new requests. In this scenario, the noise request is not recorded in the order table.

[0162] b) If the additional buffer (other cmd coalesce buffer) is empty but the requests corresponding to collect_finish_flag == 1 in the order storage area (order table) have not all been popped, block the 2nd coalesce module entry, wait until the requests corresponding to collect_finish_flag == 1 in the order storage area (order table) have all been popped, then bypass the noise request to the 2nd coalesce module exit. In this scenario, the noise request is not recorded in the order table.

[0163] c) If the other cmd coalesce buffer is empty and all requests in the order table with collect_finish_flag == 1 have been popped, then the current noise request is bypassed to the exit of the second level coalescing module. The current noise request is not recorded in the order table.

[0164] 9) After the second level coalescing module entry receives a request, if it is a noise request, and all requests in the write cmd coalesce buffer and the read cmd coalesce buffer have collect_finish_flag == 1, then the current noise request enters the other cmd coalesce buffer, and is recorded in the order table. If the other cmd coalesce buffer is full, the second level coalescing module entry is blocked.

[0165] It should be noted that, in the embodiments of the present disclosure, if the request processing method described above is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product in essence or the part that contributes to the related art, which is stored in a storage medium, includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods described in the embodiments of the present disclosure. The storage medium mentioned above includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various program code storage media. Thus, the embodiments of the present disclosure are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0166] The embodiments of the present disclosure provide a computer device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0167] The computer readable storage medium can be transitory or non-transitory.

[0168] The computer program includes computer readable code, and when the computer readable code runs in a computer device, a processor in the computer device performs part or all steps of the above method.

[0169] The computer program product includes a non-transitory computer readable storage medium storing a computer program, and when the computer program is read and executed by a computer, part or all steps of the above method are implemented. The computer program product can be implemented by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) or the like.

[0170] It should be noted that the above description of various embodiments tends to emphasize the differences between various embodiments, and the same or similar parts can be mutually referred to. The above description of the device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the device, storage medium, computer program and computer program product embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure.

[0171] It should be noted that, Figure 7 A hardware entity of a computer device in an embodiment of the present disclosure is shown in FIG. 7, which includes a processor 701, a communication interface 702 and a memory 703, wherein: Figure 7 The processor 701 generally controls the overall operation of the computer device 700.

[0172] The processor 701 generally controls the overall operation of the computer device 700.

[0173] The communication interface 702 can enable the computer device to communicate with other terminals or servers through a network.

[0174] The memory 703 is configured to store instructions and application programs executable by the processor 701, and can also cache data (for example, image data, audio data, voice communication data, and video communication data) to be processed by the processor 701 and modules in the computer device 700. The memory 703 can be implemented by FLASH or Random Access Memory (RAM). The processor 701, the communication interface 702, and the memory 703 can transmit data through the bus 704.

[0175] It should be understood that every feature, structure, or characteristic mentioned herein in relation to an embodiment can be combined with any other feature, structure, or characteristic mentioned herein in relation to another embodiment. It should be understood that the size and order of the above-described steps / processes do not mean the order of execution, and the execution order of the steps / processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned sequence number of the embodiments of the present disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0176] It should be understood that the terms "comprise", "comprising", or any other variant thereof, are intended to encompass non-exclusive inclusion, such that processes, methods, articles, or devices that comprise a list of elements do not necessarily include only those elements in the list, but can also include other elements not expressly listed, or inherent to such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element.

[0177] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative. For example, the division of the units is merely a logical function division, and actual implementation can have another division manner. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or in other forms.

[0178] The units described as separate components above can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0179] In addition, each functional unit in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional units.

[0180] Those skilled in the art can understand that all or part of the steps of the above method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps including the above method embodiments when executed; and the foregoing storage medium includes mobile storage devices, read only memory (Read Only Memory, ROM), magnetic discs or optical discs, and various storage medium that can store program codes.

[0181] Alternatively, the integrated units of the present disclosure, if implemented in the form of software functional modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present disclosure. The foregoing storage medium includes mobile storage devices, ROM, magnetic discs or optical discs, and various storage medium that can store program codes.

[0182] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A request processing method characterized by comprising: The request processing method comprises: performing primary merging on a plurality of original requests of to-be-processed instructions to obtain a plurality of primary merging requests; performing secondary merging on the plurality of primary merging requests to obtain a plurality of secondary merging requests, and issuing the secondary merging requests to a downstream module, so that the downstream module performs operations corresponding to the secondary merging requests; the granularity of the secondary merging is greater than that of the primary merging; when a disturbance request is received in the process of the secondary merging and there is a cache layer of uncompleted request merging in a secondary merging area corresponding to the original request, the disturbance request is interposed into the secondary merging requests and then issued to the downstream module, so that the downstream module performs an operation corresponding to the disturbance request; the secondary merging area is used to cache the plurality of primary merging requests to cache layers in a determined order of the primary merging requests.

2. The request processing method according to claim 1, characterized by, The method of interposing the disturbance request into the secondary merging requests and then issuing the secondary merging requests to the downstream module when the disturbance request is received in the process of the secondary merging and there is a cache layer of uncompleted request merging in a secondary merging area corresponding to the original request comprises: determining the secondary merging area corresponding to the original request; in a case where there is a cache layer of uncompleted request merging in the secondary merging area, interposing the disturbance request into the secondary merging requests and then issuing the secondary merging requests to the downstream module based on whether an additional cache area is empty or non-empty and a situation of issuing a target secondary merging request corresponding to a cache layer of completed request merging in the secondary merging area; the additional cache area is used to cache requests other than read requests and write requests.

3. The request processing method according to claim 2, characterized by, The method of determining the secondary merging area corresponding to the original request comprises: in a case where the type of the original request is a read type, taking a read request merging area as the secondary merging area; in a case where the type of the original request is a write type, taking a write request merging area as the secondary merging area.

4. The request processing method according to claim 2, characterized by, The method of interposing the disturbance request into the secondary merging requests and then issuing the secondary merging requests to the downstream module based on whether the additional cache area is empty or non-empty and the situation of issuing the target secondary merging request corresponding to the cache layer of completed request merging in the secondary merging area comprises: in a case where the additional cache area is non-empty, suspending the operation of the secondary merging; in a case where the request in the additional cache area and the target secondary merging request are both issued to the downstream module, issuing the disturbance request to the downstream module and continuing the operation of the secondary merging.

5. The request processing method according to claim 2, characterized by, The method of interposing the disturbance request into the secondary merging requests and then issuing the secondary merging requests to the downstream module based on whether the additional cache area is empty or non-empty and the situation of issuing the target secondary merging request corresponding to the cache layer of completed request merging in the secondary merging area comprises: in a case where the additional cache area is empty but the target secondary merging request is not all issued to the downstream module, suspending the operation of the secondary merging; in a case where the target secondary merging request is all issued to the downstream module, issuing the disturbance request to the downstream module and continuing the operation of the secondary merging.

6. The request processing method according to claim 2, characterized by, The disturbance request is inserted into the secondary merge request and then sent to the downstream module, including: In the case that the additional cache area is empty and the target secondary merge request is sent to the downstream module, the disturbance request is sent to the downstream module and the secondary merge operation is continued.

7. The request processing method according to claim 2, characterized by, The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request.

8. The request processing method according to claim 2, characterized by, The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request. The request processing method further includes:

9. The request processing method according to any one of claims 1 to 8, characterized by, In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request. The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request.

10. The request processing method according to any one of claims 1 to 8, characterized by, The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request.

11. A two-stage combining device, characterized by The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request. The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request. The request processing method further includes: In the case that the cache layer of the secondary merge area has completed request merging, but the additional cache area has free space, the disturbance request is stored in the additional cache area, and the arrival order of the disturbance request is recorded in the order storage area, so as to send the disturbance request to the downstream module based on the arrival order of the disturbance request. The secondary merge device includes: A secondary merge area is used to cache a plurality of primary merge requests to a cache layer in a determined order to implement secondary merge of a plurality of primary merge requests, and obtain a plurality of secondary merge requests; a plurality of primary merge requests are obtained by performing primary merge on a plurality of original requests of a to-be-processed instruction, and the granularity of the secondary merge is greater than the granularity of the primary merge; An additional cache area is used to cache other requests except read requests and write requests; An order storage area is used to record the order of requests arriving at the secondary merge device; The secondary merge device is used to send a plurality of secondary merge requests to a downstream module, so that the downstream module performs operations corresponding to the plurality of secondary merge requests; and The secondary merge device is used to send a plurality of secondary merge requests to a downstream module, so that the downstream module performs operations corresponding to the plurality of secondary merge requests. In a case that a disturbance request is received in the process of the secondary merging and a cache layer of the secondary merging area exists which has not completed request merging, the secondary merging device is further configured to insert the disturbance request into the secondary merging request, and send the secondary merging request to the downstream module, so that the downstream module performs an operation corresponding to the disturbance request.

12. The secondary merging device of claim 11, wherein, in a case that the type of the original request is a read type, the secondary merging area is a read request merging area; in a case that the type of the original request is a write type, the secondary merging area is a write request merging area; the read request merging area is configured to perform secondary merging on the primary merging request of the read type; the write request merging area is configured to perform secondary merging on the primary merging request of the write type; a depth of the cache layer of the read request merging area, the write request merging area and the additional cache area is related to a number of primary merging requests that the secondary merging device can receive at a time and a number threshold; a depth of the order storage area is a sum of depths of the read request merging area, the write request merging area and the additional cache area.

13. A request processing system characterized by comprising: The request processing system comprises: a primary merging device configured to perform primary merging on a plurality of original requests of to-be-processed instructions to obtain a plurality of primary merging requests; a secondary merging device configured to perform secondary merging on the plurality of primary merging requests to obtain a plurality of secondary merging requests; in a case that a disturbance request is received in the process of the secondary merging and a cache layer of the secondary merging area exists which has not completed request merging, the secondary merging device is further configured to insert the disturbance request into the secondary merging request, and send the secondary merging request to the downstream module, so that the downstream module performs an operation corresponding to the disturbance request. a downstream module configured to perform an operation corresponding to the plurality of secondary merging requests to implement processing on the to-be-processed instructions.

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