Data reading and writing method, system, device and storage medium

Abstract

The application relates to the field of data processing, and provides a data read-write method, a data read-write system, a data read-write device and a storage medium. The method comprises the following steps: obtaining a read-write type of a data read-write instruction; when the read-write type is a read type, obtaining an arbitration mode for the data read-write instruction; based on the arbitration mode, determining a target pointer position of a read pointer; the target pointer position represents a target read address of a cache area pointed to by the read pointer; based on the target pointer position, obtaining to-be-read data, and performing read processing on the to-be-read data. According to the application, different read modes are adopted to read data based on different arbitration modes, the target position of the read pointer can be dynamically determined according to real-time scenes, blockage or delay caused by fixed sequence access is avoided, and the flexibility and efficiency of cache area data reading are improved.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to a data reading and writing method, system, device and storage medium. Background Technology

[0002] Existing chips typically use a First-In-First-Out (FIFO) data buffer structure for data reading, which means that data is stored and retrieved in the order it arrives, i.e., the first data to enter is the first data to be retrieved. However, due to its fixed order characteristic, all data must be processed strictly in the order of entry, resulting in low flexibility in scenarios where certain specific data needs to be processed first. Summary of the Invention

[0003] This application provides a data reading and writing method, system, device, and storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0004] According to a first aspect of this application, a data read / write method is provided, the method comprising:

[0005] Get the read / write type of the data read / write command;

[0006] When the read / write type is read, obtain the arbitration method for the data read / write instruction;

[0007] Based on the arbitration method, the target pointer position of the read pointer is determined; the target pointer position represents the target read address of the cache pointed to by the read pointer.

[0008] The data to be read is obtained based on the target pointer position, and the data to be read is then processed.

[0009] In one possible implementation, it further includes:

[0010] When the read / write type is write, determine the current pointer position of the write pointer; the current pointer position represents the current storage address of the cache area pointed to by the write pointer;

[0011] Retrieve the data to be written, which contains priority encoding information and weight information;

[0012] Based on the current pointer position, the data to be written is processed.

[0013] In one possible implementation, the buffer includes at least two segment buffers; determining the target pointer location of the read pointer based on the arbitration method includes:

[0014] When the arbitration method is the first arbitration method, for any segment of the cache, the priority score for the segment of the cache is obtained based on the priority encoding information of the cached data in the segment of the cache.

[0015] Sort the total priority scores of each cache segment in descending order, and use the cache segments corresponding to the sorted total priority scores as the first target cache segments in sequence, and use the starting address of the first target cache segment as the target pointer position of the read pointer in sequence.

[0016] In one possible implementation, the step of obtaining the data to be read based on the target pointer position and performing read processing on the data to be read includes:

[0017] Based on the target pointer position, all cached data in the first target cache area is obtained, and the entire cached data is read as data to be read.

[0018] In one possible implementation, the buffer includes at least two segment buffers; determining the target pointer location of the read pointer based on the arbitration method includes:

[0019] When the arbitration method is the second arbitration method, for any segment of the cache, a weight value for the segment of the cache is obtained based on the weight information of the cached data in the segment of the cache.

[0020] During any read cycle, the segment cache with the highest weight value among all segment caches is used as the second target cache and its weight value is decreased in units. This process is repeated until the weight value of each segment cache is reduced to zero. The starting address of the second target cache in each read cycle is used as the target pointer position of the read pointer in turn.

[0021] In one possible implementation, the step of obtaining the data to be read based on the target pointer position and performing read processing on the data to be read includes:

[0022] Based on the target pointer position, a portion of the cached data in the second target cache area is obtained, and the portion of the cached data is read as data to be read.

[0023] In one possible implementation, the method further includes:

[0024] Based on the number of write operations and the number of read operations, we obtain the write pointer count and the read pointer count;

[0025] Based on the write pointer count, read pointer count, and preset counting threshold, a water level indication message is generated; the water level indication message is used to determine whether the buffer has overflowed.

[0026] In one possible implementation, the method further includes:

[0027] Obtain a data access instruction for the cache area; wherein the data access instruction includes a data access address; the real-time priority of the data access instruction is higher than the real-time priority of the data read / write instruction;

[0028] Based on the data access address and the preset mapping relationship, the address to be accessed in the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address in the cache area.

[0029] Data access is performed on the cache area based on the address to be accessed.

[0030] According to a second aspect of this application, a data read / write system is provided, characterized in that the system comprises:

[0031] The mode selection module is used to obtain the read / write type of the data read / write instruction; when the read / write type is read, it obtains the arbitration method for the data read / write instruction.

[0032] The arbitration module is used to determine the target pointer position of the read pointer based on the arbitration method; the target pointer position represents the target read address of the cache pointed to by the read pointer.

[0033] The read logic module is used to obtain the data to be read based on the target pointer position and to perform read processing on the data to be read.

[0034] In one possible implementation, the system further includes:

[0035] The write logic module is used to determine the current pointer position of the write pointer when the read / write type is write; the current pointer position represents the current storage address of the cache pointed to by the write pointer; obtain the data to be written with priority encoding information and weight information; and perform write processing on the data to be written based on the current pointer position.

[0036] In one possible implementation, the cache includes at least two segment caches;

[0037] The arbitration module includes a fixed priority module, which, when the arbitration method is the first arbitration method, obtains a total priority score for any segment of the cache based on the priority encoding information of the cached data in the segment of the cache; sorts the total priority scores of each segment of the cache in descending order, and sequentially uses each segment of the cache corresponding to the sorted total priority score as the first target cache, and sequentially uses the starting address of the first target cache as the target pointer position of the read pointer.

[0038] In one embodiment, the read logic module is used to obtain all cached data in the first target cache area based on the target pointer position, and to read all cached data as data to be read.

[0039] In one embodiment, the cache area includes at least two segment cache areas; the arbitration module includes a polling arbitration module, used to, when the arbitration method is the second arbitration method, obtain a weight value for any segment cache area based on the weight information of the cached data in the segment cache area; in any read cycle, take the segment cache area with the highest weight value among all segment cache areas as the second target cache area and decrease its weight value unit by unit, alternating until the weight value of each segment cache area is reduced to zero; and take the starting address of the second target cache area in each read cycle as the target pointer position of the read pointer in sequence.

[0040] In one possible implementation, the read logic module is used to obtain a portion of the cached data in the second target cache area based on the target pointer position, and to process the portion of the cached data as data to be read.

[0041] In one possible implementation, the system further includes:

[0042] The write pointer counting module is used to obtain the write pointer count based on the number of write operations;

[0043] The read pointer counting module is used to obtain the read pointer count based on the number of read operations;

[0044] The data level detection module is used to generate a level prompt message based on the write pointer count, read pointer count, and a preset counting threshold; the level prompt message is used to determine whether the buffer has overflowed.

[0045] In one possible implementation, the system further includes:

[0046] A fast access module is used to obtain data access instructions for the cache area; wherein, the data access instructions include a data access address; the real-time level of the data access instructions is higher than the real-time level of the data read / write instructions; based on the data access address and a preset mapping relationship, the address to be accessed in the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address of the cache area; based on the address to be accessed, data access is performed on the cache area.

[0047] According to a third aspect of this application, an electronic device is provided, comprising:

[0048] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described in this application.

[0049] According to a fourth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0050] In this application, the read / write type of the data read / write instruction is obtained; when the read / write type is a read type, the arbitration method for the data read / write instruction is obtained; based on the arbitration method, the target pointer position of the read pointer is determined; the target pointer position represents the target read address of the buffer pointed to by the read pointer; the data to be read is obtained based on the target pointer position, and the data to be read is read.

[0051] Compared with related technologies, this application has the following advantages: related technologies can only process data strictly in a fixed order regardless of the scenario requirements, while this application reads data in different ways based on different arbitration methods, and can dynamically determine the target position of the read pointer according to the real-time scenario, avoiding the blocking or delay problems caused by the fixed order access of related technologies, and improving the flexibility and efficiency of reading data from the cache area.

[0052] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0053] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0054] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0055] Figure 1 A schematic diagram illustrating the implementation flow of the data read / write method according to an embodiment of this application is shown;

[0056] Figure 2 This illustration shows an application diagram of the data read / write method according to an embodiment of this application;

[0057] Figure 3 A schematic diagram of the data read / write system according to an embodiment of this application is shown;

[0058] Figure 4 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0059] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] This application provides a data read / write method, combined with... Figure 1 , Figure 2 As shown, the method includes:

[0061] S101: Get the read / write type of the data read / write command.

[0062] In this application, data read / write instructions are instructions issued by users or other request sources. These instructions include two types: read and write. The read / write type of the data read / write instructions is obtained by decoding and analyzing the instructions.

[0063] S102: When the read / write type is read, obtain the arbitration method for the data read / write instruction.

[0064] In this step, combined Figure 2 As shown, when the read / write type is read, the data read / write instruction can include the encoding or high / low level flags corresponding to the arbitration mode of the user instruction. By analyzing the data read / write instruction, the arbitration mode for the data read / write instruction can be determined.

[0065] S103: Based on the arbitration method, determine the target pointer position of the read pointer; the target pointer position represents the target read address of the cache area pointed to by the read pointer.

[0066] In this embodiment, there are two arbitration methods: fixed priority arbitration and round-robin arbitration. The read pointer is used to locate the starting position of the read operation when reading data; it points to the storage address of the cache. Different arbitration methods have different read strategies, and therefore different starting positions (target pointer positions) of the read pointer. For a detailed explanation of the process for determining the target pointer position, please refer to the relevant sections below; it will not be repeated here.

[0067] S104: Obtain the data to be read based on the target pointer position, and perform read processing on the data to be read.

[0068] In this step, based on the address pointed to by the read pointer target pointer, cached data is read from the cache area as the data to be read and processed. For example, assuming the read pointer target pointer points to cache address 1 in the cache area, data is read starting from cache address 1. The data read may be a segment of data or a single data item. The specific number of items read will vary depending on the arbitration method. Please refer to the detailed explanation in the relevant sections below for specific reading methods, which will not be repeated here.

[0069] In the scheme shown in steps S101-S104, the read / write type of the data read / write instruction is obtained; when the read / write type is read, the arbitration method for the data read / write instruction is obtained; based on the arbitration method, the target pointer position of the read pointer is determined; the target pointer position represents the target read address of the buffer pointed to by the read pointer; the data to be read is obtained based on the target pointer position, and the data to be read is read. This application reads data in different ways based on different arbitration methods, which can dynamically determine the target position of the read pointer according to the real-time scenario, avoid blocking or delay caused by fixed sequential access, and improve the flexibility and efficiency of buffer data reading.

[0070] Some alternative solutions also include:

[0071] When the read / write type is write, determine the current pointer position of the write pointer; the current pointer position represents the current storage address of the cache area pointed to by the write pointer;

[0072] Retrieve the data to be written, which contains priority encoding information and weight information;

[0073] Based on the current pointer position, the data to be written is processed.

[0074] In this application, combined with Figure 2As shown, when the read / write type of the data read / write instruction is not read (i.e., the read / write type is write), the current pointer position of the write pointer is directly read, and the data to be written is written to the buffer based on the address pointed to by the current pointer position. The write-type data read / write instruction includes the data to be written, which can be obtained by parsing the instruction. The data to be written contains priority encoding information and weight information. The priority encoding information indicates the priority of each (batch) of data, and the weight information indicates the proportion of each (batch) of data in the total data. When writing the data to be written, it can be written according to the priority encoding information, such as writing the highest priority data first and the lowest priority data last. Alternatively, the data to be written can be written randomly according to the request order. This embodiment does not specifically limit the detailed method of write processing. This application directly writes to the current position of the write pointer as the base address, which can save extra address calculations, simplify control logic, and reduce write latency; at the same time, it supports flexible strategies of sequential or random writing, which can balance real-time performance and ease of implementation.

[0075] In some alternative schemes, the cache includes at least two segment caches; determining the target pointer location for the read pointer based on the arbitration method includes:

[0076] When the arbitration method is the first arbitration method, for any segment of the cache, the priority score for the segment of the cache is obtained based on the priority encoding information of the cached data in the segment of the cache.

[0077] Sort the total priority scores of each cache segment in descending order, and use the cache segments corresponding to the sorted total priority scores as the first target cache segments in sequence, and use the starting address of the first target cache segment as the target pointer position of the read pointer in sequence.

[0078] In this application, combined with Figure 2 As shown, the first arbitration method is a fixed priority arbitration method. It determines the target pointer location of the read pointer based on the priority encoding information of the cached data within the cache area. Specifically, in this embodiment, the cache area is segmented into 1 / N segments, where N is the number of data sources. Assuming there are 4 data sources when writing data to the cache area, the cache area is divided into 4 segments, resulting in 4 segmented cache areas. The total priority score is calculated for each segmented cache area. Specifically, assuming there are 4 types of priority encoding information, their mapping relationship with the represented priority is as shown in Table 1 below:

[0079] Table 1

[0080]

[0081] The priority encoding information consists of 2 bits of binary data. The cached data within the four cache segments may have the same priority or different priorities. The total priority of each cache segment is the sum of the priority encoding information of the cached data within that segment. For example, assuming the priority encoding information of the cached data in the first cache segment includes 00 and 01, then the total priority of the first cache segment is 00 + 01 = 01. The priority encoding information of the cached data in the second cache segment is only 10, so the total priority of the second cache segment is 10. The priority encoding information of the cached data in the third cache segment includes 01 and 10, so the total priority of the third cache segment is 01 + 10 = 11. The cache segment with the highest total priority score is selected as the first region to be read (the first target cache segment). The start address of the read pointer (target pointer position) is set to the beginning address of this cache segment to read the cached data. After the cached data in the first segment buffer is read, the segment buffer with the highest priority score from the remaining segment buffers is selected as the second area to be read and updated as the new first target buffer. The read start address (target pointer position) is set to the first address of the segment buffer to read the cached data in that segment buffer, and so on, until the cached data in all segment buffers has been read.

[0082] This application uses priority-based total score sorting for arbitration, ensuring that bandwidth is prioritized for the most valuable data segments, reducing the invalid use of cache and bus by low-priority data, and improving cache hit rate and bandwidth utilization. Simultaneously, through the segment cache priority total score mechanism, the cache is segmented according to the data source and the overall priority of each segment is quantified, achieving ordered reading from "high to low," significantly reducing access latency for high-priority data.

[0083] In some alternative solutions, obtaining the data to be read based on the target pointer position and performing read processing on the data to be read includes:

[0084] Based on the target pointer position, all cached data in the first target cache area is obtained, and all cached data is read as data to be read.

[0085] In this application, when the arbitration method is the first arbitration method, all cached data in the first target cache area is read each time. Only after all cached data in the previous first target cache area has been read can the cached data in the next first target cache area be read. By moving all data at once at the segment level, the overhead of cross-segment random access and address recalculation can be eliminated, realizing continuous and efficient batch transmission and significantly improving bus utilization.

[0086] In some alternative schemes, the cache includes at least two segment caches; determining the target pointer location for the read pointer based on the arbitration method includes:

[0087] When the arbitration method is the second arbitration method, for any segment of the cache, a weight value for the segment of the cache is obtained based on the weight information of the cached data in the segment of the cache.

[0088] During any read cycle, the segment cache with the highest weight value among all segment caches is used as the second target cache and its weight value is decreased in units. This process is repeated until the weight value of each segment cache is reduced to zero. The starting address of the second target cache in each read cycle is used as the target pointer position of the read pointer in turn.

[0089] In this application, combined with Figure 2 As shown, the second arbitration method is a round-robin arbitration method. It determines the target pointer location of the read pointer based on the weight information of the cached data within the cache area. Specifically, the weight value of each segment cache area is obtained by adding the weight information of the cached data within that segment cache area. In each read cycle, the segment cache area with the highest non-zero weight value is selected as the second target cache area, and its weight value is decremented by one. For example, suppose the weight value of the first segment cache area is 3, the weight value of the second segment cache area is 5, and the weight value of the third cache area is 1. Then, in the first read cycle, the segment cache area with a weight value of 5 is selected as the second target cache area, and its weight value is decremented by one. Thus, the weight values ​​of the first segment cache area are 3, the second segment cache area are 4, and the third cache area are 1. In the second read cycle, the segment cache area with a weight value of 4 is selected as the second target cache area, and its weight value is decremented by one. Thus, the weight values ​​of the first segment cache area are 3, the second segment cache area are 3, and the third cache area are 1. In the third read cycle, any cache segment with a weight of 3 is selected as the second target cache segment, and its weight is decremented by one... This process continues until the weights of all cache segments are reduced to zero, at which point the read operation ends. The starting address of the second target cache segment in each read cycle is the target pointer location of the read pointer.

[0090] In this application, the opportunity to read cached data in each segment of the cache is allocated according to the weight ratio, which ensures that high-weight segments get more bandwidth and avoids long-term starvation of low-weight segments, thus achieving fair and efficient bandwidth sharing.

[0091] In some alternative solutions, obtaining the data to be read based on the target pointer position and performing read processing on the data to be read includes:

[0092] Based on the target pointer position, a portion of the cached data in the second target cache area is obtained, and the portion of the cached data is read as data to be read.

[0093] In this application, when the arbitration method is the second arbitration method, each time a portion of the cached data in the first target cache area is read, it can be understood that the weight value is decremented by one for each piece of data read. This process is repeated alternately and cyclically, reading the cached data in each cache segment until the weight value of each cache segment is 0, meaning that the cached data in each cache segment has been completely read. In this embodiment, each cache segment is read alternately in units of data units. High-weight cache segments do not need to wait for the entire segment to be emptied before low-weight cache segments can receive service, significantly reducing the latency of reading cached data in low-weight cache segments.

[0094] In some alternative solutions, the method further includes:

[0095] Based on the number of write operations and the number of read operations, we obtain the write pointer count and the read pointer count;

[0096] Based on the write pointer count, read pointer count, and preset counting threshold, a water level indication message is generated; the water level indication message is used to determine whether the buffer has overflowed.

[0097] In this application, each write and read operation moves the write and read pointers once, generating a count. The write pointer count is the same as the number of write operations, and the read pointer count is the same as the number of read operations. The preset counting threshold is a pre-set baseline threshold, typically the buffer depth minus one. The used space of the buffer equals the write pointer count minus the synchronized read pointer count. By synchronizing the write and read pointers across clock domains, metastability issues caused by cross-clock domains can be avoided in asynchronous buffers, thus ensuring the accuracy of the used space calculation. The used space is compared to the baseline threshold. When the difference between the used space and the baseline threshold is less than a fixed value, it indicates that the data volume in the buffer is close to full, generating an "imminent overflow" water level warning message to notify the sender to stop or slow down data writing. When the difference between the used space and the baseline threshold is greater than another fixed value, it indicates that the data volume in the buffer is close to empty, generating an "imminent underflow" water level warning message to notify the receiver to pause data reading. This allows for dynamic adaptation to scenarios with excessively large or small data volumes, ensuring efficient buffer access.

[0098] In some alternative solutions, the method further includes:

[0099] Obtain a data access instruction for the cache area; wherein the data access instruction includes a data access address; the real-time priority of the data access instruction is higher than the real-time priority of the data read / write instruction;

[0100] Based on the data access address and the preset mapping relationship, the address to be accessed in the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address in the cache area.

[0101] Data access is performed on the cache area based on the address to be accessed.

[0102] In this application, the data access instruction is a fast access instruction, which is typically used in scenarios with high real-time requirements. It enables rapid access to or modification of cached data in the cache area. Specifically, in a chip, the cache is usually treated as a linear, sequential black box. If the CPU or other debugging tools want to directly read / modify a specific data slot, they must first disassemble this black box into an addressable SRAM. The data access instruction includes a data access address, which is the address on the aforementioned SRAM. Based on the correspondence between the SRAM address and the cache depth (cache address), the address to be accessed in the cache can be located, and the cached data corresponding to that address can be read, written, or modified. Compared to related technologies that first traverse all data sequentially and then select the target data, this application's embodiment can directly hit the data to be accessed or modified through the mapping relationship, greatly reducing time complexity and improving data access efficiency.

[0103] This application also provides a data read / write system, such as... Figure 3 As shown, the system includes:

[0104] The mode selection module is used to obtain the read / write type of the data read / write instruction; when the read / write type is read, it obtains the arbitration method for the data read / write instruction.

[0105] The arbitration module is used to determine the target pointer position of the read pointer based on the arbitration method; the target pointer position represents the target read address of the cache pointed to by the read pointer.

[0106] The read logic module is used to obtain the data to be read based on the target pointer position and to perform read processing on the data to be read.

[0107] In this embodiment of the application, in the read logic module, when the read enable signal is valid and the buffer is not empty, the data at the target read address of the buffer pointed to by the read pointer is read, and then the read pointer is incremented to point to the next readable location.

[0108] In some alternative solutions, the system further includes:

[0109] The write logic module is used to determine the current pointer position of the write pointer when the read / write type is write; the current pointer position represents the current storage address of the cache pointed to by the write pointer; obtain the data to be written with priority encoding information and weight information; and perform write processing on the data to be written based on the current pointer position.

[0110] In this embodiment of the application, in the write logic module, when the write enable signal is valid and the buffer is not full, the current storage address of the buffer pointed to by the write pointer is written with data, and then the write pointer is incremented to point to the next writable location.

[0111] In some alternative schemes, the cache area includes at least two segment cache areas;

[0112] The arbitration module includes a fixed priority module, which, when the arbitration method is the first arbitration method, obtains a total priority score for any segment of the cache based on the priority encoding information of the cached data in the segment of the cache; sorts the total priority scores of each segment of the cache in descending order, and sequentially uses each segment of the cache corresponding to the sorted total priority score as the first target cache, and sequentially uses the starting address of the first target cache as the target pointer position of the read pointer.

[0113] In this embodiment, the fixed priority module specifically includes a priority counter and a segment priority register. The priority counter is used to calculate the total priority score for each segment buffer. The segment priority register is used to store the total priority score for each segment buffer.

[0114] In some alternative solutions, the read logic module is used to obtain all cached data in the first target cache area based on the target pointer position, and to read all cached data as data to be read.

[0115] In some optional schemes, the cache area includes at least two segment cache areas; the arbitration module includes a polling arbitration module, used to, when the arbitration method is the second arbitration method, obtain a weight value for any segment cache area based on the weight information of the cached data in the segment cache area; in any read cycle, the segment cache area with the highest weight value among all segment cache areas is taken as the second target cache area and its weight value is decreased in units, alternating until the weight value of each segment cache area is reduced to zero; the starting address of the second target cache area in each read cycle is used as the target pointer position of the read pointer in sequence.

[0116] In this embodiment, the polling arbitration module specifically includes a segmented weight register, a polling state machine, a weight counter, and a weight comparator. The segmented weight register stores the weight values ​​of each segment of the cache, the weight counter decrements the weight of the second target cache segment in each read cycle, the weight comparator compares the weight values ​​of each segment of the cache, and the polling state machine determines whether the weight values ​​of each segment of the cache have all decreased to zero.

[0117] In some alternative solutions, the read logic module is used to obtain a portion of the cached data in the second target cache area based on the target pointer position, and to read the portion of the cached data as data to be read.

[0118] In some alternative solutions, the system further includes:

[0119] The write pointer counting module is used to obtain the write pointer count based on the number of write operations;

[0120] The read pointer counting module is used to obtain the read pointer count based on the number of read operations;

[0121] The data level detection module is used to generate a level prompt message based on the write pointer count, read pointer count, and a preset counting threshold; the level prompt message is used to determine whether the buffer has overflowed.

[0122] In this embodiment, the write pointer counting module and the read pointer counting module are core modules for managing data storage and retrieval. Their function is to track the write and read positions of data in the buffer, ensuring that data is transmitted correctly in sequence. The write pointer points to the next writable data storage location; it increments when data is written. The read pointer points to the next readable data storage location; it increments when data is read. In hardware implementation, the read and write pointers are typically implemented using counters. The counter's bit width is related to the buffer depth; for example, a buffer with a depth of M requires a log2(M) bit counter. To distinguish between the empty and full states of the buffer, additional flag bits or comparison logic are typically used. For example, when the read and write pointers are equal, the buffer is empty; when the write pointer has one more revolution than the read pointer, the buffer is full. In addition, the empty / full state of the buffer can also be determined by a data level detection module. Specifically, it generates a level flag signal by real-time detection of the amount of data currently stored in the buffer, allowing external systems to adjust data read and write operations based on these signals. For example, when the amount of data in the cache is close to full, the water level detection module triggers a "nearly full" flag, notifying the sender to stop or slow down data writing; when the amount of data is close to empty, it triggers a "nearly empty" flag, prompting the receiver to pause data reading. In implementation, water level detection is usually based on the write pointer counting module and the read pointer counting module to calculate the current amount of data, and generates corresponding water level prompt information by comparing it with a preset counting threshold.

[0123] In some alternative solutions, the system further includes:

[0124] A fast access module is used to obtain data access instructions for the cache area; wherein, the data access instructions include a data access address; the real-time level of the data access instructions is higher than the real-time level of the data read / write instructions; based on the data access address and a preset mapping relationship, the address to be accessed in the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address of the cache area; based on the address to be accessed, data access is performed on the cache area.

[0125] In this embodiment, external data request sources achieve fast access to or modification of data in the buffer area through the Advanced High-performance Bus (AHB) and AHB protocol interface. Specifically, the fast access module includes a depth / address converter, a read channel, and a write channel. External read / write requests are transmitted to the fast access module via the AHB bus and AHB protocol interface. The depth / address converter converts the data access address carried in the transmission into the address to be accessed (depth) of the buffer area according to a preset mapping relationship. Based on the address to be accessed, the data in the buffer area is quickly read through the read channel, and the data is quickly written to the buffer area through the write channel.

[0126] The main function of the AHB protocol interface is to receive, decode, and process read and write requests from external data request sources, and return corresponding data or response signals. Specifically, the AHB protocol interface needs to handle address decoding, determining whether to respond to the request based on the data access address provided by the external data request source. It also parses the transmission type, transmission size, and read / write signals to determine the operation type and data width. During data transmission, the AHB protocol interface returns the read data through the AHB bus, or receives data from the AHB bus and stores it at a specified address during a write operation. Furthermore, the AHB protocol interface needs to generate response signals, such as OKAY for successful operation and ERROR for failed operation. In implementation, the AHB protocol interface typically includes modules such as an address decoder, control logic, a data buffer, and a state machine. The address decoder determines the access range, the control logic parses bus signals and coordinates internal operations, the data buffer temporarily stores read and write data, and the state machine manages the timing and state transitions of the interface. Through proper design, the AHB protocol interface can efficiently and reliably interact with external data request sources, ensuring the stable operation of the system bus. In this embodiment, the data read / write system designs an interface compatible with the AHB protocol and can also directly mount the arbitration module onto the AHB bus, realizing the sharing of the buffer area. This not only saves the chip area and storage space but also avoids resource waste.

[0127] It should be noted that the data read and write system of this application embodiment is similar in principle to the aforementioned data read and write method in solving the problem. Therefore, the implementation process, implementation principle, and beneficial effects of the data read and write system can be found in the description of the implementation process, implementation principle, and beneficial effects of the aforementioned method. Repeated descriptions will not be repeated.

[0128] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0129] Figure 4 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0130] like Figure 4As shown, the electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. The RAM 403 may also store various programs and data required for the operation of the electronic device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0131] Multiple components in electronic device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of displays, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows electronic device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0132] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as data read and write methods. For example, in some embodiments, the data read and write methods may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the data read and write methods described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform data read and write methods by any other suitable means (e.g., by means of firmware).

[0133] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0134] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0135] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0136] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0137] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0138] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0139] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0140] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data read / write method, characterized in that, The method includes: Get the read / write type of the data read / write command; When the read / write type is read, obtain the arbitration method for the data read / write instruction; Based on the arbitration method, the target pointer position of the read pointer is determined; the target pointer position represents the target read address of the cache area pointed to by the read pointer; the cache area includes at least two segment cache areas; The data to be read is obtained based on the target pointer position, and the data to be read is then processed. When the read / write type is write, determine the current pointer position of the write pointer; the current pointer position represents the current storage address of the cache area pointed to by the write pointer; Retrieve the data to be written, which contains priority encoding information and weight information; Based on the current pointer position, write the data to be written; The step of determining the target pointer position of the read pointer based on the arbitration method includes: When the arbitration method is the first arbitration method, for any segment of the cache, the priority score for the segment of the cache is obtained based on the priority encoding information of the cached data in the segment of the cache; the segment of the cache includes cached data with the same priority encoding information or cached data with different priority encoding information; Sort the total priority scores of each cache segment in descending order, and take the cache segments corresponding to the total priority scores as the first target cache segments in turn, and take the starting address of the first target cache segments as the target pointer positions of the read pointer in turn. The step of obtaining the data to be read based on the target pointer position and performing read processing on the data to be read includes: Based on the target pointer position, all cached data in the first target cache area is obtained, and all cached data is read as data to be read. When the arbitration method is the second arbitration method, for any segment of the cache, a weight value for the segment of the cache is obtained based on the weight information of the cached data within the segment of the cache; the weight value of the segment of the cache is obtained by adding the weight information of the cached data within the segment of the cache. During any read cycle, the segment cache with the highest weight value among all segment caches is used as the second target cache and its weight value is decreased in units. This process is repeated until the weight value of each segment cache is reduced to zero. The starting address of the second target cache in each read cycle is used as the target pointer position of the read pointer in turn.

2. The method according to claim 1, characterized in that, The step of obtaining the data to be read based on the target pointer position and performing read processing on the data to be read includes: Based on the target pointer position, a portion of the cached data in the second target cache area is obtained, and the portion of the cached data is read as data to be read.

3. The method according to claim 1, characterized in that, The method further includes: Based on the number of write operations and the number of read operations, we obtain the write pointer count and the read pointer count; Based on the write pointer count, read pointer count, and preset counting threshold, a water level indication message is generated; the water level indication message is used to determine whether the buffer has overflowed.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Obtain a data access instruction for the cache area; wherein the data access instruction includes a data access address; the real-time priority of the data access instruction is higher than the real-time priority of the data read / write instruction; Based on the data access address and the preset mapping relationship, the address to be accessed in the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address in the cache area. Data access is performed on the cache area based on the address to be accessed.

5. A data read / write system, characterized in that, The system includes: The mode selection module is used to obtain the read / write type of the data read / write instruction; when the read / write type is read, it obtains the arbitration method for the data read / write instruction. An arbitration module is used to determine the target pointer location of the read pointer based on the arbitration method; the target pointer location represents the target read address of the cache pointed to by the read pointer; the cache includes at least two segment caches; The read logic module is used to obtain the data to be read based on the target pointer position and to perform read processing on the data to be read. The write logic module is used to determine the current pointer position of the write pointer when the read / write type is write; the current pointer position represents the current storage address of the cache pointed to by the write pointer; obtain the data to be written with priority encoding information and weight information; and perform write processing on the data to be written based on the current pointer position. The arbitration module includes a fixed priority module, which is used to obtain a total priority score for any segment of the cache based on the priority encoding information of the cached data in the segment of the cache when the arbitration method is the first arbitration method; sort the total priority scores of each segment of the cache in descending order; take the segment of the cache corresponding to the sorted total priority score as the first target cache in sequence; and take the starting address of the first target cache as the target pointer position of the read pointer in sequence. The read logic module is used to obtain all cached data in the first target cache area based on the target pointer position, and to read all cached data as data to be read. The arbitration module includes a polling arbitration module, used to, when the arbitration method is the second arbitration method, obtain a weight value for any segment of the cache based on the weight information of the cached data in the segment of the cache; the weight value of the segment of the cache is obtained by adding the weight information of the cached data in the segment of the cache; in any reading cycle, the segment of the cache with the highest weight value among all segments of the cache is taken as the second target cache and its weight value is decreased in units, alternating until the weight value of each segment of the cache is reduced to zero; the starting address of the second target cache in each reading cycle is taken as the target pointer position of the read pointer in sequence.

6. The system according to claim 5, characterized in that, The read logic module is used to obtain a portion of the cached data in the second target cache area based on the target pointer position, and to read the portion of the cached data as data to be read.

7. The system according to claim 5, characterized in that, The system also includes: The write pointer counting module is used to obtain the write pointer count based on the number of write operations; The read pointer counting module is used to obtain the read pointer count based on the number of read operations; The data level detection module is used to generate a level prompt message based on the write pointer count, read pointer count, and a preset counting threshold; the level prompt message is used to determine whether the buffer has overflowed.

8. The system according to any one of claims 5 to 7, characterized in that, The system also includes: A fast access module is used to obtain data access instructions for the cache area; wherein, the data access instructions include a data access address; the real-time level of the data access instructions is higher than the real-time level of the data read / write instructions; based on the data access address and a preset mapping relationship, the address to be accessed in the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address of the cache area; based on the address to be accessed, data access is performed on the cache area.

9. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-4.

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