Register access signal conversion and transmission method, chip and system on chip

Abstract

The invention relates to a register access signal conversion and transmission method, a chip and a system on chip. The method comprises the following steps: receiving a register access request time sequence signal from an APB interface of a local chip; generating a UCIe sideband register access request data packet according to the register access request time sequence signal; and sending the UCIe sideband register access request data packet to a target layer. The chip comprises a conversion module which is located in a protocol layer of the chip and used for receiving a register access request time sequence signal from an APB interface; generating a UCIe sideband register access request data packet according to the register access request time sequence signal; and sending the UCIe sideband register access request data packet. According to the invention, the integration of the system-on-chip is facilitated, the compatibility of the system-on-chip composed of small chips is improved, so that the system-on-chip can conveniently access the local small chips and cross-chip registers, and the function specified by a UCIe protocol sideband is realized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip data transmission, and particularly relates to a register access signal conversion transmission method, a chip and a system on chip. BACKGROUND

[0002] With the slowing down of Moore's Law, Chiplet technology has become an important technical approach to continuously improve the integration and computing power of a system on chip (SoC).

[0003] A system on chip is to integrate multiple functional modules on a single chip, while Chiplet technology is to decompose these functional modules into multiple small chips and then integrate them together through advanced packaging technology. Due to the independent design of each small chip, the communication connection protocols between the small chips may be different, and the incompatibility between different communication connection protocols limits the application of Chiplet technology in a system on chip and hinders the design of the system on chip. SUMMARY

[0004] Therefore, the present disclosure provides a register access signal conversion transmission method, a chip and a system on chip to improve the compatibility of the communication connection protocols of the small chips and thus help reduce the design difficulty of the system on chip.

[0005] The technical solution of the present disclosure is implemented as follows: According to an aspect of an embodiment of the present disclosure, a register access signal conversion transmission method is provided, comprising: receiving an APB protocol register access request timing signal from an APB interface of a local chip; generating a UCIe sideband register access request data packet according to the APB protocol register access request timing signal; sending the UCIe sideband register access request data packet to a destination layer; receiving a UCIe sideband register access completion data packet and parsing, generating an APB protocol register access completion timing signal according to the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with the UCIe sideband register access request data packet, wherein the UCIe sideband register access completion data packet is associated with the APB protocol register access request timing signal, and wherein the UCIe sideband register access completion data packet and the UCIe sideband register access request data packet belong to the same data packet corresponding to an APB protocol access; sending the APB protocol register access completion timing signal through the APB interface.

[0006] In a possible implementation, the access destination register of the APB protocol register access request timing signal is any one of a local chip adaptation layer register, a local chip physical layer register, a remote chip physical layer register, and a remote chip adaptation layer register.

[0007] In a possible implementation, when the access destination register of the APB protocol register access request timing signal is the local chip adaptation layer register, the sending of the UCIe sideband register access request data packet to a destination layer comprises the following steps. The UCIe sideband register access request data packet is sent to an adaptation layer of the local chip through an FDI interface.

[0008] In a possible implementation, when the access destination register of the APB protocol register access request timing signal is the local chip physical layer register, the sending of the UCIe sideband register access request data packet to a destination layer comprises the following steps. The UCIe sideband register access request data packet is sent to an adaptation layer of the local chip through an FDI interface, and the adaptation layer forwards the UCIe sideband register access request data packet to a physical layer of the local chip through an RDI interface.

[0009] In a possible implementation, when the access destination register of the APB protocol register access request timing signal is the remote chip physical layer register or the remote chip adaptation layer register, the sending of the UCIe sideband register access request data packet to a destination layer comprises the following steps. The UCIe sideband register access request data packet is written into a mailbox register for remote chip register access.

[0010] In a possible implementation, the mailbox register is located in an adaptation layer of the local chip.

[0011] In a possible implementation, when the access destination register of the APB protocol register access request timing signal is a local chip protocol layer register, the method further comprises the following steps. The local chip protocol layer register is directly accessed through the APB interface.

[0012] In a possible implementation, the local chip comprises a protocol layer, an adaptation layer, and a physical layer defined by a UCIe protocol. The APB interface accesses the protocol layer. The protocol layer and the adaptation layer communicate through an FDI interface of the UCIe protocol, and the adaptation layer and the physical layer communicate through an RDI interface of the UCIe protocol.

[0013] In a possible implementation, the access destination register address in the UCIe sideband register access request data packet is consistent with the access destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal.

[0014] According to another aspect of the embodiments of the present disclosure, a chip is provided, which comprises a UCIe interface defined by a UCIe protocol and an APB interface defined by an APB protocol; wherein, The chip further comprises: a conversion module in a protocol layer of the UCIe interface, configured to: receive an APB protocol register access request timing signal from the APB interface, generate a UCIe sideband register access request data packet according to the APB protocol register access request timing signal, and send the UCIe sideband register access request data packet; and in response to receiving a UCIe sideband register access completion data packet, generate an APB protocol register access completion timing signal according to the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with the UCIe sideband register access request data packet, and send the APB protocol register access completion timing signal through the APB interface.

[0015] According to another aspect of the embodiments of the present disclosure, a system-on-chip is provided, comprising: at least one small chip integrated in a package; wherein at least one of the at least one small chip is the chip as described above.

[0016] It can be seen from the above scheme that the register access signal conversion transmission method, the chip and the system on chip of the present disclosure simplify the complexity of the data link design of the system on chip composed of small chips based on the APB protocol, which helps to reduce the design difficulty of the data link, and further helps to reduce the design difficulty of the system on chip, and helps to improve the compatibility of the APB protocol and the UCIe protocol in the same system on chip. In the case that different small chips in the system on chip are independently designed by different design teams and the small chips support the UCIe protocol, the register access signal conversion transmission method of the present disclosure can be used in the specified small chip in the system on chip according to the design requirements, and the advantages of the APB protocol and the UCIe protocol can be simultaneously utilized in the system on chip. In addition, by using the chip of the present disclosure, a conversion module for signal translation and conversion between the APB protocol and the UCIe protocol is only needed to be set in the protocol layer defined by the UCIe protocol of the chip, and then the register access request can be sent to the local chip through the APB protocol in the case that the APB protocol only accesses the protocol layer. At the same time, based on the UCIe protocol, the local chip can also send a register access request to a remote chip through the APB protocol. Because the APB protocol only accesses the protocol layer defined by the UCIe protocol and does not access the adaptation layer and the physical layer defined by the UCIe protocol, the related link for the APB protocol to access the adaptation layer and the physical layer does not need to be designed in the chip, which helps to reduce the complexity of the data link design in the chip, reduces the design difficulty of the data link, and further helps to reduce the design difficulty of the chip. In addition, the system on chip can conveniently perform register access of the local small chip and the cross-chip, and realize the function specified by the UCIe protocol sideband. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a chip structure diagram of the UCIe protocol in the related art; Figure 2 is a flowchart of a register access signal conversion transmission method according to an illustrative embodiment; Figure 3 is a register access timing diagram of an APB interface according to an illustrative embodiment; Figure 4 is a UCIe sideband register access request data packet format diagram according to an illustrative embodiment; Figure 5 is a UCIe sideband register access completion data packet format diagram according to an illustrative embodiment; Figure 6This is a schematic diagram of the remote chip register access process of the UCIe protocol; Figure 7 is a schematic diagram of a specific scenario using the register access signal conversion and transmission method according to an embodiment of the present disclosure; Figure 8 This is a timing diagram of local chip register access, taking a read operation as an example; Figure 9 1 is a schematic diagram showing a detailed process state of register access of a remote chip according to an exemplary embodiment; Figure 10 is a schematic diagram of a chip according to an exemplary embodiment; Figure 11 This is a schematic diagram of the register access method of the APB protocol in the related art. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] In a system on a chip, register configuration is required to implement corresponding chip functions, and register access is implemented using corresponding protocols.

[0021] APB (Advanced Peripheral Bus) is a bus protocol used in system-on-chips. It is commonly used to access registers of various modules in the system-on-chip. APB is part of the AMBA (Advanced Microcontroller Bus Architecture) protocol and is mainly used to connect low-speed peripherals (such as UART (Universal Asynchronous Receiver-Transmitter), I 2 The APB protocol is commonly used to connect master and slave devices to SoC bus systems such as the Inter-Integrated Circuit (IC) bus and the Serial Peripheral Interface (SPI). It uses a simple interface design to connect master and slave devices. Within SoCs, the APB protocol is also commonly used to access registers in various modules.

[0022] The UCIe (Universal Chiplet Interconnect Express) protocol is a protocol for communication between small chips, aiming to achieve high-speed and efficient communication between small chips within a package. It supports multiple upper-layer protocols such as the PCIe (Peripheral Component Interconnect Express) protocol, the CXL (Compute Express Link) protocol, and a custom Streaming Protocol to meet different communication needs. Among them, the UCIe protocol proposes a new way of using the sideband as the protocol layer, the adaptation layer, and the physical layer to interact information between die and die, including register access through the sideband, which can realize the hierarchical register access of the local die and the cross-chip register access, facilitating the configuration and management of registers at different levels, while not occupying the main link data bandwidth.

[0023] Figure 1 is a chip structure diagram of the UCIe protocol in the related art. As shown in Figure 1 , the UCIe protocol specifies that the chip contains a three-layer structure composed of a protocol layer, an adaptation layer, and a physical layer.

[0024] Among them, the protocol layer is the top layer in the UCIe protocol architecture, and its main function is to define the rules and protocol format of data exchange, ensuring seamless interoperability between Chiplets of different manufacturers. The protocol layer supports multiple mainstream protocols, including PCIe 6.0, CXL 2.0 / 3.0, and user-defined Streaming Protocol. These protocols use Flit (Fragment) mode for data transmission to achieve efficient and low-latency communication. The protocol layer ensures compatibility between different protocols, and the protocol layer encapsulates data into Flit for efficient transmission between the adaptation layer and the physical layer. In the streaming transmission mode, the protocol layer is completely user-defined. The protocol layer interacts with the adaptation layer through the FDI (Flit-aware D2D Interface) interface, and passes the encapsulated Flit data to the adaptation layer. The protocol layer participates in the negotiation of protocol capabilities during link initialization to determine the supported protocols and modes of the link. The protocol layer supports multiple protocols and custom modes, providing flexibility and compatibility for Chiplet interconnection, enabling Chiplets with different functions to communicate efficiently under a standardized framework.

[0025] Wherein, the adaptation layer is a logical layer of UCIe protocol, located between the protocol layer and the physical layer, the main function of the adaptation layer is to adapt the data flit packaged by the protocol layer to the physical layer for transmission, and to manage the link state, power management and parameter negotiation, etc. The adapter is the specific implementation of the adaptation layer, which can be understood as the physical entity of the adaptation layer, and the adapter is responsible for processing various functions of the adaptation layer, such as CRC calculation, retransmission mechanism, link state management, etc. In the actual system configuration, one adaptation layer can support multiple protocol stacks, and these protocol stacks can share the same adapter through arbitration and multiplexing mechanism (Arb / Mux) in the adaptation layer. For example, one adapter can bridge multiple protocol stacks and support multiple physical layer modules. In the multi-module configuration, the function of the adapter can be extended to multiple modules.

[0026] The physical layer is responsible for implementing the Die-to-Die (D2D) electrical connection and data transmission. Its main function is to convert the data signals provided by the adaptation layer into electrical signals suitable for transmission on the physical link, and to restore these signals to data at the receiving end. The physical layer needs to handle signal encoding, modulation, demodulation and decoding operations, and is responsible for managing signal integrity, including timing, amplitude and noise control. The physical layer initializes and trains at link startup to ensure link reliability and performance, including: electrical parameter negotiation: negotiate the electrical characteristics of the link, such as voltage swing, pre-emphasis, etc.; clock recovery: recover the clock signal at the receiving end; link training: calibrate the electrical characteristics of the link through training sequences to ensure data transmission accuracy. The physical layer supports multiple low-power states to reduce power consumption, such as: L1 / L2 low-power state: when there is no data transmission, the physical layer can enter a low-power mode to save energy, and the protocol layer and adaptation layer also support low-power states, when there is no data transmission, the three layers of UCIe support low-power states, and need to negotiate with the opposite die, when confirming that there is no data transmission on both sides, the physical layer, adaptation layer and protocol layer enter low-power mode in turn; dynamic power management: dynamically adjust the power state according to the usage of the link. The physical layer supports parallel transmission of multiple physical links to improve data transmission bandwidth and efficiency. The physical layer is a key part of the UCIe architecture that implements inter-chip interconnection, and is directly responsible for electrical signal transmission and link reliability, ensuring efficient and accurate data transmission between different chips, and the design and implementation of the physical layer directly affects the performance, power consumption and reliability of the entire system. The implementation of the physical layer usually depends on specific packaging technologies and electrical characteristics. For example: standard packaging, advanced packaging such as 2.5D packaging and 3D packaging technology, which can provide higher bandwidth and lower power consumption. The design of the physical layer needs to consider many factors, including signal integrity, power consumption, packaging technology and cost, etc., and by optimizing the design of the physical layer, the performance and reliability of the UCIe system can be significantly improved.

[0027] The protocol layer and the adaptation layer communicate and transmit data through the FDI (Flit-aware D2D Interface) interface, and the adaptation layer and the physical layer communicate and transmit data through the RDI (Raw D2D Interface) interface.

[0028] The FDI interface is an interface defined in the UCIe standard, located between the protocol layer and the adaptation layer. The FDI interface supports different sizes of Flit (data slice) modes, such as 68B, 256B, etc., to adapt to different transmission requirements. The FDI interface supports mainband data transmission signals, sideband data transmission signals, and control handshake signals. The FDI interface allows multiple protocol stacks to share the same D2D adapter. Through arbitration and multiplexing mechanisms, multiple protocol stacks can realize time-sharing multiplexing of the adapter and the physical layer. The FDI interface plays a key role in the UCIe architecture, not only enabling efficient data transmission between the protocol layer and the adaptation layer, but also improving the flexibility and energy efficiency of the system by supporting multiple protocol Flit transmission and link state management.

[0029] The RDI interface is an interface defined in the UCIe standard, located between the adaptation layer and the physical layer. The RDI interface is responsible for transmitting data from the adaptation layer to the physical layer and receiving data from the physical layer. The RDI interface mainly processes raw data streams and does not involve Protocol-Aware operations, i.e., it does not process the specific protocol format of the data, but directly transmits the data in its original form. The RDI interface is designed to achieve low latency and high bandwidth data transmission to meet the requirements of inter-chip interconnection.

[0030] The RDI interface supports mainband data transmission signals, sideband data transmission signals, and control handshake signals. The RDI interface is one of the key interfaces in the UCIe architecture for efficient inter-chip interconnection. Through close cooperation with the adaptation layer and the physical layer, it ensures that data can be quickly and reliably transmitted between different chips.

[0031] Although the three-layer structure of the protocol layer, the adaptation layer, and the physical layer is a logical hierarchy in the UCIe architecture, in the chip of the UCIe architecture, each of the protocol layer, the adaptation layer, and the physical layer contains different registers respectively. In the UCIe architecture, the registers of the protocol layer, the adaptation layer, and the physical layer each have different roles. The protocol layer registers are mainly used to manage the configuration and state information related to the protocol, mainly including: state management: used to track the state of the protocol layer, such as whether the link is in an active state, whether there are unfinished transactions, etc.; register access: the protocol layer can access the adaptation layer and the physical layer through the sideband mechanism to realize cross-layer configuration and state query. The role of the adaptation layer registers mainly focuses on the configuration of link management and data transmission, mainly including: link state management: the adaptation layer registers are used to manage the state of the link, such as whether the link is in the initialization, training, or low-power state, etc.; protocol adaptation parameters: store parameters related to protocol adaptation, such as Flit size, protocol conversion parameters, etc., which are exchanged with the opposite chip through the sideband; register access: the adaptation layer registers can be accessed by the protocol layer through the sideband mechanism, and the adaptation layer can also access the physical layer registers through the sideband mechanism. The physical layer registers are mainly used to manage the electrical characteristics and link state of the physical link, mainly including: electrical parameter configuration: store electrical parameters related to the physical link, such as voltage swing, pre-emphasis, clock recovery, etc.; link training and management: store state information of link training, such as training sequence, link quality, etc.; link state management: perform link initialization, link training, and link low-power management, etc.; register access: the physical layer registers can be accessed by the adaptation layer and the protocol layer through the sideband mechanism for link initialization, debugging, and state query. The sideband mechanism in the UCIe architecture is used to transmit register access requests and link management messages between different layers. Through the sideband, the protocol layer, the adaptation layer, and the physical layer can realize cross-layer register access and link management.

[0032] Currently, in the related art, the APB protocol is widely used in register access in digital chips, which has the advantages of simple protocol, good universality, and mature design and implementation, but has the disadvantage of needing to allocate all register addresses in the SoC during SoC design, and accessing the registers through addressing. However, on the Chiplet, the APB protocol cannot directly access the registers of the opposite die across the die. In the SoC, if different dies are produced by different design production subjects, it is difficult to uniformly plan all registers in the SoC at the system level during design, and thus the allocation information of all register addresses in the SoC cannot be obtained. In this case, the SoC cannot directly access all registers in each level of each die through the APB interface.

[0033] In the UCIe protocol, the local chip adaptation layer register and the local chip physical layer register can be accessed by a dedicated sideband data packet from the protocol layer through a sideband. The UCIe protocol specifies that the protocol layer register does not support access through the sideband, and the protocol layer register is limited to internal access of the local chip and cannot directly access the remote chip protocol layer register through the sideband mechanism. If the remote chip protocol layer register needs to be accessed, it must be indirectly realized through the mailbox mechanism. As long as different chips meet the UCIe protocol specification, register access at different levels and across chips can be realized through the sideband. However, the implementation is complex and is not convenient for direct use of the SoC system level.

[0034] The mailbox mechanism in the UCIe protocol is a mechanism for indirectly accessing the registers of a remote chip. In the UCIe protocol, the protocol layer cannot directly access the registers of a remote chip through the sideband, but does so indirectly through the mailbox mechanism. The mailbox mechanism allows one chip, such as a master chip, to send a register access request to another chip, such as a slave chip, and receive a response. The working principle of the mailbox mechanism is as follows: 1. Request initiation: the local chip protocol layer (master chip protocol layer) writes content into the mailbox register of the local chip adaptation layer (master chip adaptation layer) through the FDI sideband interface according to the request type. The request includes the type of register access (such as read or write), target address, and other information; 2. Adaptation layer processing: after the local chip adaptation layer identifies the content written into the mailbox register, it generates a remote chip sideband register access request data packet and sends the request to the local chip physical layer through the RDI sideband interface. The local chip physical layer receives and converts the request into serial data and sends it to the remote chip (slave chip) through the UCIe link sideband link; 3. Remote processing: the remote chip physical layer receives the serial data and converts it into a remote chip sideband register access request data packet, which is then passed to the remote chip adaptation layer through the RDI sideband interface. The remote chip adaptation layer accesses the corresponding register according to the remote chip sideband register access request data packet and returns the access result to the remote chip physical layer; 4. Result return: the remote chip physical layer converts the access result into serial data and sends it back to the master chip through the UCIe link sideband link. The local chip physical layer (master chip physical layer) receives the serial data and parses it into sideband packet data for the access result, which is then passed to the local chip adaptation layer through the RDI sideband interface. The local chip adaptation layer writes the sideband packet data into the mailbox register and notifies the local chip protocol layer through the FDI sideband interface. The UCIe protocol specifies that the key mailbox registers involved in the mailbox mechanism include the sideband mailbox index register, the sideband mailbox data register, the mailbox status register, and the mailbox control register. The sideband mailbox index register is used to specify the access type (such as 32 / 64 bits, memory / configuration, read / write), address, and other information. The sideband mailbox data register is used to store the data to be written or the result of reading. The sideband status register is used to indicate the status of the access result, such as success or access failure. The mailbox control register is used to trigger the sideband register access request.The mailbox mechanism has the following features: 1. No need for UCIe external system intervention, such as a CPU (Central Processing Unit), improving communication efficiency; 2. Efficient and flexible: through the mailbox mechanism, efficient access to remote chip registers can be achieved while maintaining system flexibility. The Mailbox mechanism is a key technology for implementing cross-chip register access in the UCIe protocol. It realizes indirect access to remote chip registers through the cooperation of the adaptation layer and the physical layer. Accessing remote chip registers through the Mailbox mechanism also avoids occupying the main band resources, reduces the main band load, and improves the communication efficiency.

[0035] The APB and the UCIe each have their own characteristics. The APB protocol is simple, the control logic is simple, and the read-write operation is the fastest, only two clock cycles are needed, without complex waiting period and response signal. Due to its simplicity, the APB interface is easy to implement and verify, and is suitable for the connection of various low-speed peripherals. The UCIe protocol is a trend of small chip technology, but the UCIe protocol is relatively complex. The register access mode specified by the UCIe is implemented by a relatively complex sideband data packet, and contains complex mechanisms such as cross-level credit management. The implementation is more complex than the APB, which is not conducive to the use of system-on-chip integration.

[0036] However, because the APB needs to rely on the allocation of all register addresses in the system-on-chip during system-on-chip design, the registers are accessed by addressing, and in the system-on-chip, if all registers are difficult to be planned uniformly at the system level during design, and the allocation information of all register addresses in the system-on-chip cannot be obtained, then the system-on-chip cannot directly access all registers in each die of the system-on-chip through the APB interface, causing the limitation of the APB interface.

[0037] As can be seen from the above, the APB protocol is used for register access, and the UCIe protocol is used for small chip interconnection. If the allocation of all register addresses in the system-on-chip can be achieved during the design phase, then the APB protocol can be used to access all registers related to the UCIe protocol. However, as the size of the system-on-chip expands and the number of small chips increases, it will become increasingly difficult to allocate all register addresses in the system-on-chip in advance during the design phase. Therefore, it will be increasingly difficult to achieve the access of all registers in the system-on-chip using only the APB protocol. Therefore, it is more recommended to use the UCIe sideband register access to complete the register access in the UCIe.

[0038] Therefore, the present disclosure provides a register access signal conversion transmission method, a chip and a system on chip, which realizes conversion of sideband register access signals of APB protocol and UCIe protocol, helps to improve the compatibility of communication connection protocols of small chips, and helps to reduce the design difficulty of the system on chip.

[0039] Figure 2 is a flowchart of a register access signal conversion transmission method according to an illustrative embodiment. As Figure 2 shown, the register access signal conversion transmission method mainly includes the following steps 201 to 203.

[0040] Step 201, receiving an APB protocol register access request timing signal from an APB interface of a local chip; Step 202, generating a UCIe sideband register access request packet according to the APB protocol register access request timing signal; Step 203, sending the UCIe sideband register access request packet to a destination layer.

[0041] In the illustrative embodiment, the destination layer includes at least one of an adaptation layer of the local chip, a physical layer of the local chip, a physical layer of a remote chip, and a protocol layer of the remote chip.

[0042] Figure 3 is a register access timing diagram of an APB interface according to an illustrative embodiment. As Figure 3 shown, in the register access timing of the APB interface: PCLK is a global clock signal, in the illustrative embodiment, the rising edge of PCLK is sampled, Figure 3 T0, T1, T2, T3, T4, T5, T6 are the rising edge positions of each cycle of PCLK; PADDR is a target address signal, which is used to specify the target address of access, and it remains stable in the transmission process and is ready when the PENABLE signal is valid, ensuring that the address is correctly identified in the transmission process, PADDR signal plays an important role in write operation and read operation, and is the core part of APB bus communication, PADDR represents a 32-bit address bus, which can support a maximum of 2 32 address space, Figure 3Addr1 represents address content; PWRITE is a write control signal, used to indicate whether the current transmission operation is a write operation or a read operation, PWRITE = 1 indicates that the current operation is a write operation, and PWRITE = 0 indicates that the current operation is a read operation; PSEL is a slave selection signal, used to indicate the target slave of the current transmission operation, when the PSEL signal is pulled high, it indicates that the master is initiating a new transmission operation, and the target is a slave, in the APB bus system, there can be multiple slaves connected to the bus, the PSEL signal in combination with the address range of the slave can specify which slave is the target of the current operation; PENABLE is a transmission enable signal, used to indicate whether the transmission operation enters the data transmission stage, when PENABLE is low, it indicates that the current is in the setup stage, the master is preparing the transmission operation, setting PADDR (target address), PWRITE (transmission operation type) and the like, when PENABLE is high, it indicates that the current enters the access stage, the master and the slave start the actual data transmission, the pull-up of the PENABLE signal marks the start of a new transmission operation; PWDATA is a write data signal, used to transmit data from the master to the slave during the write operation of the APB protocol, the width of the PWDATA signal is usually 32 bits, but the actual data width can be adjusted according to the specific design requirements, for example, some systems can use 8-bit, 16-bit or 32-bit data width, during the write operation, the PWDATA signal provides the data to be written at the same time as the pull-up of the PENABLE signal, Figure 3 Data1 represents data content; PREADY is a ready signal, used by the slave to indicate to the master whether it has prepared to complete the current read or write operation, if the PREADY signal is pulled high, it indicates that the slave is ready, and the data transmission can be completed, if the PREADY signal remains low, it indicates that the slave is not ready, and the master needs to wait, the PREADY signal cooperates with the PENABLE signal to ensure that the data transmission between the master and the slave is synchronized.

[0043] In addition Figure 3In addition to the above, the APB interface signals also include PRDATA, PSLVERR, etc. PRDATA is a read data signal, used to transmit data from the slave device to the master device during the read operation of the APB protocol, the width of the PRDATA signal is usually the same as that of the PWDATA signal, usually 32 bits, but it can also be adjusted to other widths (such as 8 bits, 16 bits, etc.) according to specific design needs, during the read operation, the PRDATA signal provides the data read from the target address at the same time as the PREADY signal is pulled high; PSLVERR is a slave error signal, used by the slave device to report to the master device whether an error has occurred in the current transmission operation, if the PSLVERR signal is pulled high, it indicates that the slave device detects an error, such as illegal address access, timeout or other abnormal conditions, if the PSLVERR signal remains low, it indicates that the transmission operation is completed normally and no error is detected, the master device can decide whether to re-initiate the transmission operation or take other error handling measures according to the state of the PSLVERR signal.

[0044] In an illustrative embodiment, when the APB interface receives a register access request, the interaction process of its timing signals can include the following: Write operation timing: first stage, Setup stage (T1 to T2): PSEL signal is pulled high, indicating the initiation of a new transmission, PWRITE signal is pulled high, indicating that this operation is a write operation, PADDR and PWDATA signals place the target address and data to be written respectively, PENABLE signal remains low; second stage, Access stage (T2 to T3): PENABLE signal is pulled high, indicating entering the data transmission stage, PREADY signal is pulled high by the slave device, indicating that the slave device is ready to receive data, data transmission is completed at T3; third stage, end stage (T3 and after): after transmission is completed, PSEL signal and PENABLE signal are pulled low, if continuous transmission is required and the target slave device is the same, PSEL signal can remain high.

[0045] Read operation timing: first stage, Setup stage (T1-T2): PSEL signal is pulled high, indicating the initiation of a new transmission, PWRITE signal is pulled low, indicating that this operation is a read operation, PADDR signal places the target address, PENABLE signal remains low; second stage, Access stage (T2-T3): PENABLE signal is pulled high, indicating entering the data transmission stage, PREADY signal is pulled high by the slave device, indicating that the slave device is ready to send data, PRDATA signal provides valid data at the same time or after PREADY is pulled high; third stage, end stage (T3 and after): after transmission is completed, PSEL signal and PENABLE signal are pulled low. Error response: in the write operation or read operation, if an error occurs (such as illegal address access or timeout), the slave device can pull the PSLVERR signal high in the last cycle of transmission to indicate that the transmission fails.

[0046] It can be seen that the timing design of the APB protocol is relatively simple, at least two clock cycles are required for each transmission, and pipeline operation is not supported.

[0047] Figure 4 is a schematic diagram of a UCIe sideband register access request data packet format according to an illustrative embodiment. As shown in Figure 4 , it mainly includes Opcode field, SrcID field, DstID field, CP field, DP field, Addr field, BE field, EP field, Tag field, Data field, etc.

[0048] Opcode field, i.e. opcode field, with a bit width of 5 bits, used to indicate the data packet type and data width (e.g. 32 bits or 64 bits), for example: the Opcode field value "00000" corresponds to the type "32-bit memory read", indicating reading 32-bit data from the specified address; the Opcode field value "00001" corresponds to the type "32-bit memory write", indicating writing 32-bit data to the specified address; the Opcode field value "00100" corresponds to the type "32-bit configuration read", indicating reading 32-bit data from the configuration register; the Opcode field value "00101" corresponds to the type "32-bit configuration write", indicating writing 32-bit data to the configuration register; the Opcode field value "01000" corresponds to the type "64-bit memory read", indicating reading 64-bit data from the specified address; the Opcode field value "01001" corresponds to the type "64-bit memory write", indicating writing 64-bit data to the specified address; the Opcode field value "01100" corresponds to the type "64-bit configuration read", indicating reading 64-bit data from the configuration register; the Opcode field value "01101" corresponds to the type "64-bit configuration write", indicating writing 64-bit data to the configuration register; the Opcode field value "10000" corresponds to the type "no data completion"; the Opcode field value "10001" corresponds to the type "completion with 32-bit data"; the Opcode field value "10010" corresponds to the type "no data message"; the Opcode field value "11001" corresponds to the type "completion with 64-bit data"; the Opcode field value "11011" corresponds to the type "message with 64-bit data"; and other values of the Opcode field are reserved or extended operations, used for future extension or other special operations.

[0049] SrcID field, i.e. source identifier field, with a bit width of 3 bits. The SrcID field value "000" indicates "Stack 0 Protocol Layer"; the SrcID field value "001" indicates "D2D Adapter"; the SrcID field value "100" indicates "Stack 1 Protocol Layer"; and other values of the SrcID field are reserved.

[0050] DstID field, i.e. destination identifier field, with a bit width of 3 bits. The DstID field value "001" indicates "D2D Adapter"; the DstID field value "010" indicates "Physical Layer"; and other values of the DstID field are reserved.

[0051] CP field, Control Parity field, controls the parity field, 1 bit wide, is the parity of all the header bits except DP, CP field.

[0052] DP field, Data Parity field, data parity field, 1 bit wide, used for parity check on the data payload of the packet to check the correctness of the data content.

[0053] Addr field, Address field, request address field, 24 bits wide, different operation codes use the field in different ways, see the relevant UCIe specification for details.

[0054] BE field, Byte Enables field, requested byte enable field, 8 bits wide, BE field does not need to be continuous, if the operation code is used for 32-bit request, BE[7:4] is reserved.

[0055] EP field, Error Poison field, data poisoning field, 1 bit wide, if poisoning forwarding is enabled, the completer can poison the data when there is an internal error.

[0056] Tag field, Tag field, 5 bits wide, used to uniquely identify each outstanding request. The Tag field is a 5-bit field generated by the requester, which must be unique for all outstanding requests that need to be completed, and the original requester uses the tag to associate the returned completion with the original request.

[0057] Data field, Data field, 32 bits or 64 bits wide, Data field is the part of the packet used to transmit actual data, Data field is the core part of the packet. Data field can also be called payload, according to the operation code, it can be 32 bits or 64 bits wide.

[0058] For example, assuming that in a UCIe system, the sender needs to write 32-bit data "0x12345678" to a certain register of the receiver, the sender sets the Opcode field of the UCIe packet to "00001" (indicating 32-bit memory write), fills the data "0x12345678" into the Data field of the UCIe packet, and sends the packet. After receiving the packet, the receiver identifies it as a 32-bit write operation according to the Opcode field, and writes the data in the Data field to the register at the target address. The Data field supports multiple data widths and flexible data content, ensuring the efficiency and flexibility of data transmission.

[0059] As can be seen from the APB interface register access timing and the UCIe sideband register access request data packet, the APB signal contains target address information corresponding to the PADDR signal, transmission operation type information corresponding to the PWRITE signal, write data content corresponding to the PWDATA, and read data content corresponding to the PRDATA. In addition, the UCIe sideband register access request data packet contains data packet type corresponding to the Opcode field, address information corresponding to the Addr field, and data content corresponding to the Data field. Therefore, the content of the PWRITE signal can be associated with the content of the Opcode field, the content of the PADDR signal can be associated with the content of the Addr field, and the content of the PWDATA signal and the content of the PRDATA signal can be associated with the content of the Data field. Therefore, on this basis, the content of the APB interface received register access request timing signal can be translated into the content of the UCIe sideband register access request data packet, and transmitted by using the UCIe protocol. Therefore, in the illustrative embodiment, step 202 can further include: generating a corresponding UCIe sideband register access request data packet containing the same information content according to the information content carried in the APB protocol register access request timing signal.

[0060] In the illustrative embodiment, in the case of an APB protocol register access request timing signal being a register write request, i.e. in the case of the PWRITE signal in the APB interface received APB protocol register access request timing signal being "1", a corresponding UCIe sideband register access request data packet containing the same information content is generated according to the information content carried in the APB protocol register access request timing signal, which can specifically include: transmission operation type information is obtained from the PWRITE signal in the APB protocol register access request timing signal (i.e. the APB protocol register write request timing signal), and the Opcode field content in the UCIe sideband register access request data packet is generated according to the transmission operation type information; target address information is obtained from the PADDR signal in the APB protocol register access request timing signal (i.e. the APB protocol register write request timing signal), and the Addr field content in the UCIe sideband register access request data packet is generated according to the target address information; write data content is obtained from the PWDATA signal in the APB protocol register access request timing signal (i.e. the APB protocol register write request timing signal), and the Data field content in the UCIe sideband register access request data packet is generated according to the write data content; According to the UCIe protocol rule, other field contents in the UCIe sideband register access request data packet are generated.

[0061] In the illustrative embodiment, in the case of an APB protocol register access request timing signal being a register read request, that is, in the case of a PWRITE signal in the APB protocol register access request timing signal received by the APB interface being "0", according to the information content carried in the APB protocol register access request timing signal, a corresponding UCIe sideband register access request data packet containing the same information content is generated, which can specifically include: According to the PWRITE signal in the APB protocol register access request timing signal (that is, the APB protocol register read request timing signal) received from the APB interface, the transmission operation type information is obtained, and the Opcode field content in the UCIe sideband register access request data packet is generated according to the transmission operation type information. According to the PADDR signal in the APB protocol register access request timing signal (that is, the APB protocol register read request timing signal) received from the APB interface, the target address information is obtained, and the Addr field content in the UCIe sideband register access request data packet is generated according to the target address information. According to the UCIe protocol rule, other field contents in the UCIe sideband register access request data packet are generated.

[0062] In the illustrative embodiment, step 202 can be implemented in hardware. In the illustrative embodiment, the UCIe sideband register access request data packet generated by the local chip is temporarily stored in the buffer of the local chip, wherein the buffer of the local chip can be a hardware buffer implemented by hardware logic and conforming to the UCIe protocol requirement, and the buffer of the local chip can be used for temporarily storing the sideband data packet to be sent.

[0063] In the illustrative embodiment, the sending of the UCIe sideband register access request data packet to the destination layer in step 203 is based on the UCIe protocol implementation.

[0064] The register access signal conversion transmission method according to the embodiments of the present disclosure can use the APB protocol in part of the system on chip and the UCIe protocol in another part, and use an intermediate translation module or conversion module between the two to translate and convert the signals of the two protocols. Thus, the compatibility of the two in the same system on chip is realized, and the respective advantages of the APB protocol and the UCIe protocol are exerted, thereby helping to improve the compatibility of the communication connection protocol of the small chip and helping to reduce the design difficulty of the system on chip.

[0065] In the illustrative embodiment, the access destination register of the APB protocol register access request timing signal is any one of a local chip adaptation layer register, a local chip physical layer register, a remote die physical layer register, and a remote chip adaptation layer register.

[0066] In the illustrative embodiment, the APB protocol register access request timing signal does not include a register access request timing signal for accessing a local chip protocol layer register. Based on this, if the access destination register of the APB protocol register access request timing signal received from the APB interface of the local chip is a local chip protocol layer register, the register access signal conversion transmission method of the present embodiment further includes directly accessing the local chip protocol layer register through the APB interface.

[0067] In the illustrative embodiment, the access destination register of the APB protocol register access request timing signal does not include a remote chip protocol layer register. Based on this, if the access destination register of the APB protocol register access request timing signal received from the APB interface of the local chip is a remote chip protocol layer register, an error prompt information is directly returned through the APB interface.

[0068] In the illustrative embodiment, the register access signal conversion transmission method of the present embodiment can be executed in the protocol layer of the local chip. In the illustrative embodiment, the APB interface accesses the protocol layer of the local chip, and the APB interface does not access the adaptation layer of the local chip and the physical layer of the local chip. Based on the UCIe protocol, the protocol layer of the local chip, the adaptation layer of the local chip, and the physical layer of the local chip communicate through the FDI interface and the RDI interface of the UCIe protocol. In this way, because the physical connection path of the APB interface and the adaptation layer of the local chip and the physical layer of the local chip is omitted, the local chip register access interface is simplified, the integrated design difficulty is reduced, and the UCIe protocol is also compatible, the APB protocol of the local chip and the UCIe protocol are cooperated to work, the compatibility of the communication connection protocol of the small chip is improved, and the design difficulty of the system on chip is reduced.

[0069] In the illustrative embodiment, the accessed destination register is determined by the PADDR signal in the APB protocol register access request timing signal. If the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of the local chip protocol layer register, the destination register accessed by the APB protocol register access request timing signal is the local chip protocol layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of the local chip adaptation layer register, the destination register accessed by the APB protocol register access request timing signal is the local chip adaptation layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of the local chip physical layer register, the destination register accessed by the APB protocol register access request timing signal is the local chip physical layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of the remote chip physical layer register, the destination register accessed by the APB protocol register access request timing signal is the remote chip physical layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of the remote chip adaptation layer register, the destination register accessed by the APB protocol register access request timing signal is the remote chip adaptation layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of the remote chip protocol layer register, the destination register accessed by the APB protocol register access request timing signal is the remote chip protocol layer register.

[0070] In the illustrative embodiment, after the UCIe sideband register access request data packet is generated, transmission and analysis of the UCIe sideband register access request data packet are performed based on the UCIe protocol.

[0071] In the illustrative embodiment, in the case where the accessed destination register of the APB protocol register access request timing signal is the local chip adaptation layer register, the sending of the UCIe sideband register access request data packet to the destination layer in step 203 can include: sending the UCIe sideband register access request data packet to the adaptation layer of the local chip through the FDI interface.

[0072] In the illustrative embodiment, when the access destination register of the APB protocol register access request timing signal is a local chip physical layer register, the sending of the UCIe sideband register access request data packet to the destination layer in step 203 comprises: sending the UCIe sideband register access request data packet to the adaptation layer of the local chip through the FDI interface, and forwarding the UCIe sideband register access request data packet to the physical layer of the local chip through the RDI interface by the adaptation layer of the local chip.

[0073] In the illustrative embodiment, when the access destination register of the APB protocol register access request timing signal is a remote chip physical layer register or a remote chip adaptation layer register, the sending of the UCIe sideband register access request data packet is implemented based on the mailbox mechanism of the UCIe protocol.

[0074] Based on this, in the illustrative embodiment, when the access destination register of the APB protocol register access request timing signal is a remote chip physical layer register or a remote chip adaptation layer register, the sending of the UCIe sideband register access request data packet to the destination layer in step 203 comprises: writing the UCIe sideband register access request data packet into a mailbox register for remote chip register access.

[0075] The specific process of writing the UCIe sideband register access request data packet into the mailbox register for remote chip register access can specifically comprise: Generating multiple UCIe sideband register access request data packets, and sequentially writing the multiple UCIe sideband register access request data packets into the mailbox register in the adaptation layer of the local chip from the sideband through the FDI interface by the protocol layer of the local chip.

[0076] In the illustrative embodiment, based on the UCIe specification, the mailbox register is located in the adaptation layer of the local chip.

[0077] In the illustrative embodiment, the access destination register address in the UCIe sideband register access request data packet is consistent with the access destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal. In this way, it can be ensured that the APB protocol register access request received by the APB interface can be accurately implemented through the UCIe protocol.

[0078] No matter read request or write request, the initiator of the access request needs to get the corresponding access feedback to ensure the accuracy of the access execution. For example, the initiator of the read request needs to get the read data content, and the initiator of the write request needs to get the write confirmation feedback information. Therefore, after the UCIe sideband register access request data packet is sent to the destination layer in step 203, a subsequent process of obtaining related feedback information is needed. As shown in Figure 2 In addition to the above steps 201 to 203, the following steps 204 to 205 after step 203 are included in the illustrative embodiment.

[0079] Step 204, receiving and parsing the UCIe sideband register access completion data packet (UCIe Sideband Register Access Completion Packet), and generating an APB protocol register access completion timing signal according to the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with the UCIe sideband register access request data packet, and the UCIe sideband register access completion data packet and the UCIe sideband register access request data packet belong to the same APB protocol access corresponding data packet; Step 205, sending the APB protocol register access completion timing signal through the APB interface.

[0080] Figure 5 The UCIe sideband register access completion data packet format is shown in FIG. 5, which is according to an illustrative embodiment. As shown in Figure 5 The UCIe sideband register access completion data packet format is similar to the UCIe sideband register access request data packet format, and the difference is that the UCIe sideband register access completion data packet includes the rsvd field and the Status field, while the UCIe sideband register access request data packet includes the Addr field. The rsvd field, i.e. the reserved field, can be used for extension and compatibility improvement. The Status field, i.e. the status field, is used to indicate whether the register access operation is successful and other information.

[0081] Because the UCIe sideband register access completion data packet contains the data packet type corresponding to the Opcode field and the data content corresponding to the Data field, and the APB signal contains the transmission operation type information corresponding to the PWRITE signal, the write data content corresponding to the PWDATA, and the read data content corresponding to the PRDATA. Therefore, the content of the Opcode field can be associated with the content of the PWRITE signal, and the content of the Data field can be associated with the content of the PWDATA signal and / or the content of the PRDATA signal, so on this basis, the content of the UCIe sideband register access completion data packet can also be translated into an APB protocol register access completion timing signal, and returned to the sending end of the APB protocol register access request timing signal through the APB interface.

[0082] Through the processes of steps 201 to 203 and steps 501 to 502, a complete on-chip system interaction process can be completed, in which the request sending end sends a register access request based on the APB protocol, the register access request of the APB protocol is translated into a sideband register access request of the UCIe protocol, the sideband register access request of the UCIe protocol is sent, the sideband register access completion message of the UCIe protocol is received, the sideband register access completion message of the UCIe protocol is translated into a sideband register access completion message of the APB protocol, and the sideband register access completion message of the APB protocol is returned to the sending end. This process realizes the conversion between the APB protocol and the UCIe protocol, so that in the on-chip system, the data path based on the APB protocol is only connected to the protocol layer of the UCIe protocol of the chip, and the translation between the APB protocol and the UCIe protocol is completed by the protocol layer. The data path of the APB protocol can no longer access the adaptation layer and the physical layer, thereby simplifying the data link network of the APB protocol, reducing the design difficulty of the data link network of each chip in the on-chip network, and improving the compatibility between the APB protocol and the UCIe protocol.

[0083] Figure 6 is a schematic diagram of a remote chip register access process of the UCIe protocol, as shown in Figure 6 The process mainly includes the following steps 601 to 611.

[0084] In step 601, the protocol layer of the local chip sends mailbox target request information to the adaptation layer of the local chip through the FDI interface.

[0085] In this step, the protocol layer of the local chip can send a UCIe sideband register access request data packet to the adaptation layer of the local chip through the FDI interface, and write information into the mailbox of the adaptation layer of the local chip.

[0086] Step 602, the adaptation layer of the local chip checks the credit of the adapter of the remote chip, and generates a remote chip access request.

[0087] Step 603, the adaptation layer of the local chip sends the remote chip access request to the physical layer of the local chip through the RDI interface.

[0088] Step 604, the physical layer of the local chip sends the remote chip access request to the physical layer of the remote chip through the UCIe sideband.

[0089] Step 605, the physical layer of the remote chip sends the remote chip access request to the adaptation layer of the remote chip through the RDI interface.

[0090] Step 606, the adaptation layer of the remote chip decodes the remote chip access request to the physical layer of the remote chip through the RDI interface and performs a transaction for the remote chip access request.

[0091] Step 607, the adaptation layer of the remote chip sends the response for the remote chip access request to the physical layer of the remote chip through the RDI interface.

[0092] Step 608, the physical layer of the remote chip sends the response for the remote chip access request to the physical layer of the local chip through the UCIe sideband.

[0093] Step 609, the physical layer of the local chip sends the reply sideband data packet for the remote chip access request to the adaptation layer of the local chip through the RDI interface.

[0094] Step 610, the adaptation layer of the local chip updates the mailbox in the adaptation layer of the local chip with the information of the sideband data packet for the remote chip access request.

[0095] Step 611, when the mailbox in the adaptation layer of the local chip is updated, the protocol layer of the local chip obtains the mailbox request completion information from the adaptation layer of the local chip through the FDI interface.

[0096] This step can include that the protocol layer of the local chip obtains the information from the mailbox in the adaptation layer of the local chip.

[0097] When the register access request timing signal received from the APB interface of the local chip is for the case of accessing the remote chip register, the register access request of the APB protocol (the APB protocol register access request timing signal) can be translated into the sideband register access request of the UCIe protocol (the UCIe sideband register access request data packet), and then the remote chip register can be accessed in combination with the remote chip register access process of the UCIe protocol in steps 601 to 611, and the access feedback information of the UCIe protocol (such as the UCIe sideband register access completion data packet) can be translated into the access feedback information of the APB protocol (such as the register access completion timing signal of the APB protocol), and then sent to the requester of the register access request through the APB interface.

[0098] Figure 7 is a schematic diagram of one specific scenario of the register access signal conversion and transmission method of the embodiment of the present disclosure, and the scenario is the sideband register access process of the conversion from the APB protocol to the UCIe protocol. As shown in Figure 7 , the scenario mainly includes the following steps 701 to 709.

[0099] Step 701, in the chip design, the on-chip system level address space is planned in advance, including the addresses of various levels of registers, and then step 702 is performed.

[0100] Step 702, the on-chip system initiates a register access request through the APB interface, and then step 703 is performed.

[0101] Step 703, the protocol layer of the local chip analyzes the read-write type and address information and other contents of the register access request of the APB interface, and then one of steps 704 to 707 is performed according to the analysis result.

[0102] Step 704, in the case of accessing the local chip protocol layer register by the register access request, the local chip protocol layer register is directly accessed by the APB interface, and then the process is ended.

[0103] Step 705, in the case of accessing the adaptation layer register of the local chip or the physical layer register of the local chip by the register access request, the register access request of the APB interface is converted into a UCIe sideband register access request data packet, and then sent to the adaptation layer register of the local chip or the physical layer register of the local chip, and then step 708 is performed.

[0104] Step 706, in the case of accessing the adaptation layer register of the remote chip or the physical layer register of the remote chip by the register access request, a plurality of UCIe sideband register access request data packets are generated, and mailbox writing is performed, and then step 709 is performed.

[0105] Step 707, in the case of the register access request being access to the protocol layer register of the remote chip, reply error information to the system on chip through the APB interface, and then end the process.

[0106] Because the mailbox mechanism of the UCIe protocol does not support access to the protocol layer of the remote chip, the setting step 707 is performed to respond to the error.

[0107] Step 708, after receiving the UCIe sideband register access completion data packet, convert the UCIe sideband register access completion data packet back to the APB interface signal and reply to the system on chip, and then end the process.

[0108] Step 709, after waiting for the reply information of the remote chip, the protocol layer of the local chip reads the information of the mailbox, generates a UCIe sideband register access completion data packet, converts it back to the APB interface signal and replies to the system on chip, and then ends the process.

[0109] Based on the register access signal conversion transmission method of the embodiments of the present disclosure, each chip of the system on chip only needs to connect its protocol layer to the APB interface, use the UCIe protocol between its protocol layer and the adaptation layer and the physical layer, and between each chip, and perform translation between the APB protocol and the UCIe protocol in the protocol layer, so as to realize the compatibility of the two protocols of the entire system on chip and the simplification of the APB protocol data link of each chip.

[0110] Figure 8is a timing diagram of a local chip register access taking the read operation as an example. Wherein, clk is a clock signal; fdi_lp_cfg_vld is a lp_cfg_vld signal in the FDI interface, used to indicate whether the sideband information sent by the protocol layer to the adaptation layer is valid, when fdi_lp_cfg_vld is high, it means that the sideband information sent by the protocol layer is valid, and the adaptation layer will process the received sideband information, in different stages of data transmission, fdi_lp_cfg_vld signal will be independently set to 1, in the continuous data stage of transmitting the same data packet, fdi_lp_cfg_vld signal needs to be continuously set to 1 for several clock cycles, when the register access data packet is transmitted, the protocol layer will ensure that the adaptation layer correctly receives and processes the data through fdi_lp_cfg_vld signal; fdi_lp_cfg[31:0] is a sideband interface from the protocol layer to the adaptation layer in the FDI interface, used to transmit the sideband data packet content from the protocol layer to the adaptation layer, [31:0] means that the signal is a 32-bit signal; fdi_pl_cfg[31:0] is a sideband interface from the adaptation layer to the protocol layer in the FDI interface, used to transmit the sideband data packet content from the adaptation layer to the protocol layer, [31:0] means that the signal is a 32-bit signal, fdi_pl_cfg[31:0] signal corresponds to fdi_lp_cfg[31:0] signal, realizing the bidirectional communication between the protocol layer and the adaptation layer, this bidirectional communication mechanism allows effective data exchange between the protocol layer and the adaptation layer, thereby ensuring the normal operation of the entire UCIe link; rdi_lp_cfg_vld is a lp_cfg_vld signal in the RDI interface, used to indicate whether the sideband information sent by the adaptation layer to the physical layer is valid, when rdi_lp_cfg_vld signal is high, it means that the sideband information sent by the adaptation layer is valid, and the physical layer needs to process the received sideband information; PSel is a slave selection signal of APB protocol; PEnable is a transmission enable signal of APB protocol; PWrite is a write control signal of APB protocol; PAddr[31:0] is a target address signal of APB protocol, [31:0] means 32 bits; PWData[31:0] is a write data signal of APB protocol, [31:0] means 32 bits; PRData[31:0] is a read data signal of APB protocol, [31:0] means 32 bits; PReady is a ready signal of APB protocol.

[0111] As Figure 8The read access scenario timing is shown in the figure. At position 1, the system initiates a read operation through the APB interface. At position 2, the protocol layer generates a UCIe sideband register access request data packet and sends it to the adaptation layer through the FDI port. After the adaptation layer replies at position 3, the PReady signal of the APB interface is pulled up at position 4, and the read data is updated to the PRDATA signal. The system reads the data through the APB interface, and the read operation is completed.

[0112] Figure 9 The figure is a state diagram of a register access refinement process of a remote chip according to an illustrative embodiment. As shown in the figure, the refinement process state mainly includes the following state phases. Figure 9

[0113] 1. Mailbox initial reset state, which can also be referred to as MAILBOX_INIT state. In this state phase, a remote chip register access request is initiated by the APB interface. After receiving the remote chip register access request, the state jumps to the write mailbox index 0 state.

[0114] 2. Write mailbox index 0 state, which can also be referred to as WR_MAILBOX_INDDEX0 state. In this state phase, the protocol layer writes the Opcode field, BE field and low bits (0th bit to 18th bit) address information into the Adapter Sideband Mailbox Index Low register through the local chip UCIe sideband register access request data packet. After receiving the local chip UCIe sideband register access completion data packet returned by the adaptation layer, the state jumps to the write mailbox index 1 state. If the local chip UCIe sideband register access completion data packet is not received after timeout, or the UCIe sideband register access completion data packet with error information is received, the mailbox error state is entered. 3. Write mailbox index 1 state, which can also be referred to as WR_MAILBOX_INDDEX1 state. In this state phase, the protocol layer writes the high bits (19th bit to 23rd bit) address information into the Adapter Sideband Mailbox Index High register through the local chip UCIe sideband register access request data packet. After receiving the local chip UCIe sideband register access completion data packet returned by the adaptation layer, the state jumps to the write mailbox data state. If the mailbox state register information is a timeout error state, or the UCIe sideband register access completion data packet with error information is received, the mailbox error state is entered. ​4. WR_MAILBOX_DATA state, also called as write mailbox data state, in this state, the protocol layer writes the write data information (i.e. the content of PWDATA signal) of APB interface into the Adapter Sideband Mailbox Data register through the local chip UCIe sideband register access request data packet, if the register access request timing signal of APB interface is a read operation signal, this state can be skipped, after receiving the local chip UCIe sideband register access completion data packet returned by the adapter layer, jump to the WR_MAILBOX_TRG state, if the local chip UCIe sideband register access completion data packet is not received after timeout, or the UCIe sideband register access completion data packet with error information is received, then enter the mailbox error state; 5. WR_MAILBOX_TRG state, also called as write mailbox target state, in this state, the protocol layer sets the write / read trigger signal or control position of the Adapter Sideband Mailbox Control register to 1 through the local chip UCIe sideband register access request data packet, to inform the adapter layer that all information has been written, after receiving the local chip UCIe sideband register access completion data packet returned by the adapter layer, wait for the adapter layer to send the register access information in the mailbox to the remote chip, if the local chip UCIe sideband register access completion data packet returned by the adapter layer is not received after timeout, or the UCIe sideband register access completion data packet with error information is received, then the mailbox state register displays error information; in this state, the Adapter Sideband Mailbox Control register can be read at regular intervals, after the write / read trigger signal changes from 1 to 0, or a mailbox flow end signal is returned to the protocol layer by the adapter layer, then the reply information in the mailbox can be read, i.e. jump to the read mailbox state; 6、RD_MAILBOX_STATUS state, also known as mailbox status reading state, in this state, the protocol layer reads the adapter sideband mailbox status register through the local chip UCIe sideband register access request packet, if the read information is success, it indicates that the current access is successful, and then jumps to the mailbox data reading state, if the read information is CA (Completer Abort, completer aborts the operation, usually because the completer cannot complete the requested operation, or encounters an error in the processing process) or UR (Unsupported Request, unsupported request, indicating that the request is not supported, usually because the type, format or parameter of the request is beyond the capability range), it indicates that the current access is abnormal, and the mailbox status register displays error information; if the local chip UCIe sideband register access completion packet is not received after timeout, or the UCIe sideband register access completion packet with error information is received, the mailbox error state is entered; 7、RD_MAILBOX_DATA state, also known as mailbox data reading state, in this state, the execution corresponds to the register read request of the APB interface received register access request timing signal, the protocol layer reads the adapter sideband mailbox data register through the local chip UCIe sideband register access request packet, sends the read data to the PRDATA signal interface of the APB interface, and pulls the PReady signal of the APB interface to high level, then ends the process and returns to the mailbox initial reset state; if the local chip UCIe sideband register access completion packet is not received after timeout, or the UCIe sideband register access completion packet with error information is received, the mailbox error state is entered; if the register access request timing signal received by the APB interface is a register write request, the adapter sideband mailbox data register is not read in the mailbox data reading state, only the PReady signal of the APB interface is pulled to high level, then the process is ended and returns to the mailbox initial reset state; 8、MAILBOX_ERROR state, also known as mailbox error state, this state indicates that the register access is timeout or abnormal, directly returns error information to the system sending the register access request timing signal through the PSLVERR signal of the APB interface, informs that the current register access fails, then ends the process and returns to the mailbox initial reset state.

[0115] The register access signal conversion transmission method of the embodiment of the present disclosure simplifies the complexity of the data link design of the system on chip composed of small chips based on the APB protocol, helps to reduce the design difficulty of the data link, and further helps to reduce the design difficulty of the system on chip, and helps to improve the compatibility of the APB protocol and the UCIe protocol in the same system on chip. In the case that different small chips in the system on chip are independently designed by different design teams and the small chips support the UCIe protocol, the register access signal conversion transmission method of the embodiment of the present disclosure can be used in the specified small chip in the system on chip according to the design requirements, and further helps to simultaneously exert the respective advantages of the APB protocol and the UCIe protocol in the system on chip.

[0116] Figure 10 is a chip schematic diagram according to an illustrative embodiment, as shown in Figure 10 The chip includes a UCIe interface defined by the UCIe protocol and an APB interface defined by the APB protocol. The chip further includes a conversion module located in the protocol layer of the UCIe interface, configured to: receive an APB protocol register access request timing signal from the APB interface; generate a UCIe sideband register access request data packet according to the APB protocol register access request timing signal; and send the UCIe sideband register access request data packet.

[0117] In the illustrative embodiment, the conversion module is further configured to: in response to receiving a UCIe sideband register access completion data packet, generate an APB protocol register access completion timing signal according to the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with the UCIe sideband register access request data packet; and send the APB protocol register access completion timing signal through the APB interface.

[0118] Figure 11 is a register access method schematic diagram of the APB protocol in the related art, as shown in Figure 11 In the chip, the register access method of the APB protocol needs to design the wiring structure of each part of the chip for the APB protocol, including the wiring structure of the protocol layer register, the wiring structure of the adaptation layer register, and the wiring structure of the physical layer register for the APB protocol.

[0119] From Figure 10 and Figure 11It can be seen from the comparison that the chip adopting the embodiment of the present disclosure only needs to set a conversion module for signal translation and conversion between the APB protocol and the UCIe protocol in the protocol layer of the chip, and then the register access request can be sent to the local chip through the APB protocol in the case that the APB protocol only accesses the protocol layer, and at the same time, based on the UCIe protocol, the local chip can also send the register access request to the remote chip through the APB protocol. Because the APB protocol only accesses the protocol layer and does not access the adaptation layer and the physical layer in the chip, the chip can no longer be designed to access the adaptation layer and the physical layer for the APB protocol, and therefore the design difficulty of the chip is reduced.

[0120] In the illustrative embodiments, a system-on-chip is also provided, which includes at least one small chip of the integrated package. At least one of the at least one small chip adopts the chip of the above-mentioned embodiment.

[0121] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A register access signal conversion and transmission method, comprising: Receive APB protocol register access request timing signal from the APB interface of the local chip; Generate a UCIe sideband register access request data packet according to the APB protocol register access request timing signal; Sending the UCIe sideband register access request data packet to the destination layer; Receive and parse a UCIe sideband register access completion data packet, and generate an APB protocol register access completion timing signal according to the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with the UCIe sideband register access request data packet, and wherein the UCIe sideband register access completion data packet and the UCIe sideband register access request data packet belong to data packets corresponding to the same APB protocol access; The APB protocol register access completion timing signal is sent through the APB interface.

2. The register access signal conversion and transmission method according to claim 1, wherein: The access destination register of the APB protocol register access request timing signal is any one of a local chip adaptation layer register, a local chip physical layer register, a remote chip physical layer register, and a remote chip adaptation layer register.

3. The register access signal conversion and transmission method according to claim 2, wherein: In a case where the access destination register of the APB protocol register access request timing signal is the local chip adaptation layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is sent to the adaptation layer of the local chip through the FDI interface.

4. The register access signal conversion and transmission method according to claim 2, wherein: In a case where the access destination register of the APB protocol register access request timing signal is the local chip physical layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is sent to the adaptation layer of the local chip through the FDI interface, and the adaptation layer forwards the UCIe sideband register access request data packet to the physical layer of the local chip through the RDI interface.

5. The register access signal conversion and transmission method according to claim 2, wherein: In a case where the access destination register of the APB protocol register access request timing signal is the remote chip physical layer register or the remote chip adaptation layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is written to a mailbox register for remote chip register access.

6. The register access signal conversion and transmission method according to claim 5, wherein: The mailbox register is located in the adaptation layer of the local chip.

7. The register access signal conversion and transmission method according to claim 1, wherein: In a case where the access destination register of the APB protocol register access request timing signal is a local chip protocol layer register, the method further includes: The local chip protocol layer register is directly accessed through the APB interface.

8. The register access signal conversion and transmission method according to claim 1, wherein: The local chip includes a protocol layer, an adaptation layer, and a physical layer defined by the UCIe protocol; The APB interface accesses the protocol layer; The protocol layer and the adaptation layer communicate via an FDI interface of the UCIe protocol, and the adaptation layer and the physical layer communicate via an RDI interface of the UCIe protocol.

9. The register access signal conversion and transmission method according to claim 1, wherein: The access destination register address in the UCIe sideband register access request data packet is consistent with the access destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal.

10. A chip, characterized in that: The chip includes a UCIe interface defined by the UCIe protocol and an APB interface defined by the APB protocol; wherein, The chip further includes: A conversion module, located in the protocol layer of the UCIe interface, configured to: receiving an APB protocol register access request timing signal from the APB interface; generating a UCIe sideband register access request data packet according to the APB protocol register access request timing signal; and sending the UCIe sideband register access request data packet; and In response to receiving a UCIe sideband register access completion data packet, an APB protocol register access completion timing signal is generated according to the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with the UCIe sideband register access request data packet; and the APB protocol register access completion timing signal is sent through the APB interface.

11. A system on chip, characterized in that: include: at least one small chip in an integrated package; At least one of the at least one small chip adopts the chip according to claim 10.

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