An in-board synchronization platform and method based on RFSoC

Abstract

The application relates to the technical field of signal synchronous acquisition, and discloses an in-board synchronous platform and method based on RFSoC, which comprises a clock generation module, a radio frequency clock module and a multi-channel signal acquisition module integrated on the same acquisition board card, the output end of the clock generation module is connected with the input end of the radio frequency clock module, the output end of the radio frequency clock module and the output end of the clock generation module are respectively connected with the input end of the multi-channel signal acquisition module; the clock generation module sends an acquisition clock signal to the radio frequency clock module, the radio frequency clock module sends a synchronous acquisition signal to the multi-channel signal acquisition module based on the acquisition clock signal; the clock generation module sends a logic synchronous clock and an analog-digital synchronous clock to the multi-channel signal acquisition module, so as to perform delay distribution synchronization and pulse trigger synchronization on the multiple signal acquisition channels. The beneficial effect is that the signal acquisition channels in the acquisition board card can perform synchronous signal acquisition, and the integration and synchronism of the acquisition board card are effectively improved.

Description

Technical Field

[0001] This application relates to the field of signal synchronization acquisition technology, and in particular to an on-board synchronization platform and method based on RFSoC. Background Technology

[0002] A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to achieve precise regulation of electromagnetic wave transmission and reception. In a phased array, multiple antenna elements are arranged according to a specific pattern to form an array. By changing the phase and amplitude of the transmitted or received signals of each antenna element, the signals interfere with each other in space, achieving flexible beam pointing and precise focusing. A phased array system can have up to thousands of receiving channels. These channels are designed on one or more acquisition boards, forming multiple on-board synchronization platforms. The system clock design within these on-board synchronization platforms is a key element in ensuring the synchronization between the signals from multiple channels.

[0003] In related technologies, the system clock design within the on-board synchronization platform is too complex, and its integration level still needs to be improved. Summary of the Invention

[0004] This application provides an on-board synchronization platform and method based on RFSoC. A clock generation module generates a clock signal and sends it to multiple modules integrated on the same acquisition board, providing a synchronous clock basis for each module. This enables the signal acquisition channels in the acquisition board to acquire signals synchronously, effectively improving the integration and synchronization of the acquisition board.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide an on-board synchronization platform based on RFSoC, including a clock generation module, an RF clock module, and a multi-channel signal acquisition module integrated on the same acquisition board, wherein:

[0007] The output terminal of the clock generation module is connected to the input terminal of the radio frequency clock module, and the output terminal of the radio frequency clock module and the output terminal of the clock generation module are respectively connected to the input terminal of the multi-channel signal acquisition module.

[0008] The clock generation module sends a sampling clock signal to the radio frequency clock module, and the radio frequency clock module sends a synchronous sampling signal to the multi-channel signal sampling module based on the sampling clock signal, so that multiple signal sampling channels in the multi-channel signal sampling module can perform synchronous signal sampling.

[0009] The clock generation module sends a logic synchronization clock and an analog-digital synchronization clock to the multi-channel signal acquisition module to perform delay distribution synchronization and pulse trigger synchronization on the multiple signal acquisition channels based on the logic synchronization clock and the analog-digital synchronization clock; wherein the logic synchronization clock and the analog-digital synchronization clock are same-frequency signals with a constant phase difference.

[0010] The in-board synchronization platform based on the RFSoC integrates the clock generation module, the radio frequency clock module and the multi-channel signal acquisition module on the same acquisition board card, generates clock signals uniformly by the clock generation module and sends the clock signals to the multiple modules to provide synchronization clock basis for the multiple modules; on this basis, the multiple synchronization clock signals of the same frequency and constant phase difference are sent to the multi-channel signal acquisition module, so that the multiple synchronization clock signals can be used to perform synchronization processing on the multiple signal acquisition channels in the multi-channel signal acquisition module, and multi-channel synchronization in the acquisition board card is realized. Compared with the related art, the synchronization clock tree integrated in the acquisition board card is built based on a single clock generation module in the present application, the clock signals are distributed to different modules through the synchronization clock tree, so that the multiple synchronization clock signals of the same source can be used to perform synchronization processing on the signal acquisition channels in the acquisition board card, so that the signal acquisition channels in the acquisition board card can perform synchronous signal acquisition, and the integration and synchronization of the acquisition board card are effectively improved.

[0011] Optionally, the clock generation module and the multi-channel signal acquisition module are connected in a direct current coupling manner to send the logic synchronization clock and the analog-digital synchronization clock to the multi-channel signal acquisition module.

[0012] Optionally, the multiple signal acquisition channels include a first channel and a second channel, and the analog-digital synchronization clock performs pulse trigger synchronization between the first channel and the second channel.

[0013] Optionally, the logic synchronization clock and the analog-digital synchronization clock are also used to perform delay distribution synchronization on the multiple signal acquisition channels.

[0014] Optionally, the in-board synchronization platform further includes a clock frequency division module, an input end of the clock frequency division module is connected with an output end of the clock generation module, and the clock frequency division module is configured to receive a reference clock signal generated by the clock generation module, and generate a parallel data output clock and a back-end signal processing clock.

[0015] Optionally, a clock frequency of the reference clock signal is an integer multiple or a fractional multiple of a clock frequency of the parallel data output clock.

[0016] Optionally, the maximum frequency of the logic synchronous clock and the analog-digital synchronous clock does not exceed a preset upper limit of clock frequency, and the clock frequency of each of the acquisition clock signal, the reference clock signal and the parallel data output clock is an integer multiple of the clock frequency of the logic synchronous clock and the analog-digital synchronous clock.

[0017] Optionally, the logic synchronous clock, the analog-digital synchronous clock and the acquisition clock signal are respectively generated according to an external reference clock or an internal reference clock.

[0018] Optionally, the radio frequency clock module is configured to multiply the acquisition clock signal to generate the synchronous acquisition signal.

[0019] In a second aspect, the embodiments of the present application provide an in-board synchronization method based on RFSoC, which is suitable for the in-board synchronization platform based on RFSoC in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0021] Figure 1 The clock tree structure diagram of the in-board synchronization platform based on RFSoC provided by the embodiments of the present application;

[0022] Figure 2 The hardware block diagram of the in-board synchronization platform in the embodiments of the present application;

[0023] Figure 3 The flowchart of the in-board synchronization method based on RFSoC in the embodiments of the present application;

[0024] Figure 4 The structural schematic diagram of a computer device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. The terms "comprises", "comprising", "includes", "including", "has", "having" and their variants are intended to be inclusive and allow for items not listed to be present.

[0027] A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to achieve precise control of electromagnetic wave transmission and reception. In a phased array system, multiple antenna elements are arranged in an array according to a certain rule, and by changing the phase and amplitude of the signals transmitted or received by each antenna element, the signals interfere with each other in space, achieving flexible pointing and precise focusing of the beam. The receiving channels in a phased array system can reach up to thousands, and these channels are designed on one or more acquisition board cards to form multiple in-board synchronization platforms, and the system clock design in the in-board synchronization platform is a key link to ensure the synchronization between multiple channels.

[0028] In related technologies, the system clock design in the in-board synchronization platform is usually limited by the development of semiconductor process level. Independent analog-to-digital converters (ADCs) are used to collect signals, and field-programmable gate arrays (FPGAs) are used to synchronize and analyze the signals collected by each channel based on J204B protocol for subsequent processing, thereby realizing the synchronization of multiple channels in the board. In the above scheme, the synchronization between channels is determined according to the quality of external clock signals and trigger signals. With the increase in the number of channels, the synchronization between channels is more susceptible to transmission delay and signal jitter between channels, thereby reducing the synchronization. In addition, the above scheme designs multiple independent components, and each independent component needs to be designed separately, so the system structure is complex and the overall integration is low, and the scalability is also limited by the complexity of independent components, resulting in the inability to improve the flexibility of the system.

[0029] Based on the above problems, the application provides an in-board synchronization platform and method based on RFSoC, including a clock generation module, a radio frequency clock module and a multi-channel signal acquisition module integrated on the same acquisition board card, the output end of the clock generation module is connected with the input end of the radio frequency clock module, and the output end of the radio frequency clock module and the output end of the clock generation module are respectively connected with the input end of the multi-channel signal acquisition module; the clock generation module sends an acquisition clock signal to the radio frequency clock module, the radio frequency clock module sends a synchronous acquisition signal to the multi-channel signal acquisition module based on the acquisition clock signal, so that multiple signal acquisition channels in the multi-channel signal acquisition module perform synchronous signal acquisition; the clock generation module sends a logic synchronization clock and an analog-digital synchronization clock to the multi-channel signal acquisition module, so as to perform delay distribution synchronization and pulse trigger synchronization on the multiple signal acquisition channels.

[0030] The in-board synchronization platform based on RFSoC provided by the application integrates the clock generation module, the radio frequency clock module and the multi-channel signal acquisition module on the same acquisition board card, generates clock signals uniformly by the clock generation module and sends the clock signals to multiple modules to provide synchronous clock basis for the multiple modules respectively; on this basis, multiple synchronous clock signals with the same frequency and constant phase difference are sent to the multi-channel signal acquisition module, so that the multiple synchronous clock signals can be used to perform synchronous processing on multiple signal acquisition channels in the multi-channel signal acquisition module, and multi-channel synchronization in the acquisition board card is realized.

[0031] Compared with the related art, the application builds a synchronous clock tree integrated in the acquisition board card based on a single clock generation module, distributes clock signals to different modules through the synchronous clock tree, so that the multiple synchronous clock signals can be used to perform synchronous processing on signal acquisition channels in the acquisition board card, and the signal acquisition channels in the acquisition board card can perform synchronous signal acquisition, thereby effectively improving the integration and synchronization of the acquisition board card.

[0032] The in-board synchronization platform based on RFSoC provided by the present specification can be applied to a phased array system, which can be used in multiple fields such as the field of radio astronomy, the field of radar, the field of ultrasonic detection imaging and the field of meteorological detection, wherein in the field of radio astronomy, the phased array system can be used to build a phased array radio telescope to realize high-speed, real-time and synchronous acquisition and preprocessing of large-scale and wide-band radio frequency signals. It can be understood that, after adaptive modification, the application can also be used in other systems or devices for multi-channel signal acquisition, such as a multi-channel data acquisition system, a high-frequency trading system or an automatic test system.

[0033] The embodiment of the application provides an in-board synchronization platform based on RFSoC, including a clock generation module, a radio frequency clock module and a multi-channel signal acquisition module integrated on the same acquisition board card, wherein:

[0034] The output end of the clock generation module is connected with the input end of the radio frequency clock module, and the output end of the radio frequency clock module and the output end of the clock generation module are respectively connected with the input end of the multi-channel signal acquisition module.

[0035] The clock generation module sends an acquisition clock signal to the radio frequency clock module, and the radio frequency clock module sends a synchronous acquisition signal to the multi-channel signal acquisition module based on the acquisition clock signal, so that the multiple signal acquisition channels in the multi-channel signal acquisition module perform synchronous signal acquisition.

[0036] The clock generation module sends a logic synchronous clock and an analog-digital synchronous clock to the multi-channel signal acquisition module, so as to perform delay distribution synchronization and pulse trigger synchronization on the multiple signal acquisition channels based on the logic synchronous clock and the analog-digital synchronous clock; wherein the logic synchronous clock and the analog-digital synchronous clock are same-frequency signals and have a constant phase difference.

[0037] Referring to Figure 1 As shown in the figure, the in-board synchronization platform provided by the embodiment is integrated on the acquisition board card, and includes a clock generation module, a radio frequency clock module and a multi-channel signal acquisition module. The clock generation module is used to generate a same-origin clock signal and send it to multiple modules on the acquisition board card, so as to build a synchronous clock tree integrated in the acquisition board card based on a single clock generation module, and provide a synchronous clock basis for multiple modules. The clock generation module can include a single clock chip, which has multiple output interfaces to be connected with multiple modules. It can be understood that the single clock chip uniformly outputs clock signals, reduces clock drift and error between multiple clock signals, and improves the timing consistency between clock signals. In addition, the single clock chip also simplifies the hardware design on the acquisition board card, reduces the complexity of the modules, and improves the hardware stability and use convenience of the acquisition board card.

[0038] Further, the output end of the clock generation module is connected with the input end of the radio frequency clock module and the input end of the multi-channel signal acquisition module, and based on the connection with the radio frequency clock module, the acquisition clock signal is sent to the radio frequency clock module, and based on the connection with the multi-channel signal acquisition module, a logic synchronous clock PL_SYSREF and an analog-digital synchronous clock AMS_SYSREF are sent to the multi-channel signal acquisition module. It should be noted that the clock generation module corresponds to a clock frequency range, and can output clock signals in the corresponding frequency range to the connected modules through the output interface. The acquisition clock signal can be a low-frequency clock signal, and its frequency is within the clock frequency range corresponding to the clock generation module. For example, the frequency of the acquisition clock signal can be 250MHz.

[0039] The logic synchronization clock can be a low-frequency reference signal for providing a delay measurement observation window for the plurality of signal sampling channels in the delay assignment synchronization, so that each signal sampling channel can measure a respective delay value within a certain time range as a data basis for the delay assignment synchronization. The frequency of the logic synchronization clock is within the clock frequency range corresponding to the clock generation module. For example, the frequency of the logic synchronization clock can be 10 MHz.

[0040] The analog-digital synchronization clock can be a low-frequency reference signal for setting a delay measurement starting reference for the plurality of signal sampling channels in the delay assignment synchronization, so that each signal sampling channel can perform delay assignment synchronization according to the same clock reference. The frequency of the analog-digital synchronization clock is within the clock frequency range corresponding to the clock generation module. For example, the frequency of the analog-digital synchronization clock can be 10 MHz.

[0041] Specifically, the radio frequency clock module is configured to receive the acquisition clock signal sent by the clock generation module, and obtain a synchronous acquisition signal based on the acquisition clock signal, so as to synchronously send the synchronous acquisition signal to the multi-channel signal acquisition module, and provide a synchronous clock basis for the signal acquisition process of the signal acquisition channel, so that the plurality of signal acquisition channels can perform synchronous signal acquisition. The radio frequency clock module can include a radio frequency clock chip (RF Clock Chip) for generating and managing a radio frequency signal clock. The synchronous acquisition signal provided by the radio frequency clock chip to the multi-channel signal acquisition module has the advantages of low phase noise, accurate stability, and high signal quality.

[0042] Further, the input end of the radio frequency clock module is connected to the output end of the clock generation module, and the output end of the radio frequency clock module is connected to the input end of the multi-channel signal acquisition module. After receiving the acquisition clock signal, the radio frequency clock module performs clock operation on the acquisition clock signal to obtain a synchronous acquisition signal, which is sent to the multi-channel signal acquisition module. When the frequency of the synchronous acquisition signal is outside the clock frequency range corresponding to the clock generation module, the clock generation module cannot directly generate the synchronous acquisition signal for the multi-channel signal acquisition module, and needs to perform clock operation on the acquisition clock signal through the radio frequency clock module, so as to generate a synchronous acquisition signal that meets the actual needs. For example, the clock operation can be clock frequency multiplication or clock phase adjustment.

[0043] It should be noted that the synchronous acquisition signal can be a high-frequency clock signal for use as a sampling clock when each signal acquisition channel performs signal acquisition, so as to ensure that each signal acquisition channel can perform synchronous signal acquisition. The frequency of the synchronous acquisition signal can be outside the clock frequency range corresponding to the clock generation module. For example, the frequency of the synchronous acquisition signal can be 4 GHz.

[0044] Specifically, the multi-channel signal acquisition module is configured to receive the synchronous acquisition signal sent by the radio frequency clock module, and synchronously distribute the synchronous acquisition signal to multiple signal acquisition channels inside the multi-channel signal acquisition module, so that the multiple signal acquisition channels in the multi-channel signal acquisition module can perform synchronous signal acquisition based on the synchronous acquisition signal. The multi-channel signal acquisition module includes two or more signal acquisition channels, and parallel signal acquisition is performed through the signal acquisition channels to obtain the required target signal. All signal acquisition channels work in the same working mode and are configured with the same working parameters. For example, the multi-channel signal acquisition module can be an RFDC IP core, and the signal acquisition channel can be an analog-to-digital converter (ADC) channel. After the analog signal is acquired through signal acquisition, the analog signal is converted into a digital signal for subsequent further signal processing and analysis. The working parameters of the signal acquisition channel can include mixing method, NCO center frequency, decimation rate, parallel channel number, and clock frequency of AXI bus, etc.

[0045] Further, the input end of the multi-channel signal acquisition module is connected with the output end of the radio frequency clock module and the output end of the clock generation module, respectively, receives the synchronous acquisition signal from the radio frequency clock module based on the connection with the radio frequency clock module, and receives the logic synchronous clock and the analog-digital synchronous clock from the clock generation module based on the connection with the clock generation module. In some embodiments, the multi-channel signal acquisition module can be provided with only a single input end, which can be the input end of a first channel of the multiple signal acquisition channels. After receiving an external input signal, the first channel distributes the input signal to other signal acquisition channels inside the multi-channel signal acquisition module to work according to the input signal. It can be understood that at this time, the first channel serves as a reference channel for all signal acquisition channels and is in an activated state in subsequent synchronization processing and synchronous acquisition. Other signal acquisition channels are synchronized with the first channel, effectively improving the synchronization between the signal acquisition channels. In addition, the single input end also reduces the hardware resources required for setting up the multi-channel signal acquisition module, reduces the complexity of module connection design on the acquisition board card, and improves the integration of the acquisition board card.

[0046] Further, before the multiple signal acquisition channels start synchronous signal acquisition, the multi-channel signal acquisition module receives the logic synchronous clock and the analog-digital synchronous clock sent by the clock generation module, takes the logic synchronous clock and the analog-digital synchronous clock as reference clocks, and performs delay distribution synchronization on the signal acquisition channels according to the logic synchronous clock and the analog-digital synchronous clock, and performs pulse trigger synchronization on the signal acquisition channels according to the analog-digital synchronous clock, thereby eliminating the delay error and phase error between different signal acquisition channels, so that the multiple signal acquisition channels can be aligned in time sequence, and the synchronization consistency of each signal acquisition channel is improved. It should be noted that the logic synchronous clock and the analog-digital synchronous clock are generated by the clock generation module, and have the same clock frequency and a constant phase difference.

[0047] In some embodiments, the process of delay assignment synchronization comprises: enabling the logic synchronization clock and the analog synchronization clock, ensuring that the analog synchronization clock is in a periodic continuous output state; performing state checking on the acquisition board card and the multi-channel signal acquisition module, ensuring that both are in a normal working state and delay assignment synchronization can be performed; calling an API function to perform delay initialization on multiple signal acquisition channels; the multiple signal acquisition channels in the multi-channel signal acquisition module stably capture the logic synchronization clock and the analog synchronization clock, automatically test the FIFO delay values of the signal acquisition channels based on the logic synchronization clock and the analog synchronization clock, and obtain the respective FIFO delay values of each signal acquisition channel; in the case that the FIFO delay values corresponding to each signal acquisition channel are the same, it is determined that each signal acquisition channel has completed delay synchronization, and the delay assignment synchronization process is ended; in the case that the FIFO delay values corresponding to each signal acquisition channel are different, the maximum FIFO delay value is taken out from all FIFO delay values, and a redundant delay design is performed on the basis of the FIFO delay value to obtain a target delay value; the target delay value is assigned to each signal acquisition channel, the delay value of each signal acquisition channel is set to the target delay value, and delay assignment synchronization is completed. Exemplarily, the redundant delay design can be to increase a delay of 16 clock periods on the basis of the maximum FIFO delay value.

[0048] In some embodiments, the process of pulse trigger synchronization comprises: closing the reference signal receiver of each signal acquisition channel, stopping receiving the analog-digital synchronization clock; calling an API function to perform initial phase setting on each signal acquisition channel, and setting the mixed trigger source of each signal acquisition channel to the analog-digital synchronization clock; opening the reference signal receiver of each signal acquisition channel, so that each signal acquisition channel synchronously receives the analog-digital synchronization clock; capturing multiple cycles of the analog-digital synchronization clock, taking the pulse signal of the analog-digital synchronization clock in each cycle as a trigger signal, performing phase synchronization on each signal acquisition channel, and repeatedly activating the initial phase setting of each signal acquisition channel; closing the reference signal receiver of each signal acquisition channel after the multiple cycles of the analog-digital synchronization clock, and stopping receiving the analog-digital synchronization clock; performing phase acquisition on each signal acquisition channel to obtain the phase difference between each signal acquisition channel; performing individual phase setting on each signal acquisition channel according to the phase difference between each signal acquisition channel, to perform phase compensation on each signal acquisition channel so that the phases of all signal acquisition channels are the same; opening the reference signal receiver of each signal acquisition channel, and repeatedly activating the individual phase setting of each signal acquisition channel using multiple cycles of the analog-digital synchronization clock; closing the reference signal receiver of each signal acquisition channel after the multiple cycles of the analog-digital synchronization clock, and stopping receiving the analog-digital synchronization clock, to lock the phase setting of each signal acquisition channel and ensure the phase synchronization between the signal acquisition channels. It should be noted that pulse trigger synchronization is applicable to acquisition board cards with digital functions, to eliminate the phase error that may exist in each signal acquisition channel when performing digital functions. The digital function can be a function of digitally processing the collected signal, such as digital quadrature demodulation.

[0049] Referring to Figure 2 As shown in the figure, the in-board synchronization platform provided by the embodiment comprises an input interface, a clock generation module, an RFSoC series FPGA processing chip, a DDR storage module, a power module, and an output interface. The input interface comprises 8 RF signal acquisition interfaces and 2 clock signal interfaces. The clock generation module is connected with the clock signal interface, and generates various clock signals required by the in-board synchronization platform by receiving a 10MHz reference clock sent from outside. The RFSoC series FPGA processing chip is integrated with an RFdc IP core, and can simultaneously perform analog-digital conversion or digital processing on the analog signals input by the 8 RF signal acquisition interfaces. The DDR storage module is used to expand the data storage capacity of the in-board synchronization platform. The power module comprises a Core PWR and a PWR Conn, and provides the voltage required in the signal acquisition process of the in-board synchronization platform. The output interface comprises 4 QSFP28 optical ports and 1 GE Ethernet interface, wherein the single-port communication rate of the QSFP28 optical port can reach 100Gbps.

[0050] The in-board synchronization platform based on the RFSoC provided in the embodiment integrates the clock generation module, the radio frequency clock module and the multi-channel signal acquisition module on the same acquisition board card, generates clock signals uniformly through the clock generation module and sends the clock signals to the multiple modules to provide synchronous clock basis for the multiple modules respectively; on this basis, the multi-path synchronous clock signals with the same frequency and constant phase difference are sent to the multi-channel signal acquisition module, so that the multi-path synchronous clock signals can be used to perform synchronous processing on the multiple signal acquisition channels in the multi-channel signal acquisition module, and multi-channel synchronization in the acquisition board card is realized.

[0051] Compared with the related art, the application builds the synchronous clock tree integrated in the acquisition board card based on a single clock generation module, distributes the clock signals to different modules through the synchronous clock tree, so that the multi-path homologous clock signals can be used to perform synchronous processing on the signal acquisition channels in the acquisition board card, and the signal acquisition channels in the acquisition board card can perform synchronous signal acquisition, effectively improving the integration and synchronization of the acquisition board card.

[0052] As an embodiment of the application, the clock generation module and the multi-channel signal acquisition module are connected in a direct current coupling mode to send the logic synchronous clock and the analog-digital synchronous clock to the multi-channel signal acquisition module.

[0053] Specifically, the clock generation module and the multi-channel signal acquisition module are connected in a direct current coupling mode, and the clock generation module directly sends the logic synchronous clock and the analog-digital synchronous clock to the multi-channel signal acquisition module. It can be understood that in the case of alternating current coupling, the reference signal receiver is very sensitive to noise interference when it is closed and just turned on, and may produce unpredictable synchronous glitch pulses, so the stability of the clock signal needs to be ensured before the reference signal receiver is turned on. Compared with the alternating current coupling that may cause the synchronous glitch pulses, the direct current coupling mode can reduce the clock offset when the clock signal is sent to the multi-channel signal acquisition module, and improve the synchronization between the multiple signal acquisition channels in the multi-channel signal acquisition module. In addition, the direct current coupling does not require additional electronic elements, reduces the complexity of system design, and ensures the flexibility of function expansion on the acquisition board card.

[0054] As an embodiment of the application, the multiple signal acquisition channels respectively include a first channel and a second channel, and the analog-digital synchronous clock performs pulse trigger synchronization between the first channel and the second channel.

[0055] Specifically, the first channel can be any one of the plurality of signal acquisition channels, and the second channel can be any one of the plurality of signal acquisition channels other than the first channel. In the case where the multi-channel signal acquisition module is provided with only a single input end, the single input end can be the input end of the first channel, and the first channel distributes the input signal to other signal acquisition channels after receiving the input signal from outside, so as to work and synchronize according to the input signal.

[0056] In some embodiments, the phase difference between each second channel and the first channel is determined with the phase of the first channel as a reference. Each second channel is individually phase-set according to the phase difference between the first channel and each second channel, so as to compensate the phase of each second channel. After the individual phase setting, the individual phase setting of each second channel is activated by the trigger of the analog-digital synchronization clock, so that the first channel and the second channel reach a phase synchronization state.

[0057] It can be understood that the first channel is the reference channel of all signal acquisition channels, and is in an activated state in the synchronization processing and acquisition process. The second channel is synchronized with the first channel, thereby effectively improving the synchronization between the signal acquisition channels. In addition, the single input end also reduces the hardware resources required by the multi-channel signal acquisition module, reduces the complexity of the module connection design on the acquisition board card, and improves the integration of the acquisition board card.

[0058] As an embodiment of the present application, the logic synchronization clock and the analog-digital synchronization clock are also used for delay distribution synchronization of the plurality of signal acquisition channels.

[0059] Specifically, the delay distribution synchronization can include a synchronization preparation process, a synchronization detection process and a distribution synchronization process. The synchronization preparation process includes: enabling the logic synchronization clock and the analog-digital synchronization clock, ensuring that the analog-digital synchronization clock is in a periodic and continuous output state; performing state checking on the acquisition board card and the multi-channel signal acquisition module, ensuring that both are in a normal working state and can perform delay distribution synchronization; calling an API function to initialize the delay of the plurality of signal acquisition channels.

[0060] The synchronization detection process includes: the plurality of signal acquisition channels in the multi-channel signal acquisition module stably capture the logic synchronization clock and the analog-digital synchronization clock, automatically test the FIFO delay value of the signal acquisition channel based on the logic synchronization clock and the analog-digital synchronization clock, and obtain the respective FIFO delay value of each signal acquisition channel; in the case where the FIFO delay values of the respective signal acquisition channels are the same, it is determined that the delay synchronization of the respective signal acquisition channels has been completed, and the delay distribution synchronization process is ended.

[0061] The allocation synchronization process comprises: in the case that the FIFO delay values corresponding to the signal acquisition channels are different, taking the maximum FIFO delay value from all the FIFO delay values, and performing a redundant delay design on the basis of the FIFO delay value to obtain a target delay value; allocating the target delay value to each signal acquisition channel, and setting the delay value of each signal acquisition channel to the target delay value to complete the delay allocation synchronization. Exemplarily, the redundant delay design can be to add a delay of 16 clock cycles on the basis of the maximum FIFO delay value.

[0062] As an embodiment of the present application, the in-board synchronization platform further comprises a clock frequency division module, an input end of the clock frequency division module being connected with an output end of the clock generation module, for receiving the reference clock signal generated by the clock generation module, and generating a parallel data output clock and a back-end signal processing clock.

[0063] Specifically, the clock frequency division module is configured to perform a frequency division operation on the reference clock signal, and generate the parallel data output clock and the back-end signal processing clock, so as to control the output and processing of the acquisition signals, and ensure the synchronization between different acquisition signals in the above process. The clock frequency division module can comprise a PL MMCM frequency divider, and the functions of the clock frequency division module include clock frequency conversion, clock phase control, clock frequency division and multiplication, and clock synchronization, etc.

[0064] Further, the input end of the clock frequency division module is connected with the output end of the clock generation module, and receives the reference clock signal generated by the clock generation module. Exemplarily, the frequency of the reference clock signal is within the clock frequency range corresponding to the clock generation module, for example, 250 MHz. The output end of the clock frequency division module is connected with a signal receiving and processing module, so as to take the parallel data output clock and the back-end signal processing clock as reference clocks, control the synchronous output of the acquisition signals from the signal acquisition channels through the parallel data output clock, and control the synchronous signal processing of the multi-channel acquisition signals through the back-end signal processing clock. Exemplarily, the signal receiving and processing module can comprise an RFSoC series FPGA processing chip, etc. Exemplarily, the frequency of the parallel data output clock can be within the clock frequency range corresponding to the clock generation module, or can be outside the clock frequency range corresponding to the clock generation module, for example, 250 MHz. Similarly, the frequency of the back-end signal processing clock can be within the clock frequency range corresponding to the clock generation module, or can be outside the clock frequency range corresponding to the clock generation module, for example, 350 MHz. The frequencies of the parallel data output clock and the back-end signal processing clock can be determined according to actual needs respectively.

[0065] As an embodiment of the present application, the clock frequency of the reference clock signal is an integer multiple or a fractional multiple of the clock frequency of the parallel data output clock.

[0066] Specifically, the clock frequency division module is configured to perform clock operations on the reference clock signal, including clock frequency multiplication and clock frequency division, to output the parallel data output clock and the back-end signal processing clock. In order to ensure consistency between the clock signals, the parallel data output clock needs to be synchronized with the reference clock signal. In the case where the clock frequency of the reference clock signal is an integer multiple or a fractional multiple of the clock frequency of the parallel data output clock, the parallel data output clock and the reference clock signal can still be accurately synchronized before and after the clock operation, thereby avoiding timing errors caused by the clock operation, ensuring the stability of the parallel data output clock as the reference clock, and improving the synchronization between the signal acquisition channels.

[0067] As an embodiment of the present application, the maximum frequency of the logic synchronization clock and the analog-digital synchronization clock does not exceed the preset upper limit of the clock frequency, and the clock frequencies of the acquisition clock signal, the reference clock signal and the parallel data output clock are all integer multiples of the clock frequencies of the logic synchronization clock and the analog-digital synchronization clock.

[0068] Specifically, the preset upper limit of the clock frequency can be 10MHz, avoiding the introduction of noise interference by high-frequency signals to ensure sufficient synchronization accuracy.

[0069] Further, the logic synchronization clock and the analog-digital synchronization clock are configured to perform delay assignment synchronization and pulse trigger synchronization on a plurality of signal acquisition channels, and the acquisition clock signal, the reference clock signal and the parallel data output clock are configured to control the acquisition, output and signal processing process of the acquisition signals by the acquisition board card. It can be understood that if the clock domains of different modules cross without forming a good synchronization state, it may cause loss or misplacement of signal data, affecting the synchronization of the signal acquisition and processing process. By designing the clock frequency relationship between the logic synchronization clock, the analog-digital synchronization clock and the acquisition clock signal, the reference clock signal and the parallel data output clock, a consistent alignment relationship exists between the above-mentioned clock signals, ensuring the synchronization between the clock signals.

[0070] As an embodiment of the present application, the logic synchronization clock, the analog-digital synchronization clock and the acquisition clock signal are respectively generated according to an external reference clock or an internal reference clock.

[0071] Specifically, the external reference clock can be generated by a clock source such as a crystal oscillator or an atomic clock, usually having high precision and stability. The internal reference clock can be generated by a clock source such as a crystal oscillator integrated in the acquisition board card, and the external reference clock and the internal reference clock can be switched through a jumper cap, so that the clock source used can be flexibly selected. The clock generation module generates a logic synchronization clock, an analog-digital synchronization clock and an acquisition clock signal based on the external reference clock or the internal reference clock. The precision of the above-mentioned clock signals can be improved by means of the precision of the external reference clock, and it is ensured that they are not affected by the clock fluctuation or clock drift inside the in-board synchronization platform.

[0072] As an embodiment of the present application, a radio frequency clock module is used to multiply the acquisition clock signal to generate a synchronous acquisition signal.

[0073] Specifically, the frequency of the synchronous acquisition signal is outside the clock frequency range corresponding to the clock generation module, and the clock generation module cannot directly generate a synchronous acquisition signal for the multi-channel signal acquisition module, so it is necessary to multiply the acquisition clock signal through the radio frequency clock module to generate a synchronous acquisition signal that meets the actual needs. It can be understood that the radio frequency clock module can also convert a single acquisition clock signal into multiple synchronous synchronous acquisition signals, ensuring that each signal acquisition channel receives the same and synchronous synchronous acquisition signal.

[0074] Correspondingly, the present application provides an in-board synchronization method based on RFSoC, which is suitable for the in-board synchronization platform based on RFSoC in any of the above embodiments.

[0075] Referring to Figure 3 As shown in the figure, before the multiple signal acquisition channels start to perform synchronous signal acquisition, the logic synchronization clock and the analog-digital synchronization clock are used as reference clocks, the signal acquisition channels are delayed and distributed according to the logic synchronization clock and the analog-digital synchronization clock, and the signal acquisition channels are pulse triggered according to the analog-digital synchronization clock. It should be noted that the logic synchronization clock and the analog-digital synchronization clock are both generated by the clock generation module, and have the same clock frequency and constant phase difference.

[0076] Further, the process of delay assignment synchronization can comprise: enabling the logic synchronization clock PL_SYSREF and the analog-digital synchronization clock AMS_SYSREF, ensuring that the analog-digital synchronization clock AMS_SYSREF is in a periodic continuous output state; the RFDC IP core performing a state self-check, ensuring that it is in a normal working state; calling an API function XRFdc_MultiConverter_Sync to perform delay initialization on multiple signal acquisition channels; the multiple signal acquisition channels in the multi-channel signal acquisition module stably capturing the logic synchronization clock PL_SYSREF and the analog-digital synchronization clock AMS_SYSREF, performing automatic FIFO delay value testing on the signal acquisition channels based on the logic synchronization clock PL_SYSREF and the analog-digital synchronization clock AMS_SYSREF, and obtaining respective FIFO delay values of each signal acquisition channel; in the case that the FIFO delay values corresponding to the signal acquisition channels are the same, determining that the signal acquisition channels have completed delay synchronization, and ending the delay assignment synchronization process; in the case that the FIFO delay values corresponding to the signal acquisition channels are different, taking the maximum FIFO delay value from all FIFO delay values, and performing redundant delay design on the basis of the FIFO delay value to obtain a target delay value; assigning the target delay value to the signal acquisition channels, setting the delay value of each signal acquisition channel to the target delay value, and completing delay assignment synchronization. Exemplarily, the redundant delay design can be to increase a delay of 16 clock cycles on the basis of the maximum FIFO delay value.

[0077] Further, the process of pulse trigger synchronization can include: turning off the reference signal receiver of each signal acquisition channel by API function XRFdc_MTS_Sysref_Config, stopping receiving the analog synchronization clock AMS_SYSREF; calling API function XRFdc_SetMixerSettings to make initial phase setting for each signal acquisition channel, and calling API function XRFdc_UpdateEvent to apply configuration update to each signal acquisition channel; calling API function XRFdc_SetMixerSettings to set the mixing trigger source of each signal acquisition channel to the analog synchronization clock AMS_SYSREF, resetting the NCO initial phase of each signal acquisition channel by API function XRFdc_ResetNCOPhase, so as to make the initial phase setting effective; turning on the reference signal receiver of each signal acquisition channel by API function XRFdc_MTS_Sysref_Config, so that each signal acquisition channel synchronously receives the analog synchronization clock AMS_SYSREF; capturing multiple cycles of the analog synchronization clock AMS_SYSREF, taking the pulse signal of the analog synchronization clock AMS_SYSREF in each cycle as a trigger signal, and performing phase synchronization for each signal acquisition channel, so as to repeatedly activate the initial phase setting of each signal acquisition channel to align the phases of each signal acquisition channel; after the above multiple cycles of the analog synchronization clock AMS_SYSREF, turning off the reference signal receiver of each signal acquisition channel by API function XRFdc_MTS_Sysref_Config, and stopping receiving the analog synchronization clock AMS_SYSREF; performing phase acquisition for each signal acquisition channel, and obtaining the phase difference between each signal acquisition channel; making individual phase setting for each signal acquisition channel according to the phase difference between each signal acquisition channel, so as to perform phase compensation for each signal acquisition channel, so that the phases of all signal acquisition channels are the same; turning on the reference signal receiver of each signal acquisition channel, and repeatedly activating the individual phase setting of each signal acquisition channel by using multiple cycles of the analog synchronization clock AMS_SYSREF; turning off the reference signal receiver of each signal acquisition channel after the above multiple cycles of the analog synchronization clock AMS_SYSREF, and stopping receiving the analog synchronization clock AMS_SYSREF, so as to lock the phase setting of each signal acquisition channel, and ensure the phase synchronization between signal acquisition channels.

[0078] Please refer to Figure 4 , Figure 4is a structural schematic diagram of a computer device provided by an embodiment of the present application. As shown in the figure, the computer device comprises one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are communicatively connected to each other by different buses, and can be installed on a common mainboard or in other manners as needed. The processor can process instructions executed in the computer device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device such as a display device coupled to the interface. In some optional embodiments, multiple processors and / or multiple buses can be used together with multiple memories and multiple memory banks, if needed. Also, multiple computer devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 4 The processor 10 is taken as an example in the embodiment.

[0079] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic gate array, a generic array logic, or any combination thereof.

[0080] The memory 20 stores instructions executable by the at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0081] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function; the data storage area can store data created according to the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 20 can optionally include a memory remotely arranged with respect to the processor 10, which can be connected to the computer device through a network. Examples of the network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0082] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk; and the memory 20 can further include a combination of the above kinds of memories.

[0083] The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

[0084] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code originally stored in a remote storage medium or non-transitory machine readable storage medium and downloaded to a local storage medium to be stored, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, processor, microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the method shown in the above embodiments.

[0085] The embodiments of the present application provide a computer program product, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform the method of any of the embodiments of the present application.

[0086] Although the embodiments of the present application are described with reference to the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

[0087] The system, device, module or unit illustrated in the above embodiments can be specifically implemented by a computer chip or entity, or by a product with certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0088] For the convenience of description, the above device is described as various units divided by functions. Of course, the functions of each unit can be implemented in the same or multiple software and / or hardware when implementing the present application.

[0089] Those skilled in the art will appreciate that embodiments of the application can be readily used as a method, a system or a computer program product. Accordingly, the application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer-readable program code.

[0090] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0091] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0092] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0093] It should also be noted that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. In the context of the specification, the term "and / or" means "and" or "or", and the term "or" means "and" or "or". In the context of the specification, the term "exemplary" means "example" or "an example of".

[0094] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0095] The above only describes the embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of the claims of the present application.

[0096] Although the embodiments of the present application are described in conjunction with the drawings, those skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. An on-board synchronization platform based on RFSoC, characterized in that, This includes a clock generation module, an RF clock module, and a multi-channel signal acquisition module integrated on the same acquisition board, wherein: The output terminal of the clock generation module is connected to the input terminal of the radio frequency clock module, and the output terminal of the radio frequency clock module and the output terminal of the clock generation module are respectively connected to the input terminal of the multi-channel signal acquisition module. The clock generation module sends a sampling clock signal to the radio frequency clock module, and the radio frequency clock module sends a synchronous sampling signal to the multi-channel signal sampling module based on the sampling clock signal, so that multiple signal sampling channels in the multi-channel signal sampling module can perform synchronous signal sampling. The clock generation module sends a logical synchronization clock and an analog-to-digital (ADC) synchronization clock to the multi-channel signal acquisition module to perform delay allocation synchronization and pulse trigger synchronization on the multiple signal acquisition channels based on the logical synchronization clock and the ADC synchronization clock. The logical synchronization clock and the ADC synchronization clock are signals with the same frequency and a constant phase difference. The pulse trigger synchronization includes: capturing multiple cycles of the ADC synchronization clock; using the pulse signal of the ADC synchronization clock in each cycle as a trigger signal to perform phase synchronization on the multiple signal acquisition channels, repeatedly activating the initial phase settings of the multiple signal acquisition channels; performing phase acquisition on the multiple signal acquisition channels to obtain the phase difference between the multiple signal acquisition channels; performing individual phase settings on the multiple signal acquisition channels according to the phase difference to perform phase compensation on the multiple signal acquisition channels, making the phases of all signal acquisition channels the same; activating the reference signal receivers of the multiple signal acquisition channels, and repeatedly activating the individual phase settings of the multiple signal acquisition channels using the ADC synchronization clock over multiple cycles.

2. The intra-board synchronization platform according to claim 1, characterized in that, The clock generation module is connected to the multi-channel signal acquisition module via DC coupling to send the logic synchronization clock and the analog-to-digital synchronization clock to the multi-channel signal acquisition module.

3. The intra-board synchronization platform according to claim 1, characterized in that, The plurality of signal acquisition channels include a first channel and a second channel, and the analog-to-digital synchronization clock is pulse-triggered to synchronize between the first channel and the second channel.

4. The intra-board synchronization platform according to claim 1, characterized in that, The logical synchronization clock and the analog-to-digital synchronization clock are also used to perform delay allocation synchronization for the multiple signal acquisition channels.

5. The intra-board synchronization platform according to claim 1, characterized in that, The on-board synchronization platform also includes a clock divider module. The input of the clock divider module is connected to the output of the clock generation module, and is used to receive the reference clock signal generated by the clock generation module to generate a parallel data output clock and a back-end signal processing clock.

6. The intra-board synchronization platform according to claim 5, characterized in that, The clock frequency of the reference clock signal is an integer multiple or a fractional multiple of the clock frequency of the parallel data output clock.

7. The intra-board synchronization platform according to claim 5, characterized in that, The maximum frequency of the logic synchronization clock and the analog-to-digital synchronization clock does not exceed the preset upper limit of clock frequency, and the clock frequencies of the acquisition clock signal, the reference clock signal and the parallel data output clock are all integer multiples of the clock frequencies of the logic synchronization clock and the analog-to-digital synchronization clock.

8. The intra-board synchronization platform according to claim 1, characterized in that, The logic synchronization clock, the analog-to-digital synchronization clock, and the acquisition clock signal are generated based on an external reference clock or an internal reference clock, respectively.

9. The intra-board synchronization platform according to claim 1, characterized in that, The radio frequency clock module is used to multiply the frequency of the acquisition clock signal to generate the synchronous acquisition signal.

10. An on-board synchronization method based on RFSoC, characterized in that, Applicable to the on-board synchronization platform based on RFSoC according to any one of claims 1 to 9.

Images