Hardware implementation method of folding FFT (Fast Fourier Transform) operation system

Abstract

The invention discloses a hardware implementation method of a folding FFT (Fast Fourier Transform) operation system, and belongs to the technical field of radar signal processing. In a radar signal processing process, FFT (Fast Fourier Transform) operation of more than 1k points is often encountered, and only one-dimensional FFT is used, so that a large amount of resource consumption is caused, and the application of the FFT in some scenes with high sampling rates is limited. According to the method, the one-dimensional FFT with more than 1k points is disassembled into the FFT with two small points, and the effect of the one-dimensional FFT is achieved in cooperation with phase compensation. And meanwhile, the sampled signal is not always power of 2, so that a pre-processing module capable of zero padding / interception is matched. In this way, the FFT operation process of more than 1k points can be completed. According to the method, resource consumption caused by FFT operation of more than 1k points can be effectively reduced, and the area in chip design is optimized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of signal processing technology in the field of communication, and specifically relates to a hardware implementation method of a folded FFT operation system. BACKGROUND

[0002] Fourier transform is a widely used technique in the field of signal processing and mathematics. It represents a function as a weighted sum of sine and cosine functions of different frequencies, allowing the conversion of signals in the time domain to the frequency domain for analysis. Fourier transform was proposed by mathematician Joseph Fourier in the early 19th century and is still widely used in many fields, including communication, image processing, audio signal processing, etc.

[0003] In communication systems, Fourier transform is a key technology. By converting signals to the frequency domain, we can perform modulation, demodulation, and filtering operations on signals. Fourier transform enables signals to be transmitted and processed through different frequencies, achieving multiplexing and frequency band utilization. In addition, Fourier transform can help us analyze signal spectrum occupation and interference, etc., improving the performance and reliability of communication systems. In digital signal processing, Fourier transform is a basic tool. By converting signals from the time domain to the frequency domain, we can perform filtering, noise reduction, frequency analysis, etc. Fourier transform is also widely used in audio and video coding, data compression, and image processing. It provides an effective way to process and analyze digital signals and helps us extract useful information from complex data.

[0004] Fast Fourier Transform (FFT) is a method for computing Discrete Fourier Transform (DFT). It is an efficient algorithm for Fourier transform that can perform Fourier transform on signals in a short time. The core idea of FFT is to use the divide-and-conquer strategy, recursively decomposing DFT to greatly reduce its computational complexity.

[0005] The significance of FFT in the field of signal processing lies in its revolutionary efficiency (computational complexity from 0(N2) to 0(N logN)), which liberates the powerful Fourier analysis theory from the shackles of computational feasibility, making it a practical tool for real-time, large-scale, and low-cost applications in engineering practice. It is not only the core engine of almost all modern signal processing technologies such as spectrum analysis, filtering, compression, communication, imaging, etc., but also fundamentally changes the way engineers understand and process signals, laying the foundation for the digital signal processing era. Therefore, FFT is not just an algorithm, but a key bridge connecting signal processing theory and engineering practice, and one of the core technology pillars driving the development of the information age.

[0006] Although the FFT has excellent engineering application ability, in some specific scene conditions, the balance problem of resources and performance is faced. In some scenes, the FFT operation needs to be performed on a sampling signal of more than 1k points, which brings a huge resource consumption problem on the hardware platform. It is crucial to solve the resource consumption problem brought by the FFT operation of a large number of points, especially in the application scene of airborne radar and other extremely high sampling rate requirements, the implementation scheme of the FFT will significantly affect the actual performance of the system. Therefore, it is of great significance to study the hardware implementation method of the folded FFT operation system for reducing the resource consumption in the radar system. SUMMARY

[0007] The purpose of the application is to solve the resource consumption problem of more than 1k point FFT operation, and the hardware implementation method of the folded FFT is proposed to replace the one-dimensional FFT. The implementation scheme optimizes the storage resource consumption problem in the FFT operation process, and can effectively reduce the storage resource consumption problem by decomposing the FFT into two dimensions and performing one-dimensional FFT respectively.

[0008] Technical scheme: A hardware implementation method of a folded FFT operation system, the method first arranges Q-point data into M*N points in two dimensions, reads the data by column, pads zero to M0 points, performs N times of MO point FFT operation, introduces phase compensation operation, and writes the operation result back to DDR after intercepting M points. The N-point data is read by row and M times of FFT operation is performed, that is, the two-dimensional folded FFT operation is completed, and the result is equivalent to one-dimensional Q-point FFT operation. The specific steps are as follows:

[0009] 1) Zero padding initialization: after the system starts working, 0 is initialized and written into the RAM, which facilitates zero padding for non-2 power data; initialization needs to be performed again after each folded FFT operation is completed;

[0010] 2) Butterfly factor initialization: since the butterfly factor is needed for rotation in the FFT operation process, the butterfly factor is initialized and stored in the RAM when the system starts working, which facilitates data taking during operation;

[0011] 3) Transposing the read data in DDR: for Q-point FFT, the data is arranged in M*N points in two dimensions; when reading the data, M-point data is read by column N times, and the N reading processes are decomposed into reading fixed length M*G data (G

[0012] 4) FFT operation: The FFT operation adopts a step-by-step iteration architecture, and each step operation unit adopts FIFO and floating-point addition, subtraction, and multiplier to complete, that is, first, the previous half of the input data is stored in the FIFO, and when the latter half of the data is input, the data stored in the FIFO is read for addition and subtraction operation, wherein the addition result is output to the next step as the current output, and the subtraction result continues to be written into the FIFO. When the addition result is output, the subtraction result is also completely written into the FIFO. At this time, the subtraction result is read out and multiplied by the butterfly factor. The multiplication result is output as the current output and continues to flow into the next step;

[0013] 5) Bit reversal: The result of each step operation unit is stored in the RAM. Since the data entering in sequence is bit-reversed after the FFT operation, bit-reversal operation is required when reading the RAM result to obtain the sequential FFT result. Meanwhile, in order to further improve the efficiency, two RAMs are used for ping-pong operation;

[0014] 6) Phase compensation: The FFT result after bit reversal is subjected to floating-point multiplication operation with the phase compensation factor;

[0015] 7) FFT result transpose and write back DDR: The folded FFT first transposes the column dimension data, so the result after phase compensation needs to be transposed and written back to the original position when writing back DDR. The M0 point result is written into the RAM by column, and the N times of write-back process is decomposed into writing back fixed length MxG data (G

[0016] 8) Sequentially reading data in DDR: For I point FFT, the data is two-dimensionally folded and arranged into MxN point data. When the data is read for the second time, M times of N point data is read in row sequence. The read data is directly sent to the buffer FIFO for use by the next step;

[0017] 9) Repeat steps 4) to 5)

[0018] 10) Sequentially write back FFT result: The folded FFT sequentially processes the row dimension data for the second time, so the FFT result needs to be sequentially written back to the original position when writing back DDR. The FFT operation result is directly sent to the bit width conversion FIFO for writing back.

[0019] The beneficial effect of the method is that at least one depth Q RAM is needed when performing Q-point FFT operation, and if further improving the system efficiency, at least two RAMs are needed for ping-pong; meanwhile, the first-stage operation unit needs I / 2-depth FIFO buffer to input data and I / 4-depth RAM to store the twiddle factor; therefore, when Q is greater than 1024, the system will consume a large amount of resources; in the field of radar signal processing, the number of points that need to be operated by pulse compression is generally not more than 1M points, therefore, the FFT system with Q being 1024 points is used in the method to realize 1M-point FFT; through the method, one-dimensional 1M-point FFT can be decomposed into two-dimensional 1024-point FFT and once phase compensation calculation; the method effectively reduces the storage resource consumption caused by FFT operation, and is easier to realize in hardware deployment. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A hardware implementation method flowchart of the folding FFT operation system is shown in the figure.

[0021] Figure 2 A hardware implementation method architecture diagram of the folding FFT operation system is shown in the figure. DETAILED DESCRIPTION

[0022] The application will be further described below in combination with the drawings and specific embodiments, and it should be understood that the embodiments are only used to illustrate the application and not to limit the scope of the application.

[0023] In the example, the hardware implementation method architecture of the folding FFT operation system is as follows:

[0024] 1) Data transposition module: according to the use scenario, the commonly used data transposition point number is 32k or less, and the ram depth is set to 32k. Write from the specified row (in_start) to the specified row (in_end), and the input row number can be calculated. When outputting, output from the 0th row to the out_len-1th row, and in_start / in_end respectively complete the front zero padding (0 ～ in_start-1 is 0) and the rear zero padding (in_end+1 ～ out_len-1 is 0); read from the specified column (out_start) to the specified column (out_end), and the output column number can be calculated. When inputting, input from the 0th column to the in_len-1th column, and out_start / out_end respectively complete the front truncation (delete 0 ～ out_start-1 column) and the rear truncation (delete out_end+1~in_len-1 column);

[0025] 2) DDR read-write module: complete the read-write operation of DDR through AXI-Stream interface, the core module only needs to configure the read start address and read length, if it exceeds BURST_LENGTH, it is operated in several times. Because the interface bit width is 256bit, the read length needs to meet the multiple of 4, a synchronous FIFO with a width of 256 and a depth of 512 is placed at the output interface of the module for the use of the next stage module. The read module adds the dynamic configuration design of the application packet threshold, adjusts according to the configuration of the read length rd_length, achieves the compatibility of long and short read, and further improves the read efficiency. The specific implementation design is as follows: define the signal application packet threshold rd_hold_th, define the application read address counter r_addr_cnt and the read data return last counter r_rd_last_cnt (DDR returns a last signal after each read). Compare the difference value of the application packet threshold and the application read address counter and the read data return last counter, if the difference value is greater than the application packet threshold, stop continuing to apply the read address; otherwise, it can continue to apply. At the same time, it is necessary to ensure that the data buffer FIFO cannot lose data when it is back pressure full. In the extreme case, after applying threshold addresses, the data buffer FIFO is back pressure full, at this time, it is ensured that the difference value of the application packet can be cached, and crossbar cannot be occupied. The reference clock of DDR is 400MHz, the system main clock is 200MHz, and there is a cross clock domain problem. When processing, the read length arlen and the read address ardata need to be cached by asynchronous FIFO, the FIFO depth is set to 16, only for clock domain conversion processing, the crossbar is idle when the address and length in the asynchronous FIFO can be read, the programming full setting is 10, and the back pressure is updated to the read address read length enable; the data read from DDR also needs to do the same clock domain conversion operation by asynchronous FIOFO, the depth is also 16, the data in the asynchronous FIFO is read out, the valid signal is used as rd_en signal, and then it is entered into the synchronous FIFO to convert the bit width. The write operation is opposite, the write data is first entered into the synchronous FIFO to convert the bit width, and then it is entered into the asynchronous FIFO to convert the clock domain. The read-write DDR operation is realized by using AXI-Stream protocol in the user end, which simplifies the AXI4 logic. Taking the read port as an example, the read address channel only has addr, len, valid, ready four signals, the read channel only has data, valid, ready, last signal, and the write operation eliminates the write response channel;

[0026] 3) FFT operation unit module: its working scene needs to complete the FFT operation of maximum 1M points, and there are non-2 power number of data. Because the area generated by completing 1M point operation is too large, a two-dimensional folding architecture is adopted. According to the formula of FFT, it can be deduced that one FFT calculation is equivalent to two-dimensional FFT calculation, and after one-dimensional FFT is completed, the phase compensation coefficient is multiplied and two-dimensional convolution is performed. According to the FFT butterfly calculation graph, each level of FFT operation is the addition and subtraction of the first half data and the second half data, and the addition result is output to the next level, and the subtraction result is multiplied by the butterfly factor and output to the next level. Therefore, each level module needs to use FIFO to buffer the first half input, and the FIFO depth is half of the corresponding point number of the current level, such as the 10th level completing 1024-point FFT, which needs to buffer 512-point first half data; when the level is less than or equal to 5, register groups are used for storage, which will be more area-saving than using FIFO. When the second half data is input, the first half data buffered in the FIFO is read out for floating point addition and subtraction operation, and the addition result is output to the next level, and the subtraction result is written into the FIFO. When the addition result output is completed, the subtraction result is also completely written into the FIFO, and then the subtraction result is read out and multiplied by the butterfly factor, and the product result is sent to the next level module. While reading out the subtraction result, the first half of the data needed to do FFT of the next frame is written, and the above process is repeated. In order to further optimize the area, when the level is less than or equal to 5, the subtraction result is stored in the register group instead of using FIFO. After the calculation of the last level fft_level=1 module is completed, the output is written into the RAM, so that the calculated FFT result is in bitrevorder order, which needs to be rearranged for sequential output. The bitrevorder function can be easily realized in hardware, and the output is the address of the RAM data taken out by bit inversion. In order to improve the efficiency, 2 blocks of RAM are designed to complete the ping-pong processing, and the read and write of which RAM is determined by the design of the RAM empty and full flags to do the signal selection. When the next level anti-pressure FFT module is output, 2 frames of data can still be processed. At the same time, a small FIFO is used at the output interface to buffer the data read from the RAM and used for axis interface;

[0027] 4) Phase compensation module: this module completes the pipeline multiplication process of one-dimensional FFT result and phase compensation coefficient, and only one floating point complex multiplication operation unit is needed to complete the calculation, and a FIFO is used at the output port to complete the data buffering and signal back pressure.

Claims

1. A hardware implementation method for a folded FFT operation system, characterized in that The following steps are involved: 1) Zero-padding initialization: When the system starts working, it first initializes the RAM by writing 0 to facilitate zero padding of non-power-of-two data. Each time a folded FFT operation is completed, it needs to be re-initialized. 2) Butterfly factor initialization: Since the butterfly factor needs to be rotated during the FFT operation, the butterfly factor is initialized and stored in RAM after the system starts working to facilitate data retrieval during operation; 3) Transpose the data read from the DDR: For a Q-point FFT, the data is folded two-dimensionally into M×N point data. When reading data, first read M point data N times by column, and then decompose the N read processes into reading fixed-length M×G data each time (G<N). This can reduce N DDR reads to N / G DDR reads, further improving system efficiency. The read data is written to RAM by column. After all M×G data are read, they are transposed and output. At this time, the column-by-column zero padding is completed, and the output data is G times M0 point data (M0 is the power of 2 of the nearest M neighbor). 4) FFT operation: FFT operation adopts a step-by-step iterative architecture. Each level of operation unit uses FIFO and floating-point addition, subtraction, and multiplication to complete. That is, the first half of the input data is first stored in the FIFO. When the second half of the data is input, the data stored in the FIFO is read for addition and subtraction operations. The addition result flows into the next level as the output of the current level, and the subtraction result continues to be written into the FIFO. After the addition result is output, the subtraction result is also written into the FIFO. At this time, the subtraction result is read out and multiplied with the butterfly factor. The multiplication result continues to flow into the next level as the current output; 5) Bit Reversal: The results of each level of operation unit are stored in RAM. Since the sequential data is bit-reversed after the FFT operation, a bit-reversal operation is required when reading the RAM results to obtain the sequential FFT results. At the same time, to further improve efficiency, two RAMs are used for ping-pong operation. 6) Phase compensation: Perform floating-point multiplication on the bit-reversed FFT result and the phase compensation factor; 7) Transpose the FFT results and write them back to DDR: The folded FFT first transposes the column-dimensional data. Therefore, when writing the phase-compensated results back to DDR, they also need to be transposed and written back to their original position. The result at point M0 is written to RAM by column, and the N write-back processes are broken down into writing back data of a fixed length of M×G each time (G<N). This reduces the N write-backs to DDR to N / G reads from DDR, further improving system efficiency. The data size written back to RAM is M0×G, while the effective data size is M×G, so the interception work is completed during the write-back process. 8) Sequentially read data from DDR: For a 1-point FFT, the data is folded two-dimensionally into M×N points. When reading the data a second time, the N-point data is read M times in row order. The read data is directly sent to the cache FIFO for use by the next level. 9) Repeat steps 4) to 5) 10) Sequentially write back FFT results: The folded FFT processes the row-dimensional data sequentially for the second time, so when writing back to DDR, the FFT results also need to be written back to the original location in sequence; the results of the FFT operation are directly sent to the bit width conversion FIFO and wait for writing back.

2. The DDR reading process according to claim 1, wherein: Define the packet request threshold signal rd_hold_th, the request read address counter r_addr_cnt, and the read data return last count r_rd_last_cnt (DDR returns a last signal after each read). Compare the packet request threshold with the difference between the request read address count and the read data return last count. If the difference is greater than the packet request threshold, stop requesting read addresses; otherwise, continue requesting. At the same time, ensure that data is not lost if the data buffer FIFO is backpressured and full. In the extreme case, after requesting the threshold number of addresses, the data buffer FIFO is backpressured and full. In this case, the difference in the request packet can be buffered and the crossbar will not be occupied.

3. The process of transposing data read from a DDR according to claim 1, characterized in that: The read data is written into the transposition RAM, starting from the specified row (in_start) and ending at the specified row (in_end). The two can calculate the number of input rows. When outputting, the data is output from row 0 to row out_len-1. In_start / in_end respectively complete the leading zero padding (rows 0 to in_start-1 are 0) and trailing zero padding (rows in_end+1 to out_len-1 are 0). When reading from the specified column (out_start) and ending at the specified column (out_end), the two can calculate the number of output columns. When inputting, the data is fully input from column 0 to column in_len-1. Out_start / out_end respectively complete the leading truncation (deleting columns 0 to out_start-1) and trailing truncation (deleting columns out_end+1 to in_len-1).

4. The FFT operation process according to claim 1, characterized in that: Each module level requires a FIFO to cache the first half of its input. The FIFO depth is half the number of points corresponding to the current level. For example, to complete a 1024-point FFT at level 10, the first half of the 512-point data needs to be cached. When the number of levels is 5 or less, using a register bank for storage saves more space than using a FIFO. When the second half of the data arrives, the first half of the data cached in the FIFO is read out for floating-point addition and subtraction. The addition result is simultaneously output to the next level, and the subtraction result is written to the FIFO. Once the addition result is output, the subtraction result is also written to the FIFO. The subtraction result is then read out and multiplied with the butterfly factors, and the product is sent to the next module level. While the subtraction result is being read out, the first half of the data required for the next FFT frame is written, and the process repeats. To further optimize area, when the number of levels is 5 or less, the subtraction result is stored in the register bank instead of using FIF0.

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