Threshold symmetric memristor-based synaptic plastic mechanism bionic circuit

Abstract

The invention discloses a synaptic plastic mechanism bionic circuit based on a threshold symmetric memristor, and relates to the technical field of bionic circuits, the bionic circuit comprises a pre-synaptic neuron circuit, the threshold symmetric memristor and a post-synaptic neuron circuit; the bionic circuit is divided into an excitatory synaptic moldability mechanism circuit and an inhibitory synaptic moldability mechanism circuit according to a synaptic moldability mechanism; the design method of the circuit comprises the following steps: firstly, designing neuron waveforms before and after synapse, then traversing changes of memristive synapse conductance values at different time intervals to obtain a corresponding curve of the conductance changes and the time intervals, verifying the fitting degree of a biological synapse plastic mechanism curve and the curve, and if the fitting degree is low, determining that the biological synapse plastic mechanism curve is not matched with the curve. And if not, redesigning the pulse waveforms before and after synapse. The synaptic plasticity mechanism simulated by the bionic circuit provided by the invention and a biological synaptic STDP mechanism model have a small fitting error, the provided design method is higher in universality, circuit parameters can be adjusted according to different memristors, and different forms of biological synaptic plasticity mechanisms can be simulated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of bionic circuit, in particular to a synaptic plasticity mechanism bionic circuit based on threshold symmetric memristor. BACKGROUND

[0002] In today's era of rapid development of science and technology, the cross field of neuroscience and electronic engineering is giving birth to many breakthrough innovations. As the most sophisticated and complex information processing system in nature, the brain transmits and stores information between neurons through synapses. Synaptic plasticity, which refers to the dynamic adjustment of synaptic connection strength according to neuron activity, is considered as the core mechanism of high-level cognitive functions such as learning and memory.

[0003] With the deepening of the mystery of the brain, researchers are committed to simulating this magical biological process at the hardware level, which has given rise to the study of bionic circuits based on memristors. As a new type of electronic component with resistance memory characteristics, the first titanium oxide-based thin film memristor model was developed by HP Labs in 2008, confirming Professor Chua's conjecture in 1971 that there is a fourth basic circuit element - memristor - in addition to resistance, capacitance, and inductance. Memristor has unique properties such as nonlinearity, passivity, and non-volatility when power is off. When the two ends of the memristor are subjected to the same pulse stimulation as the synapse, the conductance change is very similar to the change in synaptic weight. Therefore, the memristor is considered an ideal device for developing artificial synapses.

[0004] In recent years, in order to better explain the learning and memory functions of the biological brain, the spike-timing-dependent plasticity (STDP) learning rule has been proposed, which is a mechanism for adjusting synaptic strength in the brain through the relative time of presynaptic and postsynaptic pulses. It is the theoretical basis for biological neural networks to learn and adapt to external disturbances. In order to explore the research of brain-like bionic chips, researchers began to build synaptic circuits based on memristors and implement the STDP learning function. However, artificial synaptic circuits based on memristors have the same problem as traditional COMS synaptic circuits, which are single in simulation type and have unsatisfactory fitting results.

[0005] Chinese patent CN110428050A discloses a synaptic bionic circuit based on memristor to implement diversified STDP learning rules, including an enhancement module, an inhibition module, and a memristor synaptic module. The enhancement module and the inhibition module output different signals to the memristor synaptic module through the time sequence and time interval of the input signals, respectively. The memristor synaptic module changes the conductance of the memristor accordingly by receiving the signals, thereby simulating the synaptic plasticity mechanism. SUMMARY

[0006] The technical problems to be solved by the present application are to provide a synaptic plasticity mechanism bionic circuit and a design method with smaller fitting error and stronger universality.

[0007] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0008] The synaptic plasticity mechanism bionic circuit based on a threshold symmetric memristor is characterized in that the synaptic plasticity mechanism bionic circuit is divided into an excitatory synaptic plasticity mechanism bionic circuit and an inhibitory synaptic plasticity mechanism bionic circuit; the bionic circuit comprises a presynaptic neuron circuit, a postsynaptic neuron circuit and a threshold symmetric memristor, wherein the symmetric memristor simulates a biological synaptic unit, and the conductance value thereof simulates a synaptic weight.

[0009] The postsynaptic neuron circuits of the excitatory synaptic plasticity mechanism bionic circuit and the inhibitory synaptic plasticity mechanism bionic circuit are the same, and the presynaptic neuron circuits are different; the postsynaptic neuron circuit comprises a leakage integrator module, a switch module for generating a control pulse and a neural pulse generation module; wherein the leakage integrator module simulates a subthreshold membrane potential Vmem of a biological neuron, the switch module for generating a control pulse is realized by a monostable trigger, and when the membrane potential Vmem exceeds a preset Vthr, the module controls the neural pulse generation unit to generate a postsynaptic neuron pulse Post-spike.

[0010] Preferably, the leakage integrator module is composed of an inverse integration circuit and a comparator circuit, and is used for simulating generation of the subthreshold membrane potential Vmem of the biological neuron.

[0011] The input synaptic current Isyn is connected with the inverse input end of a first comparator, a capacitor C21, a resistor R21 and a switch sw1 respectively, the positive input end of the first comparator is connected with a resistor R22, the other end of the resistor R22 is grounded, the other end of the C21, the other end of the R21 and the other end of the sw1 are connected with the output end of the first comparator, the output end of the first comparator is connected with the inverse input end of a second comparator, the positive input end of the second comparator is connected with a comparison voltage Vthr, the output end of the second comparator is connected with a resistor R23 in parallel, and the other end of the R23 is grounded.

[0012] Preferably, the switch module for generating a control pulse is a pulse generation circuit composed of an integrated monostable trigger 74121, and is specifically as follows:

[0013] The 3, 4 pins of the integrated monostable trigger are grounded, the output end of the second comparator in the leakage integration module is connected with the 5 pin through a comparison operation circuit, the 6 pin is connected with the resistor R31 and the output end of the module respectively, the other end of the R31 is grounded, the 10 pin is connected with the capacitor C30, the other end of the C30 is connected with the resistor R30 and the 11 pin respectively, the other end of the R30 is connected with Vcc.

[0014] Preferably, the nerve pulse generation module is specifically as follows:

[0015] One end of the current source I1 is grounded, and the other end is connected with the left port of the switch sw2; one end of the capacitor Cm is grounded, and the other end is connected with the left port of the switch sw2; one end of the resistor RI is grounded, and the other end is connected with the left port of the switch sw2 and the base of the transistor Q1 respectively; one end of the resistor R1 is grounded, and the other end is connected with the emitter of the transistor Q1; the negative pole of the power supply VNa+ is grounded, and the positive pole is connected with the emitter of the transistor Q2; the base of the Q2 is connected with the collector of the Q1, and the collector of the Q2 is connected with the left port of the sw2; the negative pole of the power supply VK+ is grounded, and the positive pole is connected with the emitter of the transistor Q3, and the collector of the Q3 is connected with the right port of the sw2; one end of the capacitor Cr is grounded, and the other end is connected with the base of the Q3 and one end of the resistor Rr respectively, and the other end of the Rr is connected with the right port of the sw2; one end of the current source I2 is grounded, and the other end is connected with the right port of the sw2; the right port of the sw2 is connected with one end of the sw3 through a voltage offset circuit, and the other end of the sw3 is used as an output end.

[0016] Preferably, the design method of the circuit comprises the following steps:

[0017] 1) design the pre-and post-synaptic neuron pulse waveform, and apply the ideal waveform to both ends of the memristive synapse;

[0018] 2) set the memristive synapse to be in the same initial state, change △t to obtain the memristive conductance variable △G(△t) curve;

[0019] 3) use the biological excitatory synaptic plasticity mechanism model and the inhibitory synaptic plasticity mechanism model to fit the △G(△t) curve, if it can be fitted, it means that the pre-and post-synaptic neuron pulse waveform meets the requirements of the bionic circuit design, otherwise, adjust the pre-and post-synaptic neuron pulse waveform parameters, and continue to execute the second step;

[0020] 4) if the pre-and post-synaptic neuron pulse waveform meets the requirements of the bionic circuit design, then design the post-synaptic neuron circuit according to the post-synaptic neuron pulse waveform, use the ideal segmented voltage source to simulate the pre-synaptic neuron pulse waveform, and then verify the fitting degree of the biological synaptic plasticity mechanism curve and the △G(△t) curve again, if it can be fitted, the bionic circuit design is completed, otherwise, return to the first step.

[0021] Preferably, the designed pre- and post-synaptic neuron pulse waveforms include:

[0022] When designing a bionic circuit for excitatory synaptic plasticity, the waveforms of the pulses from the front and back neurons must meet the following conditions: when Δt < 0, the voltage difference applied to the memristive synapse is negative, and as |Δt| decreases, the area of ​​the negative pulse that exceeds the negative threshold of the memristor increases. When Δt > 0, the voltage difference Vpost - Vpre applied to the memristive synapse is positive, and as |Δt| decreases, the area of ​​the positive pulse that exceeds the positive threshold of the memristor increases.

[0023] When designing a bionic circuit with inhibitory synaptic plasticity mechanism, the waveforms of the preceding and following neuronal pulses must meet the following conditions: when |△t| is less than the steady-state window t wisp When two pulses are applied to the two ends of the memristor synapse, the voltage difference that finally acts on the memristor synapse is a positive pulse, and as |△t| decreases, the area of ​​the positive pulse that exceeds the positive threshold of the memristor becomes larger; when |△t| is greater than the steady-state window t wisp When two pulses are applied to the two ends of the memristor synapse, the voltage difference that finally acts on the memristor synapse is a negative pulse, and as |△t| increases, the area of ​​the negative pulse that exceeds the negative threshold of the memristor becomes larger and finally fixed to a certain value.

[0024] Preferably, the presynaptic neuron circuit generates presynaptic neuron pulses, and the excitatory presynaptic neuron circuit is implemented by a segmented independent ideal voltage source or an FPGA digital circuit, and its segmented mathematical expression is:

[0025]

[0026] in, are the highest and lowest potentials of Pre-spike, t p =-8μs is the starting point of the pulse waveform, and its absolute value also represents the positive pulse width, t n =32μs is the end point of the pulse waveform, and also represents the negative pulse width, τ p =5, τ n =40, time constants of positive and negative pulse waveforms respectively;

[0027] The inhibitory presynaptic neuron circuit is also implemented by a segmented independent ideal voltage source or an FPGA digital circuit, and its segmented mathematical expression is:

[0028]

[0029] in, t n0= 8us, t n1 = 15us, t n2 = 25us, t n1 = t p1 = 15 is a-b section and a1-b1 section time constant, t n0 = 2 is c-b section time constant, t p0 = 10 is the time constant of d-e section.

[0030] The beneficial effects generated by the above technical scheme are:

[0031] The bionic circuit provided by the application has a small fitting error in simulating the synaptic plasticity mechanism and the synaptic STDP mechanism mathematical model by designing reasonable pre-synaptic and post-synaptic pulse waveforms of neurons.

[0032] The application simulates the weight by using the conductance value of the memristor, and controls the conductance of the memristor by the waveform across the memristor, according to different memristors, by adjusting the parameters of the pre-synaptic and post-synaptic neuron circuit, different forms of biological synaptic plasticity mechanism model can be simulated, and a basic unit is provided for brain-like computing hardware.

[0033] The bionic circuit provided by the application is not only suitable for the case that a single memristor is used as a synapse, but also suitable for a synaptic array composed of multiple memristors, the adjustment of the conductance of multiple memristors can be realized, and the scale of brain-like computing hardware containing large-scale synaptic circuits can be greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0034] The application will be further described in detail below in combination with the drawings and specific embodiments.

[0035] Figure 1 is a schematic diagram of a biological excitatory synaptic plasticity mechanism model according to the application;

[0036] Figure 2 is a schematic diagram of a biological inhibitory synaptic plasticity mechanism model according to the application;

[0037] Figure 3 is a bionic circuit block diagram of a synaptic plasticity mechanism based on a threshold symmetric memristor according to the application;

[0038] Figure 4 is a schematic diagram of a design method of a bionic circuit of a synaptic plasticity mechanism based on a threshold symmetric memristor according to the application;

[0039] Figure 5 is a schematic diagram of a post-synaptic neuron circuit according to the application;

[0040] Figure 6 is a pre-synaptic and post-synaptic neuron pulse waveform in an excitatory synaptic plasticity mechanism bionic circuit according to the application

[0041] Figure 7 is a synaptic plasticity mechanism curve implemented by the excitatory synaptic plasticity mechanism simulation circuit in the embodiment of the present application;

[0042] Figure 8 is a presynaptic neuron pulse waveform of the inhibitory synaptic plasticity mechanism simulation circuit in the embodiment of the present application;

[0043] Figure 9 is a presynaptic neuron pulse waveform of the inhibitory synaptic plasticity mechanism simulation circuit in the embodiment of the present application;

[0044] Figure 10 is a synaptic plasticity mechanism curve implemented by the inhibitory synaptic plasticity mechanism simulation circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0045] The following examples illustrate the present application. The various raw materials and equipment used in the present application are all conventional commercially available products, and can be directly obtained by market purchase. In the description of the following examples, specific details such as specific system structures, techniques, etc. are presented for the purpose of illustration, but not for the purpose of limitation, so as to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details.

[0046] It should be understood that, when used in the specification and the appended claims of the present application, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be understood that, when used in the specification and the appended claims of the present application, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations thereof, and includes these combinations.

[0047] As used in the specification and the appended claims of the present application, the term "if" can be interpreted as "when" or "upon" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrases "if it is determined" or "if [a described condition or event] is detected" can be interpreted depending on the context as meaning "upon determining" or "in response to determining" or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]".

[0048] In addition, in the description of the present application and the appended claims, the terms "first", "second", "third", etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance. In the present application, the reference "one embodiment" or "some embodiments" means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in further some embodiments" and the like appearing in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "include", "contain", "have" and their variants mean "include but not limited to", unless otherwise specifically emphasized.

[0049] The present application proposes a synapse plasticity mechanism bionic circuit based on threshold symmetric memristor, which imitates the excitatory synapse plasticity mechanism and inhibitory synapse plasticity mechanism of biological synapse respectively. A large number of biological experimental data show that the change of synaptic weight is dependent on the timing change of pre-and post-synaptic nerve pulses, and this change is summarized as pulse timing dependent plasticity, and a synaptic STDP mechanism model is established based on this mechanism, as follows:

[0050] The biological excitatory synapse plasticity mechanism model is represented by formula 1 and formula 2:

[0051]

[0052] Wherein, is the excitatory synaptic weight change amount; as Figure 1 shown in (a), Δt=t post -t pre is the pulse time interval of pre-synaptic excitatory neuron Pre-E and post-synaptic excitatory neuron Post-E, when Pre-E fires a pulse before Post-E, Δt is defined as Δt<0, and vice versa Δt>0; τ + =τ - =20ms represents the time constant; and respectively describe the dependence of the current weight of the synapse, according to the results of biological experiments, the relationship between and usually satisfies α is an asymmetric parameter; and are the learning rates when the pre-synaptic and post-synaptic pulses arrive respectively; μ represents the degree of dependence of the weight change amount on the current weight of the synapse.

[0053] When α=1, When the excitatory synaptic plasticity mechanism described The curve of the change with Δt is as follows: Figure 1 As shown. It can be seen that when Pre-E releases pulses before Post-E, Explaining excitatory synaptic weights Increase, on the contrary, decreases; in addition, as |Δt| becomes smaller, the excitatory synaptic weight The greater the change.

[0054] The biological inhibitory synaptic plasticity mechanism model is represented by Equations 3 to 8:

[0055]

[0056] When presynaptic neuron i fires a spike:

[0057]

[0058] When the postsynaptic neuron j fires a spike:

[0059]

[0060] in, is the change in excitatory synaptic weight; τ isp is the decay time constant of the inhibitory synaptic plasticity mechanism trace variable, η is the learning rate, is the inhibition factor, and ρ0 represents the target firing rate of the postsynaptic neuron in Hz.

[0061] Biological inhibitory synaptic plasticity mechanisms such as Figure 2 As shown in Figure 2, it can be seen that each pair of presynaptic and postsynaptic pulses with different firing timings but the same firing time interval |Δt| produces almost the same change in the synaptic weight. In addition, when the firing times of the two neurons before and after the synapse are close to each other, making |Δt| less than the steady-state window t wisp When , it will cause inhibitory synaptic weight Long-term potentiation (Δw IE >0), and when the discharge moments are far away from each other, making |Δt| larger than the steady-state window t wisp When , it will cause inhibitory synaptic weight Long-term inhibition and changes in synaptic weights tends to a fixed value.

[0062] Based on the above mechanism model, the present invention is divided into excitatory synaptic plasticity mechanism bionic circuit and inhibitory synaptic plasticity mechanism bionic circuit; Figure 3As shown, the biomimetic circuit includes a presynaptic neuron circuit, a postsynaptic neuron circuit and a threshold symmetric memristor, wherein the symmetric memristor simulates a biological synapse unit, the conductance value G simulates a synaptic weight, and AG represents a weight change. In the mechanism model, the change of the synaptic weight is determined by the time interval At of the presynaptic and postsynaptic neuron pulses, but AG is determined by the pulse amplitude, pulse width and shape added to the memristor. Therefore, the correlation between AG and At and the design of the voltage pulse for modulating the synaptic conductance are the keys to realizing the synaptic plasticity mechanism biomimetic circuit.

[0063] As Figure 4 , the present application proposes a design method of a synaptic plasticity mechanism biomimetic circuit based on a threshold symmetric memristor, and the specific steps are as follows:

[0064] First, the presynaptic and postsynaptic neuron pulse waveforms are designed, and the ideal waveforms are applied to both ends of the memristive synapse.

[0065] When designing the excitatory synaptic plasticity mechanism biomimetic circuit, the presynaptic and postsynaptic neuron pulse waveforms need to meet the following conditions: when At < 0, the two pulses applied to both ends of the memristive synapse result in a negative pulse of the voltage difference finally acting on the memristive synapse, and as |At| decreases, the area of the negative pulse exceeding the negative threshold of the memristor becomes larger; when At > 0, the two pulses applied to both ends of the memristive synapse result in a positive pulse of the voltage difference finally acting on the memristive synapse, and as |At| decreases, the area of the positive pulse exceeding the positive threshold of the memristor becomes larger.

[0066] When designing the inhibitory synaptic plasticity mechanism biomimetic circuit, the presynaptic and postsynaptic neuron pulse waveforms need to meet the following conditions: when |At| is smaller than the steady-state window t wisp , the two pulses applied to both ends of the memristive synapse result in a positive pulse of the voltage difference finally acting on the memristive synapse, and as |At| decreases, the area of the positive pulse exceeding the positive threshold of the memristor becomes larger; when |At| is larger than the steady-state window t wisp , the two pulses applied to both ends of the memristive synapse result in a negative pulse of the voltage difference finally acting on the memristive synapse, and as |At| increases, the area of the negative pulse exceeding the negative threshold of the memristor becomes larger and finally fixed to a certain value.

[0067] Second, the memristive synapse is set to be in the same initial state, and AG(At) curves are obtained by changing At.

[0068] Third, the biological excitatory synaptic plasticity mechanism (A-eSTDP mechanism) model and the inhibitory synaptic plasticity mechanism (SH-iSTDP mechanism) model are used to fit the AG(At) curves. If the fitting is successful, it indicates that the presynaptic and postsynaptic neuron pulse waveforms meet the biomimetic circuit design requirements, otherwise the presynaptic and postsynaptic neuron pulse waveform parameters are adjusted and the second step is continued to be executed.

[0069] Fourth, if the pre-and post-synaptic neuron pulse waveform meets the requirements of the bionic circuit design, then the post-synaptic neuron circuit is designed according to the post-synaptic neuron pulse waveform, the pre-synaptic neuron pulse waveform is simulated by using an ideal segmented voltage source, and then the fitting degree of the biological synaptic plasticity mechanism curve and the △G(△t) curve is verified again, if the fitting is successful, the bionic circuit design is completed, otherwise, it returns to the first step.

[0070] In an embodiment, the post-synaptic neuron circuit is designed.

[0071] In the bionic circuit of the two mechanisms, the post-synaptic neuron circuit is the same, and the pre-synaptic neuron circuit is different.

[0072] As Figure 5 The post-synaptic neuron circuit includes a leakage integration module, a switch module for generating a control pulse, and a neural pulse generation module, wherein the leakage integration module is responsible for simulating the subthreshold membrane potential Vmem of a biological neuron, the switch module for generating a control pulse is realized by a monostable trigger, and when the membrane potential Vmem exceeds Vthr, the module controls the neural pulse generation unit to generate a post-synaptic neuron pulse Post-spike.

[0073] The leakage integration module is divided into two parts, a reverse integration circuit and a comparator circuit, and the synaptic current I syn is added to the reverse input end of the first comparator, the capacitor C21, the resistor R21, and one end of the switch sw1, and in the initial state, the analog switch sw1 is open, and the synaptic current I syn starts to charge the capacitor C21; the positive input end of the first comparator is connected with the resistor R22, the other end of the resistor R22 is grounded, the other end of C21, the other end of R21, and the other end of sw1 are connected with the output end of the first comparator, and R21 acts as a leakage resistor, which leaks part of the current during the charging of C21, so that the membrane potential Vmem presents a sawtooth downward trend; the output end of the first comparator is connected with the reverse input end of the second comparator, the positive input end of the second comparator is connected with the comparison voltage Vthr, and when the membrane potential exceeds the discharge threshold Vthr, the amplifier in the comparator circuit outputs Vout, and the output end of the second comparator is connected in parallel with the resistor R23, and the other end of R23 is grounded. The V out The comparison operation circuit realizes the function that when Vout is greater than -4V, the operation circuit outputs 5V, otherwise, it outputs 0V.

[0074] The switch module that controls pulse generation is a pulse generating circuit composed of an integrated monostable trigger 74121, which is responsible for receiving the signal from the leakage integration module and outputting the signal Vs1. Pins 3 and 4 of the monostable trigger are grounded, and pin 5 is connected to the output end of the output voltage comparison operation circuit of the leakage integration module. The output waveform of the monostable trigger is jointly controlled by pins 3, 4 and 5. Pin 10 is connected to capacitor C30, and the other end of C30 is connected to resistor R30 and pin 11 respectively. The other end of R30 is connected to Vcc. Capacitors C30 and R30 jointly control the width of the generated pulse. Pin 6 is connected to resistor R31 and the output end of this module respectively, and the other end of R31 is grounded.

[0075] The neural pulse generation module is controlled by analog switches sw2 and sw3, which are controlled by Vs1. When Vs1 is low, sw2 and sw3 are disconnected. When Vs1 is high, sw2 and sw3 are closed.

[0076] One end of the current source I1 is grounded, and the other end is connected to the left port of the switch sw2; one end of the capacitor Cm is grounded, and the other end is connected to the left port of the switch sw2; one end of the resistor RI is grounded, and the other end is respectively connected to the left port of the switch sw2 and the base of the transistor Q1; one end of the resistor R1 is grounded, and the other end is connected to the emitter of the transistor Q1; the negative electrode of the power supply VNa+ is grounded, and the positive electrode is connected to the emitter of the transistor Q2; the base of Q2 is connected to the collector of Q1, and the collector of Q2 is connected to the left port of sw2; The negative electrode of the source VK+ is grounded, and the positive electrode is connected to the emitter of the transistor Q3. The collector of Q3 is connected to the right port of sw2. One end of the capacitor Cr is grounded, and the other end is connected to the base of Q3 and one end of the resistor Rr respectively. The other end of Rr is connected to the right port of the switch sw2. One end of the current source I2 is grounded, and the other end is connected to the right port of the switch sw2. The right port of sw2 outputs the signal Vspike. The Vspike input is connected to one end of sw3 through the voltage offset circuit. The other end of sw3 serves as the output end. When Vs1 is low, sw2 and sw3 are disconnected. In the circuit on the left side of sw2, the current I1 begins to charge Cm, causing the voltage on the left end of sw2 to gradually increase. When the voltage on the left end of sw2 exceeds the turn-on voltage of the NPN transistor Q1, Q1 and Q2 are turned on. At this time, VNa+ generates a large current I through Q2. Na+ Cm is quickly charged, so that the voltage at the left end of sw2 increases rapidly; circuit on the right side of sw2: current I2 passes through resistor R r C r Slow charging, when C r Voltage across both ends V rWhen the voltage is greater than Q3's turn-on voltage, Q3 turns on, and Vspike rapidly decreases. When Vs1 is high, SW2 and SW3 turn on. Vspike is biased downward by 0.15V via the voltage offset circuit, generating a post-synaptic neuron pulse (post-spike) at the right end of SW3. This embodiment designs a bionic circuit that evokes excitatory synaptic plasticity.

[0077] First, the presynaptic neuron pulse waveform is designed and implemented through a segmented ideal voltage source or FPGA digital circuit. The specific segmented mathematical expression is:

[0078]

[0079] in, are the highest and lowest potentials of Pre-spike, t p =-8μs is the starting point of the pulse waveform, and its absolute value also represents the positive pulse width, t n =32μs is the end point of the pulse waveform, and also represents the negative pulse width, τ p =5, τ n =40 respectively the time constant of the positive and negative pulse waveforms, the waveform diagram is as follows Figure 6 Medium V pre shown.

[0080] Then the presynaptic and postsynaptic pulse signals are added to both ends of the memristor, such as Figure 6 , Pre-spike and Post-spike at different time intervals △t and the voltage difference V between the two at different △t post -V pre , we can get from the information in the figure that when △t<0, two pulses are applied to both ends of the memristive synapse, and the voltage difference V acting on the memristive synapse is post -V pre It is a negative pulse, and as |△t| decreases, the negative pulse area that exceeds the negative threshold -Vth of the memristor becomes larger. When △t>0, two pulses are applied to both ends of the memristor synapse, and the voltage difference V post -V pre The positive pulse is a positive pulse, and as |△t| decreases, the area of ​​the positive pulse exceeding the positive threshold of the memristor increases. This variation characteristic meets the basic design requirements of the bionic circuit of the excitatory synaptic plasticity mechanism for the pulse waveform of pre- and post-synaptic neurons.

[0081] Then, by traversing △t, the change curve of the memristive synaptic conductance change △G(△t) is obtained, as shown in Figure 7 As shown in the figure, it can be seen that as |△t| (|△t|>8μs) becomes smaller, |△G| becomes larger, and when △t<0, △G<0, and when △t>0, △G>0. This law is consistent with the biological excitatory synaptic plasticity mechanism.

[0082] But it is also found that when |△t| < 8μs, the difference between the two is less than 0.1mV, which is much less than the threshold of 1mV. Figure 1 (b) The curve of the biological excitatory synaptic plasticity mechanism shown is slightly different from that of the biological neuron pulse, which is based on the assumption that the biological neuron pulse is completely the same, while the Post-spike and Pre-spike waveforms used by the bionic circuit designed in this section are different, which seems to be more in line with the actual situation that the biological neuron pulse is not exactly the same. By making appropriate offset modifications to formula 1, expression 10 is obtained, and then the Pspice simulation data of the bionic circuit is fitted using this expression. It is found that when A + = 0.023, A - = 0.05, τ + = 4μs, τ - = 15uΔG + s, = 0, ΔG - = 0.007, expression 10 can well fit the Pspice simulation data, indicating that the bionic circuit realizes the function of excitatory synaptic plasticity.

[0083]

[0084] In the embodiment, a bionic circuit for inhibitory synaptic plasticity mechanism is designed.

[0085] In the bionic circuit for inhibitory synaptic plasticity mechanism, the presynaptic neuron circuit can also be realized by a segmented independent ideal voltage source or an FPGA digital circuit, and the pulse waveform generated by it can be represented by a segmented mathematical expression:

[0086]

[0087] The waveform expressed by formula 11 is shown in Figure 8 . Wherein, t n0 = 8μs, t n1 = 15μs, t n2 = 25μs, τ n1 = τ p1 = 15 is the time constant of a-b segment and a1-b1 segment, τ n0 = 2 is the time constant of c-b segment, τ p0 = 10 is the time constant of d-e segment.

[0088] Figure 9 The Pre-spike and Post-spike of different time intervals△t and the voltage difference V post -V pre under different△t are shown.

[0089] Figure 9In, t wisp = 15μs is the steady-state window of inhibitory synaptic plasticity mechanism. Figure 9 As shown, when |△t| is less than the steady-state window t wisp When two pulses are applied to both ends of the memristive synapse, the voltage difference V post -V pre It is a positive pulse, and as |△t| decreases, the positive pulse area exceeding the positive threshold of the memristor becomes larger; when |△t| is greater than the steady-state window t wisp When two pulses are applied to both ends of the memristive synapse, the voltage difference acting on the memristive synapse is a negative pulse V post -V pre As |△t| increases, the area of ​​the negative pulse exceeding the negative threshold of the memristor increases and eventually stabilizes at a certain value. This variation meets the design requirements of bionic circuits for inhibitory synaptic plasticity mechanisms for pulse waveforms in pre- and post-synaptic neurons.

[0090] Furthermore, it is found that when |△t|<15μs, as |△t| becomes smaller, V post -V pre The larger the above-threshold area (red shaded area) is, the larger the V post -V pre The larger the suprathreshold area (red shaded area), the larger it is, and it eventually stabilizes at a certain value. According to the threshold and pulse response characteristics of the memristor, a larger suprathreshold area indicates a greater change in the memristive synaptic conductance. Furthermore, a positive suprathreshold area increases the memristive conductance, while a negative suprathreshold area decreases the memristive conductance.

[0091] Next, by traversing △t, the change curve of the memristive synaptic conductance change △G(△t) is obtained, as shown in Figure 10 shown.

[0092] It can be seen that when |△t|<15μs, as |△t| decreases, △G increases and is greater than zero; when |△t|≥15μs, as |△t| increases, △G decreases and finally stabilizes to a fixed negative value. This law is consistent with the biological excitatory synaptic plasticity mechanism. By deriving the inhibitory synaptic plasticity mechanism expressions 3-8, an equivalent expression is obtained, as shown in Equation 12. Then, using Equation 12 to fit the PSpice simulation data of the bionic circuit, it is found that when A in Equation 12 + =0.08, τ + =15us, ΔG0=-0.022, the expression can fit the simulation experimental data well ( Figure 10 red line), indicating that the bionic circuit realizes the function of inhibitory synaptic plasticity mechanism.

[0093] ΔG(Δt)=A +e -|Δt| / τ+ + ΔG0 (12)

[0094] The post-synaptic neuron circuit and the design method of the synaptic plasticity mechanism emulation circuit proposed in the application can design a synaptic plasticity mechanism emulation circuit with a small fitting error from a biological synaptic STDP mechanism mathematical model, and according to different memristors, by adjusting the parameters of the pre-synaptic and post-synaptic neuron circuit, different forms of biological synaptic plasticity mechanism models can be simulated, and a basic unit is provided for brain-like computing hardware. Extensively, the emulation circuit is not only suitable for the case of a single memristor as a synapse, but also suitable for a synaptic array composed of multiple memristors, realizes the adjustment of the conductance of multiple memristors, can greatly reduce the scale of brain-like computing hardware containing a large-scale synaptic circuit, and provides a new possibility for practical industrial use.

[0095] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0096] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A bionic circuit of synaptic plasticity mechanism based on threshold symmetric memristor, characterized in that: The synaptic plasticity mechanism bionic circuit is divided into an excitatory synaptic plasticity mechanism bionic circuit and an inhibitory synaptic plasticity mechanism bionic circuit; the bionic circuit includes a presynaptic neuron circuit, a postsynaptic neuron circuit and a threshold symmetric memristor, wherein the symmetric memristor simulates a biological synaptic unit, and its conductance value simulates the synaptic weight; The postsynaptic neuron circuits of the excitatory synaptic plasticity mechanism bionic circuit and the inhibitory synaptic plasticity mechanism bionic circuit are the same, but the presynaptic neuron circuits are different; the postsynaptic neuron circuit includes a leakage integrator module, a switch module for controlling pulse generation, and a neural pulse generation module; wherein the leakage integrator module simulates the subthreshold membrane potential Vmem of biological neurons, and the switch module for controlling pulse generation is implemented by a monostable trigger. When the membrane potential Vmem exceeds the preset Vthr, the module will control the neural pulse generation unit to generate a postsynaptic neuron pulse Post-spike.

2. The synaptic plasticity mechanism bionic circuit based on a threshold symmetric memristor according to claim 1, characterized in that: The leakage integrator module is composed of an inverse integration circuit and a comparator circuit, and is used to simulate the subthreshold membrane potential Vmem of biological neurons; The input synaptic current Isyn is respectively connected to the inverting input terminal of the first comparator, the capacitor C21, the resistor R21 and the switch sw1, the positive input terminal of the first comparator is connected to the resistor R22, the other end of the resistor R22 is grounded, the other end of C21, the other end of R21 and the other end of sw1 are connected to the output terminal of the first comparator; the output terminal of the first comparator is connected to the inverting input terminal of the second comparator, the positive input terminal of the second comparator is connected to the comparison voltage Vthr, the output terminal of the second comparator is connected in parallel with the resistor R23, and the other end of R23 is grounded.

3. The synaptic plasticity mechanism bionic circuit based on threshold symmetric memristor according to claim 1, characterized in that: The switch module for controlling pulse generation is a pulse generating circuit composed of an integrated monostable trigger 74121, specifically as follows: Pins 3 and 4 of the integrated monostable trigger are grounded, the output end of the second comparator in the leakage integration module is connected to pin 5 after passing through the comparison operation circuit, pin 6 is connected to resistor R31 and the output end of this module respectively, the other end of R31 is grounded, pin 10 is connected to capacitor C30, the other end of C30 is connected to resistor R30 and pin 11 respectively, and the other end of R30 is connected to Vcc.

4. The synaptic plasticity mechanism bionic circuit based on threshold symmetric memristor according to claim 1, characterized in that: The neural pulse generation module is specifically as follows: One end of the current source I1 is grounded, and the other end is connected to the left port of the switch sw2; one end of the capacitor Cm is grounded, and the other end is connected to the left port of the switch sw2; one end of the resistor RI is grounded, and the other end is respectively connected to the left port of the switch sw2 and the base of the transistor Q1; one end of the resistor R1 is grounded, and the other end is connected to the emitter of the transistor Q1; the negative electrode of the power supply VNa+ is grounded, and the positive electrode is connected to the emitter of the transistor Q2; the base of Q2 is connected to the collector of Q1, and the collector of Q2 is connected to the left port of sw2; the negative electrode of the power supply VK+ is grounded, and the positive electrode is connected to the emitter of the transistor Q3, and the collector of Q3 is connected to the right port of sw2; one end of the capacitor Cr is grounded, and the other end is respectively connected to the base of Q3 and one end of the resistor Rr, and the other end of the resistor Rr is connected to the right port of the switch sw2; one end of the current source I2 is grounded, and the other end is connected to the right port of the switch sw2; The right port of sw2 is connected to one end of sw3 through a voltage shift circuit, and the other end of sw3 serves as the output end.

5. The synaptic plasticity mechanism bionic circuit based on a threshold symmetric memristor according to claims 1-4, characterized in that: The design method of the circuit comprises the following steps: 1) Design the pre- and post-synaptic neuron pulse waveform and apply the ideal waveform to both ends of the memristive synapse; 2) Setting the memristor synapses to the same initial state and changing Δt to obtain the memristor-conductance variable ΔG(Δt) curve; 3) Use biological excitatory synaptic plasticity mechanism models and inhibitory synaptic plasticity mechanism models to fit the △G(△t) curve. If the fit is successful, it means that the pre- and post-synaptic neuron pulse waveforms meet the requirements of the bionic circuit design. Otherwise, readjust the pre- and post-synaptic neuron pulse waveform parameters and proceed to the second step. 4) If the pre- and post-synaptic neuron pulse waveforms meet the requirements for biomimetic circuit design, then design the post-synaptic neuron circuit based on the post-synaptic neuron pulse waveform, use an ideal segmented voltage source to simulate the pre-synaptic neuron pulse waveform, and then verify the degree of fit between the biological synaptic plasticity mechanism curve and the △G(△t) curve again. If they can fit, the biomimetic circuit design is complete; otherwise, return to the first step.

6. The synaptic plasticity mechanism bionic circuit based on threshold symmetric memristor according to claim 5, characterized in that: The designed pre- and post-synaptic neuron pulse waveforms include: When designing a bionic circuit for excitatory synaptic plasticity, the waveforms of the pulses from the front and back neurons must meet the following conditions: when Δt < 0, the voltage difference applied to the memristive synapse is negative, and as |Δt| decreases, the area of ​​the negative pulse that exceeds the negative threshold of the memristor increases. When Δt > 0, the voltage difference Vpost - Vpre applied to the memristive synapse is positive, and as |Δt| decreases, the area of ​​the positive pulse that exceeds the positive threshold of the memristor increases. When designing a bionic circuit with inhibitory synaptic plasticity mechanism, the waveforms of the preceding and following neuronal pulses must meet the following conditions: when |△t| is less than the steady-state window t wisp When two pulses are applied to the two ends of the memristor synapse, the voltage difference that finally acts on the memristor synapse is a positive pulse, and as |△t| decreases, the area of ​​the positive pulse that exceeds the positive threshold of the memristor becomes larger; when |△t| is greater than the steady-state window t wisp When two pulses are applied to the two ends of the memristor synapse, the voltage difference that finally acts on the memristor synapse is a negative pulse, and as |△t| increases, the area of ​​the negative pulse that exceeds the negative threshold of the memristor becomes larger and finally fixed to a certain value.

7. The synaptic plasticity mechanism bionic circuit based on threshold symmetric memristor according to claim 5, characterized in that: The presynaptic neuron circuit generates presynaptic neuron pulses. The excitatory presynaptic neuron circuit is implemented by a segmented independent ideal voltage source or an FPGA digital circuit. The segmented mathematical expression is: in, are the highest and lowest potentials of Pre-spike, t p =-8μs is the starting point of the pulse waveform, and its absolute value also represents the positive pulse width, t n =32μs is the end point of the pulse waveform, and also represents the negative pulse width, τ p =5, τ n =40, time constants of positive and negative pulse waveforms respectively; The inhibitory presynaptic neuron circuit is also implemented by a segmented independent ideal voltage source or an FPGA digital circuit, and its segmented mathematical expression is: in, t n0 =8μs, t n1 =15μs, t n2 =25μs, τ n1 =τ p1 =15 is the time constant of ab segment and a1-b1 segment, τ n0 =2 is the time constant of cb segment, τ p0 =10 is the time constant of segment de.

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