Geometric processing method, graphics processing chip and computer device

Abstract

The embodiment of the present disclosure discloses a geometry processing method, a graphics processing chip and a computer device. The method is applied to a graphics processing chip. Each processor core in the graphics processing chip is used for processing a corresponding data segment in the to-be-processed geometry data. The method comprises the following steps: a first processor core acquires a first write end address of first output data in a storage space; the first processor core broadcasts the first write end address and a first target processor identifier corresponding to a second data segment, the second data segment being a next data segment of the first data segment; and a second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier matches the processor identifier of the second processor core, the second output data is written into the storage space based on the first write end address. According to the embodiment of the present disclosure, the process of data writing by multiple processor cores is simplified by broadcasting, and the time consumption is reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of graphics processing technology, and in particular to a geometric processing method, a graphics processing chip, and a computer device. Background Technology

[0002] In a graphics processing chip, each processor core continuously outputs the data processed by the geometry shader or vertex shader stages to one or more buffers in the memory space during the stream out phase. In related technologies, when multiple processor cores write their corresponding output data to the memory space, a switch from multi-core mode to single-core mode is required for data writing, resulting in a complex and time-consuming process for each processor core. Summary of the Invention

[0003] In view of the above, embodiments of this disclosure provide at least one geometry processing method, graphics processing chip, and computer device.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a geometry processing method applied to a graphics processing chip, the graphics processing chip including multiple processor cores, each processor core being used to process a corresponding data segment in the geometry data to be processed, the method including:

[0006] The first processor core obtains the first write end address of the first output data in the storage space; the first output data is obtained by the first processor core through geometric processing of the corresponding first data segment, and is written into the storage space by the first processor core;

[0007] The first processor core broadcasts the first write end address and the first target processor identifier corresponding to the second data segment, wherein the second data segment is the next data segment after the first data segment;

[0008] The second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier matches the processor identifier of the second processor core, it writes the second output data into the storage space based on the first write end address. The second output data is obtained by the second processor core performing geometric processing on the corresponding second data segment.

[0009] This disclosure provides a graphics processing chip, which includes multiple processor cores. Each processor core is used to process a corresponding data segment in the geometric data to be processed, wherein:

[0010] The first processor core is used to: obtain the first write end address of the first output data in the storage space; the first output data is obtained by the first processor core performing geometric processing on the corresponding first data segment, and is written into the storage space by the first processor core;

[0011] The first processor core is also configured to: broadcast the first write end address and the first target processor identifier corresponding to the second data segment, wherein the second data segment is the next data segment of the first data segment;

[0012] The second processor core is configured to: receive the first write end address and the first target processor identifier; and, if the first target processor identifier matches the processor identifier of the second processor core, write the second output data into the storage space based on the first write end address; the second output data is obtained by the second processor core performing geometric processing on the corresponding second data segment.

[0013] This disclosure provides a computer device including the graphics processing chip described above.

[0014] In this embodiment, the first processor core performs geometric processing on the first data segment to obtain first output data. The first processor core writes the first output data into storage space and obtains the first write end address of the first output data in storage space. The second data segment is the next data segment after the first data segment. The first processor core broadcasts the first write end address and the first target processor identifier corresponding to the second data segment. The second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier and the processor identifier of the second processor core match, the second processor core performs geometric processing on the second data segment to obtain second output data and writes the second output data into storage space according to the first write end address. In this way, when writing the output data of multiple processor cores into storage space, the output data of each processor core can be written into storage space by broadcasting the write end address corresponding to the current processor core and the processor identifier corresponding to the next processor core to write data, without having to switch from multi-core mode to single-core mode, thereby simplifying the data writing process of multiple processor cores and reducing time consumption.

[0015] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0017] Figure 1 A schematic diagram illustrating the implementation flow of a geometric processing method provided in an embodiment of this disclosure;

[0018] Figure 2 This is a schematic diagram of the composition structure of a graphics processing chip provided in an embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of the composition structure of a processor core provided in an embodiment of this disclosure;

[0020] Figure 4 This is a schematic diagram of the composition structure of a computer device provided in an embodiment of the present disclosure;

[0021] Figure 5 This is a schematic diagram illustrating the implementation process of a geometric processing method in related technologies;

[0022] Figure 6 This is a schematic diagram illustrating the data output of a multiprocessor core in a related technology.

[0023] Figure 7 This is a schematic diagram illustrating how data is written to storage space in a related technology.

[0024] Figure 8 A schematic diagram illustrating the implementation process of a multi-core stream output sequential output scheme provided in this embodiment of the disclosure;

[0025] Figure 9 This is a schematic diagram illustrating a specific process for stream output synchronization provided in an embodiment of the present disclosure;

[0026] Figure 10 This is a schematic diagram illustrating synchronous processing between multiple processor cores, provided as an embodiment of the present disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0029] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0031] This disclosure provides a geometry processing method applied to a graphics processing chip. The graphics processing chip includes multiple processor cores, each processor core being used to process a corresponding data segment in the geometric data to be processed. Figure 1 This is a schematic diagram illustrating the implementation flow of a geometric processing method provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the method includes the following steps S101 to S103:

[0032] Step S101: The first processor core obtains the first write end address of the first output data in the storage space; the first output data is obtained by the first processor core through geometric processing of the corresponding first data segment, and is written into the storage space by the first processor core;

[0033] Here, the first processor core is the processor core in the graphics processing chip that processes the first data segment in geometric data.

[0034] The first write end address is the end address where the first processor core writes the first output data into the storage space.

[0035] In some implementations, the geometric data to be processed is divided into multiple data segments, and each processor core processes the corresponding data segment. For example, the first processor core processes the first data segment, and the second processor core processes the second data segment.

[0036] In some implementations, the geometric data to be processed may include, but is not limited to, at least one of vertex data, graph data, texture data, lighting data, etc.

[0037] In some implementations, the geometric processing performed by the first processor core on the first data segment may include, but is not limited to, at least one of the following: input assembler step, vertex shader stage, geometry shader stage, stream output stage, rasterization stage, pixel shader stage, and output merging stage.

[0038] In some implementations, when the first processor core receives the last task of the first data segment, it can obtain the data volume and write start address corresponding to the first output sub-data; the first processor core can determine the first write end address based on the data volume and write start address corresponding to the first output sub-data.

[0039] In some implementations, during the stream output phase, the first processor core writes the first output data into the storage space.

[0040] In some implementations, the streaming output stage involves continuously outputting vertex data from the vertex shader and geometry shader stages to memory. Here, continuous output to memory means that after each processor core writes its corresponding output data to memory, the output data in memory is continuous.

[0041] In some implementations, the storage space can be Global Memory, which mainly refers to Dynamic Random-Access Memory (DRAM) on the GPU motherboard.

[0042] Step S102: The first processor core broadcasts the first write end address and the first target processor identifier corresponding to the second data segment, wherein the second data segment is the next data segment of the first data segment;

[0043] Here, the first target processor identifier is the processor identifier of the processor core used to process the second data segment, and the second data segment is the data segment following the first data segment.

[0044] In some implementations, a corresponding processor core is pre-assigned to each data segment. After the first processor core obtains the first write end address of the first output data in the storage space, it determines the processor core to process the second data segment and determines the processor identifier corresponding to the processor core to process the second data segment as the first target processor identifier. The first processor core broadcasts the first write end address and the first target processor identifier.

[0045] For example, if the processor core used to process the second data segment is the second processor core, the first target processor identifier can be determined as the processor identifier corresponding to the second processor core.

[0046] In some implementations, each processor core processes the data segments in the geometric data to be processed sequentially according to its corresponding processor identifier. For example, the processor identifiers of each processor core can be 1, 2, and 3. The processor core with processor identifier 1 processes the first data segment, the processor core with processor identifier 2 processes the second data segment, and the processor core with processor identifier 3 processes the third data segment. The second data segment is the next data segment after the first data segment, and the third data segment is the next data segment after the second data segment. Therefore, the first target processor identifier is the next processor identifier after the processor identifier of the first processor core. For example, if the processor identifier of the first processor core is 1, the first target processor identifier is 2.

[0047] In some implementations, the first processor core may include a synchronization module for broadcasting the first write end address and the first target processor identifier.

[0048] In some implementations, the synchronization module can also be used to receive broadcast messages sent by other processor cores.

[0049] Step S103: The second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier matches the processor identifier of the second processor core, the second output data is written into the storage space based on the first write end address. The second output data is obtained by the second processor core performing geometric processing on the corresponding second data segment.

[0050] In some implementations, if the first target processor identifier is equal to the processor identifier of the second processor core, it is determined that the first target processor identifier matches the processor identifier of the second processor core.

[0051] In some implementations, the first write end address can be used as the write start address of the second output data in the storage space.

[0052] In some implementations, when the second processor core enters the stream output phase, the first write end address and the first target processor identifier are received.

[0053] In some implementations, when the second processor core receives the first write end address and the first target processor identifier, it may have already completed the geometric processing of the second data segment, or it may not have completed the geometric processing of the second data segment. If the first processor core has not completed the geometric processing of the second data segment, it continues to perform geometric processing on the second data segment. After the second processor core completes the geometric processing of the second data segment, it enters the stream output stage and writes the second output data into the storage space.

[0054] During implementation, after receiving the first write end address and the first target processor identifier, the second processor core compares its processor identifier with the first target processor identifier. If the first target processor identifier matches the second processor core's processor identifier, the second processor core is determined to be the processor core that processes the second data segment. Therefore, the second output data can be written to the storage space according to the first write end address. In this way, each processor core writes its corresponding output data to the storage space according to its corresponding write end address, making the output data in the storage space continuous.

[0055] In some implementations, the first processor core broadcasts a first write end address and a first target processor identifier. The second processor core can use the first write end address as its write start address, ensuring that the output data in the storage space is continuous after multiple processor cores write their corresponding output data. Furthermore, since each processor core has a unique processor identifier, only one processor core's identifier matches the first target processor identifier. If the second processor core's identifier matches the first target processor identifier, only the second processor core can write the corresponding second output data into the storage space, avoiding write conflicts between multiple processor cores. Therefore, it is not necessary to switch from multi-core mode to single-core mode to write the output data of each processor core into the storage space.

[0056] In this embodiment, the first processor core performs geometric processing on the first data segment to obtain first output data. The first processor core writes the first output data into a storage space and obtains the first write end address of the first output data in the storage space. The second data segment is the next data segment after the first data segment. The first processor core broadcasts the first write end address and the first target processor identifier corresponding to the second data segment. The second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier and the processor identifier of the second processor core match, the second processor core performs geometric processing on the second data segment to obtain second output data and writes the second output data into the storage space according to the first write end address. In this way, when writing output data from multiple processor cores to storage, the output data of each processor core can be written to storage by broadcasting the write end address corresponding to the current processor core and the processor identifier corresponding to the next processor core to write data. The write end address ensures that the output data in storage is continuous after each processor core writes its corresponding output data. The first target processor identifier ensures that only one processor core is writing data at any given time, avoiding data write conflicts. Therefore, there is no need to switch from multi-core mode to single-core mode, which simplifies the data writing process of multiple processor cores and reduces time consumption.

[0057] In some embodiments, the above method further includes the following step S111:

[0058] Step S111: After the first processor core determines the first write end address, the first processor core broadcasts the first write end address and the first target processor identifier; the first write end address is determined by the first processor core after receiving the first task based on the first data volume corresponding to the first output sub-data to be output by the first task and the first write start address; the first task is the last task of the first data segment.

[0059] Here, the first output sub-data is the first output sub-data obtained after the first processor core processes the first task.

[0060] In some implementations, when the first processor core receives the first task, it can obtain in advance the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task.

[0061] In some implementations, the first processor core can determine the first data volume based on the total number of vertices corresponding to the first task.

[0062] In some implementations, the first processor core can broadcast the first write end address and the first target processor identifier after determining the first write end address, without waiting for the first processor core to finish executing the first task and write the first output sub-data to the storage space before broadcasting.

[0063] In some implementations, the first processor core can process the first task in parallel and broadcast the first write end address and the first target processor identifier.

[0064] In some implementations, after determining the first end-of-write address, the first processor core executes the first task and writes the first output sub-data corresponding to the first task into the storage space.

[0065] In some implementations, the first processor core may first execute the first task, write the first output sub-data corresponding to the first task into the storage space, and then determine the first write end address based on the first data volume and the first write start address.

[0066] In some implementations, a first sub-processing unit in the first processor core performs a first task, generates first output sub-data, and writes the first output sub-data into storage space based on a first write start address.

[0067] In this embodiment, after the first processor core determines the first write end address, it broadcasts the first write end address and the first target processor identifier. The first write end address is determined by the first processor core after receiving the first task, based on the first data volume corresponding to the first output sub-data to be output by the first task and the first write start address. The first task is the last task of the first data segment. Thus, when the first processor core receives the first task, it can obtain the first data volume and the first write start address, and determine the first write end address in advance based on these data volumes and the first write start address. It can broadcast the first write end address and the first target processor identifier without waiting for the first task to complete, thereby improving the efficiency of multiple processor cores writing the corresponding output data into the storage space.

[0068] In some embodiments, the first processor core includes at least two sub-processing units, each of which is used to process a corresponding sub-data segment in the first data segment to be processed;

[0069] The method further includes the following step S131:

[0070] Step S131: In response to receiving the first task, the first sub-processing unit obtains the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task; the first task is the last task of the first sub-data segment corresponding to the first sub-processing unit; the first sub-data segment is the last data segment in the first data segment.

[0071] Here, the first sub-processing unit is the sub-processing unit that processes the last sub-data segment in the first data segment.

[0072] In some implementations, when the first sub-processing unit receives the first task, it can obtain in advance the first data volume and the first write start address corresponding to the first output sub-data to be output, and determine the first write end address based on the first data volume and the first write start address. Therefore, it is not necessary to wait until the first output sub-data is written to the storage space before determining the first write end address.

[0073] In some implementations, the first sub-processing unit obtains the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task in the vertex shader stage and the geometry shader stage, respectively.

[0074] In some implementations, the first sub-processing unit determines the first write end address corresponding to the vertex shader stage and the geometry shader stage, respectively.

[0075] In this embodiment, the first processor core includes at least two sub-processing units. Each sub-processing unit processes a corresponding sub-data segment within a first data segment to be processed. The first task is the last task of the first sub-data segment corresponding to the first sub-processing unit. The first sub-data segment is the last data segment within the first data segment. Upon receiving the first task, the first sub-processing unit obtains in advance the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task. In this way, the first sub-processing unit can determine the first write end address based on the first data volume and the first write start address when executing the first task, without waiting for the first sub-processing unit to complete the first task. This reduces the dependence on whether the first sub-processing unit has completed the first task, thereby reducing the dependency between the sub-processing units in the processor core during task execution and data writing.

[0076] In some embodiments, the process of the first processor core obtaining the first write end address of the first output data in the storage space in step S101 above may include the following step S141:

[0077] Step S141: After the first processor core writes the first output data into the storage space, it obtains the first write end address.

[0078] In some implementations, the first processor core may write the first output data into the storage space to obtain the first write end address, and then broadcast the first write end address and the first target processor identifier corresponding to the second data segment.

[0079] In this embodiment of the disclosure, after the first processor core writes the first output data into the storage space, it obtains the first write end address. Thus, after the first processor core writes the first output data into the storage space, it can directly obtain the first write end address. This method is simple to implement and can be obtained directly without calculation.

[0080] In some embodiments, the method further includes the following step S151:

[0081] Step S151: After the second processor core obtains the second write end address of the second output data in the storage space, the second processor core broadcasts the second write end address of the second output data in the storage space, and the second target processor identifier corresponding to the third data segment, wherein the third data segment is the next data segment of the second data segment.

[0082] Here, the second target processor identifier is the processor identifier of the processor core used to process the third data segment, which is the data segment following the second data segment.

[0083] In some implementations, a corresponding processor core is pre-assigned to each data segment. After the second processor core obtains the second write end address of the second output data in the storage space, it determines the processor core to process the third data segment and determines the processor identifier corresponding to the processor core to process the third data segment as the second target processor identifier. The second processor core broadcasts the second write end address and the second target processor identifier.

[0084] In some implementations, each processor core processes the data segments in the geometric data to be processed sequentially according to its corresponding processor identifier. For example, the processor identifiers of each processor core can be 1, 2, and 3. The processor core with processor identifier 1 processes the first data segment, the processor core with processor identifier 2 processes the second data segment, and the processor core with processor identifier 3 processes the third data segment. The second data segment is the next data segment after the first data segment, and the third data segment is the next data segment after the second data segment. Therefore, the second target processor identifier is the next processor identifier after the processor identifier of the second processor core. For example, if the processor identifier of the second processor core is 2, the second target processor identifier is 3.

[0085] In some implementations, when each processor core broadcasts the target processor identifier, the broadcast is performed in the order of the processor cores processing the corresponding data segments in the geometric data. For example, after the first processor core determines the corresponding write end address, it broadcasts the first target processor identifier and the corresponding write end address that match the processor identifier of the second processor core processing the second data segment; after the second processor core determines the corresponding write end address, it broadcasts the second target processor identifier and the corresponding write end address that match the processor identifier of the third processor core processing the third data segment.

[0086] When the second processor core determines that the first target processor identifier matches the processor identifier of the second processor core, the second processor begins processing the second data segment. The second processor core obtains the second write end address of the second output data in the storage space; the second processor core broadcasts the second write end address and the second target processor identifier corresponding to the third data segment. In this way, the output data of each processor core in the graphics processing chip can be written into the storage space.

[0087] In this embodiment, the third data segment is the next data segment after the second data segment. After the second processor core obtains the second write end address of the second output data in the storage space, the second processor core broadcasts the second write end address of the second output data in the storage space, as well as the second target processor identifier corresponding to the third data segment. In this way, the output data of each processor core in the graphics processing chip can be written into the storage space by sending broadcast information, so that the output data corresponding to each processor core is continuous in the storage space.

[0088] In some embodiments, the method further includes the following step S161:

[0089] Step S151: If the first target processor identifier does not match the processor identifier of the second processor core, the second processor core continues to wait to write the second output data into the storage space.

[0090] In some implementations, if the first target processor identifier does not match the processor identifier of the second processor core, the second processor core continues to wait and does not output data until it receives a target processor identifier that matches the processor identifier of the second processor core, at which point the second processor core writes the corresponding second output data into the storage space.

[0091] In this embodiment of the disclosure, if the first target processor identifier does not match the processor identifier of the second processor core, the second processor core continues to wait. Thus, each processor core continues to wait without receiving a data output command, allowing each processor core to receive the write end address corresponding to its output data. This enables the output data to be written to the storage space according to the corresponding write end address, ensuring that the data in the storage space is continuous after each processor core has written its own output data.

[0092] In some embodiments, the method further includes the following step S121:

[0093] Step S121: If the first target processor identifier does not match the processor identifier of the second processor core, the second processor core performs geometric processing on the second data segment.

[0094] In some implementations, if the first target processor identifier does not match the processor identifier of the second processor core, the second processor core performs geometric processing on the second data segment while waiting to write the second output data to the storage space.

[0095] In some implementations, when each processor core broadcasts the corresponding end-of-write address and target processor identifier, other processors can process the corresponding data segment in parallel.

[0096] In some implementations, if the first target processor identifier does not match the processor identifier of the second processor core, and the second processor core has not completed the geometric processing of the second data segment, the second processor core performs geometric processing on the second data segment.

[0097] In this embodiment of the present disclosure, when the first target processor identifier does not match the processor identifier of the second processor core, the second processor core performs geometric processing on the second data segment so that when the second processor core receives a target processor identifier that matches the processor identifier of the second processor core, the geometric processing of the second data segment has been completed, and the second output data is obtained. Thus, the second output data can be directly written into the storage space, thereby improving the efficiency of writing the output data into the storage space.

[0098] In some embodiments, the method further includes the following steps S171 and S172:

[0099] Step S171: If the first target processor identifier matches the processor identifier of the second processor core, the second processor core sends a response message to the first processor core;

[0100] Step S172: Upon receiving the response information, the first processor core stops broadcasting the first write end address and the first target processor identifier.

[0101] In this embodiment, when the first target processor identifier matches the processor identifier of the second processor core, the second processor core sends a response message to the first processor core. After receiving the response message, the first processor core stops broadcasting the first write end address and the first target processor identifier. Thus, after receiving the response message from the second processor core, the first processor core stops broadcasting, reducing its resource consumption.

[0102] This disclosure provides a graphics processing chip. Figure 2 This is a schematic diagram of the composition structure of a graphics processing chip provided in an embodiment of the present disclosure, such as... Figure 2 As shown, the graphics processing chip 200 includes multiple processor cores, each of which is used to process a corresponding data segment in the geometric data to be processed, wherein:

[0103] The first processor core 201 is used to: obtain the first write end address of the first output data in the storage space; the first output data is obtained by the first processor core 201 performing geometric processing on the corresponding first data segment, and is written into the storage space by the first processor core 201;

[0104] The first processor core 201 is further configured to: broadcast the first write end address and the first target processor identifier corresponding to the second data segment, wherein the second data segment is the next data segment of the first data segment;

[0105] The second processor core 202 is configured to: receive the first write end address and the first target processor identifier; and, if the first target processor identifier matches the processor identifier of the second processor core 202, write the second output data into the storage space based on the first write end address; the second output data is obtained by the second processor core 202 performing geometric processing on the corresponding second data segment.

[0106] In some implementations, after entering the stream output stage, the multiple processor cores in the graphics processing chip 200 write the output data corresponding to each processor core into the storage space.

[0107] In some implementations, the first processor core 201, in response to receiving a first task, obtains the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task, wherein the first task is the last task of the first data segment.

[0108] In some implementations, the first processor core 201 determines the first write end address based on the first data volume and the first write start address.

[0109] In some implementations, after determining the first write end address, the first processor core 201 executes a first task, generates first output sub-data, and writes the first output sub-data into the storage space based on the first write start address.

[0110] In some implementations, after the first processor core 201 writes the first output data into the storage space, it obtains the first write end address.

[0111] In some implementations, if the first target processor identifier matches the processor identifier of the second processor core 202, it is indicated that the second processor core 202 is the processor core currently to output data, and the second processor core 202 writes the second output data into the storage space based on the first write end address.

[0112] In this embodiment, the first processor core performs geometric processing on the first data segment to obtain first output data. The first processor core writes the first output data into storage space and obtains the first write end address of the first output data in storage space. The second data segment is the next data segment after the first data segment. The first processor core broadcasts the first write end address and the first target processor identifier corresponding to the second data segment. The second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier and the processor identifier of the second processor core match, the second processor core performs geometric processing on the second data segment to obtain second output data and writes the second output data into storage space according to the first write end address. In this way, when writing the output data of multiple processor cores into storage space, the output data of each processor core can be written into storage space by broadcasting the write end address corresponding to the current processor core and the processor identifier corresponding to the next processor core to write data, without having to switch from multi-core mode to single-core mode, thereby simplifying the data writing process of multiple processor cores and reducing time consumption.

[0113] In some embodiments, the first processor core is further configured to: after the first processor core determines the first write end address, broadcast the first write end address and the first target processor identifier; the first write end address is determined by the first processor core after receiving the first task based on the first data volume corresponding to the first output sub-data to be output by the first task and the first write start address; the first task is the last task of the first data segment.

[0114] In some implementations, after receiving the first task, the first processor core can obtain in advance the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task, and determine the first write end address based on the first write start address and the first data volume. In this way, the first processor core can execute the first task in parallel and broadcast the first write end address and the first target processor identifier corresponding to the second data segment.

[0115] In some implementations, the first processor core does not need to wait until the first output sub-data to be output by the first task is written to the storage space before determining the first data amount and the first write start address, which reduces the dependence on whether the first processor core has completed the first task, thereby reducing the dependence between the processor chips in the graphics processing chip during task execution and data writing.

[0116] In this embodiment, after the first processor core determines the first write end address, it broadcasts the first write end address and the first target processor identifier. The first write end address is determined by the first processor core after receiving the first task, based on the first data volume corresponding to the first output sub-data to be output by the first task and the first write start address. The first task is the last task of the first data segment. Thus, when the first processor core receives the first task, it can obtain the first data volume and the first write start address, and determine the first write end address in advance based on these data volumes and the first write start address. It can broadcast the first write end address and the first target processor identifier without waiting for the first task to complete, thereby improving the efficiency of multiple processor cores writing the corresponding output data into the storage space.

[0117] In some embodiments, such as Figure 3 As shown, the first processor core 201 includes at least two sub-processing units, each of which is used to process a corresponding sub-data segment in the first data segment to be processed, wherein:

[0118] The first sub-processing unit 211 is configured to: in response to receiving the first task, obtain the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task; the first task is the last task of the first sub-data segment corresponding to the first sub-processing unit; the first sub-data segment is the last data segment in the first data segment.

[0119] In some implementations, the first processor core 201 includes at least two sub-processing units, such as a first sub-processing unit 211 and a second sub-processing unit 212, for processing corresponding sub-data segments in the first data segment to be processed.

[0120] In some implementations, after receiving the first task, the first sub-processing unit 211 obtains the total number of vertices corresponding to the first task and determines the first data quantity corresponding to the first output sub-data to be output by the first task based on the total number of vertices.

[0121] In some implementations, after receiving the first task, the first sub-processing unit 211 can obtain in advance the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task, and determine the first write end address based on the first write start address and the first data volume.

[0122] In this embodiment, the first processor core includes at least two sub-processing units. Each sub-processing unit processes a corresponding sub-data segment within a first data segment to be processed. The first task is the last task of the first sub-data segment corresponding to the first sub-processing unit. The first sub-data segment is the last data segment within the first data segment. Upon receiving the first task, the first sub-processing unit obtains in advance the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task. In this way, the first sub-processing unit can determine the first write end address based on the first data volume and the first write start address when executing the first task, without waiting for the first sub-processing unit to complete the first task. This reduces the dependence on whether the first sub-processing unit has completed the first task, thereby reducing the dependency between the sub-processing units in the processor core during task execution and data writing.

[0123] In some embodiments, the first processor core is further configured to: obtain the first write end address after writing the first output data into the storage space.

[0124] In this embodiment of the disclosure, after the first processor core writes the first output data into the storage space, it obtains the first write end address. Thus, after the first processor core writes the first output data into the storage space, it can directly obtain the first write end address. This method is simple to implement and can be obtained directly without calculation.

[0125] In some embodiments, the second processor core is further configured to: after the second processor core obtains the second write end address of the second output data in the storage space, broadcast the second write end address of the second output data in the storage space, and the second target processor identifier corresponding to the third data segment, wherein the third data segment is the next data segment of the second data segment.

[0126] In this embodiment, the third data segment is the next data segment after the second data segment. After the second processor core obtains the second write end address of the second output data in the storage space, the second processor core broadcasts the second write end address of the second output data in the storage space, as well as the second target processor identifier corresponding to the third data segment. In this way, the output data of each processor core in the graphics processing chip can be sequentially written into the storage space by sending broadcast information.

[0127] In some embodiments, the second processor core is further configured to: continue waiting to write the second output data into the storage space if the first target processor identifier does not match the processor identifier of the second processor core.

[0128] In this embodiment of the disclosure, if the first target processor identifier does not match the processor identifier of the second processor core, the second processor core continues to wait. Thus, each processor core continues to wait without receiving a data output command, allowing each processor core to receive the write end address corresponding to its output data. This enables the output data to be written to the storage space according to the corresponding write end address, ensuring that the data in the storage space is continuous after each processor core has written its own output data.

[0129] In some embodiments, the second processor core is further configured to perform geometric processing on the second data segment if the first target processor identifier does not match the processor identifier of the second processor core.

[0130] In this embodiment of the present disclosure, when the geometric processing of the first target processor identifier and the processor identifier of the second processor core do not match, the second processor core performs geometric processing on the second data segment so that when the second processor core receives the target processor identifier that matches the processor identifier of the second processor core, the geometric processing of the second data segment has been completed and the second output data is obtained. Thus, the second output data can be directly written into the storage space, thereby improving the efficiency of writing the output data into the storage space.

[0131] In some embodiments, the second processor core is further configured to: send response information to the first processor core if the first target processor identifier matches the processor identifier of the second processor core;

[0132] The first processor core is further configured to: in response to receiving the response information, stop broadcasting the first write end address and the first target processor identifier.

[0133] In this embodiment, when the first target processor identifier matches the processor identifier of the second processor core, the second processor core sends a response message to the first processor core. After receiving the response message, the first processor core stops broadcasting the first write end address and the first target processor identifier. Thus, after receiving the response message from the second processor core, the first processor core stops broadcasting, reducing its resource consumption.

[0134] This disclosure provides a computer device, such as... Figure 4 As shown, the computer device 400 includes the graphics processing chip 200 described above.

[0135] The following describes the application of the embodiments of this disclosure in real-world scenarios.

[0136] like Figure 5 As shown, the processing flow of a graphics processing unit (GPU) in related technologies may include an input assembler step 501, a vertex shader stage 502, a geometry shader stage 503, a stream output stage 504, a rasterization stage 505, a pixel shader stage 506, and an output merging stage 507. The main purpose of the stream output stage 504 is to continuously output inactive vertex data from the geometry shader stage 503 or the vertex shader stage 502 to one or more buffers in the storage space 508. After the data is transferred to the storage space 508 through the stream output stage 504, it can be read back into the GPU's graphics processing pipeline for further processing during subsequent rendering processes, or the data can be copied to the storage space 508 for easy access by the central processing unit (CPU).

[0137] In related technologies, when GPUs process stream-out, if there are multiple processor cores, such as... Figure 6 As shown, each processor core needs to be streamed sequentially. The processor cores can include a first core 601, a second core 602, a third core 603, and a fourth core 604. In the stream output stage 504, after writing the output data of the first core 601 to storage space 508, the output data of the second core 602, the third core 603, and the fourth core 604 are sequentially written to storage space 508. This processing is inefficient. Even if the graphics processing stage distributes the input data in parallel across multiple processor cores, the stream output stage still processes the data serially from a single processor core.

[0138] Starting from stream output stage 504, such as Figure 7As shown, data will be continuously written to the starting address 701 allocated to the storage space 508 until the data writing is completed, and the ending address 702 of the data writing is obtained.

[0139] Currently, if the GPU is working in multi-core mode, after the system issues a streaming output command, the GPU needs to switch back to single-core mode for streaming output.

[0140] Based on the above description, this disclosure provides a multi-core stream-out sequential output scheme, which can improve the efficiency of the GPU in the stream output stage and increase the utilization of processor cores. The initial requirement to switch to single-core mode for stream output processing is optimized to allow stream output processing on each processor core without switching modes.

[0141] like Figure 8 As shown, this embodiment uses a synchronization module 801 to broadcast the stream output information of the processor cores among the various processor cores. When the current processor core is polled, the processor core enables the stream output module to enter the stream output stage to output data. When the current processor core completes its data stream output, the synchronization module broadcasts data, mainly including the end address of the current processor core in the storage space 508. This end address will be used as the starting address for the next processor core to write to the storage space 508. For example, when the first core 601 receives a broadcast message, confirming that it will output data, the first core 601 writes the output data to the storage space 508 through the first stream output stage 802. After writing the data, the first core 601 sends a synchronous broadcast message, which includes the end address of the data write by the first core 601 and the corresponding identifier of the second core 602. When the second core 602 receives the broadcast message, confirming that it will output data, the second core 602 writes the output data to the storage space 508 through the second stream output stage 803. After writing the data, the second core 602 sends a synchronous broadcast message, which includes the end address of the data write by the first core 601 and the corresponding identifier of the second core 602. This includes the end address of the data write for the second core 602 and the corresponding identifier for the third core 603; the third core 603 receives the broadcast information, confirming that it will output data, and the third core 603 writes the output data to the storage space 508 through the third stream output stage 804. After the third core 603 finishes writing the data, it sends a synchronous broadcast information, which includes the end address of the data write for the third core 603 and the corresponding identifier for the fourth core 604; the fourth core 604 receives the broadcast information, confirming that it will output data, and the fourth core 604 writes the output data to the storage space 508 through the fourth stream output stage 805.

[0142] In single-core mode streaming output, because only one processor core is outputting data, the data is continuous in the storage space, and there is no need to record the starting address.

[0143] The specific process of stream output synchronization of a processor core in an embodiment of this disclosure is as follows: Figure 9 As shown, the process may include the following steps S901 to S907:

[0144] Step S901: Should the stream output process be performed? If yes, proceed to step S902; if no, proceed to step S906.

[0145] If a processor core is currently streaming, the synchronization module must be prevented from broadcasting information; if no processor core is currently streaming, it must be determined whether the current processor core needs to stream.

[0146] Step S902: Prevent the synchronization module from broadcasting information, while continuing to process data that has not yet been output;

[0147] Step S903: Has the existing data been completely output? If yes, proceed to step S904; if no, proceed to step S902.

[0148] Step S904: Increment the current processor core identifier by 1 and broadcast the end address of the memory space;

[0149] After the output data of the current processor core is written to the storage space, the current processor core identifier is incremented by 1 to become the processor core identifier for the next processor core to perform stream output; the end address in the storage space is used as the start address for the next processor core to perform stream output.

[0150] Step S905: Are there other processor cores that have reported receiving broadcast data? If yes, end the current processor core's stream output process; if no, proceed to step S904.

[0151] Step S906: Is the broadcast identifier equal to the current processor core identifier? If yes, proceed to step S907; if no, continue waiting and proceed to step S901.

[0152] Step S907: Save the end address of the broadcast information in the storage space and start the stream output process.

[0153] The end address in the memory space is used as the starting address for the current processor core to perform stream output.

[0154] Synchronous processing between multi-processor cores, such as Figure 10As shown, after the current processor core finishes processing, the processor core identifier will be incremented by 1 and then broadcast. When a new broadcast identifier is the same as the processor core identifier of the current processor core, it means that this processor core is selected. For example, when the first core 601 determines that the first identifier 11 is equal to the first broadcast identifier 21, the first core 601 performs stream output; the first core 601 adds 1 to the first broadcast identifier 21 to obtain the second broadcast identifier 22, and broadcasts the second broadcast identifier 22; when the second core 602 determines that the second identifier 12 is equal to the second broadcast identifier 22, the second core 602 performs stream output; the second core 602 adds 1 to the second broadcast identifier 22 to obtain the third broadcast identifier 23, and broadcasts the third broadcast identifier 23; when the third core 603 determines that the third identifier 13 is equal to the third broadcast identifier 23, the third core 603 performs stream output; the third core 603 adds 1 to the third broadcast identifier 23 to obtain the fourth broadcast identifier 24, and broadcasts the fourth broadcast identifier 24; when the fourth core 604 determines that the fourth identifier 14 is equal to the fourth broadcast identifier 24, the fourth core 604 performs stream output.

[0155] In this embodiment of the disclosure, when performing streaming output with multiple processor cores, it is not necessary to switch multiple cores to single core mode for streaming output. Instead, streaming output can be achieved by polling each processor core through broadcast messages. This reduces the time spent switching modes during streaming output and improves the efficiency of streaming output when multiple processor cores are involved.

[0156] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0157] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0158] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0159] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0160] Furthermore, in the various embodiments of this disclosure, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0161] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0162] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A geometric processing method, characterized in that, The method is applied to a graphics processing chip, which includes multiple processor cores, each processor core being used to process a corresponding data segment in the geometric data to be processed. The method includes: The first processor core obtains the first write end address of the first output data in the storage space; the first output data is obtained by the first processor core through geometric processing of the corresponding first data segment, and is written into the storage space by the first processor core; The first processor core broadcasts the first write end address and the first target processor identifier corresponding to the second data segment, wherein the second data segment is the next data segment after the first data segment; The second processor core receives the first write end address and the first target processor identifier. If the first target processor identifier matches the processor identifier of the second processor core, it writes the second output data into the storage space based on the first write end address. The second output data is obtained by the second processor core performing geometric processing on the corresponding second data segment. The first processor core and the second processor core process the first data segment and the second data segment in parallel.

2. The method according to claim 1, characterized in that, The method further includes: After the first processor core determines the first write end address, the first processor core broadcasts the first write end address and the first target processor identifier; the first write end address is determined by the first processor core after receiving the first task based on the first data volume corresponding to the first output sub-data to be output by the first task and the first write start address; the first task is the last task of the first data segment.

3. The method according to claim 2, characterized in that, The first processor core includes at least two sub-processing units, each of which is used to process a corresponding sub-data segment in the first data segment to be processed; the method further includes: In response to receiving the first task, the first sub-processing unit obtains the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task; the first task is the last task of the first sub-data segment corresponding to the first sub-processing unit; the first sub-data segment is the last data segment in the first data segment.

4. The method according to claim 1, characterized in that, The first processor core obtains the first write end address of the first output data in the storage space, including: After the first processor core writes the first output data into the storage space, it obtains the first write end address.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: After the second processor core obtains the second write end address of the second output data in the storage space, the second processor core broadcasts the second write end address of the second output data in the storage space, as well as the second target processor identifier corresponding to the third data segment, wherein the third data segment is the next data segment of the second data segment.

6. The method according to any one of claims 1 to 4, characterized in that, The method further includes: If the first target processor identifier does not match the processor identifier of the second processor core, the second processor core continues to wait to write the second output data into the storage space.

7. The method according to claim 6, characterized in that, The method further includes: If the first target processor identifier does not match the processor identifier of the second processor core, the second processor core performs geometric processing on the second data segment.

8. The method according to any one of claims 1 to 4, characterized in that, The method further includes: If the first target processor identifier matches the processor identifier of the second processor core, the second processor core sends a response message to the first processor core. Upon receiving the response information, the first processor core stops broadcasting the first write end address and the first target processor identifier.

9. A graphics processing chip, characterized in that, The graphics processing chip includes multiple processor cores, each processor core being used to process a corresponding data segment in the geometric data to be processed, wherein: The first processor core is used to: obtain the first write end address of the first output data in the storage space; the first output data is obtained by the first processor core performing geometric processing on the corresponding first data segment, and is written into the storage space by the first processor core; The first processor core is also configured to: broadcast the first write end address and the first target processor identifier corresponding to the second data segment, wherein the second data segment is the next data segment of the first data segment; The second processor core is configured to: receive the first write end address and the first target processor identifier; if the first target processor identifier matches the processor identifier of the second processor core, write the second output data into the storage space based on the first write end address; the second output data is obtained by the second processor core performing geometric processing on the corresponding second data segment; the first processor core and the second processor core process the first data segment and the second data segment in parallel.

10. The graphics processing chip according to claim 9, characterized in that, The first processor core is further configured to: after the first processor core determines the first write end address, broadcast the first write end address and the first target processor identifier; the first write end address is determined by the first processor core after receiving the first task based on the first data volume corresponding to the first output sub-data to be output by the first task and the first write start address; the first task is the last task of the first data segment.

11. The graphics processing chip according to claim 10, characterized in that, The first processor core includes at least two sub-processing units, each of which is used to process a corresponding sub-data segment in the first data segment to be processed, wherein: The first sub-processing unit is configured to: in response to receiving the first task, obtain the first data volume and the first write start address corresponding to the first output sub-data to be output by the first task; the first task is the last task of the first sub-data segment corresponding to the first sub-processing unit; the first sub-data segment is the last data segment in the first data segment.

12. The graphics processing chip according to claim 9, characterized in that, The first processor core is further configured to: after writing the first output data into the storage space, obtain the first write end address.

13. The graphics processing chip according to any one of claims 9 to 12, characterized in that, The second processor core is further configured to: after the second processor core writes the second output data into the storage space, broadcast the second write end address of the second output data in the storage space, and the second target processor identifier corresponding to the third data segment, wherein the third data segment is the next data segment of the second data segment.

14. The graphics processing chip according to any one of claims 9 to 12, characterized in that, The second processor core is further configured to: continue waiting to write the second output data into the storage space if the first target processor identifier does not match the processor identifier of the second processor core.

15. The graphics processing chip according to claim 14, characterized in that, The second processor core is further configured to perform geometric processing on the second data segment when the first target processor identifier does not match the processor identifier of the second processor core.

16. The graphics processing chip according to any one of claims 9 to 12, characterized in that, The second processor core is further configured to: send response information to the first processor core if the first target processor identifier matches the processor identifier of the second processor core; The first processor core is further configured to: in response to receiving the response information, stop broadcasting the first write end address and the first target processor identifier.

17. A computer device, characterized in that, Includes the graphics processing chip as described in any one of claims 9 to 16.

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