A method for using a non-volatile memory based on an RRAM+FCM structure

Abstract

This invention proposes a method for using a non-volatile memory based on an RRAM+FCM structure, belonging to the field of novel non-volatile memory technology. It involves connecting an FCM device and an RRAM device in series to obtain a memory device; adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device; and adjusting the voltage applied across the memory terminals to adjust the memory's operating delay, thus obtaining the operating delay adjustment result. This invention solves the shortcomings of traditional ferroelectric capacitors used in memory device design, such as insufficient switching ratio and susceptibility to external signal interference leading to misjudgments. Furthermore, this invention enables multi-value storage, is applicable to a wider range of environmental conditions, and offers advantages such as high speed, low power consumption, and long retention time.

Description

Technical Field

[0001] This invention proposes a method for using a non-volatile memory based on an RRAM+FCM structure, which relates to the field of non-volatile memory technology, specifically to the field of non-volatile memory based on an RRAM+FCM structure. Background Technology

[0002] Traditional memory methods utilize a series connection of a memristor (RRAM) and a ferroelectric capacitor memory (FCM) to form an RC memory. The RRAM exhibits two resistance states—high resistance (HRS) and low resistance (LRS)—under different write voltages, such as 100KΩ and 1KΩ. RRAM has a very simple structure, is compatible with standard CMOS processes, and features low operating voltage, fast read / write speeds, and low power consumption. Its storage cells are variable resistors implemented using one or more metal oxides, and it has been widely studied in non-volatile memory applications. Ferroelectric capacitors exhibit capacitive switching between a high capacitance state (HCS) and a low capacitance state (LCS) by applying an appropriate voltage. They offer advantages such as fast read / write speeds and low power consumption. However, the high-to-low capacitance ratio can only reach a maximum of around 100, and it is easily interfered with by small external noise signals, leading to misjudgments. Traditional ferroelectric memories are also susceptible to defects and electrode interface effects, resulting in reduced device durability. Summary of the Invention

[0003] This invention provides a method for using a non-volatile memory based on an RRAM+FCM structure, addressing the problems of traditional ferroelectric capacitors, such as insufficient high-to-low capacitance ratio, susceptibility to external noise interference leading to misjudgment of status, reduced durability due to ferroelectric material defects and electrode interface effects, resulting in fewer erase / write cycles, and insufficient cycle count hindering mass production in the industrial sector.

[0004] This invention proposes a method for using a non-volatile memory based on an RRAM+FCM structure, the method comprising:

[0005] By connecting an FCM device and an RRAM device in series, a memory device can be obtained;

[0006] The high and low resistance states of RRAM devices and the high and low capacitance states of FCM devices are controlled by adjusting the applied voltage.

[0007] The operating delay of the memory is adjusted by regulating the voltage applied across the two terminals of the memory, thereby obtaining the operating delay adjustment result.

[0008] Furthermore, the RRAM device includes an RRAM bottom electrode material 100, a metal oxide 101, and a top electrode material 102.

[0009] Furthermore, the method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes: applying a bias voltage to the two terminals of the RRAM device, performing set and reset conversions to obtain the high and low resistance states, and setting an upper limit for the current.

[0010] Furthermore, the step of applying a bias voltage to the two terminals of the RRAM device and performing set and reset conversions to obtain high and low resistance states includes:

[0011] Apply a forward bias voltage to the two electrodes of the RRAM device to obtain the oxygen vacancy conductive channel formed inside the metal oxide;

[0012] When the voltage increases, the oxygen vacancy conductive channel thickens, the current increases, the resistance decreases, and a low-resistance state is obtained.

[0013] Furthermore, the step of applying a bias voltage to the two terminals of the RRAM device and performing set and reset conversions to obtain high and low resistance states also includes:

[0014] By applying a negative bias voltage to the two electrodes of the RRAM device, oxygen ions are obtained through the active electrode of the RRAM device. These oxygen ions recombine with oxygen vacancies in the conductive channel, causing the oxygen vacancy conductive channel to open, thus reducing the current and increasing the resistance, resulting in a high-resistance state. Furthermore, the device can be controlled to operate in intermediate states with different resistance values ​​by controlling the voltage magnitude.

[0015] Furthermore, the FCM device includes a pn junction region 001, a ferroelectric material 002, an FCM bottom electrode material 003, a gate electrode material 004, and an oxide layer material (005).

[0016] Furthermore, the method of adjusting the applied voltage to regulate the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes applying a bias voltage to the two terminals of the FCM device and controlling the capacitance state of the device by adjusting the magnitude of the bias voltage.

[0017] Furthermore, the method of applying a bias voltage to the two terminals of the FCM device, and controlling the capacitance state of the device by adjusting the magnitude of the bias voltage, includes:

[0018] Applying a forward bias voltage to the two electrodes of the FCM device controls the polarization of the ferroelectric material downward, attracting electrons at the interface, increasing the width of the np depletion layer, and obtaining a low capacitance state.

[0019] Applying a negative bias voltage to the two electrodes of the FCM device controls the polarization of the ferroelectric material upward, attracting holes at the interface, reducing the width of the np depletion layer, and obtaining a high capacitance state.

[0020] Furthermore, the method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the capacitance value of the FCM device includes:

[0021] The RRAM bottom electrode material 100 and the gate electrode material 004 share the same gate electrode to form the memory.

[0022] The high and low resistance states of the RRAM device are controlled by adjusting the voltage applied between the top electrode material 102 and the bottom electrode material 100.

[0023] The high and low capacitance states of the FCM device are adjusted by regulating the voltage applied between the gate electrode material 004 and the FCM bottom electrode material 003.

[0024] Furthermore, by adjusting the voltage applied across the memory terminals, the memory's operating delay is adjusted, resulting in an operating delay adjustment, including:

[0025] The RRAM and FCM device are connected in series, and the static operating point is provided by a voltage source;

[0026] The operating delay of the memory can be adjusted by regulating the voltage;

[0027] The formula for calculating the delay is:

[0028] tdelay=-R*C*ln((EV) / E)

[0029] Where tdelay is the memory delay, E is the voltage between the resistor and capacitor, V is the voltage to be reached between the capacitors, R is the resistor, and C is the capacitor.

[0030] The beneficial effects of this invention are as follows: This invention creates a novel memory by connecting a ferroelectric capacitor memory (RRAM) and a memristor in series. Due to its inherent capacitance and resistance, this memory exhibits a delay characteristic, which can be used to display a delayed switch. When different capacitance and resistance states are connected in series, the device has different RC delay values. These values ​​serve as information storage windows, and values ​​are read by adjusting the pulse width, achieving read / write functionality. Simultaneously, the nonlinear resistance characteristics of RRAM and the high retention rate of ferroelectric capacitor memory can be utilized to achieve more stable multi-value storage by adjusting the pulse width. Therefore, this invention effectively overcomes the shortcomings of ordinary ferroelectric capacitors, which are easily interfered with and prone to misjudgment, amplifies and distinguishes different storage states, and improves the durability of the device. It solves the problem of traditional ferroelectric capacitors being easily interfered with by external signals, leading to misjudgments. Furthermore, this invention enables multi-value storage, is applicable to more environmental conditions, and has advantages such as high speed, low power consumption, and long retention time, showing significant advantages compared to previous technologies.

[0031] Therefore, this invention uses the device's operating delay value as an information storage window, adjusts the voltage to change the delay, and adjusts the read signal pulse width to read different signals. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the 2D structure of an RRAM device;

[0033] Figure 2 This is a schematic diagram of the I-V state transition curve for a unipolar RRAM device.

[0034] Figure 3 This is a schematic diagram of the 2D structure of an FCM device;

[0035] Figure 4 This is a schematic diagram of the capacitor state transition (CV) of an FCM device.

[0036] Figure 5 This is a 2D structure diagram of an RRAM-FCM device;

[0037] Figure 6 This is a schematic diagram of the device's working model;

[0038] Figure 7 This is a schematic diagram of the VT waveform under different operating conditions of the device.

[0039] Reference numerals: 100, RRAM bottom electrode material; 101, metal oxide; 102, top electrode material; 001, pn junction region; 002, ferroelectric material; 003, FCM bottom electrode material; 004, gate electrode material; 005, oxide layer material. Detailed Implementation

[0040] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0041] In one embodiment of the present invention, a method for using a non-volatile memory based on an RRAM+FCM structure is proposed, the method comprising:

[0042] By connecting an FCM device in series with an RRAM device, a memory device can be obtained, such as... Figure 5 As shown;

[0043] The high and low resistance states of RRAM devices and the high and low capacitance states of FCM devices are controlled by adjusting the applied voltage.

[0044] The operating delay of the memory is adjusted by regulating the voltage applied across the two terminals of the memory, thereby obtaining the operating delay adjustment result.

[0045] The RRAM device includes an RRAM bottom electrode material 100, a metal oxide 101, and a top electrode material 102, such as Figure 1 As shown.

[0046] The method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes: applying a bias voltage to the two terminals of the RRAM device, such as... Figure 2 As shown, the system performs set and reset operations to switch between high and low resistance states and sets the upper limit of current.

[0047] The process of applying a bias voltage to the two terminals of the RRAM device and performing set and reset switching to obtain high and low resistance states includes:

[0048] Apply a forward bias voltage to the two electrodes of the RRAM device to obtain the oxygen vacancy conductive channel formed inside the metal oxide;

[0049] When the voltage increases, the oxygen vacancy conductive channel thickens, the current increases, the resistance decreases, and a low-resistance state is obtained.

[0050] The method of applying a bias voltage to the two terminals of the RRAM device, performing set and reset conversions to obtain high and low resistance states, further includes:

[0051] By applying a negative bias voltage to the two electrodes of the RRAM device, oxygen ions are obtained through the active electrode of the RRAM device. These oxygen ions recombine with oxygen vacancies in the conductive channels, causing the oxygen vacancy conductive channels to open, thus reducing the current and increasing the resistance, resulting in a high-resistance state. Furthermore, the device can be controlled to operate in intermediate states with different resistance values ​​by controlling the voltage magnitude.

[0052] The FCM device includes a pn junction region 001, a ferroelectric material 002, an FCM bottom electrode material 003, a gate electrode material 004, and an oxide layer material 005, such as Figure 3 As shown;

[0053] The method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes applying a bias voltage to the two terminals of the FCM device and controlling the capacitance state of the device by adjusting the magnitude of the bias voltage. Figure 4 As shown;

[0054] The method of applying a bias voltage to the two terminals of the FCM device and controlling the capacitance state of the device by adjusting the magnitude of the bias voltage includes:

[0055] Applying a forward bias voltage to the two electrodes of the FCM device controls the polarization of the ferroelectric material downward, attracting electrons at the interface, controlling the increase of the np depletion layer width, generating depletion layer capacitance, and obtaining a low capacitance state.

[0056] Applying a negative bias voltage to the two electrodes of the FCM device controls the ferroelectric material to polarize upwards, attracting holes at the interface, reducing the width of the np depletion layer, eliminating the depletion layer capacitance, and achieving a high-capacitance state.

[0057] The method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes:

[0058] The RRAM bottom electrode material 100 and the gate electrode material 004 share the same gate electrode to form the memory.

[0059] Sharing means that the electrode materials in these two regions are the same, and the two parts can be merged into one.

[0060] The high and low resistance states of the RRAM device are controlled by adjusting the voltage applied between the top electrode material 102 and the bottom electrode material 100.

[0061] The high and low capacitance states of the FCM device are adjusted by regulating the voltage applied between the gate electrode material 004 and the FCM bottom electrode material 003.

[0062] The working principle and technical effect of the above technical solution are as follows: the metal oxide is the region where the RRAM conductive channel is formed. For example... Figure 2 As shown, when a bias voltage is applied to the electrodes of an RRAM device, it can switch between the SET and RESET processes, corresponding to high and low resistance states. Icc is the upper limit of the current set to prevent breakdown during the SET process. For unipolar RRAM, applying a positive bias voltage to the electrodes creates a thin oxygen vacancy conductive channel within the metal oxide. As the voltage increases, the conductive channel gradually thickens, the current increases, and the resistance decreases, resulting in a low-resistance state. Conversely, gradually decreasing the bias voltage causes the active electrodes to release oxygen ions. These oxygen ions recombine with the oxygen vacancies in the channel, gradually breaking the channel, reducing the current, increasing the resistance, and resulting in a high-resistance state. Therefore, by adjusting the voltage, the device can be controlled to be in intermediate resistance states.

[0063] The capacitance state transition (CV) diagram of an FCM device shows that when a positive bias is applied, the ferroelectric polarization is downward, attracting a large number of electrons at the interface, increasing the width of the np depletion layer, and generating depletion layer capacitance. In this state, the device exhibits low capacitance, enabling fast programming. When a negative bias is applied, the ferroelectric polarization is upward, attracting holes at the interface. These holes originate from interband tunneling at the pn junction in the channel layer. In this state, the depletion layer width decreases, the depletion layer capacitance disappears, and the device exhibits high capacitance, enabling fast erasure. Therefore, the device can be controlled to operate in different capacitance states by adjusting the bias voltage.

[0064] The memory device structure diagram shows an FCM structure and an RRAM structure connected in series. The device materials and physical properties are described using the structure above. 100 and 004 share the same gate electrode. The high and low resistance states of the RRAM section are controlled by adjusting the voltage applied between the top and gate electrodes, while the high and low capacitance states of the FCM section are controlled by adjusting the voltage applied between the gate and bottom electrodes. The operating states of the two sections are determined independently.

[0065] This invention creates a novel memory by connecting a ferroelectric capacitor memory (RRAM) and a memristor in series. The memory, due to its inherent capacitance and resistance, exhibits a delay characteristic, which can be used to display a delayed switch. When different capacitance and resistance states are connected in series, the device has different RC delay values. These values ​​are used as information storage windows, and the values ​​are read by adjusting the pulse width, achieving read / write functionality. Furthermore, by utilizing the non-linear resistive characteristics of RRAM and the high retention rate of the ferroelectric capacitor memory, more stable multi-value storage can be achieved by adjusting the pulse width.

[0066] Traditional ferroelectric capacitors have an insufficient high-to-low capacitance ratio, making them susceptible to external noise signals that can lead to misjudgments of their state; they are also affected by defects in ferroelectric materials and electrode interface effects.

[0067] This invention solves the shortcomings of traditional ferroelectric capacitors in designing memory devices, such as insufficient switching ratio and susceptibility to external signal interference leading to misjudgments.

[0068] Meanwhile, the present invention can realize multi-value storage, is applicable to more environmental conditions, and has advantages such as high speed, low power consumption and long retention time, which are obvious advantages compared with previous technologies.

[0069] In terms of basic structure, RRAM devices consist of a bottom electrode material, a metal oxide, and a top electrode material, achieving resistance state modulation through the formation and breakage of oxygen vacancy conductive channels. FCM devices, on the other hand, include a pn junction region, a ferroelectric material, a bottom electrode, a gate electrode, and an oxide layer material, utilizing the ferroelectric polarization characteristics to change the depletion layer width to control the capacitance state. When the two are connected in series, an integrated gate structure is formed through the shared design of the bottom electrode and the gate electrode.

[0070] The devices achieve core performance control through a dual-path independent adjustment mechanism. For RRAM devices, applying a positive bias voltage induces the formation of oxygen vacancy conductive channels within the metal oxide. As the voltage increases, the channels widen, and the device enters a low-resistance state. Applying a negative bias voltage causes oxygen ions from the active electrode to recombine with the oxygen vacancies in the channels, breaking the channels and transitioning the device to a high-resistance state. Multiple intermediate resistance states can be stably achieved through voltage amplitude control. For FCM devices, a positive bias voltage polarizes the ferroelectric material downwards, attracting electrons at the interface and widening the np depletion layer, resulting in a low-capacitance state. A negative bias voltage polarizes upwards, attracting holes at the interface and narrowing the depletion layer, transitioning to a high-capacitance state. Continuous or stepwise capacitance changes can be achieved by adjusting the bias voltage magnitude. Furthermore, by connecting the RRAM and FCM in series, precise control of the operating delay is achieved through voltage regulation.

[0071] The independent adjustability of the resistive and capacitive states enables the device to have multi-dimensional storage capabilities, significantly improving information density compared to memory with single-parameter control. The combination of intermediate resistive state and wide-range capacitance adjustment simplifies circuit design and reduces power consumption. The shared electrode structure reduces connection losses between devices and improves control efficiency, while the adjustable operating delay enhances the device's adaptability to different circuit environments.

[0072] In one embodiment of the present invention, RRAM devices and FCM devices are connected in series, and the operating delay of the memory is adjusted by regulating the voltage applied across the two terminals of the memory, thereby obtaining an operating delay adjustment result, including:

[0073] The RRAM is connected in series with the FCM device, and the static operating point is provided by a voltage source, such as... Figure 6 As shown;

[0074] The operating delay of the memory can be adjusted by regulating the voltage;

[0075] The formula for calculating the delay is:

[0076] tdelay=-R*C*ln((EV) / E)

[0077] Where tdelay is the memory delay, E is the voltage between the resistor and capacitor, V is the voltage to be reached between the capacitors, R is the resistor, and C is the capacitor. For example... Figure 7 The figure shows the voltage-time waveform when the device is working. As can be seen from the figure, t1 and t3 are the times when the device is in the low level "0" state, and t2 and t4 are the times when the device is in the high level "1" state. Different delay values ​​will be obtained in different states of the device, such as "t2-t1" and "t4-t3".

[0078] The formula is simplified to seconds, using a formula conversion method recognized in this field.

[0079] The working principle and technical effect of the above technical solution are as follows: it is composed of RRAM and FCM connected in series, and a voltage source provides the static operating point. The working mechanism of this memory is to adjust the working delay of the voltage regulation device, so the delay of the working circuit can be calculated.

[0080] This invention uses the device's operating delay value as an information storage window. The delay is altered by adjusting the voltage, and different signals are read by adjusting the read signal pulse width: a calculated delay of 1 ns results in a read signal with a pulse width less than 1 ns (e.g., 0.1 ns) reading "0", while a pulse width greater than 1 ns (e.g., 2 ns) reads "1". An adjustable delay memory cell is constructed by connecting an RRAM device and an FCM device in series. A voltage source provides the static operating point, laying the foundation for delay adjustment. The core control mechanism dynamically adjusts the resistance (R) of the RRAM and the capacitance (C) of the FCM by changing the applied voltage, and then accurately calculates the memory's operating delay using the formula tdelay=-RCln((EV) / E) (where E is the voltage between the resistor and capacitor, and V is the required voltage for the capacitor).

[0081] like Figure 7 As shown, t1 and t3 correspond to the low-level "0" state, and t2 and t4 correspond to the high-level "1" state. The delay values ​​(such as t2-t1 and t4-t3) differ in different states. This is because the R and C parameters change with the voltage during the high-low level transition, which causes the delay result to change dynamically.

[0082] By achieving dynamic adjustment of delay through voltage regulation, the limitations of fixed delay in traditional memory are overcome, and the flexibility of circuit timing adaptation is improved. Quantitative adjustment is achieved based on explicit mathematical formulas to ensure the accuracy of delay control and meet the timing requirements of different scenarios. Combining the characteristics of RRAM and FCM, multiple delay levels are generated by utilizing the difference between high and low level states, which effectively reduces system power consumption and improves computing efficiency, making it particularly suitable for intelligent storage and computing scenarios that require flexible timing configuration.

[0083] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for using a non-volatile memory based on an RRAM+FCM structure, characterized in that, The method includes: By connecting an FCM device and an RRAM device in series, a memory device can be obtained; The high and low resistance states of RRAM devices and the high and low capacitance states of FCM devices are controlled by adjusting the applied voltage. The operating delay of the memory is adjusted by regulating the voltage applied across the two terminals of the memory, thereby obtaining the operating delay adjustment result; The method involves adjusting the voltage applied across the memory terminals to regulate the memory's operating delay, thereby obtaining the operating delay adjustment result, including: The static operating point is provided by a voltage source; The operating delay of the memory can be adjusted by regulating the voltage applied to the two poles of the memory. The formula for calculating the delay is: tdelay=-R*C*ln((EV) / E) Where tdelay is the memory delay, E is the voltage between the resistor and the capacitor, V is the voltage to be reached between the capacitors, R is the resistor, and C is the capacitor. The RRAM device includes an RRAM bottom electrode material (100), a metal oxide (101), and a top electrode material (102). The FCM device includes a pn junction region (001), a ferroelectric material (002), an FCM bottom electrode material (003), a gate electrode material (004), and an oxide layer material (005). The RRAM bottom electrode material (100) and the gate electrode material (004) share the gate electrode of the memory.

2. The method of using a non-volatile memory based on an RRAM+FCM structure according to claim 1, characterized in that, The method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes: A bias voltage is applied to the two terminals of the RRAM device, and the device is switched between set and reset states to obtain high and low resistance states, and an upper limit of current is set.

3. The method of using a non-volatile memory based on an RRAM+FCM structure according to claim 2, characterized in that, The process of applying a bias voltage to the two terminals of the RRAM device and performing set and reset switching to obtain high and low resistance states includes: Apply a forward bias voltage to the two electrodes of the RRAM device to obtain the oxygen vacancy conductive channel formed inside the metal oxide; When the voltage increases, the oxygen vacancy conductive channel thickens, the current increases, the resistance decreases, and a low-resistance state is obtained.

4. The method of using a non-volatile memory based on an RRAM+FCM structure according to claim 2, characterized in that, The method of applying a bias voltage to the two terminals of the RRAM device, performing set and reset conversions to obtain high and low resistance states, further includes: A negative bias voltage is applied to the two electrodes of the RRAM device, and oxygen ions are obtained through the active electrode of the RRAM device. The oxygen ions recombine with the oxygen vacancies in the conductive channel, and the oxygen vacancy conductive channel is controlled to open, the current decreases, the resistance increases, and a high-resistance state is obtained.

5. The method of using a non-volatile memory based on an RRAM+FCM structure according to claim 1, characterized in that, The method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes applying a bias voltage to the two terminals of the FCM device and controlling the capacitance state of the device by adjusting the magnitude of the bias voltage.

6. The method of using a non-volatile memory based on an RRAM+FCM structure according to claim 5, characterized in that, The method of applying a bias voltage to the two terminals of the FCM device and controlling the capacitance state of the device by adjusting the magnitude of the bias voltage includes: Applying a forward bias voltage to the two electrodes of the FCM device controls the polarization of the ferroelectric material downward, attracting electrons at the interface, controlling the increase of the np depletion layer width, generating depletion layer capacitance, and obtaining a low capacitance state. By applying a negative bias voltage to the two electrodes of the FCM device, the polarization of the ferroelectric material is controlled to be upward, which attracts holes at the interface, controls the reduction of the np depletion layer width, and eliminates the depletion layer capacitance, thus obtaining a high capacitance state.

7. The method of using a non-volatile memory based on an RRAM+FCM structure according to claim 1, characterized in that, The method of adjusting the applied voltage to control the high and low resistance states of the RRAM device and the high and low capacitance states of the FCM device includes: The high and low resistance states of the RRAM device are controlled by adjusting the voltage applied between the top electrode material (102) and the bottom electrode material (100); The high and low capacitive states of the FCM device are adjusted by regulating the voltage applied between the gate electrode material (004) and the FCM bottom electrode material (003).

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