Refresh control circuit and refresh control method

Abstract

The invention provides a refresh control circuit and a refresh control method, and the circuit comprises a decoding circuit which is configured to generate and output a directional refresh window signal; a plurality of address sampling circuits, each of which is configured to generate and output a corresponding address sampling signal according to the trigger signal, sample a currently activated row address according to the address sampling signal, and latch the row address as a directional refresh management address; when the corresponding trigger signal is not received, the corresponding address sampling signal is not generated; a plurality of directional refresh control circuits, each directional refresh control circuit configured to generate and output an activation enable signal during a period when the directional refresh window signal is valid if a corresponding address sampling signal has been received before the directional refresh window signal is received; and if the corresponding address sampling signal is not received before the directional refresh window signal is received, the activation enable signal is not generated during the period when the directional refresh window signal is valid.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of memory refresh control, in particular to a refresh control circuit and a refresh control method. BACKGROUND

[0002] Double data rate fifth generation memory (DDR5) has been widely promoted due to its excellent performance.

[0003] Refresh management (RFM) and direct refresh management (DRFM) are both optional functions in DDR5; wherein, both refresh management and direct refresh management refresh risk addresses in the memory to maintain the integrity of the data inside the memory.

[0004] The difference is that the risk addresses refreshed in the refresh management are provided by the address sampling module (DLUT) inside the bank, and each bank corresponds to an address sampling module, and each bank provides the corresponding risk address, and when the refresh management all-bank (RFMab) command is issued, all banks have corresponding risk addresses refreshed. In the direct refresh management, the risk addresses refreshed are provided by the storage controller (Controller), and then the direct refresh management refreshes the physically adjacent rows of the risk addresses provided by the storage controller. SUMMARY

[0005] The present disclosure provides a refresh control circuit and a refresh control method to reduce the potential row hammer risk in the DRFM mode.

[0006] The embodiment of the present disclosure provides a refresh control circuit, comprising: a decoding circuit configured to decode a received targeted refresh management command during activation of a targeted refresh management mode, generate and output a targeted refresh window signal; a plurality of address sampling circuits corresponding to a plurality of memory banks one by one; each address sampling circuit is configured to generate and output a corresponding address sampling signal in response to a trigger signal of the corresponding memory bank, sample the currently activated row address according to the address sampling signal, and latch it as a targeted refresh management address; and when the corresponding trigger signal is not received, the corresponding address sampling signal is not generated; a plurality of targeted refresh control circuits corresponding to a plurality of address sampling circuits one by one; each targeted refresh control circuit is electrically connected with the corresponding address sampling circuit, and is configured to, if the corresponding address sampling signal has been received before the targeted refresh window signal is received, generate and output an activation enable signal during the validity period of the targeted refresh window signal; and if the corresponding address sampling signal is not received before the targeted refresh window signal is received, the activation enable signal is not generated during the validity period of the targeted refresh window signal.

[0007] In some embodiments, the address sampling circuit comprises a sampling signal generation circuit and an address register, the trigger signal comprises a first trigger signal and a second trigger signal; the sampling signal generation circuit is configured to, in response to receiving the corresponding first trigger signal or the second trigger signal, generate and output an address sampling signal, and when the corresponding first trigger signal and the second trigger signal are not received, the address sampling signal is not generated; the address register is configured to sample the currently activated row address in response to the address sampling signal, and latch it as the targeted refresh management address.

[0008] In some embodiments, the sampling signal generation circuit comprises: a NOR logic unit, a first NAND logic unit and a second NAND logic unit; the first input end of the NOR logic unit receives the first trigger signal, the second input end receives the second trigger signal, and the output end is electrically connected with the first input end of the first NAND logic unit; the second input end of the first NAND logic unit is electrically connected with the output end of the second NAND logic unit, and the output end of the first NAND logic unit is used for outputting the address sampling signal; the first input end of the second NAND logic unit is electrically connected with the output end of the first NAND logic unit, the second input end of the second NAND logic unit receives a corresponding reset control signal, and the reset control signal is used for configuring the valid time of the address sampling signal as a row precharge time; the address register comprises a flip-flop; the input end of the flip-flop receives the currently activated row address, the clock end receives the address sampling signal, and the output end outputs the targeted refresh management address.

[0009] In some embodiments, the targeted refresh control circuit includes a control signal generation circuit and an activation control circuit; the control signal generation circuit is configured to receive the targeted refresh window signal and the address sampling signal, and generate and output a targeted refresh control signal according to the targeted refresh window signal and the address sampling signal; wherein, in response to the address sampling signal, the targeted refresh control signal is outputted after being flipped from an invalid level to a valid level, and in response to a flip edge of the end of the targeted refresh window signal, the targeted refresh control signal is flipped from the valid level to the invalid level; the activation control circuit is configured to receive the targeted refresh control signal, the targeted refresh window signal and a bank activation signal, and when the targeted refresh control signal is at the valid level and during the period when the targeted refresh window signal is valid, output the bank activation signal as the activation enable signal; and when the targeted refresh control signal is at the invalid level, then mask the bank activation signal during the period when the targeted refresh window signal is valid.

[0010] In some embodiments, the control signal generation circuit includes a first NOT logic unit, a second NOT logic unit, a third NAND logic unit and a fourth NAND logic unit; an input end of the first NOT logic unit receives the address sampling signal, and an input end of the second NOT logic unit receives the targeted refresh window signal; a first input end of the third NAND logic unit is electrically connected to an output end of the first NOT logic unit, a second input end of the third NAND logic unit is electrically connected to an output end of the fourth NAND logic unit, and an output end of the third NAND logic unit is used to output the targeted refresh control signal; a first input end of the fourth NAND logic unit is electrically connected to the output end of the third NAND logic unit, and a second input end of the fourth NAND logic unit is electrically connected to an output end of the second NOT logic unit; the activation control circuit includes a third NOT logic unit, a fifth NAND logic unit and a first AND logic unit; an input end of the third NOT logic unit receives the targeted refresh control signal; a first input end of the fifth NAND logic unit receives the targeted refresh window signal, and a second input end of the fifth NAND logic unit is electrically connected to an output end of the third NOT logic unit; a first input end of the first AND logic unit receives the bank activation signal, a second input end of the first AND logic unit is electrically connected to an output end of the fifth NAND logic unit, and an output end of the first AND logic unit is used to output the activation enable signal.

[0011] In some embodiments, the decoding circuit is further configured to decode a first trigger command received during the activation of the directional refresh management mode, and generate the first trigger signal corresponding to a target memory bank indicated by memory bank address information in the first trigger command, and send the first trigger signal to the corresponding address sampling circuit, or decode a second trigger command received, and generate the second trigger signal corresponding to a target memory bank indicated by memory bank address information in the second trigger command, and send the second trigger signal to the corresponding address sampling circuit.

[0012] In some embodiments, the first level of the refresh mode parameter indicates activation of the directional refresh management mode, and the second level of the refresh mode parameter indicates deactivation of the directional refresh management mode; wherein the refresh mode parameter is written into a specific mode register by a mode register write command.

[0013] The embodiments of the present disclosure provide a refresh control method, the memory includes a plurality of directional refresh control circuits and a plurality of memory banks, the plurality of directional refresh control circuits correspond to the plurality of memory banks one by one, including: decoding a received directional refresh management command during activation of a directional refresh management mode, and generating a directional refresh window signal; if any directional refresh control circuit has received the corresponding directional refresh management address before receiving the directional refresh window signal, generating and outputting an activation enable signal during the validity of the directional refresh window signal to activate the refresh operation of the word line in the corresponding memory bank; if any directional refresh control circuit has not sampled the corresponding directional refresh management address before receiving the directional refresh window signal, the activation enable signal is not generated during the validity of the directional refresh window signal.

[0014] In some embodiments, the memory further includes a plurality of address sampling circuits corresponding to the plurality of memory banks, and any address sampling circuit samples the currently activated row address in response to the trigger signal of the corresponding memory bank and latches it as the corresponding directional refresh management address; if any address sampling circuit does not receive the corresponding trigger signal, no address sampling operation is performed.

[0015] The embodiment of the present disclosure provides a refresh control circuit, comprising: a decoding circuit configured to decode a received targeted refresh management command during activation of a targeted refresh management mode, generate and output a targeted refresh window signal; a plurality of address sampling circuits corresponding to a plurality of memory banks one by one; each of the address sampling circuits is configured to generate and output a corresponding address sampling signal in response to a trigger signal of the corresponding memory bank, sample a currently activated row address according to the address sampling signal, and latch as a corresponding targeted refresh management address; and when the corresponding trigger signal is not received, the corresponding address sampling signal is not generated; a plurality of refresh address control circuits corresponding to the plurality of address sampling circuits and the plurality of memory banks one by one; each of the refresh address control circuits is electrically connected with the corresponding address sampling circuit, and is configured to, if the corresponding address sampling signal has been received before the targeted refresh window signal is received, select and output the corresponding targeted refresh management address during the validity period of the targeted refresh window signal; and if the corresponding address sampling signal has not been received before the targeted refresh window signal is received, select and output a row hammer address of the corresponding memory bank during the validity period of the targeted refresh window signal.

[0016] In some embodiments, the refresh address control circuit comprises a selection signal generation circuit and an address selection circuit; the selection signal generation circuit is configured to receive the targeted refresh window signal and the address sampling signal, and generate and output an address selection signal according to the targeted refresh window signal and the address sampling signal; wherein, if the corresponding address sampling signal has been received before the targeted refresh window signal is received, the address selection signal is switched to a first level and then output during the validity period of the targeted refresh window signal, and if the corresponding address sampling signal has not been received before the targeted refresh window signal is received, the address selection signal output during the validity period of the targeted refresh window signal maintains a second level unchanged; the address selection circuit is configured to receive the address selection signal, the targeted refresh management address and the row hammer address, and during the validity period of the targeted refresh window signal, select and output the corresponding targeted refresh management address according to the address selection signal at the first level, and select and output the row hammer address of the corresponding memory bank according to the address selection signal at the second level.

[0017] In some embodiments, the selection signal generation circuit includes: a fourth non-logic unit, a fifth non-logic unit, a sixth NAND logic unit, a seventh NAND logic unit, and a second AND logic unit; an input terminal of the fourth non-logic unit receives the address sampling signal, and an input terminal of the fifth non-logic unit receives the directional refresh window signal; a first input terminal of the sixth NAND logic unit is electrically connected to an output terminal of the fourth non-logic unit, and a second input terminal of the sixth NAND logic unit is electrically connected to an output terminal of the seventh NAND logic unit; a first input terminal of the seventh NAND logic unit is electrically connected to an output terminal of the sixth NAND logic unit, and a second input terminal of the seventh NAND logic unit is electrically connected to an output terminal of the fifth non-logic unit; a first input terminal of the second AND logic unit receives the directional refresh window signal, a second input terminal is electrically connected to an output terminal of the sixth NAND logic unit, and an output terminal is used to output the address selection signal; the address selection circuit includes: a selection unit; a first input terminal of the selection unit receives the corresponding directional refresh management address, a second input terminal receives the row hammer address of the corresponding memory bank, and a control terminal receives the address selection signal.

[0018] In some embodiments, the refresh control circuit further includes: a plurality of row hammer address registers corresponding to the plurality of memory banks; the row hammer address register is configured to store the row hammer address of the corresponding memory bank.

[0019] The embodiments of the present disclosure provide a refresh control method, applied to a memory, the memory including a plurality of directional refresh control circuits and a plurality of memory banks, the plurality of directional refresh control circuits corresponding to the plurality of memory banks one by one, including: decoding a received directional refresh management command to generate a directional refresh window signal during activation of a directional refresh management mode; if any of the directional refresh control circuits has received the corresponding directional refresh management address before receiving the directional refresh window signal, then outputting the corresponding directional refresh management address during the validity period of the directional refresh window signal to control the refresh operation of the adjacent rows of the directional refresh management address in the corresponding memory bank; if any of the directional refresh control circuits has not sampled the corresponding directional refresh management address before receiving the directional refresh window signal, then outputting the row hammer address of the corresponding memory bank during the validity period of the directional refresh window signal to control the refresh operation of the adjacent rows of the row hammer address in the corresponding memory bank.

[0020] In some embodiments, the memory further comprises a plurality of address sampling circuits corresponding to the plurality of memory banks one by one, if any of the address sampling circuits samples the current active row address in response to the trigger signal of the corresponding memory bank and latches it as the corresponding directional refresh management address; if any of the address sampling circuits does not receive the corresponding trigger signal, it does not perform the address sampling operation.

[0021] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0022] In some embodiments, by controlling the memory bank that does not receive the risk address to skip the refresh process of the default address or the adjacent row of the last risk address during the DRFM process, the row hammer attack caused by the frequent refresh of the default address or the adjacent row of the last risk address by the memory bank when the memory frequently receives the DRFM command is avoided.

[0023] In some embodiments, by controlling the memory bank that does not receive the adjacent row of the risk address to change the refresh process of the default address or the last risk address to the refresh process of the adjacent row of the row hammer address during the DRFM process, the row hammer attack caused by the frequent refresh of the default address or the adjacent row of the last risk address by the memory bank when the memory frequently receives the DRFM command is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0024] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate like elements, and in which: the drawings are not necessarily to scale as the emphasis instead is placed upon illustrating the embodiments, and; for the purpose of clarity, not every component can be shown in the drawings, and; the drawings are included to provide a more thorough understanding of the embodiments disclosed in the present patent document and the description herein and are part of the present patent document for the purpose of clarity only; as will be appreciated by a person skilled in the art, other drawings can be derived from the drawings disclosed herein without departing from the scope of the present patent document.

[0025] Figure 1 An example of the structure that may cause row hammer attack by DRFM;

[0026] Figure 2 A module structure diagram of the refresh control circuit provided by the first embodiment of the present disclosure;

[0027] Figure 3 A corresponding relationship diagram between the decoding circuit, the address sampling circuit, the directional refresh control circuit and the memory bank provided by the first embodiment of the present disclosure;

[0028] Figure 4 A module structure diagram of the address sampling circuit provided by the first embodiment of the present disclosure;

[0029] Figure 5 The truth value representation of the memory control command provided for the first embodiment of the present disclosure intends to;

[0030] Figure 6 The specific structure diagram of the sampling signal generation circuit provided for the first embodiment of the present disclosure is shown in the figure;

[0031] Figure 7 The specific structure diagram of the address register provided for the first embodiment of the present disclosure is shown in the figure;

[0032] Figure 8 The working principle timing diagram of the address sampling circuit provided for the first embodiment of the present disclosure is shown in the figure;

[0033] Figure 9 The module structure diagram of the directional refresh control circuit provided for the first embodiment of the present disclosure is shown in the figure;

[0034] Figure 10 The specific structure diagram of the control signal generation circuit provided for the first embodiment of the present disclosure is shown in the figure;

[0035] Figure 11 The generation principle timing diagram of the directional refresh control signal provided for the first embodiment of the present disclosure is shown in the figure;

[0036] Figure 12 The specific structure diagram of the activation control circuit provided for the first embodiment of the present disclosure is shown in the figure;

[0037] Figure 13 The principle timing diagram of the activation enable signal generated by different memory banks according to the memory bank activation signal provided for the first embodiment of the present disclosure is shown in the figure;

[0038] Figure 14 The module structure diagram of the refresh control circuit provided for the third embodiment of the present disclosure is shown in the figure;

[0039] Figure 15 The corresponding relationship diagram between the decoding circuit, the address sampling circuit, the refresh address control circuit and the memory bank provided for the third embodiment of the present disclosure is shown in the figure;

[0040] Figure 16 The module structure diagram of the refresh address control circuit provided for the third embodiment of the present disclosure is shown in the figure;

[0041] Figure 17 The specific structure diagram of the selection signal generation circuit provided for the third embodiment of the present disclosure is shown in the figure;

[0042] Figure 18 The specific structure diagram of the address selection circuit provided for the third embodiment of the present disclosure is shown in the figure;

[0043] Figure 19 A principle timing diagram for selecting an output direction of a refresh management address or a row hammer address by different memory banks is provided for a third embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In the description of the embodiments of the present disclosure, the technical terms "first", "second", and the like are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0045] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] In the description of the embodiments of the present disclosure, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists, A and B exist, and B exists. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0047] In the description of the embodiments of the present disclosure, the term "a plurality of" refers to two or more (including two), and similarly, "a plurality of groups" refers to two or more groups (including two groups), and "a plurality of pieces" refers to two or more pieces (including two pieces).

[0048] As known from the background art, DDR5 memory supports two refresh management modes (RFM and DRFM), and for DRFM, DDR5 memory supports two ways to provide risk addresses, one of which is to obtain a risk address in response to each memory bank precharge command (Precharge per-bank, PREpb); the second is to obtain a risk address in response to a WRPA command (Write-Pattern with Auto-Precharge) in the memory, a WRA command (Write with Auto-Precharge), or a RDA command (Read with Auto-Precharge).

[0049] In one example, when the DRFM is enabled, the PREpb command is executed, and the memory will sample the DRFM at the currently active address; or, when the DRFM is enabled, the WRPA command, the WRA command or the RDA command is executed, and the memory will sample the DRFM at the currently active address. The specification of the memory stipulates that each memory has an independent address register for DRFM risk address sampling, which is updated with each DRFM risk address sampling, thereby providing the latest risk address for the DRFM command.

[0050] Since the DRFM risk address sampling can only be performed through the PREpb command, the WRPA command, the WRA command or the RDA command, the DRFM can only provide the risk address of one memory bank at a time; and the DRFMab (DRFM all-bank) command or the DRFMsb (DRFM same-bank) command of the memory is a refresh operation for all or multiple memory banks, and for the memory banks that do not receive the risk address, the refresh of the default address (for example, the address "0000") or the last risk address will be performed in the DRFM command. When the DRFM command comes frequently, the default address or the last risk address row hammer attack can be caused, and with the progress of the technology node, this risk will continue to increase.

[0051] In one example, referring to Figure 1 , it is assumed that the memory includes 8 memory banks (B0-B7). For one DRFMab command, if the memory bank B2 receives the risk address DRFM sample, in this DRFM command, the memory bank B2 refreshes the risk address DRFM sample, and the other memory banks refresh the default address or the last risk address; if the memory bank B0 does not receive the risk address in multiple DRFMab commands, the memory bank B0 refreshes the adjacent row of the default address or the adjacent row of the last risk address multiple times, thereby causing the row hammer attack risk of the adjacent row of the default address or the adjacent row of the last risk address, and with the rapid development of the process, this risk will continue to increase.

[0052] The present disclosure provides a refresh control circuit and a refresh control method to reduce the potential row hammer risk in the mode DRFM.

[0053] The first embodiment of the present disclosure provides a refresh control circuit, comprising: a decoding circuit configured to decode a received directional refresh management command during activation of a directional refresh management mode, generate and output a directional refresh window signal; a plurality of address sampling circuits corresponding one-to-one to a plurality of memory banks; each address sampling circuit is configured to generate and output a corresponding address sampling signal in response to a trigger signal of the corresponding memory bank, sample a currently activated row address according to the address sampling signal, and latch as a directional refresh management address; and when the corresponding trigger signal is not received, the corresponding address sampling signal is not generated; a plurality of directional refresh control circuits corresponding one-to-one to the plurality of address sampling circuits; each directional refresh control circuit is electrically connected to the corresponding address sampling circuit, and is configured to generate and output an activation enable signal during a valid period of the directional refresh window signal if the corresponding address sampling signal has been received before the directional refresh window signal is received; and if the corresponding address sampling signal has not been received before the directional refresh window signal is received, the activation enable signal is not generated during the valid period of the directional refresh window signal.

[0054] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0055] Reference Figure 2 The refresh control circuit 100 provided by the embodiment includes a decoding circuit 101, a plurality of address sampling circuits 102, and a plurality of directional refresh control circuits 103.

[0056] The decoding circuit 101 is configured to decode a received directional refresh management command DRFM during activation of a directional refresh management mode, generate and output a directional refresh window signal WIN_DRFM.

[0057] The directional refresh window signal WIN DRFM is used to instruct the corresponding memory bank to perform the directional refresh operation during the period when the directional refresh window signal WIN DRFM is at the active level. The directional refresh management command DRFM includes a global directional refresh management command DRFMab and a same bank directional refresh management command DRFMsb. The global directional refresh management command DRFMab is used to instruct all memory banks to perform the directional refresh operation during the period when the directional refresh window signal WIN DRFM is at the active level. The same bank directional refresh management command DRFMsb is used to instruct one memory bank in each memory bank group to perform the directional refresh operation during the period when the directional refresh window signal WIN DRFM is at the active level. The active level duration of the directional refresh window signal WIN DRFM is the duration during which the directional refresh management command DRFM (the global directional refresh management command DRFMab or the same bank directional refresh management command DRFMsb) can perform the directional refresh management operation.

[0058] Referring to Figure 2 and Figure 3 The plurality of address sampling circuits 102 correspond one-to-one to the plurality of memory banks 104. Each address sampling circuit 102 is configured to generate and output a corresponding address sampling signal SampelDRFM in response to a trigger signal of the corresponding memory bank 104 (address sample signal SampelDRFM <n:0>corresponding to n+1 memory banks 104 in the memory, SampelDRFM is the address sampling signal corresponding to the i+1th memory bank 104), and according to the address sampling signal SAMPELDRFM <n:0>RowADD <m:0>(m+1 is the number of bits of the row address) is sampled and latched as the directional refresh management address RaDRFM <m:0>; and when the corresponding trigger signal is not received, the corresponding address sampling signal SampleDRFM is not generated <n:0>.

[0059] It should be noted that, since the address sampling circuit 102 corresponds to the memory bank 104 one by one, that is, the number of address sampling circuits 102 in the refresh control circuit 100 is the same as the number of memory banks 104 in the memory, the embodiment is described in detail taking one address sampling circuit 102 as an example. In addition, Figure 3 In the example, the decoding circuit 101, the address sampling circuit 102 and the directional refresh control circuit 103 are placed in the memory bank 104, which does not represent that the decoding circuit 101, the address sampling circuit 102 and the directional refresh control circuit 103 are placed in the memory bank 104, but is used to represent the corresponding relationship between the decoding circuit 101, the address sampling circuit 102 and the directional refresh control circuit 103 and the memory bank 104.

[0060] The trigger signal is generated based on the PREpb command, the WRPA command, the WRA command or the RDA command, and is used to instruct the memory to sample the risky address of the DRFM. In one example, the trigger signal is a single pulse signal generated according to the PREpb command, the WRPA command, the WRA command or the RDA command.

[0061] For the address sampling signal SampelDRFM <n:0>whose ith bit of data is SampelDRFM (i is an arbitrary integer between 0 and n), for indicating whether the corresponding one memory bank 104 is for the currently activated row address RowADD <m:0>Sampling is performed. In one example, SampelDRFM a positive pulse edge of the clock signal CLK, indicating that the corresponding memory bank 104 is to store the current active row address RowADD <m:0>Sampling.

[0062] If the address sampling circuit 102 receives the corresponding trigger signal, the corresponding address sampling signal SampelDRFM is generated , if the address sampling circuit 102 does not receive the corresponding trigger signal, the corresponding address sampling signal SampelDRFM is not generated n+1 memory banks 104 correspond to different address sampling signals SampelDRFM <n:0>.

[0063] wherein, if the address sampling circuit corresponding to the memory bank 104 samples the current active row address RowADD <m:0>and latched as a directional refresh management address RaDRFM <m:0>, for subsequent use in a directed refresh management address (RaDRFM) <m:0>A refresh is performed, thereby implementing a refresh operation of the memory DRFM.

[0064] With reference to Figure 2 And Figure 3 A plurality of directional refresh control circuits 103 correspond to the plurality of address sampling circuits 102 one-to-one; each directional refresh control circuit 103 is electrically connected with the corresponding address sampling circuit 102, and the directional refresh control circuit 103 is configured to, during activation of the directional refresh management mode, if the corresponding address sampling signal SampelDRFM has been received before receiving the directional refresh window WIN_DRFM If the orientation refresh window signal WIN_DRFM is active, the active enable signal SecEn is generated and output ; and if the corresponding address sample signal SampelDRFM has not been received before the directional refresh window signal WIN_DRFM is received , the activation enable signal SecEn is not generated during the period in which the directional refresh window signal WIN_DRFM is valid .

[0065] It should be noted that since the directional refresh control circuit 103 corresponds one-to-one to the address sampling circuit 102, that is, the number of directional refresh control circuits 103 in the refresh control circuit 100 is the same as the number of storage bodies 104 in the memory, this embodiment is described in detail using one directional refresh control circuit 103 as an example.

[0066] Activate the enable signal SecEn The decoding and activating operation of the control enable word line in the DRFM is used to execute the directional refresh operation.

[0067] If the corresponding address sample signal SampelDRFM has been received before receiving the directional refresh window WIN_DRFM If the address sample circuit 102 has sampled the risk address specified by the DRFM, that is, the address sample circuit 102 corresponding to the memory bank 104 has sampled the address sample signal SampelDRFM Sample current active row address RowADD <m:0>and latched as a directional refresh management address RaDRFM <m:0>; the active enable signal SecEn is generated and output during the period when the directional refresh window signal WIN_DRFM is valid at this time the activation enable signal SecEn Method for controlling enabling of a directional refresh management address (RaDRFM) <m:0>The decoding operation of the DRFM is performed in order to implement the refresh operation of the memory DRFM.

[0068] If the corresponding address sample signal SampelDRFM has not been received before the reception of the targeted refresh window signal WIN_DRFM If RowADD≠ RowADDi, then the address sampling circuit 102 does not sample the risk address specified by the DRFM, that is, the address sampling circuit 102 corresponding to the memory bank 104 does not sample the currently activated row address RowADD <m:0>(Continue to execute the targeted refresh operation, which can continue to perform refresh operation on the adjacent row of the default address or the last risky address, causing row hammer risk); therefore, the activation enable signal SecEn is not generated during the period when the targeted refresh window signal WIN_DRFM is valid At this time, the memory bank 104 skips the function of the DRFM, that is, the memory bank 104 that does not receive the specified risk address does not generate an activation enable signal SecEn , to avoid row hammer risk by skipping the refresh process of the adjacent row of the default address or the last risky address of the memory bank 104.

[0069] The embodiment sets the corresponding refresh control circuit 100, and the memory bank 104 that does not receive the risky address skips the refresh process of the adjacent row of the default address or the last risky address in the DRFM process, thereby avoiding the row hammer attack caused by the frequent refresh of the adjacent row of the default address or the last risky address of the memory bank 104 when the memory frequently receives the DRFM command.

[0070] In some embodiments, the trigger signal includes a first trigger signal DRFM_PB <n:0>and a second trigger signal DRFM_AP <n:0>. The decoding circuit 101 is further configured to decode the received first trigger command during the activation of the directional refresh management mode, and generate a first trigger signal DRFM_PB corresponding to a target memory bank 104 according to the target memory bank 104 indicated by the memory bank 104 address information in the first trigger command. and the first trigger signal DRFM_PB Send to the corresponding address sampling circuit 102, or decode the received second trigger command and generate a second trigger signal DRFM_AP corresponding to the target memory bank 104 according to the target memory bank 104 indicated by the memory bank 104 address information in the second trigger command and the second trigger signal DRFM_AP to the corresponding address sampling circuit 102.

[0071] by means of the corresponding first trigger signal DRFM_PB or a second trigger signal DRFM_AP to the corresponding address sampling circuit 102, so that the corresponding memory bank 104 can sample the adjacent row of the risk address of the DRFM for subsequent execution of refresh operation of the DRFM.

[0072] With reference to Figure 4 In some embodiments, the address sampling circuit 102 comprises a sampling signal generation circuit 112 and an address register 122. The sampling signal generation circuit 112 is configured to generate a corresponding sampling signal DRFM_PB or a second trigger signal DRFM_AP at the time, generates and outputs the address sampling signal SampelDRFM and in the absence of a corresponding first trigger signal DRFM_PB and a second trigger signal DRFM_AP at times, the address sampling signal SampelDRFM is not generated . Address register 122 is configured to be responsive to an address sample signal SampelDRFM RowADD <m:0>Sampling is performed and latched as a directional refresh management address RaDRFM <m:0>.

[0073] In some embodiments, the refresh mode parameter is at a first level to indicate DRFM mode activation, and at a second level to indicate DRFM mode deactivation; wherein the refresh mode parameter is written into a specific mode register by a mode register write command. Referring to Figure 5 In one example, the refresh mode parameter OP[0] in the mode register MR59 is a DRFM enable bit (DRFE) of the directed refresh management (DRFM), when the refresh mode parameter OP[0] in the mode register MR59 is set to a first level (which can be a high level or a low level), the DRFM mode is activated, and when the refresh mode parameter OP[0] in the mode register MR59 is set to a second level (which can be a low level or a high level), the DRFM mode is deactivated. DDR5 supports two DRFM address sampling methods: (1) PREpb instruction - when DRFM is enabled, CA5 becomes a control bit: CA5 = high level performs "precharge by bank"; CA5 = low level performs "precharge by bank and sample DRFM address". When the PREpb instruction is executed with CA5 = low level, it will instruct the DRAM to sample the DRFM address of the currently activated address. When DRFM is disabled, CA5 remains the CID3 function. (2) WRPA / WRA / RDA instruction - when the DRFM mode is enabled, the CA9 in the second cycle of the double-cycle instruction becomes a control bit: CA9 = high level performs "automatic precharge"; CA9 = low level performs "automatic precharge and sample DRFM address". When the write mode / write / read instruction with automatic precharge is executed in the second cycle with CA9 = low level, the DRFM address of the currently activated address will be sampled. When DRFM is disabled, CA9 in the second cycle of the double-cycle instruction must be "V" level. Each DRAM bank has an independent DRFM address register. Each DRFM address sampling of this bank will update this register, ensuring that the DRFM instruction initiated by the host always retains the latest address sampling result.

[0074] For the first trigger signal DRFM_PB <n:0>, the first trigger signal DRFM_PB <n:0>Based on the foregoing PREpb command generation, a first trigger signal DRFM PB <n:0>The n+1 bits of the DRFM_PB correspond respectively to the n+1 memory banks 104 in the memory. is a first trigger signal corresponding to the i+1th memory bank 104. In one example, the first trigger signal DRFM_PB <n:0>are both pulse signals, the first trigger signal DRFM_PB <n:0>DRFM_PB DRFM_PB(i+1) corresponds to the (i+1)th memory bank 104 When a pulse signal is generated, it indicates that the corresponding memory bank 104 receives the first trigger signal DRFM_PB ,DRFM_PB When no pulse signal is generated on the upper, it indicates that the corresponding memory bank 104 does not receive the first trigger signal DRFM PB .

[0075] For the second trigger signal DRFM_AP <n:0>, a second trigger signal DRFM_AP <n:0>Based on the preceding WRPA command, WRA command, or RDA command generation, a second trigger signal DRFM_AP <n:0>The n+1 bits of the address correspond to n+1 memory banks 104 in the memory, DRFM_AP is the second trigger signal corresponding to the i+1th memory bank 104. In one example, the second trigger signal DRFM_AP <n:0>Both are pulse signals, the second trigger signal DRFM_AP <n:0>The i-th bit data of the DRFM_AP is DRFM_AP(i) DRFM_AP for the i+1th memory bank When a pulse signal is generated, it indicates that the corresponding memory bank 104 receives the second trigger signal DRFM_AP ;DRFM_AP When no pulse signal is generated on the upper, it indicates that the corresponding memory bank 104 does not receive the second trigger signal DRFM_AP .

[0076] Reference is made to Figure 6 In some embodiments, the sampling signal generation circuit 112 includes a NOR logic unit 203, a first NAND logic unit 201, and a second NAND logic unit 202. A first input of the NOR logic unit 203 receives the first trigger signal DRFM_PB , the second input end receives a second trigger signal DRFM_AP , the output end (output trigger signal) is electrically connected with the first input end of the first NAND logic unit 201; the second input end of the first NAND logic unit 201 is electrically connected with the output end of the second NAND logic unit 202, and the output end of the first NAND logic unit 201 is used for outputting an address sampling signal SampleDRFM ; the first input end of the second NAND logic unit 202 is electrically connected with the output end of the first NAND logic unit 201, and the second input end of the second NAND logic unit 202 receives a corresponding reset control signal RSAOKT , reset control signal RSAOKT Apparatus for configuring address sampling signal SampleDRFM The effective time of the row precharge time (tRP) is the row precharge time. The row precharge time is used to define the shortest time interval from the issuance of the precharge command (PRECHARGE command) to the start of the next row address select (RAS) validity.

[0077] It should be noted that the NOR logic unit is Figure 6 The specific implementation form in the example is "NOR gate". In other examples, it can also be a combination of other logic gates, such as "OR gate + NOT gate". Figure 6 The specific implementation form in the example is "NAND gate". In other examples, it can also be a combination of other logic gates, such as "AND gate + NOT gate".

[0078] refer to Figure 6 and Figure 8 , taking the memory bank and sampling signal generating circuit 112 corresponding to i=0 as an example, for the sampling signal generating circuit 112, the first NAND logic unit 201 and the second NAND logic unit 202 construct an SR latch, which is triggered according to the rising edge of the trigger signal (the first trigger signal DRFM_PB <0> The rising edge of the second trigger signal DRFM_AP <0> The rising edge of the address sampling signal SampleDRFM is output <0> The rising edge of the reset control signal RSAOKT <0> The falling edge of the output address sampling signal SampleDRFM <0> The falling edge of the address sampling signal SampleDRFM is generated with a valid time of tRP (Row Precharge Time, which defines the shortest time interval from the issuance of the precharge command to the start of the next row address selection). <0> .

[0079] refer to Figure 7 In some embodiments, the address register 122 includes a flip-flop 204. The input terminal of the flip-flop 204 receives the currently activated row address RowADD. <m:0>, the clock terminal receives an address sampling signal SampleDRFM , an output end outputs a directional refresh management address RaDRFM <m:0>.

[0080] It should be noted that Figure 7 In the example, the trigger 204 is constructed as a D trigger. In other examples, the trigger 204 can also have other forms of trigger structures.

[0081] refer to Figure 7 and Figure 8 , taking i=0 as an example, the memory bank sampling 16-bit address, for the address register 122, the address register 122 is based on the address sampling signal SampleDRFM <0> The "a" address represented by the currently activated row address RowAddr<15:0> is sampled to generate the corresponding directional refresh management address RaDRFM<15:0>.

[0082] refer to Figure 9 In some embodiments, the directional refresh control circuit 103 includes a control signal generation circuit 113 and an activation control circuit 123 .

[0083] The control signal generating circuit 113 is configured to receive the directed refresh window signal WIN_DRFM and the address sampling signal SampleDRFM during the activation of the directed refresh management function. and in accordance with a directional refresh window signal WIN_DRFM and an address sample signal SampleDRFM generating and outputting a directional refresh control signal DRFM_Sample; wherein, in response to an address sample signal SampleDRFM The directional refresh control signal DRFM_Sample is outputted from an inactive level to an active level, and in response to a flip edge of the end of the directional refresh window signal WIN_DRFM, the directional refresh control signal DRFM_Sample is flipped from the active level to the inactive level.

[0084] The activation control circuit 123 is configured to receive the directional refresh control signal DRFM_Sample, the directional refresh window signal WIN_DRFM and the bank activation signal ActiveBnkEn and the bank activation signal ActiveBnkEn is asserted when the directional refresh control signal DRFM_Sample is active and during the time the directional refresh window signal WIN_DRFM is active. The output is an activation enable signal SecEn ; and the bank activate signal ActiveBnkEn is masked during the validity of the directional refresh window signal WIN_DRFM when the directional refresh control signal DRFM_Sample is at an inactive level ; and the bank activate signal ActiveBnkEn is masked during the validity of the directional refresh window signal WIN_DRFM when the directional refresh control signal DRFM_Sample is at an inactive level .

[0085] For the directional refresh control signal DRFM_Sample, the rising edge of the directional refresh control signal DRFM_Sample is determined by the address sample signal SampleDRFM The rising edge of the DRFM_Sample signal is determined by the rising edge of the DRFM signal, and the falling edge of the DRFM_Sample signal is determined by the falling edge of the WIN_DRFM signal.

[0086] When the DRFM_Sample signal is at an active level, the memory bank can be activated according to the ActiveBnkEn signal during the period when the WIN_DRFM signal is active. generating an activation enable signal SecEn to perform a directed refresh management address, RaDRFM <m:0>refresh. When the directional refresh control signal DRFM_Sample is at an inactive level, the bank is unable to refresh according to the bank activation signal ActiveBnkEn generating an activation enable signal SecEn i.e. the memory bank corresponding to the memory bank activation signal ActiveBnkEn The refresh operation of the DRFM is shielded, and the memory bank is skipped.

[0087] Reference Figure 10 In some embodiments, the control signal generation circuit 113 includes a first non-logic unit 301, a second non-logic unit 302, a third NAND logic unit 303, and a fourth NAND logic unit 304.

[0088] The input end of the first non-logic unit 301 receives an address sampling signal SampleDRFM The input end of the second non-logic unit 302 receives a directional refresh window signal WIN_DRFM; the first input end of the third NAND logic unit 303 is electrically connected with the output end of the first non-logic unit 301, the second input end of the third NAND logic unit 303 is electrically connected with the output end of the fourth NAND logic unit 304, and the output end of the third NAND logic unit 303 is used for outputting a directional refresh control signal DRFM_Sample; the first input end of the fourth NAND logic unit 304 is electrically connected with the output end of the third NAND logic unit 303, and the second input end of the fourth NAND logic unit 304 is electrically connected with the output end of the second non-logic unit 302.

[0089] It should be noted that the NAND logic unit is Figure 10 The specific implementation form in the example is "NAND gate", and in other examples, it can also be a combination of other logic gates, for example, "AND gate + NOT gate".

[0090] Reference is made to Figure 10 and Figure 11 For the memory bank corresponding to i=0 and the control signal generation circuit 113, the second trigger signal DRFM_AP<0> corresponding to the PREpb command generates an address sampling signal SampleDRFM<0>. For the control signal generation circuit 113, the third NAND logic unit 303 and the fourth NAND logic unit 304 construct an SR latch, and the latch generates the address sampling signal SampleDRFM the rising edge of the directional refresh window signal WIN_DRFM determines the falling edge of the directional refresh control signal DRFM_Sample.

[0091] Reference Figure 12 In some embodiments, the activation control circuit 123 comprises a third non-logic unit 313, a fifth NAND logic unit 305, and a first AND logic unit 310. The input terminal of the third non-logic unit 313 receives the directional refresh control signal DRFM_Sample; the first input terminal of the fifth NAND logic unit 305 receives the directional refresh window signal WIN_DRFM, and the second input terminal of the fifth NAND logic unit 305 is electrically connected to the output terminal of the third non-logic unit 313; the first input terminal of the first AND logic unit 310 receives the bank activation signal ActiveBnkEn The first input end of the first NAND logic unit 301 is electrically connected with the output end of the second NAND logic unit 302, the second input end of the first NAND logic unit 301 is electrically connected with the output end of the fifth NAND logic unit 305, and the output end of the first NAND logic unit 301 is used for outputting the active enable signal SecEn .

[0092] It should be noted that the non-logic unit in the example is implemented in the form of "NAND gate", and in other examples, it can also be a combination of other logic gates, such as "AND gate + NAND gate", etc. Figure 12 The specific implementation form of the AND logic unit in the example is "AND gate", and in other examples, it can also be a combination of other logic gates, such as "NAND gate + inverter" implementation. Figure 12 The specific implementation form of the AND logic unit in the example is "AND gate", and in other examples, it can also be a combination of other logic gates, such as "NAND gate + inverter" implementation.

[0093] Referring to Figure 12 and Figure 13 , according to the inverse data of the directional refresh control signal DRFM_Sample and the NAND result of the directional refresh window signal WIN_DRFM, in combination with the bank activation signal ActiveBnkEn to generate an activation enable signal SecEn , if the non-result is high, then the bank activation signal ActiveBnkEn is asserted to generate an activation enable signal SecEn ; if the non-result is low, then the bank activation signal ActiveBnkEn is masked No activation enable signal SecEn is generated .

[0094] Take the case of i=0, the PREpb command corresponding second trigger signal DRFM_AP<0> generates address sampling signal SampleDRFM<0>. Based on Figure 11 It can be seen that based on the rising edge of the PREpb command corresponding generated directional refresh control signal DRFM_Sample, the directional refresh window signal WIN_DRFM corresponding generates the falling edge of the directional refresh control signal DRFM_Sample. If the directional refresh control circuit corresponding to the memory bank receives the DRFMab command to generate the directional refresh window signal WIN_DRFM before, the decoding circuit receives the PREpb command pointing to the memory bank to generate the second trigger signal DRFM_AP<0>, the directional refresh control signal DRFM_Sample has rising edge and falling edge, that is, the directional refresh control signal DRFM_Sample has an effective period, and in the effective period, the memory bank activation signal ActiveBnkEn to generate an activation enable signal SecEn ; if the decoding circuit does not receive the PREpb command directed to the memory bank before the orientation refresh control circuit corresponding to the memory bank receives the DRFMab command to generate the orientation refresh window signal WIN_DRFM, there is no rising edge in the orientation refresh control signal DRFM_Sample, that is, the orientation refresh control signal DRFM_Sample has no valid period, so the active enable signal SecEn cannot be generated .

[0095] For the refresh control circuit 100 provided in the embodiment, by controlling the DRFM process, the memory bank skips the refresh process of the adjacent row of the default address or the last risk address when the risk address is not received, thereby avoiding the row hammer attack caused by the frequent refresh of the adjacent row of the default address or the last risk address in the memory bank when the memory frequently receives the DRFM command.

[0096] It should be noted that the features disclosed in the refresh control circuit 100 provided in the above embodiments can be randomly combined to obtain a new refresh control circuit 100 embodiment without conflict.

[0097] The second embodiment of the present disclosure also provides a refresh control method applied to a memory, the memory comprising a plurality of directional refresh control circuits and a plurality of memory banks, the plurality of directional refresh control circuits corresponding to the plurality of memory banks one by one, decoding a received directional refresh management command to generate a directional refresh window signal during activation of a directional refresh management mode; if the directional refresh management address corresponding to any directional refresh control circuit has been sampled before the directional refresh window signal is received, an activation enable signal is generated and output during the validity of the directional refresh window signal to activate the refresh operation of the word line in the corresponding memory bank; if the directional refresh management address corresponding to any directional refresh control circuit has not been sampled before the directional refresh window signal is received, no activation enable signal is generated during the validity of the directional refresh window signal.

[0098] Reference Figure 13 , according to the inverse data of the directional refresh control signal DRFM_Sample and the NAND result of the directional refresh window signal WIN_DRFM, in combination with the memory bank activation signal ActiveBnkEn to generate an activation enable signal SecEn , if the non-result is high, then the bank activation signal ActiveBnkEn is asserted to generate an activation enable signal SecEn ; if the non-result is low, then the bank activation signal ActiveBnkEn is masked No activation enable signal SecEn is generated .

[0099] Take the case of i=0, the PREpb command corresponding second trigger signal DRFM_AP<0> generates address sampling signal SampleDRFM<0>. Based on Figure 11 It can be seen that based on the rising edge of the PREpb command corresponding generated directional refresh control signal DRFM_Sample, the directional refresh window signal WIN_DRFM corresponding generates the falling edge of the directional refresh control signal DRFM_Sample. If the directional refresh control circuit corresponding to the memory bank receives the DRFMab command to generate the directional refresh window signal WIN_DRFM before, the decoding circuit receives the PREpb command pointing to the memory bank to generate the second trigger signal DRFM_AP<0>, the directional refresh control signal DRFM_Sample has rising edge and falling edge, that is, the directional refresh control signal DRFM_Sample has an effective period, and in the effective period, the memory bank activation signal ActiveBnkEn to generate an activation enable signal SecEn ; if the decoding circuit does not receive the PREpb command directed to the memory bank before the orientation refresh control circuit corresponding to the memory bank receives the DRFMab command to generate the orientation refresh window signal WIN_DRFM, there is no rising edge in the orientation refresh control signal DRFM_Sample, that is, the orientation refresh control signal DRFM_Sample has no valid period, so the active enable signal SecEn cannot be generated .

[0100] In some embodiments, the memory further comprises a plurality of address sampling circuits corresponding to the plurality of memory banks one by one, if any address sampling circuit responds to the trigger signal of the corresponding memory bank, the current activated row address is sampled and latched as the corresponding directional refresh management address; if any address sampling circuit does not receive the corresponding trigger signal, no address sampling operation is performed.

[0101] By controlling the DRFM process, the memory bank that does not receive the risk address skips the refresh process of the default address or the adjacent row of the last risk address, thereby avoiding the row hammer attack caused by the frequent refresh of the default address or the adjacent row of the last risk address of the memory bank when the memory frequently receives the DRFM command.

[0102] The third embodiment of the present disclosure provides a refresh control circuit, comprising: a decoding circuit configured to decode the received directional refresh management command during the activation of the directional refresh management mode, generate and output a directional refresh window signal; a plurality of address sampling circuits corresponding to the plurality of memory banks one by one; each address sampling circuit is configured to generate and output a corresponding address sampling signal in response to the trigger signal of the corresponding memory bank, sample the current activated row address according to the address sampling signal, and latch it as the corresponding directional refresh management address; and when the corresponding trigger signal is not received, the corresponding address sampling signal is not generated; a plurality of refresh address control circuits corresponding to the plurality of address sampling circuits and the plurality of memory banks one by one; the refresh address control circuit is electrically connected with the corresponding address sampling circuit, and is configured to, if the corresponding address sampling signal has been received before the directional refresh window signal is received, select and output the corresponding directional refresh management address during the validity period of the directional refresh window signal; and if the corresponding address sampling signal has not been received before the directional refresh window signal is received, select and output the row hammer address of the corresponding memory bank during the validity period of the directional refresh window signal.

[0103] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0104] Reference Figure 14 and Figure 15 The refresh control circuit 400 provided by the embodiment comprises a decoding circuit 401, a plurality of address sampling circuits 402 and a plurality of refresh address control circuits 403.

[0105] Among them, the decoding circuit 401 is the same as the decoding circuit 101 in the first embodiment, and the address sampling circuit 402 is the same as the address sampling circuit 102 in the first embodiment, which will not be repeated here.

[0106] A plurality of refresh address control circuits 403 correspond one-to-one to a plurality of address sampling circuits 402 and a plurality of memories; each refresh address control circuit 403 is electrically connected to the corresponding address sampling circuit 402, and the refresh address control circuit 403 is configured to, during activation of the directional refresh management (DRFM) function, if the corresponding address sampling signal SampleDRFM has been received before the directional refresh window signal WIN_DRFM is received RaDRFM = RaDRFM + 1 <m:0>; and if the corresponding address sample signal SampleDRFM has not been received before the directional refresh window signal WIN_DRFM is received RaDLUT = RaD + RaDoffset <m:0>.

[0107] Row hammer address RaDLUT <m:0>It is the row hammer address stored in the row hammer address register of the corresponding memory bank.

[0108] It should be noted that since the refresh address control circuit 403 corresponds to the address sampling circuit 402 one by one, that is, the number of refresh address control circuits 403 in the refresh control circuit 400 is the same as the number of memory banks in the memory, this embodiment is described in detail using one refresh address control circuit 403 as an example. Figure 15 In the example, the decoding circuit 401, the address sampling circuit 402 and the refresh address control circuit 403 are placed in the memory body 104, which does not mean that the decoding circuit 401, the address sampling circuit 402 and the refresh address control circuit 403 are set in the memory body 104, but is used to represent the corresponding relationship between the decoding circuit 401, the address sampling circuit 402 and the refresh address control circuit 403 and the memory body 104.

[0109] If the corresponding address sampling signal SampleDRFM has been received before the directional refresh window signal WIN_DRFM is received If the address sampling circuit 102 has sampled the risk address specified by the DRFM, the output is the directed refresh management address RaDRFM during the validity of the directed refresh window signal WIN_DRFM <m:0>, Directed refresh management address RaDRFM <m:0>Address sampling circuit 102 for the memory bank corresponding to the address based on address sampling signal SampelDRFM <n:0>Sample current active row address RowADD <m:0>acquired; at this time, the memory bank manages the address RaDRFM for the directional refresh during the validity of the directional refresh window signal WIN_DRFM <m:0>The refresh is performed on the adjacent row, so as to realize the refresh operation of the memory DRFM.

[0110] If the corresponding address sample signal SampelDRFM is not received before receiving the directional refresh window signal WIN_DRFM , the address sampling circuit 102 has not sampled the risk address specified by DRFM, that is, the address sampling circuit 102 corresponding to the memory bank has not sampled the currently activated row address RowADD <m:0>; select output row hammer address RaDLUT during validity of directional refresh window signal WIN_DRFM <m:0>; at this time, during the validity of the directional refresh window signal WIN_DRFM, the memory bank is directed to hammer the row address RaDLUT <m:0>adjacent row of the default address or the last risky address to the refresh process of the bank that does not receive the risky address is changed to refresh the row hammer address RaDLUT <m:0>adjacent row of the risk address.

[0111] The embodiment sets the corresponding refresh control circuit 400, and the refresh process of the adjacent row of the default address or the last risk address of the memory bank which does not receive the risk address in the DRFM process is changed to the refresh row hammer address RaDLUT <m:0>The adjacent rows of the memory bank are refreshed, thereby avoiding row hammer attacks caused by the memory bank frequently refreshing the adjacent rows of the default address or the last risky address when the memory frequently receives the DRFM command.

[0112] Reference Figure 16 In some embodiments, the refresh address control circuit 403 includes a selection signal generation circuit 413 and an address selection circuit 423.

[0113] The selection signal generation circuit 413 is configured to, during the activation of the targeted refresh management function, receive a targeted refresh window signal WIN_DRFM and an address sampling signal SampleDRFM and in accordance with a directional refresh window signal WIN_DRFM and an address sample signal SampleDRFM generating and outputting an address selection signal RaDRFMSelect ; wherein, if the corresponding address sample signal SampleDRFM has been received before receiving the directional refresh window signal WIN_DRFM RaDRFMSelect = RaDRFMSelect + RaDRFMSelect ; outputting after switching to the first level, and if a corresponding address sampling signal SampleDRFM is not received before receiving the directional refresh window signal WIN_DRFM RaDRFMSelect = RaDRFMSelect OR RaDRFMSelect The second level is maintained constant.

[0114] The activation control circuit 423 is configured to receive an address selection signal RaDRFMSelect , refresh management address RaDRFM <m:0>and row hammer address RaDLUT <m:0>and the address selection signal RaDRFMSelect is at the first level during the effective period of the directional refresh window signal WIN_DRFM selecting an output corresponding to a directional refresh management address RaDRFM <m:0>and the address selection signal RaDRFMSelect is at the second level select output corresponding to bank address RaDLUT <m:0>.

[0115] for the address selection signal RaDRFMSelect , address select signal RaDRFMSelect with the address sampling signal SampleDRFM One-to-one correspondence, address sampling signal SampleDRFM<0> corresponds to address selection signal RaDRFMSelect<0>, address sampling signal SampleDRFM<1> corresponds to address selection signal RaDRFMSelect<1>…address sampling signal SampleDRFM <n>corresponding address selection signal RaDRFMSelect <n>RaDRFMSelect <0> ~ RaDRFMSelect <n>together constitute n+1 address sampling signals SampleDRFM <n:0>Address select signal RaDRFMSelect a first level of the first set of registers is used to select a refresh management address according to a direction refresh management (RaDRFM) <m:0>Generating an output address RaRHR <m:0>, the second level is used to select the row hammer address Ra from the DLUT <m:0>Generating an output address RaRHR <m:0>, output address RaRHR <m:0>for performing refresh operations of the memory DRFM subsequently. Reference Figure 17 In some embodiments, the selection signal generation circuit 413 comprises a fourth non-logic unit 404, a fifth non-logic unit 405, a sixth NAND logic unit 406, a seventh NAND logic unit 407, and a second AND logic unit 409.

[0116] The input end of the fourth non-logic unit 404 receives the address sampling signal SampleDRFM The input end of the fifth non-logic unit 405 receives the directional refresh window signal WIN_DRFM; the first input end of the sixth NAND logic unit 406 is electrically connected with the output end of the fourth non-logic unit 404, and the second input end of the sixth NAND logic unit 406 is electrically connected with the output end of the seventh NAND logic unit 407; the first input end of the seventh NAND logic unit 407 is electrically connected with the output end of the sixth NAND logic unit 406, and the second input end of the seventh NAND logic unit 407 is electrically connected with the output end of the fifth non-logic unit 405; the first input end of the second AND logic unit 409 receives the directional refresh window signal WIN_DRFM, the second input end is electrically connected with the output end of the sixth NAND logic unit 406, and the output end is used for outputting the address selection signal RaDRFMSelect .

[0117] It should be noted that the logical unit in the Figure 17 The specific implementation form of the example is "AND gate", and in other examples, it can also be a combination of other logic gates, such as "NAND gate + inverter" implementation. The specific implementation form of the example of the NAND logic unit is "NAND gate", and in other examples, it can also be a combination of other logic gates, such as "AND gate + NOT gate", etc. Figure 17 The specific implementation form of the example is "AND gate", and in other examples, it can also be a combination of other logic gates, such as "NAND gate + inverter" implementation. The specific implementation form of the example of the NAND logic unit is "NAND gate", and in other examples, it can also be a combination of other logic gates, such as "AND gate + NOT gate", etc.

[0118] Referring to Figure 17 and Figure 19 , the PREpb command points to the memory bank B0, and the corresponding second trigger signal DRFM_AP<0> generates an address sampling signal SampleDRFM<0> as an example. The sixth NAND logic unit 406 and the seventh NAND logic unit 407 construct an SR latch, and based on the foregoing, the latch generates an address sampling signal SampleDRFM the rising edge of the directional refresh control signal DRFM_Sample is determined according to the falling edge of the directional refresh window signal WIN_DRFM. In addition, the directional refresh control signal DRFM_Sample and the directional refresh window signal WIN_DRFM generate the address selection signal RaDRFMSelect through an AND gate That is, the address selection signal RaDRFMSelect is selected in the period in which the directional refresh control signal DRFM_Sample and the directional refresh window signal WIN_DRFM are active at the same time The first level; any of the directional refresh control signal DRFM_Sample and the directional refresh window signal WIN_DRFM is invalid, the address selection signal RaDRFMSelect to a second level.

[0119] Referring to Figure 18 In some embodiments, the address selection circuit 423 comprises a selection unit 408; a first input of the selection unit 408 receives a corresponding directional refresh management address RaDRFM <m:0>, the second input receives a row hammer address RaDLUT <m:0>, the control end of the memory bank corresponding to the receiving address selection signal RaDRFMSelect .

[0120] It should be noted that, Figure 18 In the example, the selection unit 408 is configured to select the refresh management address RaDRFM based on the on-off orientation of the switch tube. In other examples, the selection unit 408 can also select the refresh management address RaDRFM based on the on-off orientation of the switch tube and the on-off orientation of the switch tube. <m:0>or row hammer address RaDLUT <m:0>The transmission path implementation.

[0121] Reference Figure 18 And Figure 19 The 16-bit address of the memory bank is sampled, i=0, PREpb points to the memory bank B0, and the corresponding second trigger signal DRFM_AP<0> generates the address sampling signal SampleDRFM<0>. The selection unit 408 selects the address selection signal RaDRFMSelect Selecting output-directed refresh management address RaDRFM <m:0>and the address selection signal RaDRFMSelect is at the second level select output row hammer address RaDLUT <m:0>.

[0122] Specifically, if the refresh address control circuit 403 corresponding to the memory bank generates the directional refresh window signal WIN_DRFM before the decoding circuit receives the PREpb command directed to the memory bank and generates the second trigger signal DRFM_AP<0>, the directional refresh control signal DRFM_Sample has a rising edge and a falling edge, i.e., the directional refresh control signal DRFM_Sample has an effective period, at this time, the address selection signal RaDRFMSelect For the first level, the output address RaRHR<15:0> is generated according to the corresponding address "a" of the directed refresh management address RaDRFM<15:0>; if the refresh address control circuit 403 of the memory bank does not receive the PREpb command pointing to the memory bank before generating the directed refresh window signal WIN_DRFM in response to the DRFMab command, the decoding circuit does not receive the PREpb command pointing to the memory bank, and there is no rising edge in the directed refresh control signal DRFM_Sample, that is, the directed refresh control signal DRFM_Sample has no valid period, at this time the address selection signal RaDRFMSelect For the second level, the output address RaRHR<15:0> is generated according to the address "m" corresponding to the row hammer address RaDLUT<15:0>.

[0123] In some embodiments, the refresh control circuit further comprises: a plurality of row hammer address registers corresponding to the plurality of memory banks one by one; the row hammer address register is configured to store the row hammer address RaDLUT of the corresponding memory bank <m:0>.

[0124] For the refresh control circuit 400 provided in the present embodiment, by controlling the DRFM process, the refresh process of the adjacent row of the default address or the last risk address of the memory bank which does not receive the risk address is changed to refresh the row hammer address RaDLUT <m:0>The adjacent row of the last risk address is refreshed, thereby avoiding the row hammer attack caused by the frequent refreshing of the adjacent row of the default address or the last risk address when the memory frequently receives the DRFM command.

[0125] It should be noted that the features disclosed in the refresh control circuit 400 provided by the above embodiments can be randomly combined to obtain new embodiments of the refresh control circuit 400 without conflict.

[0126] The fourth embodiment of the present disclosure also provides a refresh control method applied to a memory. The memory includes a plurality of directional refresh control circuits and a plurality of memory banks. The plurality of directional refresh control circuits correspond to the plurality of memory banks one by one. During the activation of the directional refresh management mode, a received directional refresh management command is decoded to generate a directional refresh window signal. If the directional refresh management address corresponding to any directional refresh control circuit has been sampled before the directional refresh window signal is received, the corresponding directional refresh management address is selected to be output during the validity period of the directional refresh window signal to control the refresh operation of the adjacent row of the directional refresh management address in the corresponding memory bank. If the directional refresh management address corresponding to any directional refresh control circuit has not been sampled before the directional refresh window signal is received, the row hammer address of the corresponding memory bank is selected to be output during the validity period of the directional refresh window signal to control the refresh operation of the adjacent row of the row hammer address in the corresponding memory bank.

[0127] Reference Figure 19 The memory bank samples a 16-bit address, i = 0, and the second trigger signal DRFM_AP<0> corresponding to the PREpb command generates an address sampling signal SampleDRFM<0>. The selection unit 408 selects the address sampling signal SampleDRFM<0> according to the address selection signal RaDRFMSelect Selecting output-directed refresh management address RaDRFM <m:0>and the address selection signal RaDRFMSelect is at the second level select output row hammer address RaDLUT <m:0>.

[0128] In particular, if the refresh address control circuit corresponding to the memory bank generates the directional refresh window signal WIN_DRFM before the decoding circuit receives the PREpb command directed to the memory bank and generates the second trigger signal DRFM_AP<0>, the directional refresh control signal DRFM_Sample has a rising edge and a falling edge, i.e. the directional refresh control signal DRFM_Sample has an effective period, at this time the address selection signal RaDRFMSelect For the first level, the output address RaRHR<15:0> is generated according to the corresponding address "a" of the directed refresh management address RaDRFM<15:0>; if the refresh address control circuit 403 of the memory bank has not received the PREpb command pointing to the memory bank before generating the directed refresh window signal WIN_DRFM in response to the DRFMab command, the decoding circuit has not received the PREpb command pointing to the memory bank, and there is no rising edge in the directed refresh control signal DRFM_Sample, that is, the directed refresh control signal DRFM_Sample has no valid period, at this time the address selection signal RaDRFMSelect For the second level, the output address RaRHR<15:0> is generated according to the address "m" corresponding to the row hammer address RaDLUT<15:0>.

[0129] In some embodiments, the memory further comprises a plurality of address sampling circuits corresponding to the plurality of memory banks, wherein if any address sampling circuit receives a trigger signal from the corresponding memory bank, the address sampling circuit samples the current active row address and latches the sampled address as the corresponding directional refresh management address; and if any address sampling circuit does not receive the trigger signal from the corresponding memory bank, the address sampling circuit does not perform the address sampling operation.

[0130] During the DRFM process, the refresh process of the memory bank that does not receive the risk address is changed from refreshing the default address or the adjacent row of the last risk address to refreshing the row hammer address RaDLUT <m:0>The adjacent row of the last risk address is stored in the memory, and the adjacent row of the last risk address is refreshed in the memory bank when the DRFM command is received frequently, so that the row hammer attack caused by the frequent refreshing of the adjacent row of the default address or the last risk address in the memory bank is avoided.

[0131] In the above embodiments, the description of each embodiment is focused on, and the part not described in detail in a certain embodiment can be referred to the detailed description of other embodiments above, and will not be described here.

[0132] The basic concept has been described above, and it is obvious that the above detailed disclosure is only used as an example and does not constitute a limitation on the application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the application. Such modifications, improvements and corrections are suggested in the application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the application.

[0133] The above describes in detail a refresh control circuit and a refresh control method provided by the embodiments of the application. The principles and implementation modes of the application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the application and its core idea. At the same time, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed. In conclusion, the content of the specification should not be understood as a limitation on the application. < / n> < / n> < / n>

Claims

1. A refresh control circuit, characterized in that: include: a decoding circuit configured to, during activation of the directed refresh management mode, decode a received directed refresh management command and generate and output a directed refresh window signal; a plurality of address sampling circuits corresponding one to one with the plurality of memory banks; each of the address sampling circuits being configured to generate and output a corresponding address sampling signal in response to a trigger signal of the corresponding memory bank, and to sample a currently activated row address according to the address sampling signal and latch the sample as a directional refresh management address; and not generating the corresponding address sampling signal when the corresponding trigger signal is not received; Multiple directional refresh control circuits correspond one-to-one to multiple address sampling circuits; each directional refresh control circuit is electrically connected to the corresponding address sampling circuit and is configured to generate and output an activation enable signal during the validity period of the directional refresh window signal if the corresponding address sampling signal has been received before the directional refresh window signal is received; and not generate the activation enable signal during the validity period of the directional refresh window signal if the corresponding address sampling signal has not been received before the directional refresh window signal is received.

2. The refresh control circuit according to claim 1, wherein: The address sampling circuit includes a sampling signal generating circuit and an address register, and the trigger signal includes a first trigger signal and a second trigger signal; The sampling signal generating circuit is configured to generate and output an address sampling signal in response to receiving the corresponding first trigger signal or the second trigger signal, and not generate the address sampling signal when not receiving the corresponding first trigger signal or the second trigger signal; The address register is configured to sample the currently activated row address in response to the address sampling signal and latch the sample as the directional refresh management address.

3. The refresh control circuit according to claim 2, wherein: include: The sampling signal generating circuit includes: a NOR logic unit, a first NAND logic unit and a second NAND logic unit; The first input terminal of the NOR logic unit receives the first trigger signal, the second input terminal receives the second trigger signal, and the output terminal is electrically connected to the first input terminal of the first NAND logic unit; The second input end of the first NAND logic unit is electrically connected to the output end of the second NAND logic unit, and the output end of the first NAND logic unit is used to output the address sampling signal; The first input terminal of the second NAND logic unit is electrically connected to the output terminal of the first NAND logic unit, and the second input terminal of the second NAND logic unit receives a corresponding reset control signal, wherein the reset control signal is used to configure the valid time of the address sampling signal to be the row precharge time; The address register includes: a trigger; The input end of the trigger receives the currently activated row address, the clock end receives the address sampling signal, and the output end outputs the directional refresh management address.

4. The refresh control circuit according to claim 2, wherein: The directional refresh control circuit includes a control signal generating circuit and an activation control circuit; The control signal generating circuit is configured to receive the directional refresh window signal and the address sampling signal, and generate and output a directional refresh control signal according to the directional refresh window signal and the address sampling signal; wherein, in response to the address sampling signal, the directional refresh control signal is flipped from an invalid level to a valid level and then output; and, in response to a flip edge indicating the end of the directional refresh window signal, the directional refresh control signal is flipped from a valid level to an invalid level; The activation control circuit is configured to receive the directional refresh control signal, the directional refresh window signal and the storage body activation signal, and output the storage body activation signal as the activation enable signal when the directional refresh control signal is at a valid level and during the valid period of the directional refresh window signal; and when the directional refresh control signal is at an invalid level, shield the storage body activation signal during the valid period of the directional refresh window signal.

5. The refresh control circuit according to claim 4, wherein: include: The control signal generating circuit includes: a first NOT logic unit, a second NOT logic unit, a third NAND logic unit and a fourth NAND logic unit; An input end of the first non-logic unit receives the address sampling signal, and an input end of the second non-logic unit receives the directional refresh window signal; The first input end of the third NAND logic unit is electrically connected to the output end of the first NAND logic unit, the second input end of the third NAND logic unit is electrically connected to the output end of the fourth NAND logic unit, and the output end of the third NAND logic unit is used to output the directional refresh control signal; The first input terminal of the fourth NAND logic unit is electrically connected to the output terminal of the third NAND logic unit, and the second input terminal of the fourth NAND logic unit is electrically connected to the output terminal of the second NAND logic unit; The activation control circuit includes: a third NOT logic unit, a fifth NAND logic unit and a first AND logic unit; An input terminal of the third non-logic unit receives the directional refresh control signal; The first input end of the fifth NAND logic unit receives the directional refresh window signal, and the second input end of the fifth NAND logic unit is electrically connected to the output end of the third NAND logic unit; The first input end of the first AND logic unit receives the storage body activation signal, the second input end of the first AND logic unit is electrically connected to the output end of the fifth NAND logic unit, and the output end of the first AND logic unit is used to output the activation enable signal.

6. The refresh control circuit according to claim 2, wherein: The decoding circuit is further configured to, during the activation of the directed refresh management mode, decode a received first trigger command, generate a first trigger signal corresponding to a target memory bank according to the memory bank address information in the first trigger command, and send the first trigger signal to a corresponding address sampling circuit, or, The received second trigger command is decoded, and according to the target memory bank indicated by the memory bank address information in the second trigger command, a second trigger signal corresponding to the target memory bank is generated, and the second trigger signal is sent to the corresponding address sampling circuit.

7. The refresh control circuit according to claim 1, wherein: When the refresh mode parameter is at a first level, the directional refresh management mode is activated, and when the refresh mode parameter is at a second level, the directional refresh management mode is deactivated; wherein the refresh mode parameter is written into a specific mode register via a mode register write command.

8. A refresh control circuit, characterized in that: include: a decoding circuit configured to, during activation of the directed refresh management mode, decode a received directed refresh management command and generate and output a directed refresh window signal; a plurality of address sampling circuits corresponding one to one with the plurality of memory banks; each of the address sampling circuits being configured to generate and output a corresponding address sampling signal in response to a trigger signal of the corresponding memory bank, and to sample a currently activated row address according to the address sampling signal and latch the sample into a corresponding directional refresh management address; and not generating the corresponding address sampling signal when the corresponding trigger signal is not received; a plurality of refresh address control circuits corresponding one to one with the plurality of address sampling circuits and the plurality of memory banks; each of the refresh address control circuits is electrically connected to the corresponding address sampling circuit and is configured to, if the corresponding address sampling signal has been received before the directional refresh window signal is received, select and output the corresponding directional refresh management address during the valid period of the directional refresh window signal; And if the corresponding address sampling signal is not received before the directional refresh window signal is received, the row hammer address of the corresponding memory bank is selected and output during the period when the directional refresh window signal is valid.

9. The refresh control circuit according to claim 8, wherein: The refresh address control circuit includes a selection signal generating circuit and an address selection circuit; The selection signal generation circuit is configured to receive the directional refresh window signal and the address sampling signal, and generate and output an address selection signal based on the directional refresh window signal and the address sampling signal; wherein, if the corresponding address sampling signal has been received before the directional refresh window signal is received, the address selection signal is switched to a first level and then output during the effective period of the directional refresh window signal; and if the corresponding address sampling signal has not been received before the directional refresh window signal is received, the address selection signal output during the effective period of the directional refresh window signal remains unchanged at a second level; The address selection circuit is configured to receive the address selection signal, the directional refresh management address and the row hammer address, and during the period when the directional refresh window signal is valid, select and output the corresponding directional refresh management address according to the address selection signal at the first level, and select and output the corresponding row hammer address of the storage body according to the address selection signal at the second level.

10. The refresh control circuit according to claim 9, wherein: include The selection signal generating circuit includes: a fourth NOT logic unit, a fifth NOT logic unit, a sixth NAND logic unit, a seventh NAND logic unit and a second AND logic unit; An input end of the fourth non-logic unit receives the address sampling signal, and an input end of the fifth non-logic unit receives the directional refresh window signal; The first input terminal of the sixth NAND logic unit is electrically connected to the output terminal of the fourth NAND logic unit, and the second input terminal of the sixth NAND logic unit is electrically connected to the output terminal of the seventh NAND logic unit; The first input end of the seventh NAND logic unit is electrically connected to the output end of the sixth NAND logic unit, and the second input end of the seventh NAND logic unit is electrically connected to the output end of the fifth NAND logic unit; The first input end of the second AND logic unit receives the directional refresh window signal, the second input end is electrically connected to the output end of the sixth NAND logic unit, and the output end is used to output the address selection signal; The address selection circuit includes: a selection unit; The first input terminal of the selection unit receives the corresponding directional refresh management address, the second input terminal receives the row hammer address of the corresponding memory bank, and the control terminal receives the address selection signal.

11. The refresh control circuit according to claim 8, wherein: The refresh control circuit further includes: a plurality of row hammer address registers corresponding one-to-one to the plurality of memory banks; the row hammer address registers are configured to store row hammer addresses of the corresponding memory banks.

12. A refresh control method, applied to a memory, wherein the memory comprises a plurality of directional refresh control circuits and a plurality of memory banks, wherein the plurality of directional refresh control circuits correspond to the plurality of memory banks in a one-to-one manner, wherein: include: During the activation of the directed refresh management mode, decoding the received directed refresh management command and generating a directed refresh window signal; If any directional refresh control circuit has sampled the corresponding directional refresh management address before receiving the directional refresh window signal, it generates and outputs an activation enable signal during the period when the directional refresh window signal is valid, so as to activate the word line in the corresponding memory bank to perform a refresh operation; If the corresponding directional refresh management address is not sampled before any of the directional refresh control circuits receives the directional refresh window signal, the activation enable signal is not generated during the validity period of the directional refresh window signal.

13. The refresh control method according to claim 12, wherein: The memory further includes a plurality of address sampling circuits corresponding one-to-one to the plurality of memory banks, and is characterized in that it further includes: If any of the address sampling circuits samples the currently activated row address in response to the trigger signal of the corresponding memory bank and latches it as the corresponding directional refresh management address; If any of the address sampling circuits does not receive the corresponding trigger signal, the address sampling operation is not performed.

14. A refresh control method, applied to a memory, wherein the memory comprises a plurality of directional refresh control circuits and a plurality of memory banks, wherein the plurality of directional refresh control circuits correspond to the plurality of memory banks in a one-to-one manner, wherein: include: During the activation of the directed refresh management mode, decoding the received directed refresh management command and generating a directed refresh window signal; If any directional refresh control circuit has sampled the corresponding directional refresh management address before receiving the directional refresh window signal, it selects to output the corresponding directional refresh management address during the period when the directional refresh window signal is valid, so as to control the adjacent row of the directional refresh management address in the corresponding memory bank to perform a refresh operation; If the corresponding directional refresh management address of any of the directional refresh control circuits has not been sampled before receiving the directional refresh window signal, the row hammer address of the corresponding storage body is selected to be output during the period when the directional refresh window signal is valid to control the adjacent rows of the row hammer address in the corresponding storage body to perform a refresh operation.

15. The refresh control method according to claim 14, wherein: The memory further includes a plurality of address sampling circuits corresponding one-to-one to the plurality of memory banks, and is characterized in that it further includes: If any of the address sampling circuits samples the currently activated row address in response to the trigger signal of the corresponding memory bank and latches it as the corresponding directional refresh management address; If any of the address sampling circuits does not receive the corresponding trigger signal, the address sampling operation is not performed.

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