Method for writing in semiconductor memory device

Abstract

The embodiment relates to a method for writing in a semiconductor memory device. According to one embodiment, a semiconductor memory device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When the write sequence is interrupted after a k-th verification operation of an n-th write cycle of the write sequence and before a (k + 1)-th verification operation is ended, a verification voltage corresponding to the first verification operation or a voltage greater than the verification voltage is supplied to the word line after the write sequence is restarted and before the (k + 1)-th verification operation is started. The time from the restart of the write sequence to the start of the (k + 1) th verification action is shorter than the time from the start of the first verification action of the nth write cycle to the end of the kth verification action.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on February 3, 2021, with application number 202110148091.3 and the invention title “Semiconductor Memory Device.”

[0003] [Related Applications]

[0004] This application claims priority based on Japanese Patent Application No. 2020-87180 (filing date: May 19, 2020), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0005] This embodiment relates to a semiconductor memory device. Background Art

[0006] A semiconductor memory device is known that includes a substrate, a plurality of gate electrodes stacked in a direction intersecting a surface of the substrate, a semiconductor layer facing the plurality of gate electrodes, and a gate insulating film disposed between the gate electrodes and the semiconductor layer. The gate insulating film includes a memory portion capable of storing data, such as an insulating charge storage layer such as silicon nitride (Si3N4) or a conductive charge storage layer such as a floating gate. Summary of the Invention

[0007] The embodiment provides a semiconductor memory device capable of increasing the speed of a write sequence without reducing reliability.

[0008] A semiconductor memory device according to one embodiment includes a memory transistor and a word line connected to the gate electrode of the memory transistor. Furthermore, the semiconductor memory device is configured to execute a write sequence in which multiple write cycles are performed on the memory transistor. The write cycle includes a programming operation in which a programming voltage is supplied to the word line, and at least one verification operation in which a verification voltage is supplied to the word line. If the write sequence is not interrupted from the start to the end, a programming operation is executed once and a verification operation is executed m times (m is a natural number greater than 2) in the nth (n is a natural number) write cycle. If the write sequence is interrupted after the completion of the kth (k is a natural number less than m) verification operation and before the completion of the k+1th verification operation in the nth write cycle, a verification voltage corresponding to the first verification operation or a voltage greater than the first verification operation is supplied to the word line after the write sequence is restarted and before the start of the k+1th verification operation. The time from the restart of the write sequence to the start of the k+1th verification operation is shorter than the time from the start of the first verification operation to the completion of the kth verification operation in the nth write cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a schematic block diagram showing the configuration of the storage system 10 according to the first embodiment.

[0010] Figure 2 It is a schematic side view showing a configuration example of the storage system 10 .

[0011] Figure 3 It is a schematic plan view showing the above-mentioned configuration example.

[0012] Figure 4 This is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment.

[0013] Figure 5 1 is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0014] Figure 6 1 is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0015] Figure 7 is a schematic perspective view of the memory die MD.

[0016] Figure 8 yes Figure 7 Schematic enlargement of a portion of the construction shown.

[0017] Figure 9 Schematic histogram for explaining the threshold voltage of the memory cell MC.

[0018] Figure 10 It is a schematic waveform diagram for explaining the read operation.

[0019] Figure 11 It is a schematic cross-sectional view for explaining the read operation.

[0020] Figure 12 is a schematic waveform diagram for explaining a write sequence.

[0021] Figure 13 is a schematic flow chart for explaining a write sequence.

[0022] Figure 14 This is a schematic cross-sectional view for explaining programming operations.

[0023] Figure 15 It is a schematic cross-sectional view for explaining the verification operation.

[0024] Figure 16 It is a schematic waveform diagram used to illustrate the verification operation.

[0025] Figure 17 is a schematic table to explain the verification action.

[0026] Figure 18 is a schematic waveform chart to explain the interruption and restart of the write sequence.

[0027] Figure 19 is a schematic waveform chart to explain the interruption and restart of the write sequence.

[0028] Figure 20 is a schematic waveform chart to explain the interruption and restart of the write sequence.

[0029] Figure 21 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 1st comparative example.

[0030] Figure 22 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 2nd comparative example.

[0031] Figure 23 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 2nd embodiment.

[0032] Figure 24 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 3rd embodiment.

[0033] Figure 25 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 4th embodiment.

[0034] Figure 26 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 5th embodiment.

[0035] Figure 27 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 6th embodiment.

[0036] Figure 28 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 7th embodiment.

[0037] Figure 29 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 8th embodiment.

[0038] Figure 30 is a schematic waveform chart to explain the interruption and restart of the write sequence of the 8th embodiment.

[0039] Figure 31 is a schematic waveform diagram to explain the interruption and restart of the write sequence of Embodiment 8. DETAILED DESCRIPTION

[0040] Next, the semiconductor storage device of the embodiments will be explained in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present application. Also, the following drawings are schematic and some of the components are omitted for the sake of convenience in explanation. Also, the same symbols are attached to the same portions in multiple embodiments, and the explanation is omitted.

[0041] Also, in the present specification, when referring to a "semiconductor storage device", sometimes a memory die is referred to, and sometimes a memory chip, a memory card, an SSD (Solid State Drive) or the like including a controller die is referred to. Also, sometimes a configuration including a host such as a smartphone, a tablet terminal, a personal computer is referred to.

[0042] Also, in the present specification, when referring to a case where a first configuration is "electrically connected" to a second configuration, the first configuration can be directly connected to the second configuration, and the first configuration can be connected to the second configuration via a wiring, a semiconductor component, or a transistor or the like. For example, in a case where three transistors are connected in series, even if a second transistor is in an OFF state, a first transistor is "electrically connected" to a third transistor.

[0043] Also, in the present specification, when referring to a case where a first configuration is "connected to" between a second configuration and a third configuration, there is a case where the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0044] Also, in the present specification, when referring to a case where a circuit makes two wirings or the like "conductive", for example, there is a case where the circuit includes a transistor or the like, the transistor or the like is provided on a current path between the two wirings, and the transistor or the like is in an ON state.

[0045] Also, in the present specification, a specific direction parallel to an upper surface of a substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0046] In addition, in the present specification, a direction along a certain plane is sometimes referred to as a first direction, a direction intersecting the first direction along the certain plane is sometimes referred to as a second direction, and a direction intersecting the plane is sometimes referred to as a third direction. The first direction, the second direction, and the third direction can or can not correspond to any one of the X direction, the Y direction, and the Z direction.

[0047] In addition, in the present specification, "upper" or "lower" and the like are based on a substrate. For example, a direction away from the substrate along the Z direction is referred to as upper, and a direction approaching the substrate along the Z direction is referred to as lower. In addition, in the case where a lower surface or a lower end of a certain constituent is mentioned, a surface or an end portion on the substrate side of the constituent is meant, and in the case where an upper surface or an upper end is mentioned, a surface or an end portion on the side opposite to the substrate of the constituent is meant. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface.

[0048] [First Embodiment]

[0049] [Storage System 10]

[0050] Figure 1 is a schematic block diagram indicating a configuration of the storage system 10 of the first embodiment.

[0051] The storage system 10 performs readout, writing, deletion, and the like of user data in accordance with a signal transmitted from the host 20. The storage system 10 is, for example, a memory chip, a memory card, an SSD, or another system that can store user data. The storage system 10 has a plurality of memory dies MD that store user data, and a controller die CD connected to the plurality of memory dies MD and the host 20. The controller die CD has, for example, a processor, a RAM (Random Access Memory), and the like, and performs processing such as conversion of a logical address and a physical address, error detection / correction, garbage collection (compression), wear leveling, and the like.

[0052] Figure 2 is a schematic side view indicating a configuration example of the storage system 10 of the present embodiment. Figure 3 is a schematic plan view indicating the configuration example. In order to facilitate explanation, a part of the configuration is omitted in Figure 2 and Figure 3

[0053] As described above, in the present embodiment, the controller die CD has the plurality of memory dies MD, and the plurality of memory dies MD are connected to the controller die CD. In addition, the controller die CD has the plurality of memory dies MD, and the plurality of memory dies MD are connected to the controller die CD. In addition, the controller die CD has the plurality of memory dies MD, and the plurality of memory dies MD are connected to the controller die CD. In addition, the controller die CD has the plurality of memory dies MD, and the plurality of memory dies MD are connected to the controller die CD. Figure 2 ​As shown, the memory system 10 of this embodiment includes a mounting substrate MSB, multiple memory die MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory die MD. Pad electrodes P are provided in the Y-direction end regions of the top surface of the mounting substrate MSB, while other portions are bonded to the bottom surfaces of the memory die MD via an adhesive or the like. Pad electrodes P are provided in the Y-direction end regions of the top surface of the memory die MD, while other portions are bonded to the bottom surfaces of other memory die MD or the controller die CD via an adhesive or the like. Pad electrodes P are provided in the Y-direction end regions of the top surface of the controller die CD.

[0054] like Figure 3 As shown, the mounting substrate MSB, the memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction. The pad electrodes P provided on the mounting substrate MSB, the memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0055] In addition, as 2 and Figure 3 The structure shown is only an example, and the specific structure can be adjusted appropriately. Figure 2 and Figure 3 In the example shown, a controller die CD is stacked on top of multiple memory die MD, and the structure is connected by bonding wires B. In this structure, the multiple memory die MD and the controller die CD are contained in a single package. However, the controller die CD can also be contained in a separate package from the memory die MD. Furthermore, the multiple memory die MD and the controller die CD can also be connected to each other via through electrodes, etc., rather than bonding wires B.

[0056] [Circuit Configuration of Memory Bare Chip MD]

[0057] Figure 4 This is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 5 and Figure 6 This is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0058] in addition, Figure 4 The figure shows a plurality of control terminals, etc. The plurality of control terminals may be described as control terminals corresponding to high-active signals (positive logic signals), as control terminals corresponding to low-active signals (negative logic signals), or as control terminals corresponding to both high-active signals and low-active signals. Figure 4 In the specification, the symbols of the control terminals corresponding to the low-active signals include an overline. In the specification, the symbols of the control terminals corresponding to the low-active signals include a slash (" / ").

[0059] As Figure 4 shown, a memory die MD has a memory cell array MCA that stores data, and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC has a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. In addition, the peripheral circuit PC has a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC has an input / output control circuit I / O and a logic circuit CTR.

[0060] [Circuit configuration of memory cell array MCA]

[0061] The memory cell array MCA has a plurality of memory blocks BLK as shown in Figure 5 . Each of the plurality of memory blocks BLK has a plurality of string units SU. Each of the plurality of string units SU has a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. In addition, the other end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0062] The memory string MS has a drain side selection transistor STD connected in series between the bit line BL and the source line SL, a plurality of memory cells MC (memory transistors), a source side selection transistor STS, and a source side selection transistor STSb. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb are sometimes referred to simply as selection transistors (STD, STS, STSb).

[0063] The memory cell MC is an electric field effect transistor having a semiconductor layer functioning as a channel region, a gate insulating film including a charge accumulation film, and a gate electrode. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge accumulation film. The memory cell MC stores one bit or a plurality of bits of data. In addition, a word line WL is connected to each of the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. The word lines WL are commonly connected to all of the memory strings MS in one memory block BLK, respectively.

[0064] The selection transistors (STD, STS, STSb) are field-effect transistors having a semiconductor layer, a gate insulating film, and a gate electrode that function as a channel region. The gate electrodes of the selection transistors (STD, STS, STSb) are connected to the selection gate lines (SGD, SGS, SGSb), respectively. The drain-side selection gate line SGD is set corresponding to the string unit SU and is commonly connected to all storage strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all storage strings MS in multiple string units SU. The source-side selection gate line SGSb is commonly connected to all storage strings MS in multiple string units SU.

[0065] [Circuit Configuration of Voltage Generating Circuit VG]

[0066] Voltage generating circuit VG( Figure 4 ) For example, Figure 5 As shown, the voltage generating circuit VG includes a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. The step-down circuit and the step-up circuit are connected to the supply voltage V CC and ground voltage V SS ( Figure 4 ) of the voltage supply line. The voltage supply line is connected to the reference Figure 2 、 Figure 3 The pad electrode P described above. The voltage generating circuit VG generates a plurality of operating voltages to be applied to the bit lines BL, source lines SL, word lines WL, and select gate lines (SGD, SGS, SGSb) during a read operation, a write sequence, and an erase sequence for the memory cell array MCA, for example, in accordance with a control signal from the sequencer SQC, and simultaneously outputs the voltages to a plurality of voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted in accordance with the control signal from the sequencer SQC.

[0067] [Circuit Configuration of Row Decoder RD]

[0068] Row decoder RD( Figure 4 ) For example, Figure 5 The following is shown: an address decoder 22, which decodes the address data D ADD and a block selection circuit 23 and a voltage selection circuit 24, which transmits the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0069] The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22 sequentially refers to the address register ADR ( Figure 4The row address RA is decoded, and a specific block selection transistor 35 and a voltage selection transistor 37 corresponding to the row address RA are set to an ON state, and the block selection transistors 35 and the voltage selection transistors 37 other than these are set to an OFF state. For example, the voltage of the specific block selection line BLKSEL and the voltage selection line 33 is set to an "H" state, and the voltage of the others is set to an "L" state. Note that, in the case of using P-channel transistors instead of N-channel transistors, the opposite voltage is applied to the wiring.

[0070] In the illustrated example, the block selection line BLKSEL is provided for each of the 1 memory block BLK in the address decoder 22. However, the configuration can be appropriately changed. For example, the block selection line BLKSEL can be provided for two or more memory blocks BLK.

[0071] The block selection circuit 23 includes a plurality of block selection sections 34 corresponding to the memory blocks BLK. Each of the plurality of block selection sections 34 includes a plurality of block selection transistors 35 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field effect type voltage resistant transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb), respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24, respectively. The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0072] The block selection circuit 23 further includes a plurality of transistors not illustrated. The plurality of transistors are electric field effect type transistors connected between the selection gate lines (SGD, SGS, SGSb) and the voltage supply line supplied with the ground voltage V SS The plurality of transistors supply the ground voltage V SS to the selection gate lines (SGD, SGS, SGSb) included in the non-selected memory block BLK.

[0073] The voltage selection circuit 24 includes a plurality of voltage selection sections 36 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). Each of the plurality of voltage selection sections 36 includes a plurality of voltage selection transistors 37. The voltage selection transistors 37 are, for example, electric field effect type transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23, respectively. The source terminals are electrically connected to the corresponding voltage supply line 31, respectively. The gate electrodes are connected to the corresponding voltage selection line 33, respectively.

[0074] In addition, in the illustrated example, an example has been shown in which the wiring CG is connected to the voltage supply line 31 via one voltage selection transistor 37. However, such a configuration is merely an example, and the specific configuration can be appropriately adjusted. For example, the wiring CG can also be connected to the voltage supply line 31 via two or more voltage selection transistors 37.

[0075] [Circuit configuration of sense amplifier module SAM]

[0076] The sense amplifier module SAM has, for example, a plurality of sense amplifier units SAU corresponding to a plurality of bit lines BL. The sense amplifier units SAU each have, as shown in Figure 6 , a sense amplifier SA connected to a bit line BL, a wiring LBUS connected to the sense amplifier SA, a latch circuit SDL connected to the wiring LBUS, a plurality of latch circuits DL connected to the wiring LBUS, and a charging transistor 55 for precharge connected to the wiring LBUS. The wiring LBUS within the sense amplifier unit SAU is connected to the wiring DBUS via a switch transistor DSW.

[0077] The sense amplifier SA has, as shown in Figure 6 , a sense transistor 41 that discharges the charge of the wiring LBUS in accordance with the current flowing in the bit line BL. The source electrode of the sense transistor 41 is connected to a voltage supply line to which a ground voltage V SS is supplied. The drain electrode is connected to the wiring LBUS via a switch transistor 42. The gate electrode is connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamp transistor 44, and a voltage-resistant transistor 45. In addition, the sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0078] In addition, the sense amplifier SA has a voltage transfer circuit that selectively turns on the node COM and the sense node SEN to a voltage supply line to which a voltage V DD is supplied or a voltage supply line to which a voltage V SRC is supplied in accordance with the data latched in the latch circuit SDL. The voltage transfer circuit has a node N1, a charging transistor 46 connected between the node N1 and the sense node SEN, a charging transistor 49 connected between the node N1 and the node COM, a charging transistor 47 connected between the node N1 and a voltage supply line to which a voltage V DD is supplied, and a discharge transistor 50 connected between the node N1 and a voltage supply line to which a voltage V SRC is supplied. In addition, the gate electrodes of the charging transistor 47 and the discharge transistor 50 are commonly connected to a node INV_S of the latch circuit SDL.

[0079] Further, the sensing transistor 41, the switching transistor 42, the discharging transistor 43, the clamp transistor 44, the charging transistor 46, the charging transistor 49, and the discharging transistor 50 are, for example, enhancement mode NMOS transistors. The voltage resistant transistor 45 is, for example, a depression type NMOS transistor. The charging transistor 47 is, for example, a PMOS transistor.

[0080] Further, the gate electrode of the switching transistor 42 is connected to a signal line STB. The gate electrode of the discharging transistor 43 is connected to a signal line XXL. The gate electrode of the clamp transistor 44 is connected to a signal line BLC. The gate electrode of the voltage resistant transistor 45 is connected to a signal line BLS. The gate electrode of the charging transistor 46 is connected to a signal line HLL. The gate electrode of the charging transistor 49 is connected to a signal line BLX. The signal lines STB, XXL, BLC, BLS, HLL, BLX are connected to the sequencer SQC.

[0081] The latch circuit SDL has a node LAT_S, INV_S, an inverter 51 having an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S, an inverter 52 having an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S, a switching transistor 53 connected to the node LAT_S and a wire LBUS, and a switching transistor 54 connected to the node INV_S and the wire LBUS. The switching transistors 53, 54 are, for example, NMOS transistors. The gate electrode of the switching transistor 53 is connected to the sequencer SQC via a signal line STL. The gate electrode of the switching transistor 54 is connected to the sequencer SQC via a signal line STI.

[0082] The plurality of latch circuits DL are respectively configured almost identically to the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is turned on with the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. The latch circuits DL are different from the latch circuit SDL in this respect.

[0083] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wire LBUS and a wire DBUS. The gate electrode of the switching transistor DSW is connected to the sequencer SQC via a signal line DBS.

[0084] Further, the signal lines STB, HLL, XXL, BLX, BLC, BLS are respectively commonly connected between all the sense amplifier units SAU included in the sense amplifier module SAM. Further, the voltage supply lines to which the voltage V DD is supplied and the voltage supply lines to which the voltage V SRCThe voltage supply lines of the sense amplifier module SAM are commonly connected between all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the signal line STI and the signal line STL of the latch circuit SDL are commonly connected between all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines corresponding to the signal line STI and the signal line STL of the plurality of latch circuits DL are commonly connected between all the sense amplifier units SAU included in the sense amplifier module SAM.

[0085] [Circuit configuration of the cache memory CM]

[0086] The cache memory CM Figure 4 has a plurality of latch circuits connected to the latch circuits in the sense amplifier module SAM via the bus DBUS. The data DAT included in the plurality of latch circuits are sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

[0087] In addition, the cache memory CM is connected to a decoding circuit and a switch circuit, not shown. The decoding circuit decodes the column address CA held in the address register ADR Figure 4 . The switch circuit, based on the output signal of the decoding circuit, causes the latch circuit corresponding to the column address CA to be connected to the bus DB Figure 4 .

[0088] [Circuit configuration of the sequencer SQC]

[0089] The sequencer SQC Figure 4 outputs an internal control signal to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG in accordance with the command data D CMD held in the command register CMR. In addition, the sequencer SQC outputs state data D ST indicating its own state to the state register STR. In addition, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. In addition, the terminal RY / / BY is implemented by, for example, the pad electrode P described with reference to Figure 2 , Figure 3 .

[0090] [Circuit configuration of the input / output control circuit I / O]

[0091] The input / output control circuit I / O has data signal input / output terminals DQ0 to DQ7, clock signal input / output terminals DQS, / DQS, an input circuit such as a comparator connected to the data signal input / output terminals DQ0 to DQ7, and an output circuit such as an OCD (Off Chip Driver) circuit. In addition, the input / output circuit I / O has a shift register and a buffer circuit connected to the input circuit and the output circuit. The input circuit, the output circuit, the shift register, and the buffer circuit are each connected to a terminal to which a power supply voltage V CCQ and a ground voltage V SS are supplied. The data signal input / output terminals DQ0 to DQ7, the clock signal input / output terminals DQS, / DQS, and the terminal to which the power supply voltage V CCQ is supplied are implemented by, for example, the pad electrodes P described with reference to Figure 2 , Figure 3 . Data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in accordance with an internal control signal from the logic circuit CTR. In addition, data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in accordance with an internal control signal from the logic circuit CTR.

[0092] [Circuit configuration of the logic circuit CTR]

[0093] The logic circuit CTR Figure 4 receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and in response thereto, outputs internal control signals to the input / output control circuit I / O. In addition, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are implemented by, for example, the pad electrodes P described with reference to Figure 2 , Figure 3 .

[0094] [Configuration of the memory die MD]

[0095] Figure 7 is a schematic perspective view of the memory die MD. Figure 8 is a schematic enlarged view of a part of the configuration shown in Figure 7 . In addition, Figure 7 and Figure 8 are diagrams for explaining the schematic configuration of the memory die MD, and do not represent the number, shape, arrangement, and the like of the specific configuration.

[0096] The memory die MD is implemented, for example, as described with reference to Figure 7The illustrated semiconductor device includes: a semiconductor substrate 100, a transistor layer L TR provided on the semiconductor substrate 100 TR , wiring layers D0, D1, D2 provided above the transistor layer L MCA , a memory cell array layer L MCA provided above the memory cell array layer L TR , and a plurality of wiring layers provided above the memory cell array layer L.

[0097] The semiconductor substrate 100 is, for example, a semiconductor substrate including P-type silicon (Si) containing a P-type impurity such as boron (B). On the surface of the semiconductor substrate 100, a semiconductor region and an insulating region STI are provided. The semiconductor region functions as, for example, a channel region of a plurality of transistors Tr constituting a peripheral circuit PC.

[0098] The transistor layer L TR includes a plurality of gate electrodes of the plurality of transistors Tr and a contact CS connected to the plurality of transistors Tr. These gate electrodes and the contact CS can include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0099] The wiring layers D0, D1, D2 include a plurality of wirings. The plurality of wirings are electrically connected to at least one of a constituent of the memory cell array MCA and a constituent of the peripheral circuit PC. The plurality of wirings can include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0100] The memory cell array layer L MCA includes a plurality of conductive layers 110 arranged in a Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120, respectively.

[0101] The conductive layer 110 is a substantially plate-shaped conductive layer extending in an X direction. One or a plurality of conductive layers 110 located at the lowermost layer among the plurality of conductive layers 110 function as gate electrodes of a plurality of source side selection gate lines SGS, SGSb Figure 5 and a plurality of source side selection transistors STS, STSb connected thereto. In addition, the plurality of conductive layers 110 located further upward function as gate electrodes of a plurality of word lines WL Figure 5 and a plurality of memory cells MC Figure 5 connected thereto. In addition, one or a plurality of conductive layers 110 located further upward function as drain side selection gate lines SGD and a plurality of drain side selection transistors STD Figure 5The conductive layer 110 functions as a gate electrode of the transistor 100. The conductive layer 110 can include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), or the like. In addition, the conductive layer 110 can include, for example, polysilicon containing an impurity such as phosphorus (P) or boron (B), or the like. Between the plurality of conductive layers 110 arranged in the Z direction, an insulating layer 101 such as silicon oxide (SiO2) is provided.

[0102] Below the conductive layer 110, a conductive layer 140 is provided. The conductive layer 140 functions as a source line SL Figure 5 ) of the transistor 100. The conductive layer 140 has a semiconductor layer 141 connected to the lower end of the semiconductor pillar 120, and a conductive layer 142 connected to the lower surface of the semiconductor layer 141. The semiconductor layer 141 can include, for example, polysilicon containing an impurity such as phosphorus (P) or boron (B), or the like. The conductive layer 142 can include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or another conductive layer. In addition, between the conductive layer 140 and the conductive layer 110, an insulating layer 101 such as silicon oxide (SiO2) is provided.

[0103] The conductive layer 110 and the conductive layer 140 are connected to a contact CC extending in the Z direction. The contact CC can include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), or the like.

[0104] The semiconductor pillar 120 is arranged in a specific pattern in the X direction and the Y direction. The semiconductor pillar 120 functions as a channel region of a plurality of memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS Figure 5 ) of the transistor 100. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided at the center portion. In addition, the outer peripheral surface of the semiconductor pillar 120 is surrounded by the conductive layer 110, and faces the conductive layer 110.

[0105] At the upper end portion of the semiconductor pillar 120, an impurity region 121 containing an N-type impurity such as phosphorus (P) is provided. The impurity region 121 is connected to the bit line BL via a contact Ch and a contact Cb.

[0106] At the lower end portion of the semiconductor pillar 120, an impurity region 122 containing an N-type impurity such as phosphorus (P) is provided. The impurity region 122 is connected to the semiconductor layer 141 of the conductive layer 140. The portion of the semiconductor pillar 120 located directly above the impurity region 122 functions as a channel region of the source side selection transistor STSb.

[0107] The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 can include, for example, silicon oxide (SiO2) or the like. Figure 8The structure shown includes a tunneling insulating film 131, a charge storage film 132, and a blocking insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110. The tunneling insulating film 131 and the blocking insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a charge-storage film such as silicon nitride (Si3N4). The tunneling insulating film 131, the charge storage film 132, and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumference of the semiconductor pillar 120.

[0108] in addition, Figure 8 1 shows an example in which the gate insulating film 130 includes the charge storage film 132 made of silicon nitride or the like. However, the gate insulating film 130 may include a floating gate made of, for example, polysilicon containing N-type or P-type impurities.

[0109] Set in the memory cell array layer L MCA The upper wiring layers include bit lines BL ( Figure 7 ), and the pad electrode P( Figure 2 、 Figure 3 ).

[0110] Bit line BL ( Figure 7 ) can include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). The bit lines BL are arranged in the X direction and extend in the Y direction. In addition, the plurality of bit lines BL are connected to each string unit SU ( Figure 5 ) includes a semiconductor column 120.

[0111] Pad electrode P( Figure 2 、 Figure 3 ) For example, it may include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as aluminum (Al).

[0112] [Threshold voltage of memory cell MC]

[0113] Next, refer to Figure 9 , the threshold voltage of the memory cell MC is described.

[0114] As described above, the memory cell array MCA includes a plurality of memory cells MC. When the plurality of memory cells MC perform a write sequence, the threshold voltages of the memory cells MC are controlled to be in a plurality of states.

[0115] Figure 9 This is a schematic histogram for explaining the threshold voltage of a memory cell MC storing 4-bit data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC in the memory cell array MCA.

[0116] Figure 9In the example, the threshold voltage of the memory cell MC is controlled to 16 states. For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the deleted state). The memory cell MC corresponding to the Er state can be assigned data "1111", for example. In addition, the S1 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. The memory cell MC corresponding to the S1 state can be assigned data "1110", for example. Similarly, the S2 state to the S15 state in the figure respectively correspond to a threshold voltage higher than the threshold voltage corresponding to the S1 state to the S14 state. The memory cells MC corresponding to these distributions are respectively assigned different 4-bit data.

[0117] For example, the threshold voltage of the memory cell MC controlled to the Er state is less than Figure 9 The read voltage V CGS1R And verification voltage V VFYS1 In addition, for example, the threshold voltage of the memory cell MC controlled to the S1 state is greater than Figure 9 The read voltage V CGS1R And verification voltage V VFYS1 , is less than the read voltage V CGS2R And verification voltage V VFYS2 In addition, for example, the threshold voltage of the memory cell MC controlled to the S2 state is greater than Figure 9 The read voltage V CGS2R And verification voltage V VFYS2 , is less than the read voltage V CGS3R And verification voltage V VFYS3 Similarly, the threshold voltages of the memory cells MC controlled to the S3 to S15 states in the figure are controlled to be within a specific range. In addition, the threshold voltages of all memory cells MC are less than Figure 9 The readout path voltage V READ .

[0118] [Reading action]

[0119] Next, refer to Figure 10 and Figure 11 , the read operation of the semiconductor memory device of this embodiment is described.

[0120] Figure 10 It is a schematic waveform diagram for explaining the read operation. Figure 10 The signal waveform shown represents the terminal RY / / BY ( Figure 4 ) signal.

[0121] At time t101, the terminal RY / / BY ( Figure 4) is "H". The controller die CD inputs a command C01 to the memory die MD at time t101, then inputs an address A01, and then inputs a command C02. The command C01 is a command to instruct execution of a read operation. At the time of inputting the command C01, for example, 8-bit data corresponding to the command C01 is set to the data signal input / output terminals DQ0-DQ7, "L, H, L" is set to the external control terminals / CEn, CLE, ALE, and in this state, the external control terminal / WE is raised from L to H. Thus, the command C01 is latched as the command data D CMD ( Figure 4 ) to the command register CMR. At the time of inputting the address A01, for example, 8-bit data included in the address A01 is sequentially set to the data signal input / output terminals DQ0-DQ7, "L, L, H" is set to the external control terminals / CEn, CLE, ALE, and in this state, the external control terminal / WE is raised from L to H a plurality of times. Thus, the address A01 is latched as the address data D ADD ( Figure 4 ) to the address register ADR. The command C02 is a command to instruct start of the read operation. The input of the command C02 is performed in the same manner as the input of the command C01.

[0122] At time t102, the read operation of the memory die MD is started, and the terminal RY / / BY Figure 4 ) of the memory die MD is in the "L" state.

[0123] At time t103, the read operation of the memory die MD is ended, and the terminal RY / / BY Figure 4 ) of the memory die MD is in the "H" state.

[0124] At time t104, the controller die CD inputs a command C03 to the memory die MD, then inputs the address A01, and then inputs a command C04. The command C03 is a command to instruct output of data read by the read operation. The command C04 is a command to instruct start of the data output. The input of the commands C03, C04 is performed in the same manner as the input of the command C01. Then, the controller die CD reads data D01 from the memory die MD. At the time of reading the data D01, for example, the signal switching of acquiring 8-bit data output from the data signal input / output terminals DQ0-DQ7 and input to the external control terminals RE, / RE is alternately performed. The controller die CD performs error detection / correction and the like on the data, and thereafter, transmits to the host 20. In addition, although the input of the command and the address is omitted in the middle, the command and the address can be input again at the time of reading the data D01. Figure 10 At time t104, the controller die CD inputs a command C03 to the memory die MD, then inputs the address A01, and then inputs a command C04. The command C03 is a command to instruct output of data read by the read operation. The command C04 is a command to instruct start of the data output. The input of the commands C03, C04 is performed in the same manner as the input of the command C01. Then, the controller die CD reads data D01 from the memory die MD. At the time of reading the data D01, for example, the signal switching of acquiring 8-bit data output from the data signal input / output terminals DQ0-DQ7 and input to the external control terminals RE, / RE is alternately performed. The controller die CD performs error detection / correction and the like on the data, and thereafter, transmits to the host 20. In addition, although the input of the command and the address is omitted in the middle, the command and the address can be input again at the time of reading the data D01.

[0125] Figure 111 is a schematic cross-sectional view for explaining the read operation. In the following description, the word line WL to be the target of the operation is referred to as the selected word line WL. S The other word lines WL are called non-selected word lines WL U In the following description, a plurality of memory cells MC included in the string unit SU are connected to the selected word line WL. S This is called the case of "selecting the memory cell MC".

[0126] During the read operation, the memory die MD performs, for example, charging of the bit line BL. Figure 6 The latch circuit SDL latches "H", and the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, H, H". As a result, the voltage V is supplied to the bit line BL and the sense node SEN. DD , start charging them. In addition, for example, the source line SL ( Figure 5 ) Supply voltage V SRC , start charging them. Voltage V SRC For example, with a ground voltage V SS The voltage V SRC For example, greater than the ground voltage V SS , is less than the voltage V DD .

[0127] In addition, for example Figure 11 As shown, a plurality of selected memory cells MC are connected to the bit lines BL and the source lines SL. For example, a voltage V is supplied to the selection gate lines (SGD, SGS0, SGSb). SG , the selection transistors (STD, STS, STSb) are turned on. In addition, the non-selected word lines WL U Supply voltage V to read path READ , will be connected to the non-select word line WL U All memory cells MC are set to the on state.

[0128] In addition, if Figure 11 As shown, the word line WL is selected S Supply any read voltage V corresponding to the data to be read CGSR ( Figure 9 The read voltage V CGS1R ~V CGS15R Thus, corresponding to Figure 9 The memory cell MC in any state becomes the on state, and the memory cell MC corresponding to any state becomes the off state.

[0129] In addition, the sense amplifier module SAM ( Figure 5) detects the on state / off state of the selected memory cell MC. For example, via Figure 6 the charging transistor 55 charges the wiring LBUS. In addition, the states of the signal lines STB, XXL, BLC, BLS, HLL, BLX are set to "L, H, H, H, L, H", and the charge of the sensing node SEN is discharged to the bit line BL. Here, the voltage of the sensing node SEN connected to the bit line BL corresponding to the memory cell MC in the on state is greatly reduced. On the other hand, the voltage of the sensing node SEN connected to the bit line BL corresponding to the memory cell MC in the off state is not reduced so much. Therefore, at a certain timing, the signal line STB is set to the "H" state, the charge of the wiring LBUS is discharged or maintained, and the signal line STL is set to the "H" state, whereby the data indicating the state of the selected memory cell MC is latched to the latch circuit SDL. In addition, the data can also be latched to any latch circuit DL other than the latch circuit SDL.

[0130] It is necessary to use a plurality of read voltages V CGSR to perform the read operation, as necessary, the selection of the word line WL S supplying the read voltage V CGSR , detecting the on state / off state of the selected memory cell MC, and latching the detected data. In addition, the latched data is subjected to arithmetic processing, and the data D01 Figure 10 is calculated.

[0131] Thereafter, according to the command C04 Figure 10 described with reference to the command C04, the data D01 Figure 10 ) is output. For example, the data D01 calculated by the sense amplifier module SAM is transmitted to the controller die CD Figure 4 ) via the cache memory CM Figure 1 , the bus DB, and the input / output control circuit I / O.

[0132] [Write sequence]

[0133] Next, the write sequence of the semiconductor storage device is described with reference to Figures 12 to 17

[0134] Figure 12 is a schematic waveform diagram to explain the write sequence. Figure 12 The signal waveform shown in FIG. 17 indicates the signal of the terminal RY / / BY Figure 4 ) of the memory die MD.

[0135] At time t111, the terminal RY / / BY Figure 4 ​) is "H". The controller die CD inputs a command Cll to the memory die MD at time t111, then inputs an address Al l, then inputs data Dll, and then inputs a command C12. The commands Cll, C12 are commands for instructing execution of a write sequence. The input of the commands Cll, C12 is performed in the same manner as the input of the command COl. The input of the address Al l is performed in the same manner as the input of the address AOl. When the data Dll is input, for example, 8-bit data included in the data Dll is sequentially set to the data signal input / output terminals DQ0-DQ7, the external control terminals / CEn, CLE, ALE are set to "L, L, L", and the external control terminal / WE is raised from the L state to the H state a plurality of times in the state. Thus, the data Dll is latched as the data DAT Figure 4 ) to the cache memory CM.

[0136] At time t112, the write sequence of the memory die MD is started, and the terminal RY / / BY Figure 4 ) of the memory die MD becomes the "L" state.

[0137] At time t1113, the write sequence of the memory die MD is ended, and the terminal RY / / BY Figure 4 ) of the memory die MD becomes the "H" state.

[0138] At time t114, the controller die CD inputs a command C13 to the memory die MD. The command C13 is a command for instructing output of status data. The input of the command C13 is performed in the same manner as the input of the command COl. Subsequently, the controller die CD reads out data D12 from the memory die MD. The data D12 is, for example, status data D ST ( Figure 4 ). The reading out of the data D12 is performed in the same manner as the reading out of the data DOl.

[0139] Figure 13 is a schematic flowchart for explaining the write sequence. Figure 14 is a schematic sectional view for explaining a programming operation included in the write sequence. Figure 15 is a schematic sectional view for explaining a verifying operation included in the write sequence. Figure 16 is a schematic waveform chart for explaining the verifying operation. Figure 17 is a schematic table for explaining the verifying operation, indicating which state of the states S1-S11 corresponds to the verifying operation performed in each write cycle. Also, Figure 17 In the table illustrated, only the portion corresponding to the states S1-S11 is indicated, and the portion corresponding to the states S12-S15 is omitted.

[0140] At step S101, Figure 13 ), the number of cycles n W Set to 1. Number of cycles n W It is recorded in a register, etc. In addition, in step S101 , 4-bit data corresponding to the data written to each memory cell MC can be latched in the plurality of latch circuits DL in the sense amplifier unit SAU.

[0141] In step S102 , a programming action is performed.

[0142] When programming actions, for example Figure 14 As shown, it is determined whether to adjust the threshold voltages of the plurality of selected memory cells MC (hereinafter referred to as "writing memory cells MC") or not to adjust the threshold voltages of the plurality of selected memory cells MC (hereinafter referred to as "disabling memory cells MC"). The determination can be made based on, for example, the sense amplifier unit SAU ( Figure 6 ) is performed on the data of the plurality of latch circuits DL in the memory cell MC. In addition, the voltage V is supplied to the bit line BL connected to the memory cell MC. SRC , supply voltage V to the bit line BL connected to the inhibited memory cell MC DD For example, the latch circuit SDL ( Figure 6 ) latches to "L", so that the latch circuit SDL ( Figure 6 ) is latched to "H". In addition, the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, H".

[0143] In addition, the write memory cell MC is connected to the bit line BL, and the inhibit memory cell MC is disconnected from the bit line BL. For example, a voltage V is supplied to the drain side select gate line SGD. SGD Voltage V SGD For example, less than Figure 11 The voltage V SG . Thus, the voltage V is supplied SRC The drain side selection transistor STD corresponding to the bit line BL is turned on and supplied with the voltage V DD The drain side selection transistor STD corresponding to the bit line BL is in the off state. U Supply write path voltage V PASS .Write path voltage V PASS For example, greater than Figure 11 The readout path voltage V READ .

[0144] In addition, the word line WL is selected S Supply programming voltage V PGM . Programming voltage V PGMGreater than the write path voltage V PASS Thus, electrons are stored in the charge storage film 132 ( Figure 8 ), the threshold voltage of the memory cell MC increases.

[0145] In step S103 ( Figure 13 ), perform verification. In addition, in step S104 ( Figure 13 ), it is determined whether the verification operation is completed. If the verification operation is not completed, the process proceeds to step S103. If the verification operation is completed, the process proceeds to step S105.

[0146] For example, in Figure 16 In the example of , the verification operation corresponding to the state S1 is started at time t121 (step S103). S Supply verification voltage V VFYS1 In addition, signal lines BLC, HLL, XXL, STB ( Figure 6 ) becomes "H, H, L, L". Along with this, the voltage V is supplied to the bit line BL connected to the memory cell MC corresponding to the state S1. DD , supply voltage V to other bit lines BL SRC In addition, for example, Figure 15 As shown, the selected memory cell MC is conductively connected to the bit line BL and the source line SL.

[0147] In addition, at time t122, the signal lines BLC, HLL, XXL, and STB ( Figure 6 ) is “H, L, H, L”.

[0148] In addition, at time t123, the signal lines BLC, HLL, XXL, STB ( Figure 6 ) is "H, L, L, H", the on-state / off-state of the selected memory cell MC is detected, and the data indicating the state of the selected memory cell MC is latched into any latch circuit DL.

[0149] At time t124, the verification operation (step S103) corresponding to state S1 is completed. In step S104, it is determined that the verification operation is not completed, and the verification operation (step S103) corresponding to state S2 is started. S Supply verification voltage V VFYS2 In addition, signal lines BLC, HLL, XXL, STB ( Figure 6 ) status is "H, L, L, L".

[0150] In addition, at time t125, the signal lines BLC, HLL, XXL, STB ( Figure 6"H, H, L, L". Along with this, a voltage V DD is supplied to the other bit lines BL SRC .

[0151] In addition, at time t126, the states of the signal lines BLC, HLL, XXL, STB Figure 6 ) are "H, L, H, L".

[0152] In addition, at time t127, the states of the signal lines BLC, HLL, XXL, STB Figure 6 ) are "H, L, L, H", the on state / off state of the selected memory cell MC is detected, and data indicating the state of the selected memory cell MC is latched to any of the latch circuits DL.

[0153] In addition, at time t128, the states of the signal lines BLC, HLL, XXL, STB Figure 6 ) are "H, L, L, L".

[0154] In addition, at time t129, the verification operation (step S103) corresponding to the state S2 ends, and in step S104, a determination that the verification operation has ended is made. Along with this, the selected word line WL S is supplied with a ground voltage V SS . In addition, the states of the signal lines BLC, HLL, XXL, STB Figure 6 ) are "L, L, L, L".

[0155] In addition, in steps S103, S104, based on the data indicating the states of the memory cells MC acquired at times t123, t127, etc., it is determined whether or not each memory cell MC has reached the target threshold voltage. For the memory cell MC determined to have reached the target threshold voltage, the data in the plurality of latch circuits DL within the sense amplifier unit SAU corresponding to the memory cell MC is updated. For example, the data in the latch circuit DL is updated to a value indicating write prohibition. Thereby, in the subsequent write sequence, the memory cell MC is treated as a prohibited memory cell MC. For the memory cell MC determined not to have reached the target threshold voltage, the data in the plurality of latch circuits DL within the sense amplifier unit SAU corresponding to the memory cell MC is maintained.

[0156] In addition, the number of times of the verification operation performed in each write cycle, etc. is adjusted according to the cycle number n W .

[0157] For example, in the example shown in Figure 17 , the cycle number n WIn the case where the state data D is 1, in steps S103, S104, the verification action corresponding to the state S1 is executed. In the verification action corresponding to the state S1, for example, the bit line BL connected to the write memory cell MC corresponding to the state S1 is charged, and the word line WL corresponding to the state S1 is selected S The verification voltage V is supplied VFYS1 .

[0158] In addition, the cycle number n is incremented by 1 W In the case where the state data D is 2, in steps S103, S104, the verification actions corresponding to the states S1, S2 are executed in this order. In the verification action corresponding to the state S2, for example, the bit line BL connected to the write memory cell MC corresponding to the state S2 is charged, and the word line WL corresponding to the state S2 is selected S The verification voltage V is supplied VFYS2 .

[0159] In addition, the cycle number n is incremented by 1 W In the case where the state data D is 3, in steps S103, S104, the verification actions corresponding to the states S1 to S3 are executed in this order. In the verification action corresponding to the state S3, for example, the bit line BL connected to the write memory cell MC corresponding to the state S3 is charged, and the word line WL corresponding to the state S3 is selected S The verification voltage V is supplied VFYS3 .

[0160] In step S105 Figure 13 ), the result of the verification action is determined. For example, in the case where the number of memory cells MC reaching the target threshold voltage is determined to be smaller than a certain number, it is determined that the verification has failed (FAIL), and the process proceeds to step S106. On the other hand, in the case where the number of memory cells MC reaching the target threshold voltage is determined to be a certain number or more, it is determined that the verification has succeeded (PASS), and the process proceeds to step S108.

[0161] In step S106, it is determined whether the cycle number n W has reached a certain number N W . In the case where it has not reached, the process proceeds to step S107. In the case where it has reached, the process proceeds to step S109.

[0162] In step S107, the cycle number n W is incremented by 1, and the process proceeds to step S102. In addition, in step S107, for example, the program voltage V PGM is incremented by a certain voltage ΔV.

[0163] In step S108, the state data D ST indicating that the write sequence has normally ended is stored in the state register STR Figure 2 , and the write sequence is ended.

[0164] In step S109, the status data D indicating that the write sequence has not ended normally is ST Stored to status register STR( Figure 2 ), ending the write sequence.

[0165] [Interruption and restart of the write sequence]

[0166] Next, refer to Figures 18 to 20 , the interruption and resumption of the write sequence of the semiconductor memory device are described.

[0167] Figure 18 Schematic waveform diagram for explaining the interruption and resumption of a write sequence. Figure 18 The signal waveform shown in FIG. 1 represents the terminal RY / / BY ( Figure 4 ) signal.

[0168] exist Figure 18 In the example shown in FIG1 , at time t115 when the write operation is being performed, the controller die CD inputs a command C21 to the memory die MD. The command C21 is a command for interrupting the write operation. The input of the command C21 is performed in the same manner as the input of the command C01.

[0169] In addition, Figure 18 In the example, the write operation is interrupted at the subsequent time t106, and the terminal RY / / BY ( Figure 4 ) becomes the “H” state.

[0170] In addition, Figure 18 In the example, subsequent execution refers to Figure 10 and Figure 11 The read action described.

[0171] In addition, Figure 18 In the example of , at the subsequent time t117, the controller die CD inputs a command C22 to the memory die MD. The command C22 is a command to restart the write operation. The input of the command C22 is performed in the same manner as the input of the command C01.

[0172] In addition, Figure 18 In the example of , the writing operation is restarted at the subsequent time t118.

[0173] Next, refer to Figure 19 and Figure 20 , supplied to the selected word line WL when interrupting and restarting the write sequence S The voltage of Figure 19 and Figure 20 Description Figure 13 The number of cycles n W is 8, such as Figure 17 As shown, an example of performing 6 verification actions.

[0174] First, for comparison, refer to Figure 19 , an example illustrating an uninterrupted write sequence.

[0175] exist Figure 19 In the example shown, the programming operation starts at time t131. That is, the selected word line WL S Supply programming voltage V PGM In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "L, L, L".

[0176] In addition, at time t132, the programming operation is completed. That is, the selected word line WL S Supply ground voltage V SS In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "L, L, L".

[0177] Furthermore, at time t133, the verification operation corresponding to state S3 is started. That is, the selected word line WL S Supply verification voltage V VFYS3 In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "H, L, L".

[0178] In addition, at time t134, the signal lines HLL, XXL, and STB ( Figure 6 ) becomes "L, H, L".

[0179] In addition, at time t135, the signal lines HLL, XXL, and STB ( Figure 6 ) becomes "L, L, H".

[0180] Furthermore, at time t136, the verification operation corresponding to state S3 is completed and the verification operation corresponding to state S4 is started. S Supply verification voltage V VFYS4 In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "H, L, L".

[0181] In addition, at time t137, the signal lines HLL, XXL, and STB ( Figure 6 ) becomes "L, H, L".

[0182] In addition, at time t138, the signal lines HLL, XXL, and STB ( Figure 6 ) becomes "L, L, H".

[0183] In addition, at time t139, the verification operation corresponding to state S4 ends, and a verification operation corresponding to state S5 is started. That is, the selected word line WL S The verify voltage V VFYS5 is supplied. In addition, the states of the signal lines HLL, XXL, STB Figure 6 ) become "H, L, L".

[0184] In addition, at time t140, the states of the signal lines HLL, XXL, STB Figure 6 ) become "L, H, L".

[0185] In addition, at time t141, the states of the signal lines HLL, XXL, STB Figure 6 ) become "L, L, H".

[0186] In addition, at time t142, the verification operation corresponding to state S5 ends, and a verification operation corresponding to state S6 is started. That is, the selected word line WL S The verify voltage V VFYS6 is supplied. In addition, the states of the signal lines HLL, XXL, STB Figure 6 ) become "H, L, L".

[0187] In addition, at time t143, the states of the signal lines HLL, XXL, STB Figure 6 ) become "L, H, L".

[0188] In addition, at time t144, the states of the signal lines HLL, XXL, STB Figure 6 ) become "L, L, H".

[0189] In addition, at time t145, the verification operation corresponding to state S6 ends, and a verification operation corresponding to state S7 is started. That is, the selected word line WL S The verify voltage V VFYS7 is supplied. In addition, the states of the signal lines HLL, XXL, STB Figure 6 ) become "H, L, L".

[0190] In addition, at time t146, the states of the signal lines HLL, XXL, STB Figure 6 ) become "L, H, L".

[0191] In addition, at time t147, the states of the signal lines HLL, XXL, STB Figure 6 ) become "L, L, H".

[0192] Furthermore, at time t148, the verification operation corresponding to state S7 is completed and the verification operation corresponding to state S8 is started. S Supply verification voltage V VFYS8 In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "H, L, L".

[0193] In addition, at time t149, the signal lines HLL, XXL, and STB ( Figure 6 ) becomes "L, H, L".

[0194] In addition, at time t150, the signal lines HLL, XXL, and STB ( Figure 6 ) becomes "L, L, H".

[0195] At time t151, the verification operation corresponding to state S8 is completed. S Supply ground voltage V SS In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "L, L, L".

[0196] Next, refer to Figure 20 , an example of interrupting and restarting a write sequence is described. In the semiconductor memory device of this embodiment, when the write sequence is interrupted after the k-th (k is a natural number less than m) verification action of the write sequence is completed and before the k+1-th verification action is completed, after the write sequence is restarted, a dummy verification action corresponding to the k-th verification action is performed, and then the actions after the k+1-th verification action are performed. In addition, Figure 17 and Figure 20 In the example of k=4, Figure 17 In the example, the verification action corresponding to the confirmation mark corresponds to the completed verification action, and the verification action corresponding to the circle corresponds to the verification action before execution. Figure 17 In the example, the number of loops n W The state where k=8 and k=4 corresponds to a state where four verification operations corresponding to states S3 to S6 have been executed and two verification operations corresponding to states S7 and S8 have not been executed.

[0197] Further, the dummy verify operation can be performed similarly to the verify operation. However, in the dummy verify operation, the data indicating whether the selection memory cell MC is in the on state or the off state can not be latched to the latch circuit. Further, in the dummy verify operation, the voltage can be supplied to the bit line BL or can not be supplied to the bit line BL. Further, in the dummy verify operation, the sense amplifier module SAM can be caused to operate in the same manner as in the verify operation, or a part or all of the sense amplifier module SAM can not be caused to operate.

[0198] In Figure 20 the example shown, at time t131 to time t144, the write sequence is performed similarly to the example shown in FIG. 13. Figure 19

[0199] Further, at time t245, the verify operation corresponding to the state S6 ends, and the write sequence is interrupted. That is, the selection word line WL S to which the ground voltage V SS is supplied is selected, and the voltage V SS is supplied to the bit line BL S . Further, the states of the signal lines HLL, XXL, STB Figure 6 become "L, L, L".

[0200] Further, at time t242, the write sequence is restarted, and the dummy verify operation corresponding to the state S6 is started. That is, the selection word line WL SS to which the ground voltage V SS is supplied is selected, and the voltage V VFYS6 is supplied to the bit line BL S . Further, the states of the signal lines HLL, XXL, STB Figure 6 become "H, L, L".

[0201] Further, at time t243, the states of the signal lines HLL, XXL, STB Figure 6 become "L, H, L".

[0202] Further, at time t244, the states of the signal lines HLL, XXL, STB Figure 6 become "L, L, H".

[0203] Thereafter, the dummy verify operation corresponding to the state S6 ends, and the operation corresponding to the time t145 onward of the write sequence is performed.

[0204] [First Comparative Example]

[0205] Next, the interruption and restart of the write sequence of the semiconductor memory device of the comparative example will be described with reference to Figure 21

[0206] In the semiconductor memory device of the first comparative example, when the write sequence is interrupted after the kth verification operation of the write sequence is completed and before the k+1th verification operation is completed, after the write sequence is restarted, the dummy verification operations corresponding to the 1st to kth verification operations are sequentially executed, and then the operations after the k+1th verification operation are executed. Figure 21 ] shows an example where k=4.

[0207] Figure 21 In the example shown, at time t131 to time t144, Figure 19 The example shown similarly performs a write sequence.

[0208] Furthermore, at time t245, the verification operation corresponding to state S6 is completed and the write sequence is interrupted. S Supply ground voltage V SS In addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "L, L, L".

[0209] Furthermore, the write sequence is restarted at time t233. Furthermore, from time t233 to time t145, the dummy verification operation corresponding to states S3 to S6 is executed.

[0210] Thereafter, the operation corresponding to time t145 and later of the write sequence is executed.

[0211] [Comparative Example 2]

[0212] Next, refer to Figure 22 , the interruption and resumption of the write sequence of the semiconductor memory device of the comparative example are described.

[0213] In the semiconductor memory device of the second comparative example, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the k+1-th verification operation is completed, the dummy verification operation is not performed after the write sequence is restarted, and the operations after the k+1-th verification operation are performed immediately after the write sequence is restarted. Figure 22 denoted by k=4.

[0214] exist Figure 22 In the example shown, at time t131 to time t144, Figure 19 The example shown similarly performs a write sequence.

[0215] Furthermore, at time t245, the verification operation corresponding to state S6 is completed and the write sequence is interrupted. S Supply ground voltage V SSIn addition, signal lines HLL, XXL, STB ( Figure 6 ) becomes "L, L, L".

[0216] Furthermore, the write sequence is restarted at time t145, and operations corresponding to time t145 and thereafter of the write sequence are executed.

[0217] [Effects of the First Embodiment]

[0218] As described above, in the semiconductor storage device of the first comparative example, when the write sequence is interrupted after the kth verification action of the write sequence is completed and before the k+1th verification action is completed, after the write sequence is restarted, the virtual verification actions corresponding to the 1st to kth verification actions are performed, and then the actions after the k+1th verification action are performed.

[0219] In this method, the time from restarting the write sequence to the k+1th verification action ( Figure 21 The time from time t233 to time t145 is prolonged, which may hinder the speed of the write sequence.

[0220] Therefore, as described above, in the semiconductor storage device of the second comparative example, when the write sequence is interrupted after the kth verification action of the write sequence is completed and before the k+1th verification action is completed, the virtual verification action is not performed after the write sequence is restarted, and the actions after the k+1th verification action are performed immediately after the write sequence is restarted.

[0221] In this method, since the (k+1)th verification operation starts immediately after the write sequence is restarted, the write sequence can be accelerated.

[0222] However, in this method, the reliability of the verification operation performed immediately after the restart of the write sequence may be lower than that of the method of the first comparative example. This is believed to be caused by the following phenomenon.

[0223] Specifically, as semiconductor memory devices become increasingly integrated, the thickness of conductive layer 110, which functions as word line WL, becomes increasingly thinner, leading to an increasingly higher resistance in conductive layer 110. Furthermore, the distance between conductive layers 110 in the Z direction becomes increasingly shorter, increasing the capacitance within conductive layer 110. Consequently, the time constant within conductive layer 110 increases, and the time required for the voltage of the entire word line WL to reach the voltage supplied to word line WL increases.

[0224] When performing a verify operation in this state, for example, a voltage may be supplied to word line WL until the voltage of the entire word line WL reaches saturation, and data indicating whether the memory cell MC is in the on or off state may be acquired in this state. However, this method increases the time required for the verify operation, which may hinder the speed of the write sequence. Therefore, to speed up the write sequence, it is possible to acquire the data before the voltage of the entire word line WL reaches saturation.

[0225] Here, in the first comparative example, in both the case where the write sequence is interrupted and the case where it is not interrupted, the selected word line WL is reset immediately before the (k+1)th verification operation. S Supply verification voltage V VFYS6 In the k+1th verification operation, the word line WL is selected. S Supply verification voltage V VFYS7 Therefore, the selected word line WL in the k+1th verification operation S The voltage can be considered to be of the same magnitude regardless of whether the write sequence is interrupted or not.

[0226] On the other hand, in the second comparative example, when the write sequence is interrupted, the selected word line WL is interrupted immediately before the (k+1)th verification operation. S Supply ground voltage V SS In the k+1th verification operation, the word line WL is selected. S Supply verification voltage V VFYS7 Therefore, it is considered that the selected word line WL in the (k+1)th verification operation when the write sequence is interrupted S The voltage of the selected word line WL is less than the voltage of the selected word line WL in the k+1th verification operation when the write sequence is not interrupted. S voltage.

[0227] Here, as described above, in the semiconductor storage device of the first embodiment, when the write sequence is interrupted after the kth verification action of the write sequence is completed and before the k+1th verification action is completed, after the write sequence is restarted, a virtual verification action corresponding to the kth verification action is performed, and then actions after the k+1th verification action are performed.

[0228] In this method, the time from restarting the write sequence to the k+1th verification action ( Figure 20 The time from time t242 to time t145) is shorter than that of the first comparative example.

[0229] In addition, in this method, before the k+1th verification operation, the selected word line WL S Supply verification voltage V VFYS6 In the k+1th verification operation, the word line WL is selected. SSupply verification voltage V VFYS7 Therefore, it is considered that the selected word line WL in the k+1th verification operation S The voltage is of the same magnitude regardless of whether the write sequence is interrupted or not.

[0230] Therefore, according to the semiconductor memory device of the first embodiment, it is possible to increase the speed of the write sequence without reducing the reliability of the write sequence.

[0231] [Second embodiment]

[0232] Next, refer to Figure 23 A semiconductor memory device according to a second embodiment will now be described. The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment differs from the semiconductor memory device according to the first embodiment in the operations performed after interrupting and restarting a write sequence.

[0233] In the semiconductor memory device of the second embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the k+1-th verification operation is completed, after the write sequence is restarted, the dummy verification operations corresponding to the k-1-th and k-th verification operations are sequentially executed, and then the operations after the k+1-th verification operation are executed. In addition, Figure 23 denoted by k=4.

[0234] Figure 23 The example shown is basically the same as the reference Figure 20 The described operations execute the write sequence and read operation in the same manner.

[0235] However, in Figure 23 In the example shown, the write sequence is restarted not at time t242 but at time t239.

[0236] Furthermore, from time t239 when the write sequence is restarted to time t145 when the verify operation corresponding to state S7 is started, the dummy verify operations corresponding to state S5 and state S6 are sequentially executed.

[0237] [Third embodiment]

[0238] Next, refer to Figure 24 A semiconductor memory device according to a third embodiment will now be described. The semiconductor memory device according to the third embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the third embodiment differs from the semiconductor memory device according to the first embodiment in the operations performed after interrupting and restarting a write sequence.

[0239] In the semiconductor storage device of the third embodiment, in the case where the write sequence is interrupted after the kth verification operation of the write sequence ends and before the (k+1)th verification operation ends, after the write sequence is restarted, two dummy verification operations corresponding to the kth verification operation are performed, and thereafter, the operation after the (k+1)th verification operation is performed. In addition, Figure 24 The case where k = 4 is shown in the example.

[0240] Figure 24 In the example shown, the write sequence and the read operation are performed substantially in the same manner as the operations described with reference to Figure 20

[0241] However, in the example shown in FIG. 24, the write sequence is restarted at time t239 instead of time t242. Figure 24

[0242] In addition, from time t239 at which the write sequence is restarted to time t145 at which the verification operation corresponding to state S7 is started, two dummy verification operations corresponding to state S6 are performed.

[0243] [Fourth Embodiment]

[0244] Next, the semiconductor storage device of the fourth embodiment will be described with reference to Figure 25 The semiconductor storage device of the fourth embodiment is substantially constructed in the same manner as the semiconductor storage device of the first embodiment. However, in the semiconductor storage device of the fourth embodiment, the operations performed after the write sequence is interrupted and after the write sequence is restarted are different from those of the semiconductor storage device of the first embodiment.

[0245] In the semiconductor storage device of the fourth embodiment, in the case where the write sequence is interrupted after the kth verification operation of the write sequence ends and before the (k+1)th verification operation ends, after the write sequence is restarted, the dummy verification operations corresponding to the (k+1)th and kth verification operations are performed in this order, and thereafter, the operation after the (k+1)th verification operation is performed. In addition, Figure 25 The case where k = 4 is shown in the example.

[0246] Figure 25 In the example shown, the write sequence and the read operation are performed substantially in the same manner as the operations described with reference to Figure 20

[0247] However, in the example shown in FIG. 24, the write sequence is restarted at time t239 instead of time t242. Figure 25

[0248] ​​​​Furthermore, from time t239 when the write sequence is restarted to time t145 when the verify operation corresponding to state S7 is started, the dummy verify operations corresponding to state S7 and state S6 are sequentially executed.

[0249] [Fifth embodiment]

[0250] Next, refer to Figure 26 A semiconductor memory device according to a fifth embodiment will now be described. The semiconductor memory device according to the fifth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the operations performed after interrupting and restarting a write sequence in the semiconductor memory device according to the fifth embodiment differ from those in the semiconductor memory device according to the first embodiment.

[0251] In the semiconductor memory device of the fifth embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the k+1-th verification operation is completed, after the write sequence is restarted, a dummy verification operation corresponding to the k+1-th verification operation is performed, and then operations after the k+1-th verification operation are performed. In addition, Figure 26 denoted by k=4.

[0252] Figure 26 The example shown is basically the same as the reference Figure 20 The described operations execute the write sequence and read operation in the same manner.

[0253] However, in Figure 26 In the example shown, a dummy verify operation corresponding to state S7 is executed from time t242 when the write sequence is restarted to time t145 when the verify operation corresponding to state S7 is started.

[0254] [Sixth embodiment]

[0255] Next, refer to Figure 27 A semiconductor memory device according to a sixth embodiment will now be described. The semiconductor memory device according to the sixth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the sixth embodiment differs from the semiconductor memory device according to the first embodiment in the operations performed after interrupting and restarting a write sequence.

[0256] In the semiconductor memory device of the sixth embodiment, when the write sequence is interrupted after the kth verification operation of the write sequence is completed and before the k+1th verification operation is completed, the selected word line WL is executed after the write sequence is restarted. S The supply ratio corresponds to the verification voltage V of the k+1th verification operation. VFYS7A dummy verification operation of a large voltage is performed, and then a dummy verification operation corresponding to the k+1th verification operation is performed, and then the operations after the k+1th verification operation are performed. Figure 27 denoted by k=4.

[0257] Figure 27 The example shown is basically the same as the reference Figure 20 The described operations execute the write sequence and read operation in the same manner.

[0258] However, in Figure 27 In the example shown, the write sequence is restarted not at time t242 but at time t239.

[0259] Furthermore, the two dummy verification operations are sequentially performed from the time t239 at which the write sequence is restarted to the time t145 at which the verification operation corresponding to the state S7 is started. Figure 27 In the example, from time t239 to time t242, the word line WL is selected. S Supply verification voltage V corresponding to state S8 VFYS8 .

[0260] [Seventh embodiment]

[0261] Next, refer to Figure 28 A semiconductor memory device according to a seventh embodiment will now be described. The semiconductor memory device according to the seventh embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the seventh embodiment differs from the semiconductor memory device according to the first embodiment in the operations performed after interrupting and restarting a write sequence.

[0262] In the semiconductor memory device of the seventh embodiment, when the write sequence is interrupted after the kth verification operation of the write sequence is completed and before the k+1th verification operation is completed, the selected word line WL is executed after the write sequence is restarted. S The supply ratio corresponds to the verification voltage V of the k+1th verification operation. VFYS7 A large voltage dummy verification operation is performed, and then the k+1th verification operation and subsequent operations are performed. Figure 28 denoted by k=4.

[0263] Figure 28 The example shown is basically the same as the reference Figure 20 The described operations execute the write sequence and read operation in the same manner.

[0264] However, in Figure 28In the example shown, the dummy verify operation is performed from the time t242 at which the write sequence is restarted to the time t145 at which the verify operation corresponding to the state S7 is started. In addition, in the example shown, the verify operation corresponding to the state S8 is performed from the time t242 to the time t145. Figure 28 In the example shown, the verify operation corresponding to the state S8 is performed from the time t242 to the time t145. S The verify voltage V VFYS8 corresponding to the state S8 is supplied.

[0265] [8th Embodiment]

[0266] Next, the semiconductor storage device of the 8th embodiment will be described with reference to Figures 29 to 31 , which is basically constructed in the same manner as the semiconductor storage device of the 1st embodiment. However, in the semiconductor storage device of the 8th embodiment, the order of execution of the verify operations is different from that of the semiconductor storage device of the 1st embodiment.

[0267] For example, in the 1st embodiment, as described with reference to Figure 17 , Figure 19 and the like, in the case where the number n W of the write cycles is 8, the verify operation corresponding to the state S3 is performed from the time t133 to the time t136, the verify operation corresponding to the state S4 is performed from the time t136 to the time t139, and the same applies to the verify operations corresponding to the states S5, S6, S7 and S8 which are sequentially performed from the time t139 to the time t151. That is, in the case where the verify operation is performed a plurality of times in each write cycle, the verify operations are performed in the order from the verify operation corresponding to the state of the low threshold voltage to the verify operation corresponding to the state of the high threshold voltage.

[0268] On the other hand, in the 8th embodiment, as exemplified with reference to Figure 29 , Figure 30 , in the case where the number n W of the write cycles is 8, the verify operation corresponding to the state S8 is performed from the time t333 to the time t336, the verify operation corresponding to the state S7 is performed from the time t336 to the time t339, and the same applies to the verify operations corresponding to the states S6, S5, S4 and S3 which are sequentially performed from the time t339 to the time t351. That is, in the case where the verify operation is performed a plurality of times in each write cycle, the verify operations are performed in the order from the verify operation corresponding to the state of the high threshold voltage to the verify operation corresponding to the state of the low threshold voltage.

[0269] In addition, in the eighth embodiment, in the case where the write sequence is interrupted after the end of the kth verification operation of the write sequence and before the end of the (k+1)th verification operation, as in the first embodiment, after the write sequence is restarted, a dummy verification operation corresponding to the kth verification operation is performed, and thereafter, the operation after the (k+1)th verification operation is performed.

[0270] In Figure 31 the example shown, the write sequence is performed as in the example shown in FIG. 34. Figure 30

[0271] In addition, at time t445, the verification operation corresponding to state S5 ends, and the write sequence is interrupted. That is, the selected word line WL S is supplied with the ground voltage V SS . In addition, the states of the signal lines HLL, XXL, STB Figure 6 become "L, L, L".

[0272] In addition, at time t442, the write sequence is restarted, and a dummy verification operation corresponding to state S5 is started. That is, the selected word line WL SS to which the ground voltage V S is supplied is supplied with the verification voltage V VFYS5 . In addition, the states of the signal lines HLL, XXL, STB Figure 6 become "H, L, L".

[0273] In addition, at time t443, the states of the signal lines HLL, XXL, STB Figure 6 become "L, H, L".

[0274] In addition, at time t444, the states of the signal lines HLL, XXL, STB Figure 6 become "L, L, H".

[0275] Thereafter, the dummy verification operation corresponding to state S5 ends, and the operation after time t345 corresponding to the write sequence is performed.

[0276] In addition, in the example, as in the first embodiment, in the case where the write sequence is interrupted after the end of the kth verification operation of the write sequence and before the end of the (k+1)th verification operation, after the write sequence is restarted, a dummy verification operation corresponding to the kth verification operation is performed, and thereafter, the operation after the (k+1)th verification operation is performed. However, this functional method is merely an example, and the specific form can be appropriately adjusted.

[0277] For example, the second embodiment Figure 23 ​) Similarly, in the case where the write sequence is interrupted after the end of the kth verification action of the write sequence and before the end of the (k+l)th verification action, after the write sequence is restarted, the virtual verification actions corresponding to the (k-l)th and kth verification actions are executed in this order.

[0278] Further, for example, the 3rd embodiment (S1 to S15) can be combined with the 4th embodiment (S1 to S15) (S1 to S15). Figure 24 ) Similarly, in the case where the write sequence is interrupted after the end of the kth verification action of the write sequence and before the end of the (k+l)th verification action, after the write sequence is restarted, the virtual verification actions corresponding to the (k-l)th and kth verification actions are executed in this order.

[0279] Further, for example, the 3rd embodiment (S1 to S15) can be combined with the 4th embodiment (S1 to S15) (S1 to S15). Figure 25 ) Similarly, in the case where the write sequence is interrupted after the end of the kth verification action of the write sequence and before the end of the (k+l)th verification action, after the write sequence is restarted, the virtual verification actions corresponding to the (k-l)th and kth verification actions are executed in this order.

[0280] Further, for example, the 3rd embodiment (S1 to S15) can be combined with the 4th embodiment (S1 to S15) (S1 to S15). Figure 26 ) Similarly, in the case where the write sequence is interrupted after the end of the kth verification action of the write sequence and before the end of the (k+l)th verification action, after the write sequence is restarted, the virtual verification actions corresponding to the (k-l)th and kth verification actions are executed in this order.

[0281] [Other Embodiments]

[0282] The semiconductor storage devices of the 1st to 8th embodiments have been described above. However, the semiconductor storage devices of the embodiments are only examples, and the specific configuration, operation, etc. can be appropriately adjusted.

[0283] For example, in the 1st to 8th embodiments, in the case where the write sequence is interrupted after the end of the kth verification action of the write sequence and before the end of the (k+l)th verification action, after the write sequence is restarted and before the (k+l)th verification action is started, any one of the verification voltages V S corresponding to the states S1 to S15 is supplied to the select word line WL VFYS1 . However, this method is only an example, and the specific method can be appropriately adjusted. For example, it can be considered that the voltage supplied to the select word line WL VFYS15 at this time is a voltage that is higher than or equal to the verification voltage corresponding to the 1st verification action. Further, for example, it can be considered that the voltage supplied to the select word line WL S at this time is set to a voltage that is higher than or equal to the verification voltage corresponding to the kth verification action, whereby the select word line WL S can be more appropriately adjusted. SIn addition, it can be considered that the voltage supplied to the selected word line WL at this time S The voltage is at least less than the programming voltage V PGM voltage.

[0284] In addition, for example, in the first to eighth embodiments, the execution time of the verification operation is the same as the execution time of the dummy verification operation, and the number of dummy verification operations executed after restarting the write sequence is less than that in the first comparative example ( Figure 21 ). However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the execution time of the dummy verification operation can be made shorter than the execution time of the verification operation. This can further speed up the write sequence.

[0285] Furthermore, for example, as described above, voltage may or may not be supplied to the bit lines BL during the dummy verify operation. Furthermore, when voltage is supplied to the bit lines BL, the specific bit lines BL to which voltage is supplied can be adjusted as appropriate. For example, in the example described above, for memory cells MC determined to have reached the target threshold voltage during the verify operation, the data within the multiple latch circuits DL within the sense amplifier unit SAU corresponding to the memory cells MC is updated to a value indicating write-inhibit. In this case, it is considered that the number of bit lines BL supplied with voltage during the dummy verify operation is less than the number of bit lines BL supplied with voltage during the verify operation.

[0286] However, this configuration is merely an example, and the specific method can be adjusted as appropriate. For example, for memory cells MC determined to have reached the target threshold voltage during a verify operation, a verify path flag can be individually latched within the sense amplifier unit SAU corresponding to the memory cell MC, thereby maintaining the 4-bit data corresponding to the memory cell MC. Furthermore, the number of bit lines BL supplied with voltage during a dummy verify operation can be set to the same number as the number of bit lines BL supplied with voltage during the actual verify operation.

[0287] [other]

[0288] While several embodiments of the present invention have been described, these embodiments are presented merely as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention recited in the claims and their equivalents.

[0289] [Explanation of Symbols]

[0290] MC storage unit

[0291] WL word line

[0292] BL bit line.

Claims

1. A method for writing in a semiconductor memory device, the method comprising: Programming a memory transistor of the semiconductor memory device; After programming the memory transistor, sequentially performing a plurality of verification operations, the verification operations including: a first verification operation, a second verification operation performed after the first verification operation, a third verification operation performed after the second verification operation, and a fourth verification operation performed after the third verification operation, wherein in the first verification operation, the second verification operation, the third verification operation, and the fourth verification operation, voltages of a first level, a second level, a third level, and a fourth level are applied to a word line electrically connected to the memory transistor, respectively; and After receiving a command to restart the write sequence that was interrupted before the fourth verification action was completed, the verification action is performed at least once but not more than twice before the fourth verification action is re-executed.

2. The method according to claim 1, wherein Before re-executing the fourth verification operation, the third verification operation is re-executed.

3. The method according to claim 1, wherein Before re-performing the fourth verification operation, the second verification operation is re-performed, and then the third verification operation is re-performed.

4. The method according to claim 1, wherein Before re-executing the fourth verification operation, the third verification operation is re-executed, and then the second verification operation is re-executed.

5. The method according to claim 1, wherein Before re-performing the fourth verification operation, the third verification operation is re-performed twice.

6. The method according to claim 1, wherein Before re-executing the fourth verification operation, a dummy fourth verification operation is performed.

7. The method according to claim 1, wherein The verification operation includes a fifth verification operation in which a voltage of a fifth level higher than any one of the first level, the second level, the third level, and the fourth level is applied to the word line; and Before re-executing the fourth verification operation, a dummy fifth verification operation is executed, and then a dummy fourth verification operation is executed.

8. The method according to claim 1, wherein The verification operation includes a fifth verification operation in which a voltage of a fifth level higher than any one of the first level, the second level, the third level, and the fourth level is applied to the word line; and Before re-executing the fourth verification operation, a dummy fifth verification operation is performed.

9. The method according to claim 1, wherein The first level is lower than the second level, the second level is lower than the third level, and the third level is lower than the fourth level.

10. The method according to claim 1, wherein The first level is higher than the second level, the second level is higher than the third level, and the third level is higher than the fourth level.

11. A method for writing in a semiconductor memory device, the method comprising: Programming a memory transistor of the semiconductor memory device; After programming the storage transistor, a plurality of verification actions are sequentially performed, the verification actions including: a first verification action, a second verification action that is completed after the first verification action, and a third verification action that is started after the second verification action; and After receiving a command to resume the write sequence that was interrupted before the third verification action was completed, at least one dummy verification action is performed, and then the third verification action is performed.

12. The method according to claim 11, wherein In each of the first verification operation, the second verification operation, and the third verification operation, data indicating whether the memory transistor is on or off is latched; and In each dummy verification action, data indicating whether the storage transistor is turned on or off is not latched.

13. The method according to claim 11, wherein After receiving a command to resume the write sequence that was interrupted before the third verification operation was completed, at least two dummy verification actions are performed, and then the third verification action is performed.

14. The method according to claim 13, wherein In the first verification operation, the second verification operation, and the third verification operation, voltages of a first level, a second level, and a third level are applied to a word line electrically connected to the memory transistor, respectively; and During the at least two dummy verification actions, voltages of different levels are applied to the word line.

15. The method according to claim 13, wherein In the first verification operation, the second verification operation, and the third verification operation, voltages of a first level, a second level, and a third level are applied to a word line electrically connected to the memory transistor, respectively; and During the at least two dummy verification actions, voltages of the same level are applied to the word lines.

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