Method and device for testing bad block processing capability of flash translation layer, equipment and medium

Abstract

The invention discloses a bad block processing capability testing method, device and equipment of a flash memory conversion layer and a medium, and relates to the technical field of hard disk testing, and the method comprises the following steps: analyzing an error injection instruction submitted by a user, obtaining a target error, an error injection position and an error triggering condition, when executing a target access operation on a current data block, determining that the triggering condition is met, and if the triggering condition is met, executing the target access operation on the current data block. The target error is injected into the solid state disk, bad blocks generated in the data access operation process are dynamically simulated, the remapping operation after the target error is injected by the flash memory conversion layer is monitored, the result is compared with the expected remapping operation result and the remapping block count, and the bad block processing capacity test result of the flash memory conversion layer is generated. The technical problems that bad blocks generated in the use process cannot be dynamically simulated and the real-time response capability of the FTL cannot be verified can be solved, and the technical effects of simulating a real bad block scene through the trigger condition and the target error and testing the bad block processing capability of the FTL in time are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hard disk testing, and particularly relates to a bad block processing capability test method, device and equipment of a flash translation layer and a medium. BACKGROUND

[0002] Solid State Drives (SSD) have become the core storage medium in the fields of data centers, consumer electronics and industrial storage due to their high-speed reading and writing, low latency and anti-impact characteristics, but the NAND flash memory (NAND) as the core storage medium of the SSD has inherent defects, limited erasing and writing times and physical reliability problems, and with the improvement of storage density, the charge leakage and cross-interference problems of the NAND unit are aggravated, resulting in a significant increase in the probability of generating bad blocks.

[0003] As a core firmware module of the SSD, the flash translation layer (FTL) is responsible for mapping the logical address (LBA) to the physical address (PBA), and ensuring the reliability and service life of the SSD through mechanisms such as bad block management, wear leveling and garbage collection, and the bad block management is one of the key functions of the FTL, but the existing test method screens out factory bad blocks by using a preset bad block table (BBT) to verify the bad block processing capability of the FTL, but cannot dynamically simulate the bad blocks generated in the use process, and cannot verify the real-time response capability of the FTL. SUMMARY

[0004] The present application provides a bad block processing capability test method, device and equipment of a flash translation layer and a medium to at least solve the problem that the related art cannot dynamically simulate the bad blocks generated in the use process, and cannot verify the real-time response capability of the FTL.

[0005] The application provides a bad block processing capability test method of a flash translation layer, and the method comprises the following steps: obtaining an error injection instruction submitted by a user, wherein the error injection instruction at least comprises a target error causing a bad block, an injection position of the target error and an error trigger condition, the target error is an error injected for a target access operation; analyzing the error injection instruction, and when a target access operation is performed on a current data block and it is determined that the error trigger condition is met, injecting the target error into a solid state disk based on the injection position of the target error; monitoring a remapping operation of the flash translation layer after the target error is injected and checking a remapping block count; comparing the remapping operation result and the remapping block count of the flash translation layer after the target error is injected, which are monitored, with expected remapping operation results and a remapping block count, and generating a bad block processing capability test result of the flash translation layer.

[0006] The application further provides a bad block processing capability test device of a flash translation layer, and the device comprises the following modules: an error injection instruction obtaining module, which is used to obtain an error injection instruction submitted by a user, wherein the error injection instruction at least comprises a target error causing a bad block, an injection position of the target error and an error trigger condition, the target error is an error injected for a target access operation; an instruction analyzing module, which is used to analyze the error injection instruction, and when a target access operation is performed on a current data block and it is determined that the error trigger condition is met, inject the target error into a solid state disk based on the injection position of the target error; a remapping operation monitoring module, which is used to monitor a remapping operation of the flash translation layer after the target error is injected and check a remapping block count; and a bad block processing capability test module, which is used to compare the remapping operation result and the remapping block count of the flash translation layer after the target error is injected, which are monitored, with expected remapping operation results and a remapping block count, and generate a bad block processing capability test result of the flash translation layer.

[0007] The application further provides an electronic device, which comprises a memory for storing a computer program and a processor for executing the computer program to realize the steps of any of the bad block processing capability test methods of the flash translation layer.

[0008] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the steps of any of the bad block processing capability test methods of the flash translation layer.

[0009] By the present application, by analyzing the error injection instruction submitted by the user, the target error and the error injection position and the error trigger condition are obtained, when performing the target access operation on the current data block, it is determined that the trigger condition is met, the target error is injected into the solid state disk based on the error injection position, the bad block generated in the data access operation process is simulated dynamically, the remapping operation of the flash translation layer after the target error injection is monitored, and the remapping block count is checked, and compared with the expected remapping operation result and the remapping block count, and the bad block processing capability test result of the flash translation layer is generated, so that the technical problems that the generated bad block in the use process cannot be dynamically simulated, and the real-time response capability of the FTL cannot be verified can be solved, and the technical effects that the real bad block scene is simulated through the trigger condition and the target error, and the bad block processing capability of the FTL is tested in time are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0011] Figure 1 A flowchart of a bad block processing capability test method of a flash translation layer provided by an embodiment of the present application is shown in the figure.

[0012] Figure 2 Another flowchart of a bad block processing capability test method of a flash translation layer provided by an embodiment of the present application is shown in the figure.

[0013] Figure 3 An example diagram of the content of the standardized command set defined by the serial terminal provided by an embodiment of the present application is shown in the figure.

[0014] Figure 4 An example diagram of the content of the NVMe CLI management command set provided by an embodiment of the present application is shown in the figure.

[0015] Figure 5 A flowchart of error injection command analysis provided by an embodiment of the present application is shown in the figure.

[0016] Figure 6 An example diagram of the error injection position in the read-write-erase operation provided by an embodiment of the present application is shown in the figure.

[0017] Figure 7 An example diagram of dynamically triggering the error trigger condition provided by an embodiment of the present application is shown in the figure.

[0018] Figure 8A logic example diagram of a bad block handling capability test of a flash memory translation layer provided by an embodiment of the present invention;

[0019] Figure 9 A schematic structural diagram of a device for testing the bad block processing capability of a flash memory translation layer provided by an embodiment of the present invention;

[0020] Figure 10 A schematic diagram of the hardware structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0022] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0023] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] Existing testing methods for verifying the bad block handling capabilities of FTLs have the following problems: The test scenarios are limited: Traditional testing relies on passive monitoring of Self-Monitoring, Analysis, and Reporting Technology (SMART) parameters and cannot actively simulate bad block generation during different operation stages (read, write, and erase), resulting in insufficient test coverage. Existing technologies artificially create bad blocks through high-temperature aging, high-voltage writing, or overclocking erasure, which is inefficient and highly destructive, making repeatable testing impossible. Manufacturer-specific tools only support specific master controllers, while general-purpose tools (such as the open-source benchmark tool Flexible I / O Tester (FIO)) lack sophisticated error injection capabilities and have poor platform compatibility.

[0025] According to the embodiment of the present application, a method for testing the bad block processing capability of a flash translation layer is provided. It should be noted that the steps shown in the flowchart can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0026] In the present embodiment, a method for testing the bad block processing capability of a flash translation layer is provided, which can be used in a computer device, Figure 1 is a flowchart of the method for testing the bad block processing capability of a flash translation layer according to the embodiment of the present application, as shown in the figure, the flow includes the following steps: Figure 1

[0027] In step S101, a user-submitted error injection instruction is obtained.

[0028] The error injection instruction at least includes a target error causing a bad block, an injection position of the target error, and an error triggering condition, and the target error is an error injected for a target access operation.

[0029] The present embodiment does not limit the way of obtaining the error injection instruction, including but not limited to receiving the error injection instruction through the management command set of the NVMe (Non-Volatile Memory Express: a high-speed communication protocol for SSD, optimizing flash access performance) protocol, and analyzing the command result through the error injection module to extract the error injection parameters, or receiving the error injection instruction through an independent management channel, such as a system management bus, a debugging interface, and a network interface, etc., which are only examples; wherein the error injection instruction at least includes a target error for a target access operation causing a bad block, such as a target data block marked as a bad block for a write operation, a data packet lost during data reading, etc., which are only examples, and also includes an injection position of the target error (the error can be accurately injected into the target position to test specific functions) and an error triggering condition, wherein the error triggering condition can include an operation number threshold for the target access operation, and when the operation number threshold is reached, the target error is injected into the corresponding position.

[0030] In step S102, the error injection instruction is analyzed, and when the target access operation is performed on the current data block and it is determined that the error triggering condition is met, the target error is injected into the solid state disk based on the injection position of the target error.

[0031] ​The embodiment of the present application can analyze the obtained error injection instruction to obtain the error injection parameter in the error injection instruction, such as analyzing the operation code field of the instruction header to determine whether it is an error injection instruction, extracting the target operation defined in the instruction (such as marking the target data block as a bad block), analyzing the injection position corresponding to the target error, and analyzing the error trigger condition (i.e. operation number threshold) dynamically adjusted by the user based on the real-time load state (such as queue depth and cache occupancy rate), balancing the randomness and controllability of the test, and avoiding system crash caused by excessive testing.

[0032] The embodiment of the present application performs access operations (including write, read and erase operations) on data blocks in a solid state disk, and can monitor whether the error trigger condition is met in real time when performing access operations on all data blocks. When performing a target access operation on a current data block and determining that the error trigger condition is met (such as when performing a write operation on the current data block, it is determined that the number of write operations has reached the preset operation number threshold), the target error can be injected into the solid state disk based on the injection position of the target error, such as the target error being to mark the data block as a bad block. The current data block can be marked as a bad block, so that the FLT performs remapping operation based on the injected error, which can avoid physical damage to the flash memory particles and reduce the cost of single disk testing.

[0033] Step S103, monitoring the remapping operation of the flash translation layer after the target error is injected and checking the remapping block count.

[0034] The embodiment of the present application can add remapping related attributes (number of remapping blocks, remapping address list) in the NVMe SMART log. After each mapping operation, the SMART log is updated and the cache is refreshed, and the remapping table is obtained to calculate the number of changes from logical address to physical address, count the number of bad block markers and the number of spare block allocations, which are only examples.

[0035] Step S104, comparing the remapping operation result and the remapping block count of the monitored flash translation layer after the target error is injected with the expected remapping operation result and the remapping block count, to generate the bad block handling capability test result of the flash translation layer.

[0036] The embodiment of the present application can compare the remapping operation result and the remapping block count of the monitored flash translation layer after the target error is injected with the expected remapping operation result and the remapping block count, such as the number of changes from logical address to physical address being consistent with the hardware counter, and the counted number of bad block markers and the number of spare block allocations being equal to a certain error range of the remapping block count. If the monitored result is consistent with the expected result, it is determined that the bad block handling capability of the flash translation layer is reliable, and the bad block handling capability test result of the flash translation layer is generated.

[0037] The application provides a bad block processing capability test method of a flash translation layer, acquires a user-submitted error injection instruction, analyzes the error injection instruction, executes a target access operation on a current data block, and determines whether a target error trigger condition is met; when the target error trigger condition is met, the target error is injected into a solid state disk based on an injection position of the target error, so that a bad block generated in a data block access operation process is dynamically simulated; a remapping operation of the flash translation layer after the target error is injected and a remapping block count are monitored; a remapping operation result and a remapping block count of the flash translation layer after the target error is injected are compared with expected remapping operation results and remapping block counts, a bad block processing capability test result of the flash translation layer is generated, real-time response capability of the FTL is verified, a real bad block scene is simulated through a trigger condition and a target error, and the bad block processing capability of the FTL is tested in a timely manner.

[0038] In the embodiment, a data error correction method based on a low-density parity-check code is provided, which can be used for a computer device, Figure 2 A flowchart of the data error correction method based on the low-density parity-check code according to the embodiment of the application is shown in Figure 2 The flowchart includes the following steps:

[0039] In step S201, a user-submitted error injection instruction is acquired.

[0040] The error injection instruction at least includes a target error causing a bad block, an injection position of the target error, and an error trigger condition, and the target error is an error injected for a target access operation.

[0041] Specifically, the step S201 includes the following steps.

[0042] In step S2011, a user-submitted error injection instruction is acquired through a serial terminal, or an original error injection instruction submitted by a user through a command line interface tool is acquired, and a mapping table of the flash translation layer is analyzed to convert the injection position of the target error in the original error injection instruction into a physical block address, so that the error injection instruction is obtained.

[0043] The embodiments of the present application consider that different modes are applied for command transmission and reception in different product development stages. For example, when the SSD hardware or master chip is in the prototype development stage and the operating system and driver are not fully ready, the command transmission and reception can be performed through the serial port. When the SSD is integrated into the system as a complete product and there is complete operating system and driver support, the serial port can be cancelled. When the serial port communication has many shortcomings, the NVMe CLI tool can be used for command transmission and reception. Therefore, the present application can transmit and receive error injection commands through the serial terminal and can also transmit and receive error injection commands through the command line interface tool (taking the command line interface (CLI) tool as an example). In an optional implementation, before obtaining the error injection instruction submitted by the user, command authority verification can be added to verify whether the user is an authorized test user, prevent unauthorized operation, and implement command execution log auditing function to judge whether the execution process of the error injection instruction is normal and safe, which is only an example.

[0044] As shown in Figure 3 , the embodiments of the present application define a standardized command set for the UART interface of the master development board, including the target error, operation type, error type, injection position of the target error and error trigger condition (trigger mode) in the error injection instruction. Figure 4 As shown in , for the NVMe CLI tool, the NVMe management command set is extended and the Error Injection command is newly added. Because the CLI tool uses a logical address in the flash device and the data is actually stored in the flash cell corresponding to the physical address, after obtaining the original error injection instruction submitted by the user through the CLI tool, the mapping table of the flash conversion layer can be parsed to convert the injection position of the target error in the original error injection instruction into a physical address to obtain the error injection instruction. It is ensured that the actual position of data storage can be accurately found, the error can be accurately injected into the corresponding position, the FTL can normally perform remapping, bad block management and other operations, and the bad block processing capability of the FTL can be effectively verified.

[0045] Figure 5As shown, the user sends an error injection command, and it can be determined whether the error injection command is submitted by the user through a serial terminal (for example, connected to the SSD main control board through UART or TTL) or through the NVMe CLI tool (for example, calling the nvme bb-inject-error command). If it is determined that the error injection command is sent through the serial terminal, then after the error injection command is parsed, the target error can be injected directly when the error trigger condition is currently monitored to be met. If it is determined that the error injection command is sent through the CLI tool, then in the process of parsing the error injection command, the injection position of the parsed target error needs to be converted into a physical address in order to accurately inject the target error. Subsequently, when the error trigger condition is currently monitored to be met, the target error is injected. This is just an example.

[0046] The present invention implements the injection of underlying hardware errors through serial port debugging commands, adapts to the private protocols of various master controllers, and can extend the NVMe CLI command set. It supports injecting errors at logical addresses and automatically maps them to physical addresses. It is compatible with the standardized NVMe protocol, achieves cross-platform compatibility, one-time development, multi-platform applicability, and shortens the test development cycle.

[0047] Furthermore, the target error includes injecting errors at different stages of the write operation, read operation, and / or erase operation into the physical layer, logical layer, and flash translation layer of the solid-state drive, respectively.

[0048] The embodiment of the present invention defines three levels of error types: physical layer (NAND flash memory), logical layer (master control logic) and FTL layer (firmware layer), covering the full-link failure scenario from hardware to firmware, and injecting bad block errors in sequence during the read, write and erase operations of the solid-state drive to fully verify the bad block management capability of FTK.

[0049] In a specific embodiment, Figure 6 As shown, the error set for the write operation in the physical layer of the solid-state drive is to inject a NAND Program Fail error during the data programming (Program) phase; the error set for the read operation is to simulate charge leakage to cause data bit flipping; the error set for the transmission channel in the logical layer is to inject data packet loss, and the error set for the Error-Correcting Code (ECC) check is to destroy the ECC check code of the data page, triggering an uncorrectable error; the error set for the garbage collection (GC) mechanism in the FTL layer is to force the migration of bad block data during the GC process; and the error set for the mapping table damage is to tamper with the logical address mapping entry of the logical-to-physical mapping table (L2P). This is just an example. For detailed error settings, please refer toFigure 6 In this regard, no further elaboration is made.

[0050] Further, the target error is injected into the solid state disk, including: before writing the current data block, marking the current data block as a bad block, and / or, in writing the current data block, controlling the state register to return a data write failure instruction, and / or, after writing the current data block, modifying the error correction code of the user data, and / or, when performing a data read operation on the current data block, destroying the error correction code of the data page, and / or, when performing a metadata read operation on the current data block, mapping the logical address to an invalid physical address, and / or, before erasing the current data block, erasing the marked bad block, and / or, in erasing the current data block, modifying the timer configuration of the flash controller to make the operation timeout.

[0051] The embodiments of the present application set different error injections for different stages of the write operation, such as tampering with the bad block table (BBT) before writing the current data block, marking the current data block as a bad block, such as modifying the out-of-band (OOB) area of the BBT, so that the FTL triggers remapping before writing; in writing the current data block, simulating NAND state register errors, such as returning a data write failure (0xXX (NAND ProgramFail)) status code when the master sends a Program instruction, forcing the write to be aborted and starting the standby fast replacement; after writing the current data block, modifying the ECC check bit of the user data, such as flipping specific bits (Bit Flip) to destroy the ECC after the data write is completed, simulating data damage caused by charge leakage, only as an example.

[0052] The embodiments of the present application set different error injections for reading operations, such as injecting uncorrectable ECC errors when performing a data read operation on the current data block, such as destroying the ECC check code of the data page, so that the error correction engine (such as LDPC) of the master cannot recover the data, triggering the data migration process of the FTL; when performing a metadata read on the current data block, destroying the L2P mapping table entry of the FTL, such as mapping the logical address 0x2000 to the invalid physical address 0xFFFF, verifying the metadata recovery mechanism (such as backup table switching) of the FTL, only as an example.

[0053] The embodiment of the present application sets different error injections for the erase operation, such as forcibly erasing the marked bad block before erasing the current data block, such as sending an Erase instruction to the bad block, detecting the abnormal processing logic (such as refusing to erase and recording logs) of the FTL; in the current data block erasing, an erase timeout error can be returned, such as modifying the timer configuration of the NAND controller to make the erase operation timeout (such as more than 3ms), simulating the physical failure caused by unstable voltage, only as an example, the specific target error type or the access operation targeted can be updated according to the actual application, and the error is updated based on the error found in the actual application, and is not limited.

[0054] Development stage: verify the firmware exception handling logic through code-level error injection (such as memory overflow, interrupt loss); mass production stage: test the multi-core cooperative error correction efficiency through physical layer error simulation (such as erase timeout, ECC check failure); compatibility test: support automatic adaptation and verification of cross-vendor master control (such as different FTL algorithms), realize the automatic test framework in the whole life cycle.

[0055] The present application covers the bad block processing logic of FTL in each stage of read, write and erase, exposes design defects in advance, and realizes the bad block processing ability of FTL in the whole process.

[0056] Step S202, the error injection instruction is parsed, when the target access operation is performed on the current data block and it is determined that the error trigger condition is met, the target error is injected into the solid state disk based on the injection position of the target error.

[0057] The error trigger condition includes a target access operation number threshold and a trigger probability.

[0058] Further, when the target access operation is performed on the current data block, the recorded target access operation number is increased; it is judged whether the increased target operation access number reaches the target access operation number threshold; if the increased target access operation number reaches the target access operation number threshold, the target error is injected into the solid state disk based on the injection position of the target error.

[0059] The embodiment of the present application receives an error trigger condition input by a user, analyzes a target access operation number threshold value in the error trigger condition, which is dynamically adjusted by the user based on a real-time load state, and then increases the recorded target access operation number when performing a target access operation on a current data block, for example, by adding one to the recorded target access operation number, and judges whether the increased target access operation number reaches the target access operation number threshold value submitted by the user. If the increased target access operation number reaches the target access operation number threshold value, the target error is injected into the solid state disk based on the injection position of the target error, for example, the target error is injected into the solid state disk based on the injection position of the target error, and the data block is marked as a bad block in the target error injection position. In the pre-write stage, when performing a pre-write operation on the current data block, the target access operation number in the pre-write stage is added by one, and it is judged whether the target access operation number after the addition reaches the target access operation number threshold value. If the target access operation number threshold value is reached, the current data block is marked as a bad block in the pre-write stage to verify the remapping operation capability of the FTL, and the recorded target access operation number can be cleared to accurately verify the effect of randomly triggering a bad block.

[0060] In an optional embodiment, the user can dynamically adjust the target access operation number threshold value and the trigger probability based on the real-time load state, but the user cannot obtain the current load state in real time, and the target access operation number threshold value and the trigger probability are adjusted at different times. Therefore, the future load state can be predicted based on the historical load state data of the solid state disk, and the target access operation number threshold value and the trigger probability can be dynamically adjusted based on the predicted future load state and the target access operation number threshold value and the trigger probability input by the user, so that the target access operation number threshold value and the trigger probability are adjusted based on the target access operation number threshold value and the trigger probability, and the adjusted target access operation number threshold value and the trigger probability can be prompted to the user, so that the user can clearly understand the actual process of the current error injection, and the failure condition in the actual use scenario can be simulated to provide more comprehensive and accurate evaluation for the FTL remapping capability test.

[0061] The error trigger condition designed in the present application includes a target access operation number threshold value, and the target error is injected into the solid state disk when the currently recorded target access operation number reaches the target access operation threshold value, thereby realizing a dynamic trigger mechanism and simulating the effect of randomly generating a bad block in an actual application.

[0062] In an optional embodiment, a random number is generated when performing a target access operation on a current data block, and it is judged whether the random number is less than the trigger probability. If the random number is less than the trigger probability, the target error is injected into the solid state disk based on the injection position of the target error.

[0063] The error triggering condition of the embodiment of the application can also include a triggering probability. The user can also adjust the triggering probability based on the real-time load state and can also trigger the error randomly based on a Poisson distribution model. When the error triggering condition includes the triggering probability (for example, a random probability of 20%), a random number of 0-1 can be generated when the target access operation is performed on the current data block, for example, 0.1. Then, it can be judged whether the generated random number is less than the triggering probability. If the random number is less than the triggering probability, that is, 0.1 is less than 0.2, the target error can be injected into the solid state disk based on the injection position of the target error. In an alternative embodiment, the embodiment of the application can use the adaptive probability adjustment algorithm of the system response to dynamically optimize the error injection strategy according to the FTL remapping efficiency and can support the combined use of multiple probability distribution models to realize the conditional probability chain and the probability superposition calculation.

[0064] In an alternative embodiment, if the random number is not less than the triggering probability, the recorded target access operation number is increased, and the step of judging whether the increased target access operation number reaches the target access operation number threshold is returned.

[0065] The embodiment of the application generates a random number of 0-1, for example, 0.3, when the target access operation is performed on the current data block. If the generated random number is greater than the triggering probability, the target access operation number threshold can be randomly or by default generated, and the current recorded target access operation number is incremented by one. It is judged whether the incremented target access operation number reaches the target access operation number threshold. If the target access operation number threshold is reached, the target error can be injected into the solid state disk. In the error triggering condition, the target access operation number threshold and the error triggering probability can be included. The error can be randomly injected in the solid state disk through the error triggering probability. When the generated random number is not less than the triggering probability, the current recorded target access operation number can be incremented by one, and it is judged whether the incremented target access operation number reaches the target access operation number threshold. If the incremented target access operation number reaches the target access operation number threshold, the target error can be injected into the solid state disk. If the incremented target access operation number does not reach the target access operation number threshold, the target access operation state is continuously monitored. Only as an example, the target error can be randomly injected based on the target access operation number threshold, and the target error can be injected through the random triggering probability, which is not limited.

[0066] In specific embodiments, for example, Figure 7As shown, the error trigger condition submitted by the user is received, it is judged whether the error trigger condition is a trigger probability, if the error trigger condition is a trigger probability, a random number can be generated when performing the target access operation on the current data block, and it is judged whether the generated random number is less than the trigger probability, if the generated random number is less than the trigger probability, the target error can be injected into the solid state disk based on the injection position of the target error; if the generated random number is not less than the trigger probability, the target access operation number recorded at present is incremented by one, and it is judged whether the target access operation number after the incrementing by one reaches a target access operation number threshold, if the target access operation number after the incrementing by one reaches the target access operation number threshold, the target error can be injected into the solid state disk based on the injection position of the target error, if the target access operation number after the incrementing by one does not reach the target access operation number threshold, no error injection processing is performed, the target access operation state is continuously monitored, and details are described in the above embodiment, which will not be repeated here, and the error trigger condition combined with the trigger probability and the target error operation number threshold is realized, and a complex fault scenario is simulated.

[0067] The present application supports the trigger probability and / or the target access operation number threshold to realize the random injection of the target error into the solid state disk, and balances the randomness and controllability of the bad block processing capability.

[0068] Step S203, monitoring the remapping operation of the flash translation layer after the target error is injected and checking the remapping block count.

[0069] Specifically, the above step S203 includes:

[0070] Step S2031, analyzing the SMART log, monitoring the number of spare blocks and the number of media errors.

[0071] Step S2032, obtaining a logical address to physical address mapping table, and comparing the address mapping changes before and after the error injection.

[0072] Step S2033, using a data block copying tool and a hash check tool, comparing the original data and the data after remapping to perform data consistency check.

[0073] Step S2034, checking the remapping block count of the flash translation layer after the remapping operation.

[0074] SMART is a health monitoring system built into the solid state disk, including the number of spare blocks and media errors and other key information, used to predict hard disk failure and record health parameters, which can parse nvme smart-log output, track the number of reallocated blocks (Reallocated_Block_Count) and media errors (Media_Errors), and monitor the changes in SMART parameters in real time or periodically; The logical address to physical address mapping table can also be obtained by the nvme get-log command, and the address mapping changes before and after error injection are compared; The original data and remapped data can also be compared using the data block copy tool (Disk Dump, dd) and the hash check tool (Message-Digest Algorithm 5 Checksum, md5sum) to verify data consistency and ensure that there are no silent errors, such as Figure 8 As shown, the remapping block count of the flash translation layer after the remapping operation can be obtained.

[0075] In step S204, the remapping operation result and the remapping block count of the monitored flash translation layer after the target error injection are compared with the expected remapping operation result and the remapping block count, and the bad block handling capability test result of the flash translation layer is generated.

[0076] The present application can compare the remapping operation result and the remapping block count of the monitored flash translation layer after the target error injection with the expected remapping operation result and the remapping block count, and generate the bad block handling capability test result of the flash translation layer. The embodiment of the present application can design a real-time monitoring interface to display the probability model parameters, error injection effect and bad block handling capability test result of the flash translation layer, so that the user can intuitively and clearly understand the bad block handling capability test result of the flash translation layer. For details, please refer to the above embodiment, which will not be repeated here.

[0077] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better implementation.

[0078] In this embodiment, a bad block handling capability test device for a flash translation layer is also provided, which is used to implement the above embodiments and preferred embodiments, which have been described. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0079] The present embodiment provides a bad block handling capability test device for a flash translation layer, which isFigure 9 As shown, the method comprises: an error injection instruction obtaining module 901, configured to obtain an error injection instruction submitted by a user, the error injection instruction comprising at least a target error causing a bad block, an injection position of the target error, and an error trigger condition, the target error being an error injected for a target access operation;

[0080] an instruction analysis module 902, configured to analyze the error injection instruction, and when a target access operation is performed on a current data block and it is determined that the error trigger condition is met, inject the target error into the solid state disk based on the injection position of the target error;

[0081] a remapping operation monitoring module 903, configured to monitor a remapping operation of the flash translation layer after the target error is injected, and check a remapping block count;

[0082] a bad block processing capability test module 904, configured to compare the remapping operation result and the remapping block count of the flash translation layer after the target error is injected, with an expected remapping operation result and remapping block count, and generate a bad block processing capability test result of the flash translation layer.

[0083] In an optional implementation, the error injection instruction obtaining module 901 comprises: an instruction analysis unit, configured to obtain an error injection instruction submitted by a user through a serial terminal, or obtain an original error injection instruction submitted by a user through a command line interface tool, and analyze a mapping table of the flash translation layer to convert the injection position of the target error in the original error injection instruction into a physical block address, to obtain the error injection instruction.

[0084] In an optional implementation, the error trigger condition comprises a target access operation number threshold and a trigger probability, and the instruction analysis module 902 comprises: a number increasing unit, configured to increase a recorded target access operation number when a target access operation is performed on a current data block; a number judgment unit, configured to judge whether the increased target access operation number reaches the target access operation number threshold; an error injection unit, configured to inject the target error into the solid state disk based on the injection position of the target error if the increased target access operation number reaches the target access operation number threshold, or a random number generation unit, configured to generate a random number when a target access operation is performed on a current data block; a random number judgment unit, configured to judge whether the random number is less than the trigger probability; and an error injection unit, configured to inject the target error into the solid state disk based on the injection position of the target error if the random number is less than the trigger probability.

[0085] In an optional implementation, the instruction parsing module 902 further includes a number judgment returning unit configured to, if the random number is not less than the trigger probability, increase the recorded target access operation number, and return a step of judging whether the target access operation number after the increase reaches the target access operation number threshold.

[0086] In an optional implementation, the target error includes injecting different phase errors for a write operation and / or a read operation and / or an erase operation in a physical layer, a logical layer and a flash translation layer in the solid state disk respectively.

[0087] In an optional implementation, the instruction parsing module 902 includes a bad block marking unit configured to mark the current data block as a bad block before writing the current data block, and / or a data write failure returning unit configured to control the state register to return a data write failure instruction in the writing of the current data block, and / or an error correction code modifying unit configured to modify an error correction code of the user data after the writing of the current data block, and / or an error correction code destroying unit configured to destroy the error correction code of the data page when performing a data read operation on the current data block, and / or an address invalid mapping unit configured to map the logical address to an invalid physical address when performing a metadata read operation on the current data block, and / or a bad block erasing unit configured to erase the marked bad block before erasing the current data block, and / or a timing modifying unit configured to modify a timer configuration of the flash controller to cause an operation timeout in the erasing of the current data block.

[0088] In an optional implementation, the remapping operation monitoring module 903 includes a log parsing unit configured to parse a SMART log to monitor a number of spare blocks used and a number of media errors, an address mapping change obtaining unit configured to obtain a logical address to physical address mapping table and compare address mapping changes before and after error injection, a data comparison unit configured to compare original data and remapped data using a data block duplication tool and a hash check tool to perform data consistency verification, and a mapping block counting unit configured to check a remapping block count of the flash translation layer after the remapping operation.

[0089] The features of the embodiments of the device for testing the bad block processing capability of the flash translation layer can be seen from the related descriptions of the embodiments of the method for testing the bad block processing capability of the flash translation layer, which will not be repeated here.

[0090] The embodiments of the present application also provide an electronic device, as shown in the figure, including a memory 10 and a processor 20, the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-mentioned embodiments of the method for testing the bad block processing capability of the flash translation layer. Figure 10

[0091] ​The embodiment of the present application also provides a computer readable storage medium, which stores a computer program, and the computer program is arranged to execute the steps in any of the above-mentioned flash translation layer bad block processing capability test method embodiments when running.

[0092] In an example embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0093] The embodiment of the present application also provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned flash translation layer bad block processing capability test method embodiments.

[0094] The embodiment of the present application also provides another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned flash translation layer bad block processing capability test method embodiments.

[0095] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0096] The above describes in detail the flash translation layer bad block processing capability test method, device, equipment and medium provided by the present application. The principles and implementation manners of the present application are described by applying specific examples in this paper, and the above example description is only used to help understand the method and core idea of the present application. It should be pointed out that, for ordinary skilled person in the technical field, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for testing the bad block processing capability of a flash memory translation layer, characterized in that: The method comprises: Obtaining an error injection instruction submitted by a user, the error injection instruction including at least a target error that causes a bad block, an injection location of the target error, and an error triggering condition, wherein the target error is an error injected into a target access operation; parsing the error injection instruction, and when performing a target access operation on the current data block and determining that the error triggering condition is satisfied, injecting a target error into the solid-state drive based on an injection position of the target error; Monitor the flash translation layer's remapping operations after target error injection and check the remapped block count; The remapping operation result and remapping block count of the monitored flash translation layer after the target error injection are compared with the expected remapping operation result and remapping block count to generate a bad block handling capability test result of the flash translation layer.

2. The method according to claim 1, characterized in that The obtaining of the error injection instruction submitted by the user includes: Obtain the error injection instruction submitted by the user through the serial port terminal, or obtain the original error injection instruction submitted by the user through the command line interface tool, and parse the mapping table of the flash translation layer, convert the injection position of the target error in the original error injection instruction into a physical block address to obtain the error injection instruction.

3. The method according to claim 1, characterized in that The error triggering condition includes a target access operation number threshold and a triggering probability. When the target access operation is performed on the current data block and it is determined that the error triggering condition is satisfied, the target error is injected into the solid-state drive based on the injection position of the target error, including: When a target access operation is performed on the current data block, the number of recorded target access operations is increased; Determine whether the increased target operation access number reaches the target access operation number threshold; If the increased target access operation number reaches the target access operation number threshold, the target error is injected into the solid-state drive based on the injection position of the target error, or, When performing a target access operation on the current data block, a random number is generated; Determining whether the random number is less than the trigger probability; If the random number is less than the trigger probability, the target error is injected into the solid state drive based on the injection position of the target error.

4. The method according to claim 3, characterized in that The method further comprises: If the random number is not less than the trigger probability, the recorded number of target access operations is increased, and the process returns to the step of determining whether the increased number of target access operations reaches the target access operation number threshold.

5. The method according to claim 1, wherein The target errors include injecting errors at different stages for write operations, read operations, and / or erase operations into the physical layer, the logical layer, and the flash translation layer in the solid state drive.

6. The method according to claim 5, characterized in that Inject targeted errors into SSDs, including: Before writing to the current data block, mark the current data block as a bad block, and / or, When writing the current data block, the control status register returns a data write failure instruction, and / or, After writing the current data block, modify the error correction code of the user data, and / or, When performing a data read operation on the current data block, the error correction code of the data page is destroyed, and / or When performing a metadata read operation on the current data block, a logical address is mapped to an invalid physical address, and / or, Before erasing the current data block, erase the marked bad blocks, and / or, During erasing of the current data block, the timer configuration of the flash memory controller is modified to cause the operation to time out.

7. The method according to claim 1, characterized in that The monitoring of the flash translation layer's remapping operation after target error injection and checking the remapping block count include: Parse SMART logs to monitor spare block usage and media errors; Obtain the logical address to physical address mapping table and compare the address mapping changes before and after the error injection; Use data block replication tools and hash verification tools to compare the original data and the remapped data to verify data consistency; A remap block count of the flash translation layer after a remap operation is checked.

8. A device for testing the bad block processing capability of a flash memory translation layer, characterized in that: The device comprises: An error injection instruction acquisition module is used to acquire an error injection instruction submitted by a user, wherein the error injection instruction includes at least a target error that causes a bad block, an injection location of the target error, and an error triggering condition, wherein the target error is an error injected into a target access operation; an instruction parsing module, configured to parse the error injection instruction and, when performing a target access operation on a current data block and determining that the error triggering condition is satisfied, inject a target error into the solid-state drive based on an injection position of the target error; a remapping operation monitoring module, configured to monitor the remapping operation of the flash translation layer after target error injection and check the remapping block count; The bad block handling capability test module is used to compare the remapping operation results and remapping block counts of the monitored flash translation layer after the target error is injected with the expected remapping operation results and remapping block counts, and generate a bad block handling capability test result of the flash translation layer.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the bad block processing capability testing method of the flash memory conversion layer according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the bad block processing capability testing method of the flash translation layer according to any one of claims 1 to 7.

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