Preparation method of semiconductor device
By forming a multi-layer TEOS and interlayer dielectric layer structure on the surface of the copper interconnect layer, etching to form contact holes and removing the second TEOS layer, the problem of copper migration defects is solved and the device performance and yield are improved.
Patent Information
- Application Number
- CN202510779436.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
In the copper interconnect fabrication process, copper migration defects can easily lead to device performance degradation, which is difficult to effectively solve with existing technologies.
After forming a barrier layer on the surface of the metal interconnection layer, a first TEOS layer, an interlayer dielectric layer, and a second TEOS layer are deposited in sequence. Contact holes are formed by etching to change the film layer structure on the surface of the metal interconnection layer. After the contact holes are formed, the second TEOS layer is removed, and the first TEOS layer and the interlayer dielectric layer are used as the final interlayer dielectric layer to improve the stress distribution of the metal interconnection structure.
Without increasing the height of the device, the copper migration defect is effectively improved, and the performance and yield of the device are improved.
Smart Images
Figure CN120809669A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device. BACKGROUND
[0002] With the integrated circuit entering the era of very large scale integration, copper has become the main interconnection metal of integrated circuit due to its smaller resistivity, good anti-electric migration performance and anti-stress migration ability. However, in the copper interconnection preparation process, copper migration defects are prone to occur due to the introduction of thermal stress and mechanical stress in subsequent thin film process and etching process, which seriously affects the performance of the device. SUMMARY
[0003] The present application provides a preparation method of a semiconductor device, which can solve the problem that copper migration defects are prone to occur in the traditional copper interconnection preparation process, thereby seriously affecting the performance of the device.
[0004] The present application provides a preparation method of a semiconductor device, which comprises:
[0005] A semiconductor structure is provided, wherein a metal interconnection layer is formed in the semiconductor structure, and a barrier layer is formed on the semiconductor structure;
[0006] A first TEOS layer is formed, which covers the barrier layer;
[0007] An interlayer dielectric layer is formed, which covers the first TEOS layer;
[0008] A second TEOS layer is formed, which covers the interlayer dielectric layer;
[0009] The second TEOS layer, the interlayer dielectric layer, the first TEOS layer and the barrier layer are etched to form a plurality of contact holes, wherein part of the contact holes open the semiconductor structure to expose the metal interconnection layer;
[0010] The second TEOS layer is removed;
[0011] A metal material layer is formed, which fills the contact holes.
[0012] Optionally, in the preparation method of the semiconductor device, the second TEOS layer is formed by using a chemical vapor deposition process.
[0013] Optionally, in the preparation method of the semiconductor device, the thickness of the second TEOS layer is 1000 angstroms to 3000 angstroms.
[0014] Optionally, in the method for manufacturing the semiconductor device, the first TEOS layer is formed by a chemical vapor deposition process.
[0015] Optionally, in the method for manufacturing the semiconductor device, the first TEOS layer has a thickness of 3000 angstroms to 7000 angstroms.
[0016] Optionally, in the method for manufacturing the semiconductor device, the interlayer dielectric layer is made of silicon nitride.
[0017] Optionally, in the method for manufacturing the semiconductor device, the interlayer dielectric layer has a thickness of 5000 angstroms to 8000 angstroms.
[0018] The technical scheme of the present application has at least the following advantages:
[0019] The present application provides a method for manufacturing a semiconductor device. After forming a barrier layer on the surface of a metal interconnection layer, a first TEOS layer, an interlayer dielectric layer and a second TEOS layer are sequentially deposited. The first TEOS layer, the interlayer dielectric layer and the second TEOS layer are used as the final interlayer dielectric layer of the metal interconnection structure. Then, the first TEOS layer, the interlayer dielectric layer and the second TEOS layer are etched to form a contact hole. By introducing the second TEOS layer on the basis of the first TEOS layer and the interlayer dielectric layer, the film layer structure of the surface of the metal interconnection layer can be changed in the process of etching to form the contact hole, so that the stress of the surface of the metal interconnection layer can be changed in the process of forming the contact hole. After the contact hole is formed, the second TEOS layer is removed. In this way, the migration defect of the metal (copper) can be effectively improved without increasing the height of the device, so that the performance of the device is improved and the yield of the device is increased. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical scheme in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0021] Figure 1 is a flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present application;
[0022] Figures 2-5 is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present application;
[0023] In the drawings, the reference signs are explained as follows:
[0024] 10 - semiconductor structure, 11 - metal interconnect layer, 12 - barrier layer, 13 - first TEOS layer, 14 - interlayer dielectric layer, 15 - second TEOS layer, 16 - contact hole, 17 - metal material layer. DETAILED DESCRIPTION
[0025] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.
[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0027] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0029] The embodiment of the present application provides a preparation method of a semiconductor device, referring to Figure 1 , Figure 1 is a flowchart of the preparation method of the semiconductor device of the embodiment of the present application, and the preparation method of the semiconductor device comprises:
[0030] First, step S1 is performed: referring to Figure 2 , Figure 2is a schematic view of a semiconductor structure after forming a second TEOS layer according to an embodiment of the present application, providing a semiconductor structure 10, wherein a metal interconnection layer 11 is formed in the semiconductor structure 10, and a barrier layer 12 is formed on the semiconductor structure 11.
[0031] In the embodiment, the barrier layer 12 is made of NDC (nitrogen-doped silicon carbide).
[0032] Further, in the embodiment, the metal interconnection layer 11 is made of copper.
[0033] It is worth noting that the semiconductor structure 10 can be a semiconductor structure prepared by a front-end process of a conventional CMOS device or the like, and the present application does not make any limitation on specific film layers of the semiconductor structure 10, as long as the semiconductor structure 10 has a metal interconnection layer 11 formed near a surface thereof.
[0034] Then, step S2 is performed: continuing to refer to Figure 2 , a first TEOS layer 13 is formed, covering the barrier layer 12.
[0035] Preferably, the first TEOS layer 13 is formed by a chemical vapor deposition process.
[0036] Preferably, the first TEOS layer 13 has a thickness of 3000 angstroms to 7000 angstroms.
[0037] Next, step S3 is performed: continuing to refer to Figure 2 , an interlayer dielectric layer 14 is formed, covering the first TEOS layer 13.
[0038] In the embodiment, the interlayer dielectric layer 14 is made of silicon nitride.
[0039] Preferably, the interlayer dielectric layer 14 has a thickness of 5000 angstroms to 8000 angstroms.
[0040] In the embodiment, the interlayer dielectric layer 14 serves as a passivation protection layer.
[0041] Further, step S4 is performed: continuing to refer to Figure 2 , a second TEOS layer 15 is formed, covering the interlayer dielectric layer 14.
[0042] Preferably, the second TEOS layer 15 is formed by a chemical vapor deposition process.
[0043] Preferably, the second TEOS layer 15 has a thickness of 1000 angstroms to 3000 angstroms.
[0044] Next, step S5 is performed: referring to Figure 3 , Figure 3 is a schematic diagram of a semiconductor structure after forming a plurality of contact holes according to an embodiment of the present application. First, a photoresist layer (not shown) is formed on the second TEOS layer 15. Then, a contact hole pattern is defined on the photoresist layer by a photolithography process to form a patterned photoresist layer. Next, the second TEOS layer 15, the interlayer dielectric layer 14, the first TEOS layer 13 and the barrier layer 12 are etched to form a plurality of contact holes 16 using the patterned photoresist layer as a mask, wherein some of the contact holes 16 open the semiconductor structure 10 to expose the metal interconnection layer 11.
[0045] Further, step S6 is performed: referring to Figure 4 , Figure 4 is a schematic diagram of a semiconductor structure after removing the second TEOS layer according to an embodiment of the present application. The second TEOS layer 15 is removed.
[0046] In this embodiment, the dry etching process is used to remove the second TEOS layer 15.
[0047] In this application, after forming the barrier layer on the surface of the metal interconnection layer, the first TEOS layer, the interlayer dielectric layer and the second TEOS layer are deposited in sequence. The first TEOS layer, the interlayer dielectric layer and the second TEOS layer are used as the final interlayer dielectric layer of the metal interconnection structure. Then, the first TEOS layer, the interlayer dielectric layer and the second TEOS layer are etched to form contact holes. In this application, the second TEOS layer is introduced on the basis of the first TEOS layer and the interlayer dielectric layer, so that the film layer structure on the surface of the metal interconnection layer can be changed during the etching process to form the contact holes, thereby changing the stress on the surface of the metal interconnection layer during the formation of the contact holes. The second TEOS layer is removed after the formation of the contact holes. In this way, the copper migration defect can be effectively improved without increasing the height of the device, thereby improving the performance of the device and increasing the yield of the device.
[0048] Finally, step S7 is performed: referring to Figure 5 , Figure 5 is a schematic diagram of a semiconductor structure after forming a metal material layer according to an embodiment of the present application. The metal material layer 17 is formed to fill the contact holes 16.
[0049] In this embodiment, the metal material layer 17 is made of metal copper.
[0050] Obviously, the above embodiments are merely example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated and it is impossible to enumerate all the embodiments. The changes or variations derived from the above are still within the protection scope of the present application.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: A semiconductor structure is provided, wherein a metal interconnection layer is formed in the semiconductor structure, and a barrier layer is formed on the semiconductor structure; forming a first TEOS layer, wherein the first TEOS layer covers the barrier layer; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the first TEOS layer; forming a second TEOS layer, wherein the second TEOS layer covers the interlayer dielectric layer; Etching the second TEOS layer, the interlayer dielectric layer, the first TEOS layer, and the barrier layer to form a plurality of contact holes, wherein some of the contact holes open the semiconductor structure to expose the metal interconnection layer; removing the second TEOS layer; A metal material layer is formed, wherein the metal material layer fills the contact hole.
2. The method for preparing a semiconductor device according to claim 1, wherein: The second TEOS layer is formed by a chemical vapor deposition process.
3. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the second TEOS layer is 1000 angstroms to 3000 angstroms.
4. The method for preparing a semiconductor device according to claim 1, wherein: The first TEOS layer is formed by a chemical vapor deposition process.
5. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the first TEOS layer is 3000 angstroms to 7000 angstroms.
6. The method for preparing a semiconductor device according to claim 1, wherein: The material of the interlayer dielectric layer is silicon nitride.
7. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the interlayer dielectric layer is 5000 angstroms to 8000 angstroms.