Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method. The packaging structure comprises a substrate; the interconnection structure is bonded on the substrate, the interconnection structure comprises a rewiring layer and a first plastic package layer located on the rewiring layer, the interconnection structure further comprises a chip bridge embedded in the first plastic package layer, the first plastic package layer is exposed out of the surface of the chip bridge, and the surface, exposed out of the chip bridge, of the first plastic package layer is a bonding surface; the first chip is bonded on the bonding surface of the interconnection structure, and the first chip is electrically connected with the rewiring layer and the chip bridge; and the chip structure is bonded on the bonding surface of the interconnection structure at the side part of the first chip, the chip structure is electrically connected with the rewiring layer, and the chip structure is electrically connected with the first chip through a chip bridge. The packaging effect of the packaging structure can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a packaging structure and a packaging method. BACKGROUND

[0002] Conventional chip manufacturing techniques are being pushed to their limits for the size of monolithic chips. However, applications are yearning for the ability to use the latest technology to implement large size integrated circuits, with high speed and small volume interconnections between chips being a great challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to implement interconnections between chips through the Si Bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the current packaging structure is relatively complex in structure. SUMMARY

[0005] Embodiments of the present application solve the problem of providing a packaging structure and a packaging method, which are beneficial to improve the packaging effect of the packaging structure.

[0006] To solve the above problems, the present application provides a packaging structure, comprising: a substrate; an interconnection structure bonded to the substrate, the interconnection structure comprising a redistribution layer and a first plastic encapsulation layer on the redistribution layer, the interconnection structure further comprising a chip bridge embedded in the first plastic encapsulation layer, the first plastic encapsulation layer exposing a surface of the chip bridge, and the surface of the first plastic encapsulation layer exposing the chip bridge being a bonding surface; a first chip bonded to the bonding surface of the interconnection structure, and the first chip being electrically connected to the redistribution layer and the chip bridge; and a chip structure bonded to the bonding surface of the interconnection structure on a side of the first chip, and the chip structure being electrically connected to the redistribution layer, and the chip structure being electrically connected to the first chip through the chip bridge.

[0007] Optionally, on the bonding surface, the first plastic encapsulation layer is flush with the surface of the chip bridge.

[0008] Optionally, the chip bridge penetrates the first plastic encapsulation layer and is electrically connected to the redistribution layer.

[0009] Optionally, the redistribution layer comprises a dielectric layer and an electrical connection structure penetrating the dielectric layer; and the electrical connection structure on a side of the chip bridge further penetrates the first plastic encapsulation layer.

[0010] Optionally, the packaging structure further comprises: a second plastic encapsulation layer on the first plastic encapsulation layer, the second plastic encapsulation layer covering a sidewall of the chip structure, a sidewall of the first chip, and filling between the chip structure and the first chip.

[0011] Optionally, the packaging structure further comprises: a first conductive bump located between the first plastic encapsulation layer and the first chip, and between the first plastic encapsulation layer and the chip structure, and electrically connecting the redistribution layer and the first chip, and electrically connecting the redistribution layer and the chip structure; a second conductive bump located between the chip bridge and the first chip, and between the chip bridge and the chip structure, and electrically connecting the chip bridge and the first chip, and electrically connecting the chip bridge and the chip structure.

[0012] Optionally, the packaging structure further comprises: a first sealing layer filled in the gap between adjacent first conductive bumps and in the gap between adjacent second conductive bumps, and covering the first conductive bump and the second conductive bump.

[0013] Optionally, the packaging structure further comprises: a third conductive bump located between the interconnection structure and the substrate, and electrically connecting the interconnection structure and the substrate.

[0014] Optionally, the packaging structure further comprises: a second sealing layer located between the interconnection structure and the substrate, and filled in the gap between the interconnection structure and the substrate, and in the gap between adjacent third conductive bumps.

[0015] Correspondingly, the embodiment of the present application also provides a packaging method, comprising: providing a substrate; forming an interconnection structure comprising a redistribution layer, and a first plastic encapsulation layer on the redistribution layer, the interconnection structure further comprising a chip bridge embedded in the first plastic encapsulation layer, the first plastic encapsulation layer exposing the surface of the chip bridge, and the surface of the first plastic encapsulation layer exposing the chip bridge being a bonding surface; providing a first chip; providing a chip structure; bonding the chip structure and the first chip on the bonding surface of the interconnection structure, the chip structure being located on the side of the first chip, the chip structure being electrically connected with the redistribution layer, the first chip being electrically connected with the redistribution layer, and the first chip being electrically connected with the chip structure through the chip bridge; after bonding the chip structure and the first chip on the bonding surface of the interconnection structure, bonding the interconnection structure on the substrate, and the bonding surface facing away from the substrate.

[0016] Optionally, in the step of forming the interconnection structure, the first plastic encapsulation layer is flush with the surface of the chip bridge on the bonding surface.

[0017] Optionally, in the step of forming the interconnection structure, the chip bridge is electrically connected with the redistribution layer through the first plastic encapsulation layer.

[0018] Optionally, the step of forming the interconnection structure comprises: providing a first carrier substrate; forming the chip bridge and the first plastic encapsulation layer covering the sidewall and the side of the chip bridge on the first carrier substrate, the first plastic encapsulation layer exposing the surface of the chip bridge, and the surface of the first plastic encapsulation layer and the chip bridge facing the first carrier substrate being a bonding surface; forming the redistribution layer covering the chip bridge and the first plastic encapsulation layer, the redistribution layer, the first plastic encapsulation layer and the chip bridge constituting the interconnection structure; after forming the interconnection structure, further comprising: removing the first carrier substrate.

[0019] Optionally, the step of forming the chip bridge on the first carrier substrate and the first encapsulation layer covering the sidewall of the chip bridge and the first carrier substrate comprises: providing an initial chip bridge comprising a substrate and a circuit structure layer on the substrate; bonding the initial chip bridge to the first carrier substrate, wherein the circuit structure layer of the initial chip bridge faces the first carrier substrate; forming the first encapsulation layer covering the initial chip bridge and the first carrier substrate; and thinning the initial chip bridge and the first encapsulation layer to remove the substrate and the first encapsulation layer higher than the circuit structure layer, and leaving the remaining circuit structure layer as the chip bridge.

[0020] Optionally, the step of forming the redistribution layer covering the chip bridge comprises: forming a dielectric layer covering the chip bridge; and forming an electrical connection structure penetrating through the dielectric layer, wherein the electrical connection structure and the dielectric layer form the redistribution layer, and the electrical connection structure further penetrates through the first encapsulation layer at the side of the chip bridge.

[0021] Optionally, the step of removing the first carrier substrate comprises: bonding a second carrier substrate to the interconnection structure; and removing the first carrier substrate to expose the bonding surface with the second carrier substrate as a support.

[0022] Optionally, after the chip structure and the first chip are bonded to the bonding surface of the interconnection structure, and before the interconnection structure is bonded to the substrate, the packaging method further comprises: forming a second encapsulation layer on the first encapsulation layer, wherein the second encapsulation layer covers the sidewall of the chip structure, the sidewall of the first chip, and fills between the chip structure and the first chip.

[0023] Optionally, after the interconnection structure is formed, and before the chip structure and the first chip are bonded to the bonding surface of the interconnection structure, the packaging method further comprises: forming a first conductive bump on the first encapsulation layer of the bonding surface; and forming a second conductive bump on the chip bridge of the bonding surface; and in the step of bonding the chip structure and the first chip to the bonding surface of the interconnection structure, the first conductive bump electrically connects the redistribution layer with the first chip and the redistribution layer with the chip structure, and the second conductive bump electrically connects the chip bridge with the first chip and the chip bridge with the chip structure.

[0024] Optionally, after the chip structure and the first chip are bonded to the bonding surface of the interconnection structure, and before the interconnection structure is bonded to the substrate, the packaging method further comprises: forming a third conductive bump on the substrate; and in the step of bonding the interconnection structure to the substrate, the third conductive bump electrically connects the interconnection structure with the substrate.

[0025] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0026] The embodiment of the present application provides a packaging structure, an interconnection structure is bonded on a substrate, the interconnection structure comprises a rewiring layer and a first plastic sealing layer on the rewiring layer, and the interconnection structure further comprises a chip bridge embedded in the first plastic sealing layer, the first plastic sealing layer exposes the surface of the chip bridge, and the surface of the first plastic sealing layer exposing the chip bridge is a bonding surface; in the embodiment of the present application, the chip bridge is used to realize the electrical connection between the chip structure and the first chip, the rewiring layer and the first plastic sealing layer are used to realize the electrical connection between the chip structure and the substrate and between the first chip and the substrate, and the chip bridge is embedded in the first plastic sealing layer, so that the chip bridge can be embedded in the interconnection structure by using the first plastic sealing layer, the formation of the interconnection structure is relatively simple and the cost is relatively low, the integration of the rewiring layer and the chip bridge is further improved, and furthermore, the chip bridge is embedded in the interconnection structure, compared with bonding the chip bridge on the interconnection structure, the height difference caused by the chip bridge is reduced, the bonding of the first chip and the chip structure on the interconnection structure is facilitated, and therefore the packaging effect of the packaging structure is improved.

[0027] The embodiment of the present application provides a packaging method for forming an interconnection structure, the interconnection structure comprises a rewiring layer and a first plastic sealing layer on the rewiring layer, and the interconnection structure further comprises a chip bridge embedded in the first plastic sealing layer, the first plastic sealing layer exposes the surface of the chip bridge, and the surface of the first plastic sealing layer exposing the chip bridge is a bonding surface; in the embodiment of the present application, the chip bridge is used to realize the electrical connection between the chip structure and the first chip, the rewiring layer and the first plastic sealing layer are used to realize the electrical connection between the chip structure and the substrate and between the first chip and the substrate, and the chip bridge is embedded in the first plastic sealing layer, so that the chip bridge can be embedded in the interconnection structure by using the first plastic sealing layer, the formation of the interconnection structure is relatively simple and the cost is relatively low, the integration of the rewiring layer and the chip bridge is further improved, and furthermore, the chip bridge is embedded in the interconnection structure, compared with bonding the chip bridge on the interconnection structure, the height difference caused by the chip bridge is reduced, the bonding of the first chip and the chip structure on the interconnection structure is facilitated, and therefore the packaging effect of the packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of a packaging structure;

[0029] Figure 2 It is a structural schematic diagram of an embodiment of the packaging structure of the present application;

[0030] Figures 3 to 12 It is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present application. DETAILED DESCRIPTION

[0031] As known from the background, the structure of the current packaging structure is relatively complex, and the packaging cost is relatively high and the application is relatively poor. Now a packaging structure is combined to analyze the reasons why the packaging cost is relatively high and the application is relatively poor.

[0032] Figure 1 is a structural schematic diagram of a packaging structure.

[0033] The packaging structure comprises: a substrate 10, comprising a bonding surface, a groove is formed on one side of the bonding surface of the substrate 10; a silicon bridge 20 bonded on the bonding surface of the substrate 10; a first chip 31 bonded on the substrate 10 on one side of the groove; a second chip 32 bonded on the substrate 10 on the other side of the groove; a first bump 11 located between the first chip 31 and the substrate 10 on the side of the groove, and between the second chip 32 and the substrate 10, for electrically connecting the first chip 31 and the substrate 10, and the second chip 32 and the substrate 10; a chip bridge 20 bonded on the first chip 31 and the second chip 32, and facing one side of the substrate 10, the chip bridge 20 is located in the groove; a second bump 12 located between the first chip 31 and the chip bridge 20, and between the second chip 32 and the chip bridge 20, for electrically connecting the first chip 31 and the chip bridge 20, and the second chip 32 and the chip bridge 20, so that the first chip 31 and the second chip 32 are electrically connected through the chip bridge 20.

[0034] The silicon bridge 20 is used to electrically connect the first chip 31 and the second chip 32, at present, the chip bridge 20 is usually thick, and the second bump 12 also has a certain height, so the total height of the second bump 12 and the chip bridge 20 bonded on the first chip 31 and the second chip 32 is large, thereby the height of the first bump 11 needs to be increased to compensate for the height from the top surface of the first chip 31 and the second chip 32 to the bottom surface of the chip bridge 20, and at the same time, a groove needs to be additionally formed in the substrate 10 to place the chip bridge 20 to compensate for the height difference between the height from the top surface of the first chip 31 and the second chip 32 to the bottom surface of the chip bridge 20 and the height from the top surface of the first chip 31 and the second chip 32 to the bottom of the first bump 11, so that the packaging structure is complex and the packaging cost is high.

[0035] In order to solve the technical problems, the embodiment of the present application provides a packaging structure, comprising: a substrate; an interconnection structure bonded on the substrate, the interconnection structure comprising a redistribution layer and a first plastic encapsulation layer on the redistribution layer, the interconnection structure further comprising a chip bridge embedded in the first plastic encapsulation layer, the first plastic encapsulation layer exposing the surface of the chip bridge, and the surface of the first plastic encapsulation layer exposing the chip bridge being a bonding surface; a first chip bonded on the bonding surface of the interconnection structure, and the first chip being electrically connected with the redistribution layer and the chip bridge; a chip structure bonded on the bonding surface of the interconnection structure on the side of the first chip, and the chip structure being electrically connected with the redistribution layer, and the chip structure being electrically connected with the first chip through the chip bridge.

[0036] In the embodiment of the present application, the chip bridge is used to realize the electrical connection between the chip structure and the first chip, the re-wiring layer and the first plastic encapsulation layer are used to realize the electrical connection between the chip structure and the substrate and between the first chip and the substrate, the chip bridge is embedded in the first plastic encapsulation layer, and the first plastic encapsulation layer is used to enable the chip bridge to be embedded in the interconnection structure, so that the interconnection structure is formed more simply and at a lower cost, and the integration of the re-wiring layer and the chip bridge is improved. Moreover, the chip bridge is embedded in the interconnection structure, which is beneficial to reducing the height difference caused by the chip bridge and facilitating the bonding of the first chip and the chip structure on the interconnection structure, thereby improving the packaging effect of the packaging structure.

[0037] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0038] Figure 2 FIG. 1 is a structural schematic diagram of a packaging structure according to an embodiment of the present application.

[0039] The packaging structure comprises a substrate 700, an interconnection structure 340 bonded on the substrate 700, the interconnection structure comprising a re-wiring layer 320 and a first plastic encapsulation layer 330 on the re-wiring layer 320, the interconnection structure 340 further comprising a chip bridge 200 embedded in the first plastic encapsulation layer 330, the first plastic encapsulation layer 330 exposing the surface of the chip bridge 200, the surface of the first plastic encapsulation layer 330 exposing the chip bridge 200 being a bonding surface 30a, a first chip 440 bonded on the bonding surface 30a of the interconnection structure 340 on the side of the chip structure 400, the first chip 440 being electrically connected with the re-wiring layer 320 and the chip bridge 200, and a chip structure 400 bonded on the bonding surface 30a of the interconnection structure 340 on the side of the first chip 440, the chip structure 400 being electrically connected with the re-wiring layer 320 and the first chip 440 through the chip bridge 200.

[0040] The substrate 700 is used to provide a process operation basis for realizing the bonding of the chip structure 400, the first chip 440 and the interconnection structure 340.

[0041] In the embodiment, the substrate 700 comprises a base and an interconnection layer on the base, the exposed surface of the interconnection layer being a process operation platform.

[0042] The interconnection layer is used to realize the bonding with the interconnection structure, thereby realizing the electrical connection with the chip structure 400 and the first chip 440, and is further used to realize the electrical connection with the base, thereby realizing the electrical connection between the chip structure 400 and the first chip 440 and the base.

[0043] In the embodiment, the interconnection layer is a redistribution layer. Specifically, the redistribution layer can include one or more redistribution interconnection layers.

[0044] The substrate is used to realize electrical connection between the chip structure 400 and the first chip 440 through the interconnection layer, and is capable of being electrically connected with an external structure, thereby realizing electrical connection between the chip structure 400 and the first chip 440 and the external structure.

[0045] Specifically, in the embodiment, the substrate is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0046] The interconnection structure 340 is used to provide a process operation basis for realizing bonding between the chip structure 400 and the first chip 440, and the bonding surface 30a is used as a process operation platform for realizing bonding between the chip structure 400 and the first chip 440.

[0047] Specifically, in the embodiment, the interconnection structure 340 is used to be electrically connected with the chip structure 400 and the first chip 440, and realize electrical connection between the chip structure 400 and the substrate 700, electrical connection between the first chip 440 and the substrate 700, and electrical connection between the chip structure 400 and the first chip 440.

[0048] In the embodiment, the chip bridge 200 is used to realize electrical connection between the chip structure 400 and the first chip 440, the redistribution layer 320 and the first encapsulation layer 330 are used to realize electrical connection between the chip structure 400 and the substrate 700 and between the first chip 440 and the substrate 700, and the chip bridge 200 is embedded in the first encapsulation layer 330. Therefore, the chip bridge 200 can be embedded in the interconnection structure 340 by using the first encapsulation layer 330, which is beneficial to the integration of the redistribution layer 320 and the chip bridge 200, and is beneficial to the embedding of the chip bridge 200 in the interconnection structure 340, which is beneficial to reducing the height difference caused by the chip bridge 200 and is beneficial to the bonding of the first chip 440 and the chip structure 400 on the interconnection structure 340, thereby improving the packaging effect of the packaging structure.

[0049] The redistribution layer 320 is used to realize electrical connection between the chip structure 400 and the substrate 700 and between the first chip 440 and the substrate 700.

[0050] In the embodiment, the redistribution layer 320 is a redistribution layer (Redistribution Layer) including one or more redistribution interconnection layers. Specifically, the redistribution layer 320 includes the dielectric layer 300 and the electrical connection structures 310 penetrating through the dielectric layer 300.

[0051] The dielectric layer 300 is configured to isolate the electrical connection structures 310 from each other, and the electrical connection structures 310 are configured to realize the electrical connection between the chip structure 400 and the substrate 700 and the electrical connection between the first chip 440 and the substrate 700.

[0052] In the embodiment, the electrical connection structures 310 on the side of the chip bridge 200 also penetrate through the first encapsulation layer 330.

[0053] The electrical connection structures 310 on the side of the chip bridge 200 also penetrate through the first encapsulation layer 330, so that the chip structure 400 on the first encapsulation layer 330 can be electrically connected to the substrate 700 through the electrical connection structures 310, and the first chip 440 on the first encapsulation layer 330 can be electrically connected to the substrate 700 through the electrical connection structures 310.

[0054] The first encapsulation layer 330 is configured to encapsulate the chip bridge 200 in the interconnection structure 340.

[0055] In the embodiment, the material of the first encapsulation layer 330 is a molding material, for example, an epoxy resin. The epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical performance, and low cost. In other embodiments, other suitable encapsulation materials can also be used for the first encapsulation layer.

[0056] The chip bridge 200 is configured to realize the electrical connection between the chip structure 400 and the first chip 440.

[0057] In the embodiment, the chip bridge 200 has a circuit structure formed therein, and the first chip 440 and the chip structure 400 are electrically connected through the circuit structure.

[0058] In the embodiment, the chip bridge 200 includes a silicon bridge (Si bridge) or an interposer.

[0059] It should be noted that, in the embodiment, the thickness of the chip bridge 200 should not be too large or too small. If the thickness of the chip bridge 200 is too large, the thickness of the interconnection structure 340 will be too large, which is not conducive to improving the integration of the encapsulation structure. If the thickness of the chip bridge 200 is too small, the formation of the circuit structure in the chip bridge 200 will be affected, and the electrical connection performance of the chip bridge 200 will be affected. Therefore, in the embodiment, the thickness of the chip bridge 200 is 2 μm to 15 μm.

[0060] In the embodiment, the first plastic sealing layer 330 is flush with the surface of the chip bridge 200 on the bonding surface 30a.

[0061] The first plastic sealing layer 330 is flush with the surface of the chip bridge 200, so that the flatness of the bonding surface 30a is better, which provides a better process platform for the bonding of the chip structure 400 and the first chip 440, and the first plastic sealing layer 330 is flush with the surface of the chip bridge 200, which is beneficial to further improve the integration of the interconnection structure 340. Moreover, the first plastic sealing layer 330 is flush with the surface of the chip bridge 200, and the chip bridge 200 is completely embedded in the interconnection structure 340, which is beneficial to completely avoid the height difference caused by the chip bridge 200, further beneficial to the bonding of the first chip 440 and the chip structure 400 on the interconnection structure, thereby further beneficial to improve the packaging effect of the packaging structure.

[0062] In the embodiment, the chip bridge 200 penetrates through the first plastic sealing layer 330 and is electrically connected with the redistribution layer 320.

[0063] The chip bridge 200 penetrates through the first plastic sealing layer 330 and is electrically connected with the redistribution layer 320, so that the first chip 440 and the chip structure 400 bonded on the chip bridge 200 can not only be interconnected through the chip bridge 200, but also be electrically connected with the redistribution layer 320 through the chip bridge 200 respectively, to realize more circuit structures, thereby beneficial to improve the circuit diversity of the packaging structure, and beneficial to realize a more complex circuit structure.

[0064] The first chip 440 is used to be electrically connected with the interconnection structure 340, to realize the electrical connection between the first chip 440 and the chip structure 400, and the electrical connection between the first chip 440 and the substrate 700.

[0065] Specifically, in the embodiment, the first chip 440 is electrically connected with the redistribution layer 320, and is electrically connected with the substrate 700 through the redistribution layer 320, and the first chip 440 is electrically connected between each chip structure 400 through the chip bridge 200.

[0066] In the embodiment, the first chip 440 is a logic chip, and the embodiment is used as a first logic chip to control the storage chip of the chip structure 400. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).

[0067] The chip structure 400 is used to be electrically connected with the interconnection structure 340, to realize the electrical connection between the chip structure 400 and the first chip 440, and the electrical connection between the chip structure 400 and the substrate 700.

[0068] In the embodiment, the chip structure 400 includes one or a plurality of second chips 410 stacked in the longitudinal direction (as indicated by the Z direction). Figure 2 The electrical connection between each second chip 410 and the first chip 440, and the electrical connection between each second chip 410 and the substrate 700 are realized.

[0069] Specifically, in the embodiment, the chip structure 400 is electrically connected with the wiring layer 320, and is electrically connected with the substrate 700 through the re-wiring layer 320. The chip structure 400 is electrically connected with the first chip 440 through the chip bridge 200.

[0070] In the embodiment, in the chip structure 400, the plurality of second chips 410 stacked in the longitudinal direction form a high bandwidth memory (HBM) structure. By using the HBM structure, it is beneficial to meet the requirement for higher information transmission speed.

[0071] The second chip 410 includes a bottom chip located at the bottommost position, and a top chip stacked on the bottom chip. The number of the top chip can be one or more. In the embodiment, the number of the top chip is taken as four for example. In other embodiments, the number of the top chip can also be other numbers.

[0072] Therefore, in the embodiment, the top chip is a storage chip. In a specific implementation, the top chip is a high bandwidth memory (HBM) chip.

[0073] In the embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as a logic control chip in the chip structure 400.

[0074] In the embodiment, the bottom chip is electrically connected with the substrate 700, and is electrically connected with the adjacent second chip 410 in the longitudinal direction, so as to realize the electrical integration between the second chips 410 and the electrical integration between the second chip 410 and the substrate 700.

[0075] In the embodiment, the number of the chip structure 400 is multiple. By using multiple chip structures 400 to be electrically connected with the first chip 440, it is beneficial to increase the memory of the packaging structure, improve the chip speed, and reduce the chip power consumption.

[0076] In the embodiment, the packaging structure further includes a first conductive bump 510 located between the first molding layer 330 and the first chip 440, and between the first molding layer 330 and the chip structure 400, and electrically connecting the re-wiring layer 320 and the first chip 440, and electrically connecting the re-wiring layer 320 and the chip structure 400.

[0077] The first conductive bump 510 is configured to realize electrical connection between the first chip 440 and the redistribution layer 320 through the first encapsulation layer 330, and electrical connection between the chip structure 400 and the redistribution layer 320 through the first encapsulation layer 330.

[0078] In this embodiment, the material of the first conductive bump 510 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the first conductive bump 510 is tin.

[0079] In this embodiment, the first conductive bump 510 can be a micro bump (uBump), which has a high density and is conducive to improving the communication speed between the first chip 440 and the redistribution layer 320, and between the chip structure 400 and the redistribution layer 320.

[0080] In this embodiment, the packaging structure further includes a second conductive bump 520 located between the chip bridge 200 and the first chip 440, and between the chip bridge 200 and the chip structure 400, and electrically connected to the chip bridge 200 and the first chip 440, and electrically connected to the chip bridge 200 and the chip structure 400.

[0081] The second conductive bump 520 is configured to realize electrical connection between the first chip 440 and the chip bridge 200, and electrical connection between the chip structure 400 and the chip bridge 200.

[0082] In this embodiment, the material of the second conductive bump 520 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the second conductive bump 520 is tin.

[0083] In this embodiment, the second conductive bump 520 can be a micro bump (uBump), which has a high density and is conducive to improving the communication speed between the first chip 440 and the chip bridge 200, and between the chip structure 400 and the chip bridge 200.

[0084] In this embodiment, the packaging structure further includes a first sealing layer 600 filled in the gaps between adjacent first conductive bumps 510 and between adjacent second conductive bumps 520, and covering the first conductive bumps 510 and the second conductive bumps 520.

[0085] The first sealing layer 600 is configured to realize sealing between the interconnection structure and the first chip 440, realize sealing between the interconnection structure and the chip structure 400, and realize sealing of the first conductive bump 510 and the second conductive bump 520.

[0086] In this embodiment, the packaging structure further includes a second plastic encapsulation layer 610 on the first plastic encapsulation layer 330, the second plastic encapsulation layer 610 covering the sidewall of the chip structure 400, the sidewall of the first chip 440, and filling between the chip structure 400 and the first chip 440.

[0087] The second plastic encapsulation layer 610 is used to protect the chip structure 400 and the first chip 440.

[0088] In this embodiment, the material of the second plastic encapsulation layer 610 is a molding material, for example, epoxy resin. The epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical performance, and low cost. In other embodiments, other suitable packaging materials can also be selected for the second plastic encapsulation layer.

[0089] In this embodiment, the packaging structure further includes a third conductive bump 530 between the interconnection structure 340 and the substrate 700, and electrically connecting the interconnection structure 340 and the substrate 700.

[0090] The third conductive bump 530 is used to realize electrical connection between the interconnection structure 340 and the substrate 700.

[0091] In this embodiment, the material of the third conductive bump 530 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the third conductive bump 530 is tin.

[0092] In this embodiment, the third conductive bump 530 can be a C4 (Controlled Collapse Chip Connection) with excellent electrical performance and thermal characteristics, and in the case of the same third conductive bump spacing, the I / O number can be very high, and is not limited by the size of the redistribution structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0093] In this embodiment, the packaging structure further includes a second sealing layer 620 between the interconnection structure 340 and the substrate 700, and filling the gap between the interconnection structure 340 and the substrate 700, and the gap between adjacent third conductive bumps 530.

[0094] The second sealing layer 620 is used to realize sealing between the interconnection structure 340 and the substrate 700, and to realize sealing of the third conductive bump 530.

[0095] In this embodiment, the packaging structure further includes a fourth conductive bump 540 at the bottom of the substrate 700.

[0096] The fourth conductive bump 540 is used to realize electrical connection between the substrate 700 and the outside.

[0097] In this embodiment, the material of the fourth conductive bump 540 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the fourth conductive bump 540 is tin.

[0098] In this embodiment, the fourth conductive bump 540 can be a Ball Grid Array (BGA) structure.

[0099] Figures 3 to 12 is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the application.

[0100] In combination with reference Figures 3 to 6 The interconnection structure 340 is formed, including the re-routed layer 320 and the first encapsulation layer 330 on the re-routed layer 320, and the interconnection structure 340 further includes the chip bridge 200 embedded in the first encapsulation layer 330, and the first encapsulation layer 330 exposes the surface of the chip bridge 200, and the surface of the first encapsulation layer 330 exposing the chip bridge 200 is the bonding surface 30a.

[0101] The interconnection structure 340 is used to provide a process operation basis for subsequent implementation of the bonding of the chip structure and the first chip, and the bonding surface 30a is used as a process operation platform for subsequent implementation of the bonding of the chip structure and the first chip.

[0102] Specifically, in this embodiment, the interconnection structure 340 is used for subsequent electrical connection with the chip structure and the first chip, to achieve electrical connection between the chip structure 340 and the substrate, electrical connection between the first chip and the substrate, and electrical connection between the chip structure and the first chip.

[0103] In this embodiment, the chip bridge 200 is used for subsequent electrical connection between the chip structure and the first chip, the re-routed layer 320 and the first encapsulation layer 330 are used for subsequent electrical connection between the chip structure and the substrate and between the first chip and the substrate, and the chip bridge 200 is embedded in the first encapsulation layer 330. Therefore, the chip bridge 200 can be embedded in the interconnection structure 340 by using the first encapsulation layer 330, so that the formation of the interconnection structure 340 is relatively simple and the cost is relatively low, and the integration of the re-routed layer 320 and the chip bridge 200 is also improved. Moreover, the chip bridge 200 is embedded in the interconnection structure 340, which is beneficial to reduce the height difference caused by the chip bridge 200 and facilitate the subsequent bonding of the first chip and the chip structure on the interconnection structure 340, thereby improving the packaging effect of the packaging structure.

[0104] The re-routed layer 320 is used for subsequent electrical connection between the chip structure and the substrate and between the first chip and the substrate.

[0105] In the embodiment, the redistribution layer 320 is a redistribution structure (Redistribution Layer) including one or more redistribution interconnection layers.

[0106] The first molding layer 330 is used to encapsulate the chip bridge 200 in the interconnection structure 340.

[0107] In the embodiment, the material of the first molding layer 330 is a molding material, for example, an epoxy resin. The epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical performance, and low cost. In other embodiments, the first molding layer can also be selected from other suitable packaging materials.

[0108] The chip bridge 200 is used to realize electrical connection between the chip structure and the first chip subsequently.

[0109] In the embodiment, the chip bridge 200 has a circuit structure formed therein, and the first chip and the chip structure are electrically connected through the circuit structure subsequently.

[0110] In the embodiment, the chip bridge 200 includes a silicon bridge (Si bridge) or an interposer.

[0111] It should be noted that in the step of forming the interconnection structure 340, the thickness of the chip bridge 200 should not be too large or too small. If the thickness of the chip bridge 200 is too large, it will easily lead to the thickness of the interconnection structure 340 being too large, which is not conducive to improving the integration of the packaging structure. If the thickness of the chip bridge 200 is too small, it will easily affect the formation of the circuit structure in the chip bridge 200 and affect the electrical connection performance of the chip bridge 200. Therefore, in the step of forming the interconnection structure 340, the thickness of the chip bridge 200 is 2 μm to 15 μm.

[0112] In the step of forming the interconnection structure 340, the first molding layer 330 is flush with the surface of the chip bridge 200 on the bonding surface 30a.

[0113] The first molding layer 330 is flush with the surface of the chip bridge 200, which makes the flatness of the bonding surface 30a better, provides a better process platform for the bonding of the chip structure 400 and the first chip 440, and the first molding layer 330 being flush with the surface of the chip bridge 200 is conducive to further improving the integration of the interconnection structure 340. Moreover, the first molding layer 330 being flush with the surface of the chip bridge 200 and the chip bridge 200 being completely embedded in the interconnection structure 340 are conducive to completely avoiding the height difference caused by the chip bridge 200, further conducive to the bonding of the first chip 440 and the chip structure 400 on the interconnection structure, and thus further conducive to improving the packaging effect of the packaging structure.

[0114] In the step of forming the interconnection structure 340, the chip bridge 200 penetrates through the first encapsulation layer 330 and is electrically connected with the re-distribution layer 320.

[0115] The chip bridge 200 penetrates through the first encapsulation layer 330 and is electrically connected with the re-distribution layer 320, so that the first chip and the chip structure bonded on the chip bridge 200 in the subsequent step can not only be interconnected through the chip bridge 200, but also be electrically connected with the re-distribution layer 320 through the chip bridge 200 respectively, so as to realize more circuit structures, thereby facilitating to improve the circuit diversity of the packaging structure and to realize a relatively complex circuit structure.

[0116] Reference Figure 3 The step of forming the interconnection structure 340 includes: providing the first bearing substrate 100.

[0117] The first bearing substrate 100 is used for bearing the interconnection structure and providing a process platform for forming the interconnection structure 340.

[0118] In the embodiment, the first bearing substrate 100 is a wafer. In other embodiments, the first bearing substrate can also be a glass substrate.

[0119] In the embodiment, the first bearing substrate 100 is provided with the first adhesive layer 110.

[0120] The first adhesive layer 110 is used for adhering the chip bridge 200 on the first bearing substrate 100.

[0121] Reference Figures 3 to 5 The first adhesive layer 110 is used for adhering the chip bridge 200 on the first bearing substrate 100.

[0122] In the embodiment, the first encapsulation layer 330 exposes the surface of the chip bridge 200, and the surface of the chip bridge 200 facing the first bearing substrate 100 is the bonding surface 30a, so that after the interconnection structure 340 is adhered to the second bearing substrate and the first bearing substrate 100 is removed, the chip bridge 200 is exposed, thereby preparing for bonding the first chip and the chip structure.

[0123] Specifically, reference Figure 3 The step of forming the chip bridge 200 on the first bearing substrate 100 and the first encapsulation layer 330 covering the sidewall and the side of the chip bridge 200 includes: providing an initial chip bridge 201 including a substrate (not marked) and a circuit structure layer (not marked) on the substrate.

[0124] The initial chip bridge 201 is used to form the chip bridge 200, the circuit structure layer is used to form the circuit structure of the chip bridge 200, and the substrate is used as a support for forming the circuit structure.

[0125] With reference to the foregoing Figure 3 The initial chip bridge 201 is adhered to the first carrier substrate 100, wherein the circuit structure layer of the initial chip bridge 201 faces the first carrier substrate 100.

[0126] The circuit structure layer of the initial chip bridge 201 faces the first carrier substrate 100, so that the substrate of the initial chip bridge 201 is exposed, thereby enabling the initial chip bridge 201 to be thinned.

[0127] Specifically, in the embodiment, the initial chip bridge 201 is adhered to the first adhesive layer 110 of the first carrier substrate 100.

[0128] With reference to the foregoing Figure 4 The first encapsulation layer 330 covering the initial chip bridge 201 and the first carrier substrate 100 is formed.

[0129] The first encapsulation layer 330 covering the initial chip bridge 201 and the first carrier substrate 100 is formed, which prepares for subsequent thinning processing.

[0130] With reference to the foregoing Figure 5 The initial chip bridge 201 and the first encapsulation layer 330 are subjected to thinning processing, the substrate and the first encapsulation layer 330 higher than the circuit structure layer are removed, and the remaining circuit structure layer is reserved as the chip bridge 200.

[0131] The initial chip bridge 201 is subjected to thinning processing to remove the substrate, thereby obtaining the chip bridge 200 with a smaller thickness, which is conducive to embedding the chip bridge 200 in the interconnection structure 340, reducing the height difference caused by the introduction of the chip bridge 200, and reducing the occupied volume of the chip bridge 200. Moreover, the removal of the substrate exposes the circuit structure layer, so that the redistribution layer 320 formed to cover the chip bridge 200 can be electrically connected to the chip bridge 200.

[0132] With reference to the foregoing Figure 6 The redistribution layer 320 covering the chip bridge 200 and the first encapsulation layer 330 is formed, and the redistribution layer 320, the first encapsulation layer 330, and the chip bridge 200 constitute the interconnection structure 340.

[0133] The chip bridge 200 is embedded in the interconnection structure 340 by forming the chip bridge 200 and the first plastic encapsulation layer 330 first, and then forming the re-wiring layer 320 covering the chip bridge 200 and the first plastic encapsulation layer 330. The forming process is simple and easy to operate, and the process of additionally slotting the interconnection structure 340 for embedding the chip bridge 200 in the interconnection structure 340 is omitted, thereby simplifying the process flow and reducing the process cost.

[0134] Specifically, with further reference to Figure 6 , the step of forming the re-wiring layer 320 covering the chip bridge 200 and the first plastic encapsulation layer 330 comprises forming a dielectric layer 300 covering the chip bridge 200 and the first plastic encapsulation layer 330.

[0135] The dielectric layer 300 is used to isolate the electrical connection structures in the re-wiring layer 320 from each other.

[0136] In this embodiment, the electrical connection structure 310 is formed to penetrate the dielectric layer 300, and the electrical connection structure 310 and the dielectric layer 300 constitute the re-wiring layer 320. On the side of the chip bridge 200, the electrical connection structure 310 also penetrates the first plastic encapsulation layer 330.

[0137] The electrical connection structure 310 is used for subsequent electrical connection between the chip structure and the substrate, and electrical connection between the first chip and the substrate.

[0138] In this embodiment, the electrical connection structure 310 on the side of the chip bridge 200 also penetrates the first plastic encapsulation layer 330.

[0139] The electrical connection structure 310 on the side of the chip bridge 200 also penetrates the first plastic encapsulation layer 330, so that the chip structure subsequently located on the first plastic encapsulation layer 330 can be electrically connected to the substrate through the electrical connection structure 310, and the first chip located on the first plastic encapsulation layer 330 can be electrically connected to the substrate 700 through the electrical connection structure 310.

[0140] With reference to Figure 7 and Figure 8 , after forming the interconnection structure 340, the method further comprises removing the first carrier substrate 100.

[0141] The first carrier substrate 100 is removed to expose the bonding surface 30a, which prepares for subsequent bonding of the first chip and the chip structure on the interconnection structure 340.

[0142] Specifically, with reference to Figure 7 , the step of removing the first carrier substrate 100 comprises bonding a second carrier substrate 120 on the interconnection structure 340.

[0143] The second carrier substrate 120 is used to carry the interconnection structure 340, and provides a process platform for subsequent bonding of the first chip and the chip structure on the interconnection structure 340.

[0144] In this embodiment, the second carrier substrate 120 is a wafer. In other embodiments, the second carrier substrate can also be a glass substrate.

[0145] In this embodiment, the second adhesive layer 130 is formed on the second carrier substrate 120.

[0146] The second adhesive layer 130 is used to adhere the interconnection structure 340 to the second carrier substrate 120.

[0147] Correspondingly, in this embodiment, the interconnection structure 340 is adhered to the second adhesive layer 130.

[0148] Referring to Figure 8 With the second carrier substrate 120 as support, the first carrier substrate 100 is removed, and the bonding surface 30a is exposed.

[0149] The interconnection structure 340 is flipped so that the bonding surface 30a faces upwards, providing an easy-to-operate platform for subsequent bonding of the first chip and the chip structure to the bonding surface 30a of the interconnection structure 340.

[0150] Referring to Figure 9 After the interconnection structure 340 is formed, before the chip structure and the first chip are bonded to the bonding surface 30a of the interconnection structure, the packaging method further includes: forming first conductive bumps 510 on the first encapsulation layer 330 of the bonding surface 30a; and forming second conductive bumps 520 on the chip bridge 200 of the bonding surface 30a.

[0151] The first conductive bumps 510 are used to subsequently realize electrical connection between the first chip and the redistribution layer 320, and electrical connection between the chip structure and the redistribution layer 320.

[0152] In this embodiment, the material of the first conductive bump 510 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the first conductive bump 510 is tin.

[0153] In this embodiment, the first conductive bump 510 can be a micro bump (uBump), which has a high density and is conducive to improving the communication speed between the first chip and the redistribution layer 320, and between the chip structure and the redistribution layer 320.

[0154] The second conductive bump 520 is used to subsequently realize electrical connection between the first chip and the chip bridge 200, and electrical connection between the chip structure and the chip bridge 200.

[0155] In this embodiment, the material of the second conductive bump 520 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the second conductive bump 520 is tin.

[0156] In this embodiment, the second conductive bump 520 can be a micro bump (uBump), which has a high density and is conducive to improving the communication speed between the first chip and the chip bridge 200 and between the chip structure and the chip bridge 200.

[0157] Reference Figure 10 , a first chip 440 is provided; and a chip structure 400 is provided.

[0158] The first chip 440 is configured to be electrically connected to the interconnection structure, so as to realize the electrical connection between the first chip 440 and the chip structure 400, and the subsequent electrical connection between the first chip 440 and the substrate.

[0159] In this embodiment, the first chip 440 is a logic chip, and this embodiment is taken as a first logic chip for controlling the storage chip of the chip structure 400. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).

[0160] The chip structure 400 is configured to be electrically connected to the interconnection structure, so as to realize the electrical connection between the chip structure 400 and the first chip 440, and the subsequent electrical connection between the chip structure 400 and the substrate.

[0161] In this embodiment, the chip structure 400 includes one or a plurality of second chips 410 stacked along a longitudinal direction (as indicated by the Z direction in the figure). Figure 2 In this embodiment, the plurality of second chips 410 stacked along the longitudinal direction in the chip structure 400 form a high bandwidth memory (HBM) structure, which is conducive to meeting the requirement for higher information transmission speed.

[0162] In this embodiment, in the chip structure 400, the plurality of second chips 410 stacked along the longitudinal direction form a high bandwidth memory (HBM) structure, which is conducive to meeting the requirement for higher information transmission speed.

[0163] In this embodiment, the second chip 410 includes a bottom chip at the bottom and a top chip stacked on the bottom chip, and the number of the top chip can be one or more. In this embodiment, the number of the top chip is taken as four for illustration. In other embodiments, the number of the top chip can also be other numbers.

[0164] Therefore, in the embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a high bandwidth memory (HBM) chip.

[0165] In the embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as a logic control chip in the chip structure 400.

[0166] With reference to Figure 10 After the chip structure 400 and the first chip 440 are bonded to the bonding surface 30a of the interconnection structure 340, the chip structure 400 is located at the side of the first chip 440, the chip structure 400 is electrically connected to the redistribution layer 320, the first chip 440 is electrically connected to the redistribution layer 320, and the first chip 440 is electrically connected to the chip structure 400 through the chip bridge 200.

[0167] Specifically, the first chip 440 is electrically connected to the wiring layer 320, and is subsequently electrically connected to the substrate through the redistribution layer 320, the first chip 440 is electrically connected to each chip structure 400 through the chip bridge 200, the chip structure 400 is electrically connected to the wiring layer 320, and is subsequently electrically connected to the substrate through the redistribution layer 320, and the chip structure 400 is electrically connected to the first chip 440 through the chip bridge 200.

[0168] In the step of bonding the chip structure 400 and the first chip 440 to the bonding surface 30a of the interconnection structure 340, in the embodiment, the first conductive bumps 510 electrically connect the interconnection structure 340 and the first chip 440, and electrically connect the interconnection structure 340 and the chip structure 400, and the second conductive bumps 520 electrically connect the chip bridge 200 and the first chip 440, and electrically connect the chip bridge 200 and the chip structure 400.

[0169] With reference to Figure 11 The packaging method further includes: forming a first sealing layer 600 filled in gaps between adjacent first conductive bumps 510 and between adjacent second conductive bumps 520, and the first sealing layer 600 covers the first conductive bumps 510 and the second conductive bumps 520.

[0170] The first sealing layer 600 is used to seal the interconnection structure and the first chip 440, seal the interconnection structure and the chip structure 400, and seal the first conductive bumps 510 and the second conductive bumps 520.

[0171] With reference to Figure 11After the chip structure 400 and the first chip 440 are bonded on the bonding surface 30a of the interconnection structure 340, before the interconnection structure 400 is subsequently bonded on the substrate, the packaging method further comprises: forming a second plastic encapsulation layer 610 on the first plastic encapsulation layer 330, the second plastic encapsulation layer 610 covering the sidewall of the chip structure 400, the sidewall of the first chip 440, and filling between the chip structure 400 and the first chip 440.

[0172] The second plastic encapsulation layer 610 is used to protect the chip structure 400 and the first chip 440.

[0173] In the embodiment, the material of the second plastic encapsulation layer 610 is a molding material, for example, an epoxy resin. The epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical performance, and low cost. In other embodiments, other suitable packaging materials can also be selected for the second plastic encapsulation layer.

[0174] Reference Figure 12 After the chip structure 400 and the first chip 440 are bonded on the bonding surface 30a of the interconnection structure 340, before the interconnection structure 340 is subsequently bonded on the substrate, the packaging method further comprises: removing the second carrier substrate 120.

[0175] The second carrier substrate 120 is removed to expose the surface of the interconnection structure 340 facing away from the bonding surface 30a, in preparation for subsequent bonding of the interconnection structure 340 on the substrate.

[0176] Continuing to refer to Figure 12 , a substrate 700 is provided.

[0177] The substrate 700 is used to provide a process operation basis for achieving bonding of the chip structure 400, the first chip 440, and the interconnection structure 340.

[0178] In the embodiment, the substrate 700 includes a base and an interconnection layer on the base, the exposed surface of the interconnection layer being a process operation platform.

[0179] The interconnection layer is used to achieve bonding with the interconnection structure, thereby achieving electrical connection with the chip structure 400 and the first chip 440, and is also used to achieve electrical connection with the base, thereby enabling electrical connection between the chip structure 400 and the first chip 440 and the base.

[0180] In the embodiment, the interconnection layer is a redistribution structure (Redistribution Layer). Specifically, the redistribution structure can include one or more redistribution interconnection layers.

[0181] The substrate is used to realize electrical connection between the interconnection layer and the chip structure 400 and the first chip 440, and is capable of being electrically connected with an external structure, so as to realize electrical connection between the chip structure 400 and the first chip 440 and the external structure.

[0182] Specifically, in the embodiment, the substrate is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0183] In the embodiment, after the chip structure 400 and the first chip 440 are bonded to the bonding surface 30a of the interconnection structure 340, before the interconnection structure 340 is bonded to the substrate 700, the packaging method further comprises: forming a third conductive bump 530 on the substrate 700.

[0184] The third conductive bump 530 is used to realize electrical connection between the interconnection structure and the substrate 700.

[0185] In the embodiment, the material of the third conductive bump 530 comprises one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 530 is tin.

[0186] In the embodiment, the third conductive bump 530 can be a C4 (Controlled Collapse Chip Connection) having excellent electrical performance and thermal characteristics, and in the case of the same third conductive bump spacing, the number of I / Os can be very high, and is not limited by the size of the redistribution structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0187] Continuing to refer to Figure 12 After the chip structure 400 and the first chip 440 are bonded to the bonding surface 30a of the interconnection structure, the interconnection structure is bonded to the substrate 700, and the bonding surface 30a faces away from the substrate 700.

[0188] Specifically, the first chip 440 is electrically connected to the wiring layer 320, is electrically connected to the substrate 700 through the redistribution layer 320, is electrically connected between the chip structure 400 and the first chip 440 through the chip bridge 200, the chip structure 400 is electrically connected to the wiring layer 320, is electrically connected to the substrate 700 through the redistribution layer 320, and is electrically connected between the chip structure 400 and the first chip 440 through the chip bridge 200.

[0189] In the embodiment, the bottom chip is electrically connected between the substrate 700 and the adjacent second chip 410 in the longitudinal direction, so as to realize electrical integration between the second chips 410 and electrical integration between the second chips 410 and the substrate 700.

[0190] In the embodiment, the number of the chip structures 400 is multiple, and the multiple chip structures 400 are electrically connected with the first chip 440, which is beneficial to increase the memory of the packaging structure, improve the chip speed, and reduce the chip power consumption.

[0191] Correspondingly, in the embodiment, in the step of bonding the interconnection structure on the substrate 700, the third conductive bump 530 electrically connects the interconnection structure and the substrate 700.

[0192] In the embodiment, after the interconnection structure is bonded on the substrate 700, the packaging method further includes: forming a second sealing layer 620 between the interconnection structure and the substrate 700, the second sealing layer 620 being filled in the gap between the interconnection structure and the substrate 700 and in the gap between the adjacent third conductive bumps 530.

[0193] The second sealing layer 620 is used to seal the interconnection structure and the substrate 700, and seal the third conductive bump 530.

[0194] In the embodiment, the packaging method further includes: forming a fourth conductive bump 540 at the bottom of the substrate 700.

[0195] The fourth conductive bump 540 is used to electrically connect the substrate 700 and the outside.

[0196] In the embodiment, the material of the fourth conductive bump 540 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the fourth conductive bump 540 is tin.

[0197] In the embodiment, the fourth conductive bump 540 can be a Ball Grid Array (BGA) structure.

[0198] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: substrate; An interconnect structure bonded to the substrate, the interconnect structure comprising a redistribution layer and a first plastic encapsulation layer located on the redistribution layer, the interconnect structure further comprising a chip bridge embedded in the first plastic encapsulation layer, the first plastic encapsulation layer exposing the chip bridge surface, and the surface of the first plastic encapsulation layer exposing the chip bridge serving as a bonding surface; a first chip bonded to a bonding surface of the interconnect structure, and the first chip is electrically connected to the redistribution layer and the chip bridge; A chip structure is bonded to the bonding surface of the interconnection structure on the side of the first chip, and the chip structure is electrically connected to the redistribution layer, and the chip structure is electrically connected to the first chip through the chip bridge.

2. The packaging structure according to claim 1, wherein: On the bonding surface, the first plastic packaging layer is flush with the surface of the chip bridge.

3. The packaging structure according to claim 1, wherein: The chip bridge passes through the first plastic packaging layer and is electrically connected to the redistribution layer.

4. The packaging structure according to claim 1, wherein: The rewiring layer includes a dielectric layer and an electrical connection structure penetrating the dielectric layer; The electrical connection structure on the side of the chip bridge also passes through the first plastic packaging layer.

5. The packaging structure according to claim 1, wherein: The packaging structure further includes: a second plastic packaging layer located on the first plastic packaging layer, the second plastic packaging layer covers the sidewalls of the chip structure and the sidewalls of the first chip, and fills between the chip structure and the first chip.

6. The packaging structure according to claim 1, wherein: The packaging structure further includes: a first conductive bump, located between the first plastic packaging layer and the first chip, and between the first plastic packaging layer and the chip structure, and electrically connecting the redistribution layer and the first chip, and electrically connecting the redistribution layer and the chip structure; The second conductive bump is located between the chip bridge and the first chip, and between the chip bridge and the chip structure, and electrically connects the chip bridge and the first chip, and electrically connects the chip bridge and the chip structure.

7. The packaging structure according to claim 6, wherein: The packaging structure further includes a first sealing layer, which fills the gaps between adjacent first conductive bumps and between adjacent second conductive bumps and covers the first conductive bumps and the second conductive bumps.

8. The packaging structure according to claim 1, wherein: The packaging structure further includes a third conductive bump located between the interconnection structure and the substrate and electrically connecting the interconnection structure and the substrate.

9. The packaging structure according to claim 8, wherein: The packaging structure further includes: a second sealing layer located between the interconnection structure and the substrate, and filling the gap between the interconnection structure and the substrate and the gap between adjacent third conductive bumps.

10. A packaging method, characterized in that: include: providing a substrate; forming an interconnect structure comprising a redistribution layer and a first plastic encapsulation layer located on the redistribution layer, wherein the interconnect structure further comprises a chip bridge embedded in the first plastic encapsulation layer, wherein a surface of the chip bridge is exposed by the first plastic encapsulation layer, and a surface of the first plastic encapsulation layer exposed by the chip bridge serves as a bonding surface; providing a first chip; Providing chip structure; Bonding the chip structure and the first chip to the bonding surface of the interconnect structure, wherein the chip structure is located on the side of the first chip, the chip structure is electrically connected to the redistribution layer, the first chip is electrically connected to the redistribution layer, and the first chip is electrically connected to the chip structure via the chip bridge; After bonding the chip structure and the first chip to the bonding surface of the interconnection structure, the interconnection structure is bonded to the substrate, with the bonding surface facing away from the substrate.

11. The packaging method according to claim 10, wherein: In the step of forming the interconnection structure, on the bonding surface, the first plastic encapsulation layer is flush with the surface of the chip bridge.

12. The packaging method according to claim 10, wherein: In the step of forming the interconnection structure, the chip bridge penetrates the first plastic packaging layer and is electrically connected to the redistribution layer.

13. The packaging method according to claim 10, wherein: The steps of forming the interconnect structure include: providing a first carrier substrate; forming the chip bridge and a first plastic encapsulation layer of the first carrier substrate covering the sidewalls and side portions of the chip bridge on the first carrier substrate, wherein the first plastic encapsulation layer exposes the surface of the chip bridge, and the surface of the first plastic encapsulation layer and the chip bridge facing the first carrier substrate serves as the bonding surface; forming a redistribution layer covering the chip bridge and the first plastic encapsulation layer, wherein the redistribution layer, the first plastic encapsulation layer and the chip bridge constitute the interconnection structure; After forming the interconnection structure, the method further includes: removing the first carrier substrate.

14. The packaging method according to claim 13, wherein: The step of forming the chip bridge on the first carrier substrate and the first plastic packaging layer of the first carrier substrate covering the sidewalls and side portions of the chip bridge comprises: providing an initial chip bridge, comprising a substrate and a circuit structure layer located on the substrate; bonding the initial chip bridge to the first carrier substrate, wherein the circuit structure layer of the initial chip bridge faces the first carrier substrate; forming a first plastic encapsulation layer covering the initial chip bridge and the first carrier substrate; The initial chip bridge and the first plastic packaging layer are thinned to remove the substrate and the first plastic packaging layer higher than the circuit structure layer, and the remaining circuit structure layer is retained as the chip bridge.

15. The packaging method according to claim 13, wherein: The step of forming a redistribution layer covering the chip bridge and the first plastic encapsulation layer includes: forming a dielectric layer covering the chip bridge and the first plastic encapsulation layer; An electrical connection structure is formed that penetrates the dielectric layer. The electrical connection structure and the dielectric layer constitute the redistribution layer. On the side of the chip bridge, the electrical connection structure also penetrates the first plastic packaging layer.

16. The packaging method according to claim 13, wherein: The step of removing the first carrier substrate includes: bonding a second carrier substrate to the interconnect structure; Using the second carrier substrate as support, removing the first carrier substrate to expose the bonding surface; After bonding the chip structure and the first chip to the bonding surface of the interconnection structure and before bonding the interconnection structure to the substrate, the method further includes: removing the second carrier substrate.

17. The packaging method according to claim 10, wherein: After bonding the chip structure and the first chip to the bonding surface of the interconnect structure and before bonding the interconnect structure to the substrate, the packaging method further includes: forming a second plastic encapsulation layer on the first plastic encapsulation layer, wherein the second plastic encapsulation layer covers the side walls of the chip structure and the side walls of the first chip, and fills the space between the chip structure and the first chip.

18. The packaging method according to claim 10, wherein: After forming the interconnect structure and before bonding the chip structure and the first chip to the bonding surface of the interconnect structure, the packaging method further includes: forming a first conductive bump on the first plastic encapsulation layer of the bonding surface; forming a second conductive bump on the chip bridge of the bonding surface; In the step of bonding the chip structure and the first chip to the bonding surface of the interconnection structure, the first conductive bump electrically connects the redistribution layer to the first chip, and electrically connects the redistribution layer to the chip structure, and the second conductive bump electrically connects the chip bridge to the first chip, and electrically connects the chip bridge to the chip structure.

19. The packaging method according to claim 10, wherein: After bonding the chip structure and the first chip to the bonding surface of the interconnect structure and before bonding the interconnect structure to the substrate, the packaging method further includes: forming a third conductive bump on the substrate; In the step of bonding the interconnect structure to the substrate, the third conductive bump electrically connects the interconnect structure and the substrate.

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