A three-dimensional integrated dual-path modulation radio frequency front-end chip, device and equipment

Abstract

The application provides a three-dimensional integrated dual-path modulation radio frequency front-end chip, device and equipment, and relates to the technical field of radio frequency front-end integration. The chip comprises: a first layer, a second layer and a third layer stacked vertically from bottom to top; the first layer comprises a power amplifier switch chip; the second layer comprises a low-noise amplifier chip; the low-noise amplifier chip is interconnected with a transceiver switch in the power amplifier switch chip through a bonding process; the low-noise amplifier chip and the power amplifier chip are assembled together through gold-gold ball planting stacking and realize radio frequency signal transmission through hot-via; the third layer comprises a switch driver chip; the switch driver chip is adhered to the top of the low-noise amplifier chip through insulating glue. The application effectively solves the problem of large volume of the existing radio frequency front-end integration mode through the chip stacking and interconnection mode.

Description

Technical Field

[0001] This invention relates to the field of radio frequency front-end integration technology, and in particular to a three-dimensional integrated dual-channel modulation radio frequency front-end chip, device, and equipment. Background Technology

[0002] The radio frequency (RF) front-end (RF front-end) is a crucial component of wireless communication systems, located between the antenna and the baseband processing unit, responsible for processing RF signals. Its transmitting function involves modulating and up-converting the low-frequency signal output from the baseband processing unit into a high-frequency RF signal, amplifying its power, and then transmitting it through the antenna. Its receiving function involves amplifying the RF signal received by the antenna using a low-noise amplifier in the RF front-end to increase signal strength, followed by filtering and down-conversion to convert the RF signal into a low-frequency signal that the baseband processing unit can process. In the post-Moore's Law era, increasing the integration density of the RF front-end through traditional methods of shrinking transistor size has become extremely difficult. Currently, RF front-ends are developing towards miniaturization, diversification, and intelligence.

[0003] Monolithic heterogeneous integration technology has attracted attention due to its high integration density. Traditional RF front-ends use a tiled layout, integrating multiple chips with different functions (such as power amplifiers, low-noise amplifiers, transceiver switches, and switch drivers) together in a plane using micro-assembly processes. The tiled layout, with multiple chips scattered in a plane, results in a large overall size, which cannot meet the miniaturization requirements of electronic systems. Summary of the Invention

[0004] This invention provides a three-dimensional integrated dual-channel modulation radio frequency front-end chip, device, and equipment to solve the problem of large size in existing radio frequency front-end integration methods.

[0005] In a first aspect, embodiments of the present invention provide a three-dimensional integrated dual-channel modulation radio frequency front-end chip, comprising: a first layer, a second layer, and a third layer stacked vertically from bottom to top; the first layer includes a power amplifier switch chip; the second layer includes a low-noise amplifier chip; the low-noise amplifier chip is interconnected with a transceiver switch in the power amplifier switch chip via a bonding process; the low-noise amplifier chip and the power amplifier chip are assembled together by gold-plated ball stacking and radio frequency signal transmission is achieved via hot-via; the third layer includes a switch driver chip; the switch driver chip is bonded to the top of the low-noise amplifier chip with insulating adhesive.

[0006] In one possible implementation, the power amplifier switch chip includes a power amplifier and a transceiver switch; the power amplifier and the transceiver switch are fabricated on the same chip using a monolithic integration process, forming the power amplifier switch chip.

[0007] In one possible implementation, the areas of the first, second, and third layers increase sequentially from top to bottom.

[0008] In one possible implementation, the power amplifier switch chip is fabricated using GaN technology.

[0009] In one possible implementation, the low-noise amplifier chip is fabricated using a GaAs process.

[0010] In one possible implementation, the switch driver chip is fabricated using a CMOS process.

[0011] In one possible implementation, the circuit topology of the RF front-end chip includes two channels with a symmetrical structure; each channel includes a transmit link and a receive link; each channel is equipped with a single-pole double-throw switch; the transmit channel and the receive channel are separated by the single-pole double-throw switch driven by the switch driver, thereby realizing the switching of the transmit and receive links.

[0012] In one possible implementation, the transmit links of both channels operate simultaneously to enable signal transmission from the radio frequency front end; the receive links of both channels operate simultaneously to enable signal reception from the radio frequency front end.

[0013] In a second aspect, embodiments of the present invention provide a three-dimensional integrated dual-channel modulation radio frequency front-end device, comprising the three-dimensional integrated dual-channel modulation radio frequency front-end chip described in any one of the first aspects.

[0014] Thirdly, embodiments of the present invention provide a three-dimensional integrated dual-channel modulation radio frequency front-end device, including the three-dimensional integrated dual-channel modulation radio frequency front-end device in the second aspect.

[0015] This invention provides a three-dimensional integrated dual-channel modulation RF front-end chip, device, and equipment. By employing a bottom-up vertical stacking method, a power amplifier switch chip, a low-noise amplifier chip, and a switch driver chip are stacked vertically. This three-dimensional integration method changes the chip layout, significantly reducing the area occupied on the plane compared to a flat layout, thus effectively controlling the overall size. The low-noise amplifier chip and the transceiver switches in the power amplifier switch chip are interconnected via bonding technology. The low-noise amplifier and power amplifier are assembled using gold-to-gold ball-mounted stacking, and RF signal transmission is achieved using hot-vias. The switch driver chip is bonded to the low-noise amplifier chip with insulating adhesive. These specific interconnection and assembly processes tightly connect the chips, making the connections between chips more compact and avoiding the significant space waste that may result from traditional connection methods. For example, the hot-via technology used in the gold-to-gold ball-mounted stacking effectively shortens the distance between chips and reduces the length of the signal transmission path while achieving signal transmission, thereby optimizing the connection space between chips while achieving functionality and contributing to a reduction in overall size. The three-dimensional integrated dual-channel modulation RF front-end chip of this invention effectively solves the problem of large size in existing RF front-end integration methods through chip stacking and interconnection. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a three-dimensional integrated dual-channel modulation radio frequency front-end chip provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the circuit topology of the dual-channel modulation radio frequency front-end chip provided in an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0019] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0020] The implementation of the present invention will be described in detail below with reference to the accompanying drawings:

[0021] Figure 1 This is a schematic diagram of the structure of a three-dimensional integrated dual-channel modulation radio frequency front-end chip provided in an embodiment of the present invention. Figure 1 This is a schematic diagram of a stacked dual-channel modulation chip structure. (Refer to...) Figure 1 The RF front-end chip includes: a first layer 101, a second layer 102, and a third layer 103 stacked vertically from bottom to top; the first layer 101 includes a power amplifier switch chip; the second layer 102 includes a low-noise amplifier chip; the low-noise amplifier chip is interconnected with the transceiver switch in the power amplifier switch chip through a bonding process; the low-noise amplifier and the power amplifier are assembled together by gold-plated ball stacking and RF signal transmission is achieved through hot-via; the third layer 103 includes a switch driver chip; the switch driver chip is bonded to the top of the low-noise amplifier with insulating adhesive.

[0022] In some embodiments, the radio frequency (RF) front-end chip includes a first layer 101, a second layer 102, and a third layer 103 stacked vertically from bottom to top. The RF front-end chip provided in this embodiment of the invention adopts a vertically stacked three-layer structure, achieving high integration and high performance through heterogeneous integration and specific interconnect processes. The chip is divided into a first layer 101, a second layer 102, and a third layer 103 from bottom to top, significantly reducing the planar size by replacing the traditional flat layout with vertical stacking.

[0023] In some embodiments, the first layer 101 includes a power amplifier switch chip. For example, the first layer 101 integrates a power amplifier (PA) and a transceiver switch. Compared to the traditional approach of designing and assembling the power amplifier and transceiver switch separately, this approach integrates them into a single chip, avoiding secondary matching during assembly, reducing size, and improving performance consistency.

[0024] For example, the power amplifier switch chip is fabricated using GaN technology.

[0025] In some embodiments, the second layer 102 includes a low-noise amplifier chip. For example, the low-noise amplifier chip is responsible for amplifying the signals received from the link.

[0026] For example, the low-noise amplifier chip is fabricated using GaAs technology.

[0027] For example, the low-noise amplifier chip is interconnected with the transceiver switch in the power amplifier switch chip via a bonding process. The low-noise amplifier and the power amplifier in the power amplifier switch chip are assembled together using gold-to-gold ball-mounted stacking, and RF signal transmission is achieved through hot-vias. The low-noise amplifier chip is connected to the underlying power amplifier switch chip in two ways. First, it is assembled with the power amplifier section via gold-to-gold ball-mounted stacking, utilizing hot-vias to achieve vertical transmission of RF signals, ensuring signal transmission efficiency. Second, it is electrically connected to the transceiver switch section via a bonding process (such as bonding wire interconnection), ensuring switching control of the transceiver link. Furthermore, in the gold-to-gold ball-mounted stacking process, to ensure the alignment accuracy of the hot-via pads (critical interconnect points) of the low-noise amplifier chip and the power amplifier switch chip, the hot-via pads are slightly larger than the conventional ground pads. For example, the hot-via pad size is 160×100μm, while the ground pad size is 100×100μm.

[0028] In some embodiments, the third layer 103 includes a switch driver chip; the switch driver chip is bonded to the top of the low-noise amplifier with insulating adhesive.

[0029] For example, the switch driver chip is responsible for driving the state switching of the transceiver switch, realizing the switching of the transmit / receive link. The switch driver chip is bonded to the low-noise amplifier in the middle layer with insulating adhesive, and is also interconnected with the transceiver switch on the bottom layer through a bonding process to complete the transmission of control signals.

[0030] For example, the switch driver chip is fabricated using CMOS technology.

[0031] It should be noted that vertical stacking replaces flat tiling, with the three layers of chips arranged compactly in the vertical direction, significantly reducing the overall size. The integrated design of the power amplifier and switch avoids signal loss caused by secondary matching, improving broadband performance. Hot-via and gold-to-gold ball-mounted stacking processes ensure efficient RF signal transmission and reduce path loss. Optimal processes are used for different functional chips (GaN for power amplifiers, GaAs for low-noise amplifiers, and CMOS for drivers), achieving a balance between performance and cost through heterogeneous integration.

[0032] This invention provides a three-dimensional integrated dual-channel modulation RF front-end chip, device, and equipment. By employing a bottom-up vertical stacking method, the power amplifier switch chip, low-noise amplifier chip, and switch driver chip are stacked vertically. This three-dimensional integration method changes the chip layout, significantly reducing the area occupied on the plane compared to a flat layout, thus effectively controlling the overall size.

[0033] Furthermore, the low-noise amplifier chip and the transceiver switches in the power amplifier switch chip are interconnected via bonding technology. The low-noise amplifier and power amplifier are assembled using gold-to-gold ball-mounted stacking and RF signal transmission is achieved using hot-via. The switch driver chip is bonded to the low-noise amplifier with insulating adhesive. These specific interconnection and assembly processes tightly connect the various chips, making the connections between chips more compact and avoiding the significant space waste that may result from traditional connection methods. For example, the gold-to-gold ball-mounted stacking with hot-via technology can effectively shorten the distance between chips and reduce the length of the signal transmission path while achieving signal transmission, thereby optimizing the connection space between chips while achieving functionality and helping to reduce the overall size. The three-dimensional integrated dual-channel modulation RF front-end chip of this invention effectively solves the problem of large size in existing RF front-end integration methods through chip stacking and interconnection.

[0034] In traditional designs, the power amplifier and transceiver switch are two separate chips that need to be manufactured separately and then assembled using micro-assembly processes. For example, they require separate manufacturing and assembly, secondary matching and impedance adjustment, large space requirements when spliced ​​together, performance differences due to assembly errors, and signal loss and matching compensation required between the chips. The following embodiments of this invention integrate the power amplifier (PA) and transceiver switch onto a single chip using a monolithic integration process, forming a power amplifier-switch chip.

[0035] In one possible implementation, the power amplifier switch chip includes a power amplifier and a transceiver switch; the power amplifier and the transceiver switch are fabricated on the same chip using a monolithic integration process, forming the power amplifier switch chip.

[0036] This invention integrates power amplifier and transceiver switch into a single chip, achieving both power amplification and transceiver switching. Monolithic integration eliminates the splicing gap and additional connection structures between two chips, significantly reducing the overall size of the RF front-end and meeting the miniaturization requirements of devices. Simultaneously, it avoids the secondary matching between chips in traditional discrete designs (signal reflection / loss due to assembly gaps and impedance mismatch), resulting in superior signal transmission stability and efficiency, especially in broadband scenarios. Furthermore, it reduces assembly steps after chip manufacturing, lowers production complexity, improves performance consistency during mass production, and avoids individual performance fluctuations caused by assembly differences. This invention integrates the power amplifier and transceiver switch into a single chip, resulting in a smaller power amplifier switch chip with a simpler assembly process and better consistency. This meets the requirements of miniaturization and high performance for the entire system, further improving the performance of the RF front-end of the overall system.

[0037] In one possible implementation, the areas of the first layer 101, the second layer 102, and the third layer 103 increase sequentially from top to bottom.

[0038] It should be noted that the areas of the first layer 101, the second layer 102, and the third layer 103 increase from top to bottom, that is, the top layer (third layer, switch driver chip) has the smallest area, the middle layer (second layer 102, low noise amplifier chip) has the next largest area, and the bottom layer (first layer, power amplifier switch chip) has the largest area.

[0039] Three-layer chips require electrical connections through processes such as bonding and ball-mounting. The upper layer chip has a smaller area than the lower layer, allowing sufficient space for connection operations. For example, the top-layer switch driver chip needs to interconnect with the bottom-layer transceiver switch via bonding. If the top layer's area is smaller than the middle and bottom layers, it avoids obstructing the bonding pads of the middle and bottom layers, ensuring the bonding wires can extend from the edge of the top-layer chip to the corresponding pads of the bottom-layer chip, simplifying bonding operations and reducing the risk of short circuits. As another example, the middle-layer low-noise amplifier needs to connect to the bottom-layer power amplifier via gold-to-gold ball-mounting and transmit RF signals via hot-via. The middle layer's smaller area allows the bottom-layer chip's pads and hot-via interfaces to be fully exposed, facilitating precise alignment during ball-mounting and the design of signal transmission paths.

[0040] Vertically stacked chips require a stable mechanical structure, and a design where the upper layer has a smaller area than the lower layer reduces the risk of center of gravity shift. For example, the bottom chip (power amplifier switch chip) has the largest area, serving as the base of the entire stacked structure and providing more stable support, reducing tilting or detachment caused by uneven weight distribution of upper chips. The upper chip (switch driver) has the smallest area, reducing pressure on the middle and bottom layers. Especially when used with insulating adhesive bonding, this reduces the risk of cracking caused by uneven stress on the adhesive, improving the overall structural reliability.

[0041] Figure 2 This is a schematic diagram of the circuit topology of the dual-channel modulation radio frequency front-end chip provided in an embodiment of the present invention. (Refer to...) Figure 2 PA stands for power amplifier, LNA stands for low noise amplifier, RF1 and RF3 are the transmit links, and RF2 and RF4 are the receive links.

[0042] In one possible implementation, the circuit topology of the RF front-end chip includes two channels with a symmetrical structure; each channel includes a transmit link and a receive link; each channel is equipped with a single-pole double-throw switch; the transmit channel and the receive channel are separated by the single-pole double-throw switch driven by the switch driver, thereby realizing the switching of the transmit and receive links.

[0043] The RF front-end chip adopts a symmetrical dual-path design in its circuit topology, and the transceiver link is flexibly switched through a single-pole double-throw switch.

[0044] The circuit is divided into two channels, which can be understood as an upper channel and a lower channel. The two channels are completely symmetrical, meaning that the circuit composition, component parameters, and connection methods of each channel are identical. The advantages of this symmetrical design are: it enables parallel processing of signals in both channels, improving the system's signal processing efficiency; the symmetrical structure reduces interference between the two signals, ensuring the consistency of signal transmission, such as matching performance parameters like gain and loss.

[0045] Each channel contains two independent links. The transmit link is responsible for amplifying the radio frequency signal to be transmitted through a power amplifier and outputting it; the receive link is responsible for receiving external radio frequency signals and amplifying them with a low-noise amplifier for subsequent processing.

[0046] Two links share some interfaces of the channel, such as the RF signal input / output terminals, but are completely independent in function and need to be isolated and switched by a switch.

[0047] Each channel is equipped with a single-pole double-throw switch, which is used to select either the transmit link or the receive link to achieve physical isolation and functional switching between the two.

[0048] For example, in the transmit link, the RF switches at both the input and output ends adopt a pure parallel topology, with one switch connected in parallel at each of the input and output ends;

[0049] For example, in the receiving link, the RF switch at the input end adopts a two-stage parallel topology, and the output end adopts a series-parallel topology, consisting of a parallel switch and a series switch.

[0050] For example, the RF front-end chip is divided into upper and lower channels with a symmetrical structure. A high-isolation single-pole double-throw switch is driven by a switch driver to separate the transmit channel and the receive channel, thereby realizing the switching of the transmit and receive links.

[0051] In one possible implementation, the transmit links of both channels operate simultaneously to enable signal transmission from the radio frequency front end; the receive links of both channels operate simultaneously to enable signal reception from the radio frequency front end.

[0052] It should be noted that the dual-channel cooperative working mode in both transmit and receive states means that the transmit links of the two channels are started simultaneously to enhance the transmit capability, and the receive links are started simultaneously to improve the receive performance. The efficient signal processing of the RF front end is achieved through the parallel operation of the two channels.

[0053] The broadband dual-channel modulation RF front-end circuit topology of this invention is divided into upper and lower channels, which are symmetrical in structure. A high-isolation single-pole double-throw switch driven by a switch driver separates the transmit and receive channels, realizing the switching of the transmit and receive links. Specifically, RF-1 and RF-3 operate simultaneously as the transmit link; RF-2 and RF-4 operate simultaneously as the receive link.

[0054] This invention provides a three-dimensional integrated dual-channel modulation radio frequency front-end device, including a three-dimensional integrated dual-channel modulation radio frequency front-end chip in any of the above possible implementations.

[0055] This invention provides a three-dimensional integrated dual-channel modulation radio frequency front-end device, including the aforementioned three-dimensional integrated dual-channel modulation radio frequency front-end device.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensionally integrated dual-path modulated radio frequency front-end chip, characterized by, include: The first, second, and third layers are stacked vertically from bottom to top; The first layer includes a power amplifier switch chip; The second layer includes a low-noise amplifier chip; the low-noise amplifier chip is interconnected with the transceiver switch in the power amplifier switch chip through a bonding process; the low-noise amplifier chip and the power amplifier chip are assembled together by gold-gold ball stacking and radio frequency signal transmission is achieved through hot-via. The third layer includes a switch driver chip; the switch driver chip is bonded to the top of the low-noise amplifier chip with insulating adhesive. The power amplifier switching chip includes a power amplifier and a transceiver switch; The power amplifier and transceiver switch are fabricated on the same chip using a monolithic integration process, forming a power amplifier-switch chip. The area of ​​the first, second, and third layers increases sequentially from top to bottom; The power amplifier switch chip is fabricated using GaN technology; the low-noise amplifier chip is fabricated using GaAs technology; and the switch driver chip is fabricated using CMOS technology.

2. The three-dimensional integrated dual-channel modulation RF front-end chip as described in claim 1, characterized in that, The circuit topology of the radio frequency front-end chip includes two channels with a symmetrical structure. Each channel includes a transmit link and a receive link; Each channel is equipped with a single-pole double-throw switch; The transmit and receive channels are separated by a single-pole double-throw switch driven by a switch driver, enabling the switching of the transmit and receive links.

3. The three-dimensional integrated dual-channel modulation RF front-end chip as described in claim 1, characterized in that, The two transmission links operate simultaneously to enable signal transmission from the radio frequency front end; the two reception links operate simultaneously to enable signal reception from the radio frequency front end.

4. A three-dimensional integrated dual-channel modulation radio frequency front-end device, characterized in that, Includes a three-dimensional integrated dual-channel modulation radio frequency front-end chip as described in any one of claims 1 to 3.

5. A three-dimensional integrated dual-channel modulation radio frequency front-end device, characterized in that, Includes the three-dimensional integrated dual-channel modulation radio frequency front-end device as described in claim 4.

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