A mid-band massive MIMO prototype system

Abstract

The application relates to a medium frequency band super large scale MIMO prototype system, which comprises a user end and a base station end comprising an upper computer module and subsystems, the original bit stream or the received bit stream is transmitted and received by the upper computer module, the corresponding downlink and uplink positive and negative combination processing of modulation and coding is carried out on the baseband MIMO signal processing module in the subsystem, and the corresponding downlink and uplink positive and negative combination processing of modulation, frequency conversion and conversion is carried out on the analog-digital conversion and digital intermediate frequency module in the subsystem, the frequency conversion and transceiving of the radio frequency signal are realized by the first radio frequency front end module in the subsystem, and then the communication with the user end is realized; the designed prototype system satisfies the medium frequency band super large scale MIMO system configuration, has the characteristics of flexible expansion and deployment, supports the real-time uplink and downlink data service transmission of multiple users, has large bandwidth and high throughput, and can be used for key technology verification and rapid deployment test of advanced communication algorithms.

Description

Technical Field

[0001] This invention relates to a mid-band ultra-large-scale MIMO prototype system, belonging to the field of wireless communication technology. Background Technology

[0002] Mid-band ultra-large-scale MIMO technology leverages the abundant spectrum resources of the mid-band and is considered one of the potential key technologies for mobile communications.

[0003] Mid-band frequencies, as an emerging spectrum resource for 6G, possess both bandwidth and coverage advantages and are considered one of the key frequency bands for 6G. Ultra-large-scale MIMO technology, as an evolution of massive MIMO technology, increases the number of antennas by configuring ultra-large-scale array antennas at the base station, deeply exploring the spatial resource dimension, and is expected to support massive user spatial multiplexing transmission, thereby achieving a significant improvement in spectrum efficiency.

[0004] From a practical deployment perspective, mid-band ultra-large-scale MIMO systems need to support real-time processing of massive amounts of data, high-speed data interaction, and high scalability for flexible system deployment. To explore the effectiveness of mid-band ultra-large-scale MIMO technology in real-world scenarios and to deploy and validate advanced algorithms, the assumptions of a prototype system are particularly important. Therefore, designing a prototype system for mid-band ultra-large-scale MIMO technology is beneficial for leveraging the advantages of the ultra-large-scale MIMO wireless transmission system. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a mid-band ultra-large-scale MIMO prototype system with flexible expansion characteristics and support for multi-user real-time signal processing. It can be used for key technology verification and rapid deployment of advanced communication algorithms in the development of mid-band ultra-large-scale MIMO systems, and has significant economic benefits.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention designs a mid-band ultra-large-scale MIMO prototype system, including a base station and a user terminal that communicate with each other. The base station includes a host computer module and at least one subsystem connected and communicating with the host computer module. The structures of each subsystem are the same. Each subsystem includes a baseband MIMO signal processing module, an analog-to-digital converter and digital intermediate frequency module, and a first radio frequency front-end module connected in series. The host computer module is connected to the baseband MIMO signal processing module in each subsystem for communication. Through communication between the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module, the host computer module sends control commands to the analog-to-digital converter and digital intermediate frequency module, and the analog-to-digital converter and digital intermediate frequency module reads data for analysis and debugging.

[0007] In the downlink at the base station, the raw bit stream is output by the host computer module, and then undergoes modulation and coding processing by the baseband MIMO signal processing module in the subsystem, and modulation and frequency conversion processing by the analog-to-digital conversion and digital intermediate frequency module, before being transmitted by the first radio frequency front-end module. In the uplink at the base station, the radio frequency signal is received by the first radio frequency front-end module in the subsystem, and then undergoes conversion and modulation processing by the analog-to-digital conversion and digital intermediate frequency module, and encoding and modulation processing by the baseband MIMO signal processing module before being uploaded to the host computer module.

[0008] As a preferred embodiment of the present invention: the host computer module in the base station includes a host, a PXIe chassis, a PXIe controller, and a PXIe timing synchronization unit. The host is connected to the PXIe controller via Ethernet for communication. The PXIe controller and the PXIe timing synchronization unit are respectively connected to the communication carrier of the PXIe chassis via PXIe interfaces. Based on the communication carrier of the PXIe chassis, communication interaction between the PXIe controller and the PXIe timing synchronization unit is realized. The communication carrier of the PXIe chassis also interfaces with the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module in each subsystem via PXIe interfaces, realizing communication between the host computer module and the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module in the subsystem. The host computer module is used for application development, configuration and deployment, as well as system initialization, parameter configuration and module scheduling.

[0009] As a preferred technical solution of the present invention: the baseband MIMO signal processing module in the base station includes an FPGA coprocessing unit and at least one PXIe bus expansion card. The FPGA coprocessing unit and each PXIe bus expansion card are respectively connected to the communication carrier of the PXIe chassis in the host computer module through the PXIe interface, so that the PXIe controller in the host computer module can communicate with the FPGA coprocessing unit through the communication carrier of the PXIe chassis. The FPGA coprocessing unit connects to the analog-to-digital converter and digital intermediate frequency module in the same subsystem through a high-speed interface to transmit data signals. Each PXIe bus expansion card connects to the analog-to-digital converter and digital intermediate frequency module in the same subsystem through a high-speed interface, so that the PXIe bus expansion card can transmit control signals to the connected analog-to-digital converter and digital intermediate frequency module. The PXIe controller in the host computer module reads the baseband data related to the communication of the analog-to-digital converter and digital intermediate frequency module through the communication carrier of the PXIe chassis and the PXIe bus expansion card, and performs analysis and debugging in the PXIe controller.

[0010] In the baseband MIMO signal processing module, based on the control signal, in the downlink of the base station, the FPGA coprocessing unit first performs QAM modulation to obtain the corresponding QAM symbol sequence for the raw bit stream output from the host computer module, then adds preset pilot framing, and finally performs precoding processing to output the digital signal to the analog-to-digital conversion and digital intermediate frequency module in the same subsystem.

[0011] In the uplink of the base station, the FPGA coprocessing unit first performs channel estimation processing, channel equalization processing, and signal detection processing sequentially on the digital signal output from the analog-to-digital converter and digital intermediate frequency module to obtain the corresponding QAM symbol sequence. Then, after QAM demodulation, the corresponding original bit stream is obtained and uploaded to the host computer module.

[0012] As a preferred technical solution of the present invention: the analog-to-digital conversion and digital intermediate frequency module in the base station includes at least one USRP software radio device, and each USRP software radio device is connected to each PXIe bus expansion card in the baseband MIMO signal processing module of the same subsystem to realize control signal transmission; at the same time, each USRP software radio device is connected to the FPGA coprocessing unit in the baseband MIMO signal processing module of the same subsystem to realize data signal transmission;

[0013] In the analog-to-digital conversion and digital intermediate frequency module, each USRP software-defined radio device is connected to the first RF front-end module in the same subsystem via a low-loss SMA cable to transmit analog intermediate frequency signals; at the same time, each USRP software-defined radio device is connected to the first RF front-end module in the same subsystem via a GPIO interface to transmit control signals.

[0014] In the downlink at the base station, the USRP software radio device sequentially performs OFDM modulation, digital up-conversion, I / Q calibration, and digital-to-analog signal conversion on the digital signal output from the FPGA coprocessor unit in the baseband MIMO signal processing module of the same subsystem to obtain the corresponding analog intermediate frequency signal, and outputs it to the first radio frequency front-end module in the same subsystem.

[0015] In the uplink of the base station, the USRP software radio device sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration on the analog intermediate frequency signal output from the first radio frequency front-end module in the same subsystem to obtain the corresponding digital signal, and outputs it to the FPGA coprocessing unit in the baseband MIMO signal processing module in the same subsystem.

[0016] Each USRP software radio device sends a control signal to the first radio front-end module based on the wireless frame format received from the PXIe controller in the host computer module via control signals, in order to control the first radio front-end module to switch between uplink and downlink functions.

[0017] As a preferred technical solution of the present invention: the MGT high-speed transceiver interface of the FPGA coprocessing unit in the baseband MIMO signal processing module of the base station is connected to the QSFP28 interface of the first USRP software radio device in each USRP software radio device group in the analog-to-digital conversion and digital intermediate frequency module of the same subsystem, so as to realize the high-speed interface connection between the FPGA coprocessing unit and each USRP software radio device, and realize data signal transmission through the Aurora protocol.

[0018] In the analog-to-digital conversion and digital intermediate frequency module, each USRP software radio device is connected to the Mini SAS HD interface of each PXIe bus expansion card in the baseband MIMO signal processing module of the same subsystem via its Mini SAS HD interface. This enables high-speed interface docking between each USRP software radio device and the connected PXIe bus expansion card, and control signal transmission is achieved through the PCIe protocol.

[0019] As a preferred embodiment of the present invention: the first radio frequency front-end module in the base station includes a local oscillator unit, at least one TR component unit, and at least one antenna unit. Each antenna unit is connected to each TR component unit via an equal-phase low-loss radio frequency SMA cable. Each USRP software radio device in the analog-to-digital conversion and digital intermediate frequency module is connected to each TR component unit, enabling analog intermediate frequency signal transmission between each USRP software radio device and its connected TR component unit. Each TR component unit is connected to the local oscillator unit via a radio frequency line, and the local oscillator unit provides a unified local oscillator signal to each TR component unit. Each TR component unit includes a transmit link and a receive link.

[0020] In the base station, each TR component unit switches the transmit link to form the downlink of the base station or switches the receive link to form the uplink of the base station based on the received control signal. In the uplink of the base station, the TR component unit receives the radio frequency signal received and forwarded by the connected antenna unit, performs downconversion processing to obtain the corresponding analog intermediate frequency signal, and outputs it to the corresponding USRP software radio device. In the downlink of the base station, the TR component unit receives the analog intermediate frequency signal output by the corresponding USRP software radio device, performs upconversion processing to obtain the corresponding radio frequency signal, and outputs it to the corresponding antenna unit for transmission.

[0021] As a preferred embodiment of the present invention: the user terminal includes an intermediate frequency (IF) and baseband MIMO signal processing module and a second radio frequency (RF) front-end module that are interconnected. The IF and baseband MIMO signal processing module includes a PXIe controller, a PXIe timing synchronization unit, a PXIe chassis, at least one PXIe bus expansion card, and at least one USRP software-defined radio device. The PXIe controller, PXIe timing synchronization unit, and each PXIe bus expansion card are respectively connected to the communication carrier of the PXIe chassis, and communication interaction between the PXIe controller, PXIe timing synchronization unit, and each PXIe bus expansion card is realized based on the communication carrier of the PXIe chassis. Each USRP software-defined radio device connects to the Mini SAS HD interface of each PXIe bus expansion card via its Mini SAS HD interface, realizing high-speed interface interfacing between each USRP software-defined radio device and the connected PXIe bus expansion card, and transmitting data signals and control signals via the PCIe protocol. Each USRP software-defined radio device is connected to the second RF front-end module.

[0022] In the downlink at the user end, the second RF front-end module receives and processes RF signals to obtain analog intermediate frequency signals, which are then forwarded to the connected USRP software radio equipment. The USRP software radio equipment then sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration to obtain the corresponding digital signals. The FPGA inside the USRP software radio equipment then sequentially performs channel estimation, channel equalization, and signal detection to obtain the corresponding QAM symbol sequence. After QAM demodulation, the corresponding raw bit stream is obtained and forwarded to the connected PXIe bus expansion card. The PXIe bus expansion card then uploads the data to the PXIe controller or other PXIe interface cards.

[0023] In the uplink at the user end, the PXIe controller outputs the raw bit stream to the PXIe bus expansion card, which forwards it to the connected USRP software radio device. The FPGA inside the USRP software radio device first performs QAM modulation to obtain the corresponding QAM symbol sequence, then adds preset pilot frames, and sequentially performs OFDM modulation, digital upconversion, I / Q calibration, and digital-to-analog signal conversion to obtain the corresponding analog intermediate frequency signal, which is then output to the connected second RF front-end module. The second RF front-end module processes the analog intermediate frequency signal to obtain the RF signal for transmission.

[0024] Alternatively, the user terminal may include an intermediate frequency (IF) and baseband MIMO signal processing module and a second radio frequency (RF) front-end module that are interconnected. The IF and baseband MIMO signal processing module includes at least one USRP software radio device, at least one PCIe bus expansion card, and at least one host. Each host and each PCIe bus expansion card are connected and communicate with each other through the PCIe slots inside the host. Each USRP software radio device is connected to the Mini SAS HD interface of each PCIe bus expansion card via its Mini SAS HD interface, enabling high-speed interface docking between each USRP software radio device and the connected PCIe bus expansion card, and transmitting data signals and control signals through the PCIe protocol. Each USRP software radio device is connected to the second RF front-end module.

[0025] In the downlink at the user end, the second RF front-end module receives and processes RF signals to obtain analog intermediate frequency signals, which are then forwarded to the connected USRP software radio device. The USRP software radio device then sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration to obtain the corresponding digital signals. The FPGA inside the USRP software radio device first sequentially performs channel estimation processing, channel equalization processing, and signal detection processing to obtain the corresponding QAM symbol sequence. After QAM demodulation, the corresponding raw bit stream is obtained and forwarded to the connected PCIe bus expansion card, which then uploads it to the host.

[0026] In the uplink at the user end, the host outputs the raw bit stream to the PCIe bus expansion card, which forwards it to the connected USRP software radio device. The FPGA inside the USRP software radio device first performs QAM modulation to obtain the corresponding QAM symbol sequence, then adds preset pilot framing, and performs precoding processing. After that, OFDM modulation, digital upconversion, I / Q calibration, and digital-to-analog signal conversion are performed in sequence to obtain the corresponding analog intermediate frequency signal, which is then output to the connected second RF front-end module. The second RF front-end module processes the analog intermediate frequency signal to obtain the RF signal for transmission.

[0027] As a preferred embodiment of the present invention: the second radio frequency front-end module in the user terminal includes a local oscillator unit, at least one TR component unit, and at least one antenna unit. Each antenna unit is grouped and connected to each TR component unit via radio frequency lines. Each USRP software radio device in the user terminal is grouped and connected to each TR component unit, enabling analog intermediate frequency signal transmission and control signal transmission between each USRP software radio device and its connected TR component unit. Each TR component unit is connected to the local oscillator unit via radio frequency lines, and the local oscillator unit provides a unified local oscillator signal to each TR component unit. Each TR component unit includes a transmit link and a receive link.

[0028] In the user terminal, each TR component unit switches the transmit link to form the user terminal's uplink or switches the receive link to form the user terminal's downlink based on the received control signal. In the user terminal's downlink, the TR component unit receives and processes the radio frequency signal received and forwarded by the connected antenna unit to obtain the corresponding analog intermediate frequency signal, and outputs it to the corresponding USRP software radio device. In the user terminal's uplink, the TR component unit receives and processes the analog intermediate frequency signal output by the corresponding USRP software radio device to obtain the corresponding radio frequency signal, and outputs it to the corresponding antenna unit for transmission.

[0029] As a preferred embodiment of the present invention: the structures of each TR component unit are identical. In the structure of each TR component unit, one end of the first single-pole double-throw switch is connected to the corresponding antenna unit. One end of the first single-pole double-throw switch is connected in series from input to output with a first low-noise amplifier, a first bandpass filter, and a second low-noise amplifier. The output end of the second low-noise amplifier is connected to one end of the second single-pole double-throw switch. The other end of the second single-pole double-throw switch is connected in series with a drive amplifier from input to output. The system consists of a first bandpass filter, a power amplifier, and an output terminal of the power amplifier connected to the other end of the first single-pole double-throw switch. The second single-pole double-throw switch is connected in series with a second bandpass filter, a mixer, and a third bandpass filter, and then connected to the first end of the third single-pole double-throw switch. The mixer receives the local oscillator signal and operates accordingly. The two ends of the third single-pole double-throw switch are respectively connected to the input terminal of the first variable gain amplifier and the output terminal of the second variable gain amplifier. The output terminal of the first variable gain amplifier and the input terminal of the second variable gain amplifier are respectively connected to the USRP software-defined radio device.

[0030] The TR component unit controls the first, second, and third single-pole double-throw (SPD) switches to operate synchronously based on the received control signal. A receiving link is formed by sequentially connecting a first low-noise amplifier, a first bandpass filter, a second low-noise amplifier, a second bandpass filter, a mixer, a third bandpass filter, and a first variable gain amplifier; alternatively, a transmitting link is formed by sequentially connecting a second variable gain amplifier, a third bandpass filter, a mixer, a second bandpass filter, a driver amplifier, a first bandpass filter, and a power amplifier. In the receiving link, the receiving antenna unit receives and forwards the RF signal, sequentially performing low-noise amplification, filtering, low-noise amplification, filtering, down-conversion, filtering, and gain amplification to obtain the corresponding analog intermediate frequency (IF) signal, which is then output to the corresponding USRP software-defined radio device. In the transmitting link, the receiving antenna unit receives the analog IF signal output from the corresponding USRP software-defined radio device, sequentially performing gain amplification, filtering, up-conversion, filtering, driver amplification, filtering, and power amplification to obtain the corresponding RF signal, which is then output to the corresponding antenna unit for transmission.

[0031] The mid-frequency ultra-large-scale MIMO prototype system described in this invention, compared with existing technologies, has the following technical advantages:

[0032] This invention designs a mid-band ultra-large-scale MIMO prototype system, including a user terminal and a base station terminal including a host computer module and various subsystems. The host computer module transmits and receives the original bit stream or received bit stream. Through the baseband MIMO signal processing module in the subsystem, corresponding to the downlink and uplink modulation and coding combinations, and the analog-to-digital conversion and digital intermediate frequency modules in the subsystem, corresponding to the downlink and uplink modulation, frequency conversion, and conversion combinations, the first radio frequency front-end module in the subsystem realizes the frequency conversion and transmission and reception of the radio frequency signal, thereby realizing communication with the user terminal. The prototype system designed in this invention meets the configuration of a mid-band ultra-large-scale MIMO system, has flexible expansion and deployment characteristics, supports multi-user real-time uplink and downlink data service transmission, has large bandwidth and high throughput, and can be used for key technology verification and rapid deployment testing of advanced communication algorithms. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the base station end in the mid-band ultra-large-scale MIMO prototype system designed in this invention;

[0034] Figure 2 This is a schematic diagram of the link communication at the base station end in the mid-band ultra-large-scale MIMO prototype system designed in this invention;

[0035] Figure 3 This is a schematic diagram of a user-end embodiment in the mid-band ultra-large-scale MIMO prototype system designed in this invention;

[0036] Figure 4 This is a schematic diagram of the second embodiment of the user end in the mid-frequency ultra-large-scale MIMO prototype system designed in this invention;

[0037] Figure 5 This is a schematic diagram of the link communication at the user end in the mid-band ultra-large-scale MIMO prototype system designed in this invention;

[0038] Figure 6 This is a schematic diagram of the TR component unit in the user terminal of the mid-frequency ultra-large-scale MIMO prototype system designed in this invention. Detailed Implementation

[0039] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0040] This invention designs a mid-band ultra-large-scale MIMO prototype system, including a base station and a user terminal that communicate with each other. In practical applications, such as... Figure 1 As shown, the specific design of the base station includes a host computer module and at least one subsystem connected and communicating with the host computer module. The structures of each subsystem are the same. Each subsystem includes a baseband MIMO signal processing module, an analog-to-digital converter and digital intermediate frequency module, and a first radio frequency front-end module connected in series. The host computer module is connected to the baseband MIMO signal processing module in each subsystem for communication. It also communicates with the analog-to-digital converter and digital intermediate frequency module through the baseband MIMO signal processing module. The host computer module sends control commands to the analog-to-digital converter and digital intermediate frequency module, and the analog-to-digital converter and digital intermediate frequency module reads data for analysis and debugging.

[0041] The above design includes a host computer module and a base station terminal for each subsystem that communicates with the host computer module. In application, such as... Figure 2 As shown, in the downlink at the base station, the raw bit stream is output by the host computer module, and after passing through the modulation and coding processing of the baseband MIMO signal processing module in the subsystem, and the modulation and frequency conversion processing of the analog-to-digital conversion and digital intermediate frequency module, it is transmitted by the first radio frequency front-end module. In the uplink at the base station, the radio frequency signal is received by the first radio frequency front-end module in the subsystem, and after passing through the conversion and frequency conversion modulation processing of the analog-to-digital conversion and digital intermediate frequency module, and the encoding and modulation processing of the baseband MIMO signal processing module, it is uploaded to the host computer module.

[0042] In practical applications, the above design involves specific design for each module, such as... Figure 1As shown, the host computer module in the base station design includes a host, a PXIe-1095 chassis, a PXIe-8881 controller, and a PXIe-6674T timing synchronization unit. The host communicates with the PXIe-8881 controller via Ethernet. The PXIe-8881 controller and the PXIe-6674T timing synchronization unit are connected to the communication carrier of the PXIe-1095 chassis via PXIe interfaces. Communication between the PXIe-8881 controller and the PXIe-6674T timing synchronization unit is achieved based on the communication carrier of the PXIe-1095 chassis. The communication carrier of the PXIe-1095 chassis also interfaces with the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module in each subsystem via PXIe interfaces, enabling communication between the host computer module and the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module in the subsystem. The host computer module is used for application development, configuration and deployment, as well as system initialization, parameter configuration and module scheduling.

[0043] For the baseband MIMO signal processing module in the base station, in practical applications, such as Figure 1 As shown, the specific design includes an FPGA coprocessor unit (model PXIe-7903) and at least one PXIe-8394 bus expansion card. The FPGA coprocessor unit and each PXIe-8394 bus expansion card are connected to the communication carrier of the PXIe-1095 chassis in the host computer module via PXIe interfaces. This enables the PXIe-8881 controller in the host computer module to communicate with the FPGA coprocessor unit via the communication carrier of the PXIe-1095 chassis. The FPGA coprocessor unit interfaces with analog-to-digital converters and digital converters within the same subsystem via a high-speed interface. The intermediate frequency (IF) module transmits data signals. Each PXIe-8394 bus expansion card connects to the analog-to-digital converter (ADC) and digital IF module in the same subsystem via a high-speed interface. This enables control signal transmission between the PXIe-8394 bus expansion card and the connected ADC and IF module. Additionally, the PXIe-8881 controller in the host computer module reads baseband data related to communication with the ADC and IF module via the communication carrier of the PXIe-1095 chassis and the PXIe-8394 bus expansion card, and performs analysis and debugging on the PXIe-8881 controller. In practical applications, the baseband MIMO signal processing module may employ four PXIe-7903 FPGA coprocessor units and sixteen PXIe-8394 bus expansion cards.

[0044] The above-described specific design of the baseband MIMO signal processing module, in practical applications, is based on control signals, such as... Figure 2As shown, in the downlink at the base station, the FPGA coprocessing unit first performs QAM modulation on the raw bit stream output from the host computer module to obtain the corresponding QAM symbol sequence, then adds preset pilot framing, and finally performs zero-forcing precoding (precoding) processing to output the digital signal to the analog-to-digital converter and digital intermediate frequency module in the same subsystem; in the uplink at the base station, the FPGA coprocessing unit first performs channel estimation processing, channel equalization processing, and signal detection processing sequentially on the digital signal output from the analog-to-digital converter and digital intermediate frequency module to obtain the corresponding QAM symbol sequence, and then performs QAM demodulation to obtain the corresponding raw bit stream to upload to the host computer module.

[0045] In practical applications, for analog-to-digital conversion and digital intermediate frequency modules in base stations, such as... Figure 1 As shown, the specific design includes at least one USRP X410 software radio device. Each USRP X410 software radio device is connected to a PXIe-8394 bus expansion card in the baseband MIMO signal processing module of the same subsystem to realize control signal transmission. At the same time, each USRP X410 software radio device is connected to the FPGA coprocessing unit in the baseband MIMO signal processing module of the same subsystem to realize data signal transmission.

[0046] In the analog-to-digital conversion and digital intermediate frequency module, each USRP X410 software radio device is connected to the first RF front-end module in the same subsystem via a low-loss SMA cable to transmit analog intermediate frequency signals; at the same time, each USRP X410 software radio device is connected to the first RF front-end module in the same subsystem via a GPIO interface to transmit control signals.

[0047] Regarding the high-speed interface design between the FPGA coprocessor unit and the analog-to-digital converter and digital intermediate frequency module in the same subsystem, and the high-speed interface design between each PXIe-8394 bus expansion card and the analog-to-digital converter and digital intermediate frequency module in the same subsystem, in practical applications, the MGT high-speed transceiver interface of the FPGA coprocessor unit is specifically designed to connect to the QSFP28 interface of the first USRP X410 software radio device in each USRP X410 software radio device group in the analog-to-digital converter and digital intermediate frequency module in the same subsystem. This achieves high-speed interface connection between the FPGA coprocessor unit and each USRP X410 software radio device, and data signal transmission is achieved through the Aurora protocol. Furthermore, each USRP X410 software radio device is designed to connect to the Mini SAS HD interface of each PXIe-8394 bus expansion card in the baseband MIMO signal processing module in the same subsystem via its Mini SAS HD interface. This achieves high-speed interface connection between each USRP X410 software radio device and the connected PXIe-8394 bus expansion card, and control signal transmission is achieved through the PCIe protocol.

[0048] The above-mentioned specific design of the analog-to-digital conversion and digital intermediate frequency module, in practical applications, such as... Figure 2 As shown, in the downlink at the base station, the USRP X410 software-defined radio sequentially performs OFDM modulation, digital up-conversion, I / Q calibration, and digital-to-analog signal conversion on the digital signal output from the FPGA coprocessor unit in the baseband MIMO signal processing module of the same subsystem to obtain the corresponding analog intermediate frequency (IF) signal, and outputs it to the first RF front-end module in the same subsystem. In the uplink at the base station, the USRP X410 software-defined radio sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration on the analog IF signal output from the first RF front-end module of the same subsystem to obtain the corresponding digital signal, and outputs it to the FPGA coprocessor unit in the baseband MIMO signal processing module of the same subsystem.

[0049] Each USRP X410 software radio device sends a control signal to the first radio front-end module based on the wireless frame format received from the PXIe-8881 controller in the host computer module via control signals, in order to control the first radio front-end module to switch between uplink and downlink functions.

[0050] For the first radio frequency front-end module in the base station, in practical applications, such as Figure 1As shown, the specific design includes a local oscillator unit, at least one TR component unit, and at least one antenna unit. Each antenna unit is connected to each TR component unit via an equal-phase low-loss RF SMA cable. Each USRP software radio device in the analog-to-digital conversion and digital intermediate frequency module is connected to each TR component unit to realize analog intermediate frequency signal transmission between each USRP software radio device and the connected TR component unit. Each TR component unit is connected to the local oscillator unit via an RF line, and the local oscillator unit provides a unified local oscillator signal to each TR component unit. Each TR component unit includes a transmit link and a receive link. In practical applications, it may contain 8 TR component units, and each TR component unit can support 32 independent transmit and receive channels.

[0051] In practical applications, such as base stations Figure 2 As shown, each TR component unit switches the transmit link to form the downlink of the base station or switches the receive link to form the uplink of the base station based on the received control signal. In the uplink of the base station, the TR component unit receives the radio frequency signal received and forwarded by the connected antenna unit, performs downconversion processing to obtain the corresponding analog intermediate frequency signal, and outputs it to the corresponding USRP software radio device. In the downlink of the base station, the TR component unit receives the analog intermediate frequency signal output by the corresponding USRP software radio device, performs upconversion processing to obtain the corresponding radio frequency signal, and outputs it to the corresponding antenna unit for transmission.

[0052] Corresponding to the base station structure designed above, this invention further addresses the user end and designs two embodiments for practical applications. Embodiment one is as follows: Figure 3As shown, the user-end design includes an intermediate frequency (IF) and baseband MIMO signal processing module and a second radio frequency (RF) front-end module that are interconnected. The IF and baseband MIMO signal processing module includes a PXIe-8861 controller, a PXIe-6674T timing synchronization unit, a PXIe-1092 chassis, at least one PXIe-8394 bus expansion card, and at least one USRP X410 software-defined radio. The PXIe-8861 controller, PXIe-6674T timing synchronization unit, and each PXIe-8394 bus expansion card are connected to the communication carrier of the PXIe-1092 chassis. Communication between the PXIe-8861 controller, PXIe-6674T timing synchronization unit, and each PXIe-8394 bus expansion card is achieved based on the communication carrier of the PXIe-1092 chassis. Each USRP X410 software-defined radio connects to the Mini SAS HD interface of each PXIe-8394 bus expansion card. The HD interface enables high-speed interface docking between each USRP X410 software radio device and the connected PXIe-8394 bus expansion card, and realizes data signal transmission and control signal transmission through the PCIe protocol; each USRP X410 software radio device is connected to the second RF front-end module.

[0053] Regarding the user terminal of the above-described embodiment one, in practical applications, such as Figure 5 As shown, in the downlink of the user end in Embodiment 1, the second RF front-end module receives and processes the RF signal to obtain the analog intermediate frequency signal, which is then forwarded to the connected USRP X410 software radio device. The USRP X410 software radio device then sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration to obtain the corresponding digital signal. The FPGA inside the USRP X410 software radio device first sequentially performs channel estimation processing, channel equalization processing, and signal detection processing to obtain the corresponding QAM symbol sequence. After QAM demodulation, the corresponding raw bit stream is obtained and forwarded to the connected PXIe-8394 bus expansion card. The PXIe-8394 bus expansion card then uploads the data to the PXIe-8861 controller or other PXIe interface cards.

[0054] like Figure 5As shown, in the uplink of the user end in Embodiment 1, the PXIe-8861 controller outputs the raw bit stream to the PXIe-8394 bus expansion card, which forwards it to the connected USRP X410 software radio. The FPGA inside the USRP X410 software radio first performs QAM modulation to obtain the corresponding QAM symbol sequence, then adds a preset pilot frame, and sequentially performs OFDM modulation, digital up-conversion, I / Q calibration, and digital-to-analog signal conversion to obtain the corresponding analog intermediate frequency signal, which is then output to the connected second RF front-end module. The second RF front-end module processes the analog intermediate frequency signal to obtain the RF signal for transmission.

[0055] In addition, a second embodiment was designed for the user end, such as... Figure 4 As shown, the system specifically includes an intermediate frequency (IF) and baseband MIMO signal processing module and a second radio frequency (RF) front-end module that are interconnected. The IF and baseband MIMO signal processing module includes at least one USRP X410 software-defined radio device, at least one PCIe-8398 bus expansion card, and at least one host. Each host and each PCIe-8398 bus expansion card are connected and communicate with each other through the PCIe slot inside the host. Each USRP X410 software-defined radio device is connected to the Mini SAS HD interface of each PCIe-8398 bus expansion card via its Mini SAS HD interface, enabling high-speed interface docking between each USRP X410 software-defined radio device and the connected PCIe-8398 bus expansion card, and realizing data signal transmission and control signal transmission through the PCIe protocol. Each USRP X410 software-defined radio device is connected to the second RF front-end module.

[0056] Regarding the user terminal of the above-described embodiment two, in practical applications, such as Figure 5 As shown, in the downlink of the user end in Embodiment 2, the second RF front-end module receives and processes the RF signal to obtain the analog intermediate frequency signal, which is then forwarded to the connected USRP X410 software radio device. The USRP X410 software radio device then sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration to obtain the corresponding digital signal. The FPGA inside the USRP X410 software radio device first sequentially performs channel estimation processing, channel equalization processing, and signal detection processing to obtain the corresponding QAM symbol sequence. After QAM demodulation, the corresponding raw bit stream is obtained and forwarded to the connected PCIe-8398 bus expansion card, which then uploads it to the connected host.

[0057] like Figure 5As shown, in the uplink of the user terminal in Embodiment 2, the host outputs the raw bit stream to the PCIe-8398 bus expansion card, which forwards it to the connected USRP X410 software radio device. The FPGA inside the USRP X410 software radio device first performs QAM modulation to obtain the corresponding QAM symbol sequence, then adds a preset pilot frame, and then performs precoding processing. After that, OFDM modulation, digital upconversion, I / Q calibration, and digital-to-analog signal conversion are performed in sequence to obtain the corresponding analog intermediate frequency signal, which is then output to the connected second RF front-end module. The second RF front-end module processes the analog intermediate frequency signal to obtain the RF signal for transmission.

[0058] Regarding the second radio frequency front-end module in the user terminal designed in Embodiments 1 and 2 above, in practical applications, such as Figure 3 and Figure 4 As shown, the specific design includes a local oscillator unit, at least one TR component unit, and at least one antenna unit. Each antenna unit is grouped and connected to each TR component unit via an RF line. Each USRP software radio device in the user terminal is grouped and connected to each TR component unit, enabling analog intermediate frequency signal transmission and control signal transmission between each USRP software radio device and the connected TR component unit. Each TR component unit is connected to the local oscillator unit via an RF line, and the local oscillator unit provides a unified local oscillator signal to each TR component unit. Each TR component unit includes a transmit link and a receive link.

[0059] In the user terminals involved in Embodiments 1 and 2, each TR component unit switches the transmit link to form the uplink of the user terminal or switches the receive link to form the downlink of the user terminal based on the received control signal. In the downlink of the user terminal, the TR component unit receives and processes the radio frequency signal received and forwarded by the connected antenna unit to obtain the corresponding analog intermediate frequency signal, and outputs it to the corresponding USRP software radio device. In the uplink of the user terminal, the TR component unit receives and processes the analog intermediate frequency signal output by the corresponding USRP software radio device to obtain the corresponding radio frequency signal, and outputs it to the corresponding antenna unit for transmission.

[0060] In practical applications, specific designs are carried out for the TR component units in the second RF front-end module. The structures of each TR component unit are identical, such as... Figure 6As shown, in the structure of each TR component unit, one end of the TR component unit is formed by one side of the first single-pole double-throw switch and connected to the corresponding antenna unit. One end of the first single-pole double-throw switch is connected in series from input to output with a first low-noise amplifier, a first bandpass filter, and a second low-noise amplifier. The output of the second low-noise amplifier is connected to one end of the second single-pole double-throw switch. The other end of the second single-pole double-throw switch is connected in series from input to output with a driver amplifier, a first bandpass filter, and a power amplifier. The output of the power amplifier is connected to the other end of the first single-pole double-throw switch. One end of the second single-pole double-throw switch is connected in series with a second bandpass filter, a mixer, and a third bandpass filter and then connected to one end of the third single-pole double-throw switch. The mixer receives the local oscillator signal and operates. The two ends of the third single-pole double-throw switch are respectively connected to the input of the first variable gain amplifier and the output of the second variable gain amplifier. The output of the first variable gain amplifier and the input of the second variable gain amplifier are respectively connected to the USRP software radio device.

[0061] In practical applications, the TR component unit designed above controls the first single-pole double-throw switch, the second single-pole double-throw switch, and the third single-pole double-throw switch to work synchronously based on the received control signal. A receiving link is formed by sequentially connecting a first low-noise amplifier, a first bandpass filter, a second low-noise amplifier, a second bandpass filter, a mixer, a third bandpass filter, and a first variable gain amplifier; or a transmitting link is formed by sequentially connecting a second variable gain amplifier, a third bandpass filter, a mixer, a second bandpass filter, a driver amplifier, a first bandpass filter, and a power amplifier. In the receiving link, the receiving antenna unit receives and forwards the RF signal, sequentially performing low-noise amplification, filtering, low-noise amplification, filtering, down-conversion, filtering, and gain amplification to obtain the corresponding analog intermediate frequency (IF) signal, which is then output to the corresponding USRP software-defined radio device. In the transmitting link, the receiving antenna unit receives the analog IF signal output by the corresponding USRP software-defined radio device, sequentially performing gain amplification, filtering, up-conversion, filtering, driver amplification, filtering, and power amplification to obtain the corresponding RF signal, which is then output to the corresponding antenna unit for transmission.

[0062] Regarding the first RF front-end module in the base station and the second RF front-end module in the user terminal, each antenna element includes an identical and independent sub-array antenna. The sub-array antenna structure is not dependent on a specific antenna type and is adapted to a typical mid-frequency range. In practical applications, for example, an antenna element includes 8 independent and identical sub-array antennas, each sub-array antenna contains 128 microstrip line antennas with linear polarization, totaling 1024 array elements. Each sub-array antenna contains 4 array elements in the vertical direction and 32 array elements in the horizontal direction. Every 4 antennas in the vertical direction are combined into one antenna sub-array, which can achieve a beamwidth of 20.7 degrees in the vertical plane and 87.8 degrees in the horizontal plane.

[0063] In practical applications, the prototype system of the mid-band ultra-large-scale MIMO designed in this invention can support 1 to 4 subsystems, 4 to 1024 array elements, 1 to 256 transceiver channels, and 1 to 12 users at the base station end. The system bandwidth can reach up to 400MHz. Because this invention adopts a subsystem design and uses high-speed interfaces to connect different modules within the subsystems and between subsystems, the design scheme supports a significantly increased number of channels, high system scalability, and flexible deployment.

[0064] The aforementioned technical solution designs a mid-band ultra-large-scale MIMO prototype system, including a user terminal and a base station terminal including a host computer module and various subsystems. The host computer module transmits and receives the original bit stream or received bit stream. Through the baseband MIMO signal processing module in the subsystem, corresponding to the forward and reverse combination processing of downlink and uplink modulation and coding, and the analog-to-digital conversion and digital intermediate frequency modules in the subsystem, corresponding to the forward and reverse combination processing of downlink and uplink modulation, frequency conversion, and conversion, the first radio frequency front-end module in the subsystem realizes the frequency conversion and transmission and reception of radio frequency signals, thereby realizing communication with the user terminal. The prototype system designed by this invention meets the configuration of a mid-band ultra-large-scale MIMO system, has flexible expansion and deployment characteristics, supports multi-user real-time uplink and downlink data service transmission, has large bandwidth and high throughput, and can be used for key technology verification and rapid deployment testing of advanced communication algorithms.

[0065] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A prototype system for mid-frequency ultra-large-scale MIMO, characterized in that: The system includes a base station and a user terminal that communicate with each other. The base station includes a host computer module and at least one subsystem connected and communicating with the host computer module. The subsystems have the same structure and each subsystem includes a baseband MIMO signal processing module, an analog-to-digital converter and digital intermediate frequency module, and a first radio frequency front-end module connected in series. The host computer module is connected to the baseband MIMO signal processing module in each subsystem for communication and communicates with the analog-to-digital converter and digital intermediate frequency module. The host computer module sends control commands to the analog-to-digital converter and digital intermediate frequency module and reads data for analysis and debugging. In the downlink at the base station, the raw bit stream is output by the host computer module, and then undergoes modulation and coding processing by the baseband MIMO signal processing module in the subsystem, and modulation and frequency conversion processing by the analog-to-digital conversion and digital intermediate frequency module, before being transmitted as a radio frequency signal by the first radio frequency front-end module. In the uplink at the base station, the radio frequency signal is received by the first radio frequency front-end module in the subsystem, and then undergoes conversion and modulation processing by the analog-to-digital conversion and digital intermediate frequency module, and encoding and modulation processing by the baseband MIMO signal processing module before being uploaded to the host computer module. The host computer module in the base station includes a host, a PXIe chassis, a PXIe controller, and a PXIe timing synchronization unit. The host communicates with the PXIe controller via Ethernet. The PXIe controller and the PXIe timing synchronization unit are connected to the communication carrier of the PXIe chassis via PXIe interfaces. Based on the communication carrier of the PXIe chassis, communication interaction between the PXIe controller and the PXIe timing synchronization unit is realized. The communication carrier of the PXIe chassis also interfaces with the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module in each subsystem via PXIe interfaces, realizing communication between the host computer module and the baseband MIMO signal processing module and the analog-to-digital converter and digital intermediate frequency module in the subsystem. The host computer module is used for application development, configuration and deployment, as well as system initialization, parameter configuration and module scheduling. The baseband MIMO signal processing module in the base station includes an FPGA coprocessor unit and at least one PXIe bus expansion card. The FPGA coprocessor unit and each PXIe bus expansion card are connected to the communication carrier of the PXIe chassis in the host computer module through the PXIe interface. This enables the PXIe controller in the host computer module to communicate with the FPGA coprocessor unit through the communication carrier of the PXIe chassis. The FPGA coprocessor unit connects to the analog-to-digital converter and digital intermediate frequency module in the same subsystem through a high-speed interface for data signal transmission. Each PXIe bus expansion card connects to the analog-to-digital converter and digital intermediate frequency module in the same subsystem through a high-speed interface. This enables the PXIe bus expansion card to transmit control signals to the connected analog-to-digital converter and digital intermediate frequency module. The PXIe controller in the host computer module reads the baseband data related to the communication between the analog-to-digital converter and digital intermediate frequency module through the communication carrier of the PXIe chassis and the PXIe bus expansion card, and performs analysis and debugging on the PXIe controller. In the baseband MIMO signal processing module, based on the control signal, in the downlink of the base station, the FPGA coprocessing unit first performs QAM modulation to obtain the corresponding QAM symbol sequence for the raw bit stream output from the host computer module, then adds preset pilot framing, and finally performs precoding processing to output the digital signal to the analog-to-digital conversion and digital intermediate frequency module in the same subsystem. In the uplink of the base station, the FPGA coprocessing unit first performs channel estimation processing, channel equalization processing, and signal detection processing sequentially on the digital signal output from the analog-to-digital converter and digital intermediate frequency module to obtain the corresponding QAM symbol sequence. Then, after QAM demodulation, the corresponding original bit stream is obtained and uploaded to the host computer module.

2. The mid-frequency ultra-large-scale MIMO prototype system according to claim 1, characterized in that: The analog-to-digital conversion and digital intermediate frequency module in the base station includes at least one USRP software radio device. Each USRP software radio device is connected to a PXIe bus expansion card in the baseband MIMO signal processing module of the same subsystem to realize control signal transmission. At the same time, each USRP software radio device is connected to the FPGA coprocessing unit in the baseband MIMO signal processing module of the same subsystem to realize data signal transmission. In the analog-to-digital conversion and digital intermediate frequency module, each USRP software-defined radio device is connected to the first RF front-end module in the same subsystem via a low-loss SMA cable to transmit analog intermediate frequency signals; at the same time, each USRP software-defined radio device is connected to the first RF front-end module in the same subsystem via a GPIO interface to transmit control signals. In the downlink at the base station, the USRP software radio device sequentially performs OFDM modulation, digital up-conversion, I / Q calibration, and digital-to-analog signal conversion on the digital signal output from the FPGA coprocessor unit in the baseband MIMO signal processing module of the same subsystem to obtain the corresponding analog intermediate frequency signal, and outputs it to the first radio frequency front-end module in the same subsystem. In the uplink of the base station, the USRP software radio device sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration on the analog intermediate frequency signal output from the first radio frequency front-end module in the same subsystem to obtain the corresponding digital signal, and outputs it to the FPGA coprocessing unit in the baseband MIMO signal processing module in the same subsystem. Each USRP software radio device sends a control signal to the first radio front-end module based on the wireless frame format received from the PXIe controller in the host computer module via control signals, in order to control the first radio front-end module to switch between uplink and downlink functions.

3. The mid-frequency ultra-large-scale MIMO prototype system according to claim 2, characterized in that: The MGT high-speed transceiver interface of the FPGA coprocessor unit in the baseband MIMO signal processing module of the base station is connected to the QSFP28 interface of the first USRP software radio device in each USRP software radio device group in the analog-to-digital conversion and digital intermediate frequency module of the same subsystem, so as to realize the high-speed interface connection between the FPGA coprocessor unit and each USRP software radio device, and realize data signal transmission through the Aurora protocol. In the analog-to-digital conversion and digital intermediate frequency module, each USRP software radio device is connected to the Mini SAS HD interface of each PXIe bus expansion card in the baseband MIMO signal processing module of the same subsystem via its Mini SAS HD interface. This enables high-speed interface docking between each USRP software radio device and the connected PXIe bus expansion card, and control signal transmission is achieved through the PCIe protocol.

4. The mid-frequency ultra-large-scale MIMO prototype system according to claim 3, characterized in that: The first radio frequency front-end module in the base station includes a local oscillator unit, at least one TR component unit, and at least one antenna unit. Each antenna unit is connected to each TR component unit via an equal-phase low-loss radio frequency SMA cable. Each USRP software radio device in the analog-to-digital conversion and digital intermediate frequency module is connected to each TR component unit to realize analog intermediate frequency signal transmission between each USRP software radio device and the connected TR component unit. Each TR component unit is connected to the local oscillator unit via a radio frequency line, and the local oscillator unit provides a unified local oscillator signal to each TR component unit. Each TR component unit includes a transmit link and a receive link. In the base station, each TR component unit switches the transmit link to form the downlink of the base station or switches the receive link to form the uplink of the base station based on the received control signal. In the uplink of the base station, the TR component unit receives the radio frequency signal received and forwarded by the connected antenna unit, performs downconversion processing to obtain the corresponding analog intermediate frequency signal, and outputs it to the corresponding USRP software radio device. In the downlink of the base station, the TR component unit receives the analog intermediate frequency signal output by the corresponding USRP software radio device, performs upconversion processing to obtain the corresponding radio frequency signal, and outputs it to the corresponding antenna unit for transmission.

5. The mid-band ultra-large-scale MIMO prototype system according to claim 1, characterized in that: The user terminal includes an intermediate frequency (IF) and baseband MIMO signal processing module and a second radio frequency (RF) front-end module that are interconnected. The IF and baseband MIMO signal processing module includes a PXIe controller, a PXIe timing synchronization unit, a PXIe chassis, at least one PXIe bus expansion card, and at least one USRP software-defined radio (SDR). The PXIe controller, PXIe timing synchronization unit, and each PXIe bus expansion card are connected to the communication carrier of the PXIe chassis, and communication between the PXIe controller, PXIe timing synchronization unit, and each PXIe bus expansion card is realized based on the communication carrier of the PXIe chassis. Each USRP SDR connects to the Mini SAS HD interface of each PXIe bus expansion card via its Mini SAS HD interface, realizing high-speed interface docking between each USRP SDR and the connected PXIe bus expansion card, and realizing data signal transmission and control signal transmission through the PCIe protocol. Each USRP SDR is connected to the second RF front-end module. In the downlink at the user end, the second RF front-end module receives and processes RF signals to obtain analog intermediate frequency signals, which are then forwarded to the connected USRP software radio equipment. The USRP software radio equipment then sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration to obtain the corresponding digital signals. The FPGA inside the USRP software radio equipment then sequentially performs channel estimation, channel equalization, and signal detection to obtain the corresponding QAM symbol sequence. After QAM demodulation, the corresponding raw bit stream is obtained and forwarded to the connected PXIe bus expansion card. The PXIe bus expansion card then uploads the data to the PXIe controller or other PXIe interface cards. In the uplink at the user end, the PXIe controller outputs the raw bit stream to the PXIe bus expansion card, which forwards it to the connected USRP software radio device. The FPGA inside the USRP software radio device first performs QAM modulation to obtain the corresponding QAM symbol sequence, then adds preset pilot frames, and sequentially performs OFDM modulation, digital upconversion, I / Q calibration, and digital-to-analog signal conversion to obtain the corresponding analog intermediate frequency signal, which is then output to the connected second RF front-end module. The second RF front-end module processes the analog intermediate frequency signal to obtain the RF signal for transmission. Alternatively, the user terminal may include an intermediate frequency (IF) and baseband MIMO signal processing module and a second radio frequency (RF) front-end module that are interconnected. The IF and baseband MIMO signal processing module includes at least one USRP software radio device, at least one PCIe bus expansion card, and at least one host. Each host and each PCIe bus expansion card are connected and communicate with each other through the PCIe slots inside the host. Each USRP software radio device is connected to the Mini SAS HD interface of each PCIe bus expansion card via its Mini SAS HD interface, enabling high-speed interface docking between each USRP software radio device and the connected PCIe bus expansion card, and transmitting data signals and control signals through the PCIe protocol. Each USRP software radio device is connected to the second RF front-end module. In the downlink at the user end, the second RF front-end module receives and processes RF signals to obtain analog intermediate frequency signals, which are then forwarded to the connected USRP software radio device. The USRP software radio device then sequentially performs analog-to-digital signal conversion, digital down-conversion, OFDM demodulation, and I / Q calibration to obtain the corresponding digital signals. The FPGA inside the USRP software radio device first sequentially performs channel estimation processing, channel equalization processing, and signal detection processing to obtain the corresponding QAM symbol sequence. After QAM demodulation, the corresponding raw bit stream is obtained and forwarded to the connected PCIe bus expansion card, which then uploads it to the host. In the uplink at the user end, the host outputs the raw bit stream to the PCIe bus expansion card, which forwards it to the connected USRP software radio device. The FPGA inside the USRP software radio device first performs QAM modulation to obtain the corresponding QAM symbol sequence, then adds preset pilot framing, and performs precoding processing. After that, OFDM modulation, digital upconversion, I / Q calibration, and digital-to-analog signal conversion are performed in sequence to obtain the corresponding analog intermediate frequency signal, which is then output to the connected second RF front-end module. The second RF front-end module processes the analog intermediate frequency signal to obtain the RF signal for transmission.

6. The mid-frequency ultra-large-scale MIMO prototype system according to claim 5, characterized in that: The second radio frequency front-end module in the user terminal includes a local oscillator unit, at least one TR component unit, and at least one antenna unit. Each antenna unit is grouped and connected to each TR component unit via radio frequency lines. Each USRP software radio device in the user terminal is grouped and connected to each TR component unit, enabling analog intermediate frequency signal transmission and control signal transmission between each USRP software radio device and its connected TR component unit. Each TR component unit is connected to the local oscillator unit via radio frequency lines, and the local oscillator unit provides a unified local oscillator signal to each TR component unit. Each TR component unit includes a transmit link and a receive link. In the user terminal, each TR component unit switches the transmit link to form the user terminal's uplink or switches the receive link to form the user terminal's downlink based on the received control signal. In the user terminal's downlink, the TR component unit receives and processes the radio frequency signal received and forwarded by the connected antenna unit to obtain the corresponding analog intermediate frequency signal, and outputs it to the corresponding USRP software radio device. In the user terminal's uplink, the TR component unit receives and processes the analog intermediate frequency signal output by the corresponding USRP software radio device to obtain the corresponding radio frequency signal, and outputs it to the corresponding antenna unit for transmission.

7. A mid-frequency ultra-large-scale MIMO prototype system according to claim 4 or 6, characterized in that: The structures of each TR component unit are identical. In the structure of each TR component unit, one end of the TR component unit is formed by one side of the first single-pole double-throw switch and connected to the corresponding antenna unit. One end of the first single-pole double-throw switch is connected in series from input to output with a first low-noise amplifier, a first bandpass filter, and a second low-noise amplifier. The output of the second low-noise amplifier is connected to one end of the second single-pole double-throw switch. The other end of the second single-pole double-throw switch is connected in series from input to output with a driver amplifier, a first bandpass filter, and a power amplifier. The output of the power amplifier is connected to the other end of the first single-pole double-throw switch. One end of the second single-pole double-throw switch is connected in series with a second bandpass filter, a mixer, and a third bandpass filter and then connected to one end of the third single-pole double-throw switch. The mixer receives the local oscillator signal and operates. The two ends of the third single-pole double-throw switch are respectively connected to the input of the first variable gain amplifier and the output of the second variable gain amplifier. The output of the first variable gain amplifier and the input of the second variable gain amplifier are respectively connected to the USRP software radio device. The TR component unit controls the first single-pole double-throw switch, the second single-pole double-throw switch, and the third single-pole double-throw switch to operate synchronously based on the received control signal. A receiving link is formed by sequentially connecting a first low-noise amplifier, a first bandpass filter, a second low-noise amplifier, a second bandpass filter, a mixer, a third bandpass filter, and a first variable gain amplifier. Alternatively, a transmitting link is formed by sequentially connecting a second variable gain amplifier, a third bandpass filter, a mixer, a second bandpass filter, a driver amplifier, a first bandpass filter, and a power amplifier. In the receiving link, the receiving antenna unit receives and forwards the radio frequency signal, which undergoes low-noise amplification, filtering, low-noise amplification, filtering, down-conversion, filtering, and gain amplification processes to obtain the corresponding analog intermediate frequency signal, which is then output to the corresponding USRP software radio device. In the transmit link, the analog intermediate frequency signal output by the corresponding USRP software radio device is received, and gain amplification, filtering, up-conversion, filtering, drive amplification, filtering, and power amplification are performed sequentially to obtain the corresponding radio frequency signal, which is then output to the corresponding antenna unit for transmission.

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